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[mirror_ubuntu-bionic-kernel.git] / drivers / watchdog / iTCO_wdt.c
1 /*
2 * intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets)
3 *
4 * (c) Copyright 2006-2008 Wim Van Sebroeck <wim@iguana.be>.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * 82801AA (ICH) : document number 290655-003, 290677-014,
18 * 82801AB (ICHO) : document number 290655-003, 290677-014,
19 * 82801BA (ICH2) : document number 290687-002, 298242-027,
20 * 82801BAM (ICH2-M) : document number 290687-002, 298242-027,
21 * 82801CA (ICH3-S) : document number 290733-003, 290739-013,
22 * 82801CAM (ICH3-M) : document number 290716-001, 290718-007,
23 * 82801DB (ICH4) : document number 290744-001, 290745-020,
24 * 82801DBM (ICH4-M) : document number 252337-001, 252663-005,
25 * 82801E (C-ICH) : document number 273599-001, 273645-002,
26 * 82801EB (ICH5) : document number 252516-001, 252517-003,
27 * 82801ER (ICH5R) : document number 252516-001, 252517-003,
28 * 82801FB (ICH6) : document number 301473-002, 301474-007,
29 * 82801FR (ICH6R) : document number 301473-002, 301474-007,
30 * 82801FBM (ICH6-M) : document number 301473-002, 301474-007,
31 * 82801FW (ICH6W) : document number 301473-001, 301474-007,
32 * 82801FRW (ICH6RW) : document number 301473-001, 301474-007,
33 * 82801GB (ICH7) : document number 307013-002, 307014-009,
34 * 82801GR (ICH7R) : document number 307013-002, 307014-009,
35 * 82801GDH (ICH7DH) : document number 307013-002, 307014-009,
36 * 82801GBM (ICH7-M) : document number 307013-002, 307014-009,
37 * 82801GHM (ICH7-M DH) : document number 307013-002, 307014-009,
38 * 82801HB (ICH8) : document number 313056-003, 313057-009,
39 * 82801HR (ICH8R) : document number 313056-003, 313057-009,
40 * 82801HBM (ICH8M) : document number 313056-003, 313057-009,
41 * 82801HH (ICH8DH) : document number 313056-003, 313057-009,
42 * 82801HO (ICH8DO) : document number 313056-003, 313057-009,
43 * 82801HEM (ICH8M-E) : document number 313056-003, 313057-009,
44 * 82801IB (ICH9) : document number 316972-001, 316973-006,
45 * 82801IR (ICH9R) : document number 316972-001, 316973-006,
46 * 82801IH (ICH9DH) : document number 316972-001, 316973-006,
47 * 82801IO (ICH9DO) : document number 316972-001, 316973-006,
48 * 6300ESB (6300ESB) : document number 300641-003, 300884-010,
49 * 631xESB (631xESB) : document number 313082-001, 313075-005,
50 * 632xESB (632xESB) : document number 313082-001, 313075-005
51 */
52
53 /*
54 * Includes, defines, variables, module parameters, ...
55 */
56
57 /* Module and version information */
58 #define DRV_NAME "iTCO_wdt"
59 #define DRV_VERSION "1.04"
60 #define PFX DRV_NAME ": "
61
62 /* Includes */
63 #include <linux/module.h> /* For module specific items */
64 #include <linux/moduleparam.h> /* For new moduleparam's */
65 #include <linux/types.h> /* For standard types (like size_t) */
66 #include <linux/errno.h> /* For the -ENODEV/... values */
67 #include <linux/kernel.h> /* For printk/panic/... */
68 #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
69 (WATCHDOG_MINOR) */
70 #include <linux/watchdog.h> /* For the watchdog specific items */
71 #include <linux/init.h> /* For __init/__exit/... */
72 #include <linux/fs.h> /* For file operations */
73 #include <linux/platform_device.h> /* For platform_driver framework */
74 #include <linux/pci.h> /* For pci functions */
75 #include <linux/ioport.h> /* For io-port access */
76 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
77 #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
78 #include <linux/io.h> /* For inb/outb/... */
79
80 #include "iTCO_vendor.h"
81
82 /* TCO related info */
83 enum iTCO_chipsets {
84 TCO_ICH = 0, /* ICH */
85 TCO_ICH0, /* ICH0 */
86 TCO_ICH2, /* ICH2 */
87 TCO_ICH2M, /* ICH2-M */
88 TCO_ICH3, /* ICH3-S */
89 TCO_ICH3M, /* ICH3-M */
90 TCO_ICH4, /* ICH4 */
91 TCO_ICH4M, /* ICH4-M */
92 TCO_CICH, /* C-ICH */
93 TCO_ICH5, /* ICH5 & ICH5R */
94 TCO_6300ESB, /* 6300ESB */
95 TCO_ICH6, /* ICH6 & ICH6R */
96 TCO_ICH6M, /* ICH6-M */
97 TCO_ICH6W, /* ICH6W & ICH6RW */
98 TCO_ICH7, /* ICH7 & ICH7R */
99 TCO_ICH7M, /* ICH7-M */
100 TCO_ICH7MDH, /* ICH7-M DH */
101 TCO_ICH8, /* ICH8 & ICH8R */
102 TCO_ICH8ME, /* ICH8M-E */
103 TCO_ICH8DH, /* ICH8DH */
104 TCO_ICH8DO, /* ICH8DO */
105 TCO_ICH8M, /* ICH8M */
106 TCO_ICH9, /* ICH9 */
107 TCO_ICH9R, /* ICH9R */
108 TCO_ICH9DH, /* ICH9DH */
109 TCO_ICH9DO, /* ICH9DO */
110 TCO_631XESB, /* 631xESB/632xESB */
111 };
112
113 static struct {
114 char *name;
115 unsigned int iTCO_version;
116 } iTCO_chipset_info[] __devinitdata = {
117 {"ICH", 1},
118 {"ICH0", 1},
119 {"ICH2", 1},
120 {"ICH2-M", 1},
121 {"ICH3-S", 1},
122 {"ICH3-M", 1},
123 {"ICH4", 1},
124 {"ICH4-M", 1},
125 {"C-ICH", 1},
126 {"ICH5 or ICH5R", 1},
127 {"6300ESB", 1},
128 {"ICH6 or ICH6R", 2},
129 {"ICH6-M", 2},
130 {"ICH6W or ICH6RW", 2},
131 {"ICH7 or ICH7R", 2},
132 {"ICH7-M", 2},
133 {"ICH7-M DH", 2},
134 {"ICH8 or ICH8R", 2},
135 {"ICH8M-E", 2},
136 {"ICH8DH", 2},
137 {"ICH8DO", 2},
138 {"ICH8M", 2},
139 {"ICH9", 2},
140 {"ICH9R", 2},
141 {"ICH9DH", 2},
142 {"ICH9DO", 2},
143 {"631xESB/632xESB", 2},
144 {NULL, 0}
145 };
146
147 #define ITCO_PCI_DEVICE(dev, data) \
148 .vendor = PCI_VENDOR_ID_INTEL, \
149 .device = dev, \
150 .subvendor = PCI_ANY_ID, \
151 .subdevice = PCI_ANY_ID, \
152 .class = 0, \
153 .class_mask = 0, \
154 .driver_data = data
155
156 /*
157 * This data only exists for exporting the supported PCI ids
158 * via MODULE_DEVICE_TABLE. We do not actually register a
159 * pci_driver, because the I/O Controller Hub has also other
160 * functions that probably will be registered by other drivers.
161 */
162 static struct pci_device_id iTCO_wdt_pci_tbl[] = {
163 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH)},
164 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0)},
165 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2)},
166 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M)},
167 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3)},
168 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M)},
169 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4)},
170 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M)},
171 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH)},
172 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5)},
173 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)},
174 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6)},
175 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M)},
176 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W)},
177 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)},
178 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)},
179 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)},
180 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)},
181 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)},
182 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)},
183 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)},
184 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)},
185 { ITCO_PCI_DEVICE(0x2918, TCO_ICH9)},
186 { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)},
187 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)},
188 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)},
189 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)},
190 { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)},
191 { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)},
192 { ITCO_PCI_DEVICE(0x2673, TCO_631XESB)},
193 { ITCO_PCI_DEVICE(0x2674, TCO_631XESB)},
194 { ITCO_PCI_DEVICE(0x2675, TCO_631XESB)},
195 { ITCO_PCI_DEVICE(0x2676, TCO_631XESB)},
196 { ITCO_PCI_DEVICE(0x2677, TCO_631XESB)},
197 { ITCO_PCI_DEVICE(0x2678, TCO_631XESB)},
198 { ITCO_PCI_DEVICE(0x2679, TCO_631XESB)},
199 { ITCO_PCI_DEVICE(0x267a, TCO_631XESB)},
200 { ITCO_PCI_DEVICE(0x267b, TCO_631XESB)},
201 { ITCO_PCI_DEVICE(0x267c, TCO_631XESB)},
202 { ITCO_PCI_DEVICE(0x267d, TCO_631XESB)},
203 { ITCO_PCI_DEVICE(0x267e, TCO_631XESB)},
204 { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)},
205 { 0, }, /* End of list */
206 };
207 MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
208
209 /* Address definitions for the TCO */
210 /* TCO base address */
211 #define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60
212 /* SMI Control and Enable Register */
213 #define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30
214
215 #define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Curr. Value */
216 #define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */
217 #define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */
218 #define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */
219 #define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
220 #define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */
221 #define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */
222 #define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */
223 #define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */
224
225 /* internal variables */
226 static unsigned long is_active;
227 static char expect_release;
228 static struct { /* this is private data for the iTCO_wdt device */
229 /* TCO version/generation */
230 unsigned int iTCO_version;
231 /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
232 unsigned long ACPIBASE;
233 /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
234 unsigned long __iomem *gcs;
235 /* the lock for io operations */
236 spinlock_t io_lock;
237 /* the PCI-device */
238 struct pci_dev *pdev;
239 } iTCO_wdt_private;
240
241 /* the watchdog platform device */
242 static struct platform_device *iTCO_wdt_platform_device;
243
244 /* module parameters */
245 #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
246 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
247 module_param(heartbeat, int, 0);
248 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
249
250 static int nowayout = WATCHDOG_NOWAYOUT;
251 module_param(nowayout, int, 0);
252 MODULE_PARM_DESC(nowayout,
253 "Watchdog cannot be stopped once started (default="
254 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
255
256 /*
257 * Some TCO specific functions
258 */
259
260 static inline unsigned int seconds_to_ticks(int seconds)
261 {
262 /* the internal timer is stored as ticks which decrement
263 * every 0.6 seconds */
264 return (seconds * 10) / 6;
265 }
266
267 static void iTCO_wdt_set_NO_REBOOT_bit(void)
268 {
269 u32 val32;
270
271 /* Set the NO_REBOOT bit: this disables reboots */
272 if (iTCO_wdt_private.iTCO_version == 2) {
273 val32 = readl(iTCO_wdt_private.gcs);
274 val32 |= 0x00000020;
275 writel(val32, iTCO_wdt_private.gcs);
276 } else if (iTCO_wdt_private.iTCO_version == 1) {
277 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
278 val32 |= 0x00000002;
279 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
280 }
281 }
282
283 static int iTCO_wdt_unset_NO_REBOOT_bit(void)
284 {
285 int ret = 0;
286 u32 val32;
287
288 /* Unset the NO_REBOOT bit: this enables reboots */
289 if (iTCO_wdt_private.iTCO_version == 2) {
290 val32 = readl(iTCO_wdt_private.gcs);
291 val32 &= 0xffffffdf;
292 writel(val32, iTCO_wdt_private.gcs);
293
294 val32 = readl(iTCO_wdt_private.gcs);
295 if (val32 & 0x00000020)
296 ret = -EIO;
297 } else if (iTCO_wdt_private.iTCO_version == 1) {
298 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
299 val32 &= 0xfffffffd;
300 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
301
302 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
303 if (val32 & 0x00000002)
304 ret = -EIO;
305 }
306
307 return ret; /* returns: 0 = OK, -EIO = Error */
308 }
309
310 static int iTCO_wdt_start(void)
311 {
312 unsigned int val;
313 unsigned long val32;
314
315 spin_lock(&iTCO_wdt_private.io_lock);
316
317 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
318
319 /* disable chipset's NO_REBOOT bit */
320 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
321 spin_unlock(&iTCO_wdt_private.io_lock);
322 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
323 return -EIO;
324 }
325
326 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
327 val32 = inl(SMI_EN);
328 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
329 outl(val32, SMI_EN);
330
331 /* Force the timer to its reload value by writing to the TCO_RLD
332 register */
333 if (iTCO_wdt_private.iTCO_version == 2)
334 outw(0x01, TCO_RLD);
335 else if (iTCO_wdt_private.iTCO_version == 1)
336 outb(0x01, TCO_RLD);
337
338 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
339 val = inw(TCO1_CNT);
340 val &= 0xf7ff;
341 outw(val, TCO1_CNT);
342 val = inw(TCO1_CNT);
343 spin_unlock(&iTCO_wdt_private.io_lock);
344
345 if (val & 0x0800)
346 return -1;
347 return 0;
348 }
349
350 static int iTCO_wdt_stop(void)
351 {
352 unsigned int val;
353 unsigned long val32;
354
355 spin_lock(&iTCO_wdt_private.io_lock);
356
357 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
358
359 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
360 val = inw(TCO1_CNT);
361 val |= 0x0800;
362 outw(val, TCO1_CNT);
363 val = inw(TCO1_CNT);
364
365 /* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */
366 val32 = inl(SMI_EN);
367 val32 &= 0x00002000;
368 outl(val32, SMI_EN);
369
370 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
371 iTCO_wdt_set_NO_REBOOT_bit();
372
373 spin_unlock(&iTCO_wdt_private.io_lock);
374
375 if ((val & 0x0800) == 0)
376 return -1;
377 return 0;
378 }
379
380 static int iTCO_wdt_keepalive(void)
381 {
382 spin_lock(&iTCO_wdt_private.io_lock);
383
384 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
385
386 /* Reload the timer by writing to the TCO Timer Counter register */
387 if (iTCO_wdt_private.iTCO_version == 2)
388 outw(0x01, TCO_RLD);
389 else if (iTCO_wdt_private.iTCO_version == 1)
390 outb(0x01, TCO_RLD);
391
392 spin_unlock(&iTCO_wdt_private.io_lock);
393 return 0;
394 }
395
396 static int iTCO_wdt_set_heartbeat(int t)
397 {
398 unsigned int val16;
399 unsigned char val8;
400 unsigned int tmrval;
401
402 tmrval = seconds_to_ticks(t);
403 /* from the specs: */
404 /* "Values of 0h-3h are ignored and should not be attempted" */
405 if (tmrval < 0x04)
406 return -EINVAL;
407 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
408 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
409 return -EINVAL;
410
411 iTCO_vendor_pre_set_heartbeat(tmrval);
412
413 /* Write new heartbeat to watchdog */
414 if (iTCO_wdt_private.iTCO_version == 2) {
415 spin_lock(&iTCO_wdt_private.io_lock);
416 val16 = inw(TCOv2_TMR);
417 val16 &= 0xfc00;
418 val16 |= tmrval;
419 outw(val16, TCOv2_TMR);
420 val16 = inw(TCOv2_TMR);
421 spin_unlock(&iTCO_wdt_private.io_lock);
422
423 if ((val16 & 0x3ff) != tmrval)
424 return -EINVAL;
425 } else if (iTCO_wdt_private.iTCO_version == 1) {
426 spin_lock(&iTCO_wdt_private.io_lock);
427 val8 = inb(TCOv1_TMR);
428 val8 &= 0xc0;
429 val8 |= (tmrval & 0xff);
430 outb(val8, TCOv1_TMR);
431 val8 = inb(TCOv1_TMR);
432 spin_unlock(&iTCO_wdt_private.io_lock);
433
434 if ((val8 & 0x3f) != tmrval)
435 return -EINVAL;
436 }
437
438 heartbeat = t;
439 return 0;
440 }
441
442 static int iTCO_wdt_get_timeleft(int *time_left)
443 {
444 unsigned int val16;
445 unsigned char val8;
446
447 /* read the TCO Timer */
448 if (iTCO_wdt_private.iTCO_version == 2) {
449 spin_lock(&iTCO_wdt_private.io_lock);
450 val16 = inw(TCO_RLD);
451 val16 &= 0x3ff;
452 spin_unlock(&iTCO_wdt_private.io_lock);
453
454 *time_left = (val16 * 6) / 10;
455 } else if (iTCO_wdt_private.iTCO_version == 1) {
456 spin_lock(&iTCO_wdt_private.io_lock);
457 val8 = inb(TCO_RLD);
458 val8 &= 0x3f;
459 spin_unlock(&iTCO_wdt_private.io_lock);
460
461 *time_left = (val8 * 6) / 10;
462 } else
463 return -EINVAL;
464 return 0;
465 }
466
467 /*
468 * /dev/watchdog handling
469 */
470
471 static int iTCO_wdt_open(struct inode *inode, struct file *file)
472 {
473 /* /dev/watchdog can only be opened once */
474 if (test_and_set_bit(0, &is_active))
475 return -EBUSY;
476
477 /*
478 * Reload and activate timer
479 */
480 iTCO_wdt_start();
481 return nonseekable_open(inode, file);
482 }
483
484 static int iTCO_wdt_release(struct inode *inode, struct file *file)
485 {
486 /*
487 * Shut off the timer.
488 */
489 if (expect_release == 42) {
490 iTCO_wdt_stop();
491 } else {
492 printk(KERN_CRIT PFX
493 "Unexpected close, not stopping watchdog!\n");
494 iTCO_wdt_keepalive();
495 }
496 clear_bit(0, &is_active);
497 expect_release = 0;
498 return 0;
499 }
500
501 static ssize_t iTCO_wdt_write(struct file *file, const char __user *data,
502 size_t len, loff_t *ppos)
503 {
504 /* See if we got the magic character 'V' and reload the timer */
505 if (len) {
506 if (!nowayout) {
507 size_t i;
508
509 /* note: just in case someone wrote the magic
510 character five months ago... */
511 expect_release = 0;
512
513 /* scan to see whether or not we got the
514 magic character */
515 for (i = 0; i != len; i++) {
516 char c;
517 if (get_user(c, data + i))
518 return -EFAULT;
519 if (c == 'V')
520 expect_release = 42;
521 }
522 }
523
524 /* someone wrote to us, we should reload the timer */
525 iTCO_wdt_keepalive();
526 }
527 return len;
528 }
529
530 static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd,
531 unsigned long arg)
532 {
533 int new_options, retval = -EINVAL;
534 int new_heartbeat;
535 void __user *argp = (void __user *)arg;
536 int __user *p = argp;
537 static struct watchdog_info ident = {
538 .options = WDIOF_SETTIMEOUT |
539 WDIOF_KEEPALIVEPING |
540 WDIOF_MAGICCLOSE,
541 .firmware_version = 0,
542 .identity = DRV_NAME,
543 };
544
545 switch (cmd) {
546 case WDIOC_GETSUPPORT:
547 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
548 case WDIOC_GETSTATUS:
549 case WDIOC_GETBOOTSTATUS:
550 return put_user(0, p);
551
552 case WDIOC_SETOPTIONS:
553 {
554 if (get_user(new_options, p))
555 return -EFAULT;
556
557 if (new_options & WDIOS_DISABLECARD) {
558 iTCO_wdt_stop();
559 retval = 0;
560 }
561 if (new_options & WDIOS_ENABLECARD) {
562 iTCO_wdt_keepalive();
563 iTCO_wdt_start();
564 retval = 0;
565 }
566 return retval;
567 }
568 case WDIOC_KEEPALIVE:
569 iTCO_wdt_keepalive();
570 return 0;
571
572 case WDIOC_SETTIMEOUT:
573 {
574 if (get_user(new_heartbeat, p))
575 return -EFAULT;
576 if (iTCO_wdt_set_heartbeat(new_heartbeat))
577 return -EINVAL;
578 iTCO_wdt_keepalive();
579 /* Fall */
580 }
581 case WDIOC_GETTIMEOUT:
582 return put_user(heartbeat, p);
583 case WDIOC_GETTIMELEFT:
584 {
585 int time_left;
586 if (iTCO_wdt_get_timeleft(&time_left))
587 return -EINVAL;
588 return put_user(time_left, p);
589 }
590 default:
591 return -ENOTTY;
592 }
593 }
594
595 /*
596 * Kernel Interfaces
597 */
598
599 static const struct file_operations iTCO_wdt_fops = {
600 .owner = THIS_MODULE,
601 .llseek = no_llseek,
602 .write = iTCO_wdt_write,
603 .unlocked_ioctl = iTCO_wdt_ioctl,
604 .open = iTCO_wdt_open,
605 .release = iTCO_wdt_release,
606 };
607
608 static struct miscdevice iTCO_wdt_miscdev = {
609 .minor = WATCHDOG_MINOR,
610 .name = "watchdog",
611 .fops = &iTCO_wdt_fops,
612 };
613
614 /*
615 * Init & exit routines
616 */
617
618 static int __devinit iTCO_wdt_init(struct pci_dev *pdev,
619 const struct pci_device_id *ent, struct platform_device *dev)
620 {
621 int ret;
622 u32 base_address;
623 unsigned long RCBA;
624
625 /*
626 * Find the ACPI/PM base I/O address which is the base
627 * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
628 * ACPIBASE is bits [15:7] from 0x40-0x43
629 */
630 pci_read_config_dword(pdev, 0x40, &base_address);
631 base_address &= 0x0000ff80;
632 if (base_address == 0x00000000) {
633 /* Something's wrong here, ACPIBASE has to be set */
634 printk(KERN_ERR PFX "failed to get TCOBASE address\n");
635 pci_dev_put(pdev);
636 return -ENODEV;
637 }
638 iTCO_wdt_private.iTCO_version =
639 iTCO_chipset_info[ent->driver_data].iTCO_version;
640 iTCO_wdt_private.ACPIBASE = base_address;
641 iTCO_wdt_private.pdev = pdev;
642
643 /* Get the Memory-Mapped GCS register, we need it for the
644 NO_REBOOT flag (TCO v2). To get access to it you have to
645 read RCBA from PCI Config space 0xf0 and use it as base.
646 GCS = RCBA + ICH6_GCS(0x3410). */
647 if (iTCO_wdt_private.iTCO_version == 2) {
648 pci_read_config_dword(pdev, 0xf0, &base_address);
649 RCBA = base_address & 0xffffc000;
650 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4);
651 }
652
653 /* Check chipset's NO_REBOOT bit */
654 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
655 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
656 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
657 goto out;
658 }
659
660 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
661 iTCO_wdt_set_NO_REBOOT_bit();
662
663 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
664 if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
665 printk(KERN_ERR PFX
666 "I/O address 0x%04lx already in use\n", SMI_EN);
667 ret = -EIO;
668 goto out;
669 }
670
671 /* The TCO I/O registers reside in a 32-byte range pointed to
672 by the TCOBASE value */
673 if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) {
674 printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n",
675 TCOBASE);
676 ret = -EIO;
677 goto unreg_smi_en;
678 }
679
680 printk(KERN_INFO PFX
681 "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
682 iTCO_chipset_info[ent->driver_data].name,
683 iTCO_chipset_info[ent->driver_data].iTCO_version,
684 TCOBASE);
685
686 /* Clear out the (probably old) status */
687 outb(8, TCO1_STS); /* Clear the Time Out Status bit */
688 outb(2, TCO2_STS); /* Clear SECOND_TO_STS bit */
689 outb(4, TCO2_STS); /* Clear BOOT_STS bit */
690
691 /* Make sure the watchdog is not running */
692 iTCO_wdt_stop();
693
694 /* Check that the heartbeat value is within it's range;
695 if not reset to the default */
696 if (iTCO_wdt_set_heartbeat(heartbeat)) {
697 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
698 printk(KERN_INFO PFX "heartbeat value must be 2 < heartbeat < 39 (TCO v1) or 613 (TCO v2), using %d\n",
699 heartbeat);
700 }
701
702 ret = misc_register(&iTCO_wdt_miscdev);
703 if (ret != 0) {
704 printk(KERN_ERR PFX
705 "cannot register miscdev on minor=%d (err=%d)\n",
706 WATCHDOG_MINOR, ret);
707 goto unreg_region;
708 }
709
710 printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
711 heartbeat, nowayout);
712
713 return 0;
714
715 unreg_region:
716 release_region(TCOBASE, 0x20);
717 unreg_smi_en:
718 release_region(SMI_EN, 4);
719 out:
720 if (iTCO_wdt_private.iTCO_version == 2)
721 iounmap(iTCO_wdt_private.gcs);
722 pci_dev_put(iTCO_wdt_private.pdev);
723 iTCO_wdt_private.ACPIBASE = 0;
724 return ret;
725 }
726
727 static void __devexit iTCO_wdt_cleanup(void)
728 {
729 /* Stop the timer before we leave */
730 if (!nowayout)
731 iTCO_wdt_stop();
732
733 /* Deregister */
734 misc_deregister(&iTCO_wdt_miscdev);
735 release_region(TCOBASE, 0x20);
736 release_region(SMI_EN, 4);
737 if (iTCO_wdt_private.iTCO_version == 2)
738 iounmap(iTCO_wdt_private.gcs);
739 pci_dev_put(iTCO_wdt_private.pdev);
740 iTCO_wdt_private.ACPIBASE = 0;
741 }
742
743 static int __devinit iTCO_wdt_probe(struct platform_device *dev)
744 {
745 int found = 0;
746 struct pci_dev *pdev = NULL;
747 const struct pci_device_id *ent;
748
749 spin_lock_init(&iTCO_wdt_private.io_lock);
750
751 for_each_pci_dev(pdev) {
752 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
753 if (ent) {
754 if (!(iTCO_wdt_init(pdev, ent, dev))) {
755 found++;
756 break;
757 }
758 }
759 }
760
761 if (!found) {
762 printk(KERN_INFO PFX "No card detected\n");
763 return -ENODEV;
764 }
765
766 return 0;
767 }
768
769 static int __devexit iTCO_wdt_remove(struct platform_device *dev)
770 {
771 if (iTCO_wdt_private.ACPIBASE)
772 iTCO_wdt_cleanup();
773
774 return 0;
775 }
776
777 static void iTCO_wdt_shutdown(struct platform_device *dev)
778 {
779 iTCO_wdt_stop();
780 }
781
782 #define iTCO_wdt_suspend NULL
783 #define iTCO_wdt_resume NULL
784
785 static struct platform_driver iTCO_wdt_driver = {
786 .probe = iTCO_wdt_probe,
787 .remove = __devexit_p(iTCO_wdt_remove),
788 .shutdown = iTCO_wdt_shutdown,
789 .suspend = iTCO_wdt_suspend,
790 .resume = iTCO_wdt_resume,
791 .driver = {
792 .owner = THIS_MODULE,
793 .name = DRV_NAME,
794 },
795 };
796
797 static int __init iTCO_wdt_init_module(void)
798 {
799 int err;
800
801 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s\n",
802 DRV_VERSION);
803
804 err = platform_driver_register(&iTCO_wdt_driver);
805 if (err)
806 return err;
807
808 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME,
809 -1, NULL, 0);
810 if (IS_ERR(iTCO_wdt_platform_device)) {
811 err = PTR_ERR(iTCO_wdt_platform_device);
812 goto unreg_platform_driver;
813 }
814
815 return 0;
816
817 unreg_platform_driver:
818 platform_driver_unregister(&iTCO_wdt_driver);
819 return err;
820 }
821
822 static void __exit iTCO_wdt_cleanup_module(void)
823 {
824 platform_device_unregister(iTCO_wdt_platform_device);
825 platform_driver_unregister(&iTCO_wdt_driver);
826 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
827 }
828
829 module_init(iTCO_wdt_init_module);
830 module_exit(iTCO_wdt_cleanup_module);
831
832 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
833 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
834 MODULE_VERSION(DRV_VERSION);
835 MODULE_LICENSE("GPL");
836 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
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