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hw/arm/allwinner-r40: add Clock Control Unit
[mirror_qemu.git] / hw / arm / allwinner-r40.c
1 /*
2 * Allwinner R40/A40i/T3 System on Chip emulation
3 *
4 * Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qemu/error-report.h"
23 #include "qemu/bswap.h"
24 #include "qemu/module.h"
25 #include "qemu/units.h"
26 #include "hw/qdev-core.h"
27 #include "hw/sysbus.h"
28 #include "hw/char/serial.h"
29 #include "hw/misc/unimp.h"
30 #include "hw/usb/hcd-ehci.h"
31 #include "hw/loader.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/arm/allwinner-r40.h"
34
35 /* Memory map */
36 const hwaddr allwinner_r40_memmap[] = {
37 [AW_R40_DEV_SRAM_A1] = 0x00000000,
38 [AW_R40_DEV_SRAM_A2] = 0x00004000,
39 [AW_R40_DEV_SRAM_A3] = 0x00008000,
40 [AW_R40_DEV_SRAM_A4] = 0x0000b400,
41 [AW_R40_DEV_MMC0] = 0x01c0f000,
42 [AW_R40_DEV_MMC1] = 0x01c10000,
43 [AW_R40_DEV_MMC2] = 0x01c11000,
44 [AW_R40_DEV_MMC3] = 0x01c12000,
45 [AW_R40_DEV_CCU] = 0x01c20000,
46 [AW_R40_DEV_PIT] = 0x01c20c00,
47 [AW_R40_DEV_UART0] = 0x01c28000,
48 [AW_R40_DEV_GIC_DIST] = 0x01c81000,
49 [AW_R40_DEV_GIC_CPU] = 0x01c82000,
50 [AW_R40_DEV_GIC_HYP] = 0x01c84000,
51 [AW_R40_DEV_GIC_VCPU] = 0x01c86000,
52 [AW_R40_DEV_SDRAM] = 0x40000000
53 };
54
55 /* List of unimplemented devices */
56 struct AwR40Unimplemented {
57 const char *device_name;
58 hwaddr base;
59 hwaddr size;
60 };
61
62 static struct AwR40Unimplemented r40_unimplemented[] = {
63 { "d-engine", 0x01000000, 4 * MiB },
64 { "d-inter", 0x01400000, 128 * KiB },
65 { "sram-c", 0x01c00000, 4 * KiB },
66 { "dma", 0x01c02000, 4 * KiB },
67 { "nfdc", 0x01c03000, 4 * KiB },
68 { "ts", 0x01c04000, 4 * KiB },
69 { "spi0", 0x01c05000, 4 * KiB },
70 { "spi1", 0x01c06000, 4 * KiB },
71 { "cs0", 0x01c09000, 4 * KiB },
72 { "keymem", 0x01c0a000, 4 * KiB },
73 { "emac", 0x01c0b000, 4 * KiB },
74 { "usb0-otg", 0x01c13000, 4 * KiB },
75 { "usb0-host", 0x01c14000, 4 * KiB },
76 { "crypto", 0x01c15000, 4 * KiB },
77 { "spi2", 0x01c17000, 4 * KiB },
78 { "sata", 0x01c18000, 4 * KiB },
79 { "usb1-host", 0x01c19000, 4 * KiB },
80 { "sid", 0x01c1b000, 4 * KiB },
81 { "usb2-host", 0x01c1c000, 4 * KiB },
82 { "cs1", 0x01c1d000, 4 * KiB },
83 { "spi3", 0x01c1f000, 4 * KiB },
84 { "rtc", 0x01c20400, 1 * KiB },
85 { "pio", 0x01c20800, 1 * KiB },
86 { "owa", 0x01c21000, 1 * KiB },
87 { "ac97", 0x01c21400, 1 * KiB },
88 { "cir0", 0x01c21800, 1 * KiB },
89 { "cir1", 0x01c21c00, 1 * KiB },
90 { "pcm0", 0x01c22000, 1 * KiB },
91 { "pcm1", 0x01c22400, 1 * KiB },
92 { "pcm2", 0x01c22800, 1 * KiB },
93 { "audio", 0x01c22c00, 1 * KiB },
94 { "keypad", 0x01c23000, 1 * KiB },
95 { "pwm", 0x01c23400, 1 * KiB },
96 { "keyadc", 0x01c24400, 1 * KiB },
97 { "ths", 0x01c24c00, 1 * KiB },
98 { "rtp", 0x01c25000, 1 * KiB },
99 { "pmu", 0x01c25400, 1 * KiB },
100 { "cpu-cfg", 0x01c25c00, 1 * KiB },
101 { "uart0", 0x01c28000, 1 * KiB },
102 { "uart1", 0x01c28400, 1 * KiB },
103 { "uart2", 0x01c28800, 1 * KiB },
104 { "uart3", 0x01c28c00, 1 * KiB },
105 { "uart4", 0x01c29000, 1 * KiB },
106 { "uart5", 0x01c29400, 1 * KiB },
107 { "uart6", 0x01c29800, 1 * KiB },
108 { "uart7", 0x01c29c00, 1 * KiB },
109 { "ps20", 0x01c2a000, 1 * KiB },
110 { "ps21", 0x01c2a400, 1 * KiB },
111 { "twi0", 0x01c2ac00, 1 * KiB },
112 { "twi1", 0x01c2b000, 1 * KiB },
113 { "twi2", 0x01c2b400, 1 * KiB },
114 { "twi3", 0x01c2b800, 1 * KiB },
115 { "twi4", 0x01c2c000, 1 * KiB },
116 { "scr", 0x01c2c400, 1 * KiB },
117 { "tvd-top", 0x01c30000, 4 * KiB },
118 { "tvd0", 0x01c31000, 4 * KiB },
119 { "tvd1", 0x01c32000, 4 * KiB },
120 { "tvd2", 0x01c33000, 4 * KiB },
121 { "tvd3", 0x01c34000, 4 * KiB },
122 { "gpu", 0x01c40000, 64 * KiB },
123 { "gmac", 0x01c50000, 64 * KiB },
124 { "hstmr", 0x01c60000, 4 * KiB },
125 { "dram-com", 0x01c62000, 4 * KiB },
126 { "dram-ctl", 0x01c63000, 4 * KiB },
127 { "tcon-top", 0x01c70000, 4 * KiB },
128 { "lcd0", 0x01c71000, 4 * KiB },
129 { "lcd1", 0x01c72000, 4 * KiB },
130 { "tv0", 0x01c73000, 4 * KiB },
131 { "tv1", 0x01c74000, 4 * KiB },
132 { "tve-top", 0x01c90000, 16 * KiB },
133 { "tve0", 0x01c94000, 16 * KiB },
134 { "tve1", 0x01c98000, 16 * KiB },
135 { "mipi_dsi", 0x01ca0000, 4 * KiB },
136 { "mipi_dphy", 0x01ca1000, 4 * KiB },
137 { "ve", 0x01d00000, 1024 * KiB },
138 { "mp", 0x01e80000, 128 * KiB },
139 { "hdmi", 0x01ee0000, 128 * KiB },
140 { "prcm", 0x01f01400, 1 * KiB },
141 { "debug", 0x3f500000, 64 * KiB },
142 { "cpubist", 0x3f501000, 4 * KiB },
143 { "dcu", 0x3fff0000, 64 * KiB },
144 { "hstmr", 0x01c60000, 4 * KiB },
145 { "brom", 0xffff0000, 36 * KiB }
146 };
147
148 /* Per Processor Interrupts */
149 enum {
150 AW_R40_GIC_PPI_MAINT = 9,
151 AW_R40_GIC_PPI_HYPTIMER = 10,
152 AW_R40_GIC_PPI_VIRTTIMER = 11,
153 AW_R40_GIC_PPI_SECTIMER = 13,
154 AW_R40_GIC_PPI_PHYSTIMER = 14
155 };
156
157 /* Shared Processor Interrupts */
158 enum {
159 AW_R40_GIC_SPI_UART0 = 1,
160 AW_R40_GIC_SPI_TIMER0 = 22,
161 AW_R40_GIC_SPI_TIMER1 = 23,
162 AW_R40_GIC_SPI_MMC0 = 32,
163 AW_R40_GIC_SPI_MMC1 = 33,
164 AW_R40_GIC_SPI_MMC2 = 34,
165 AW_R40_GIC_SPI_MMC3 = 35,
166 };
167
168 /* Allwinner R40 general constants */
169 enum {
170 AW_R40_GIC_NUM_SPI = 128
171 };
172
173 #define BOOT0_MAGIC "eGON.BT0"
174
175 /* The low 8-bits of the 'boot_media' field in the SPL header */
176 #define SUNXI_BOOTED_FROM_MMC0 0
177 #define SUNXI_BOOTED_FROM_NAND 1
178 #define SUNXI_BOOTED_FROM_MMC2 2
179 #define SUNXI_BOOTED_FROM_SPI 3
180
181 struct boot_file_head {
182 uint32_t b_instruction;
183 uint8_t magic[8];
184 uint32_t check_sum;
185 uint32_t length;
186 uint32_t pub_head_size;
187 uint32_t fel_script_address;
188 uint32_t fel_uEnv_length;
189 uint32_t dt_name_offset;
190 uint32_t dram_size;
191 uint32_t boot_media;
192 uint32_t string_pool[13];
193 };
194
195 bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int unit)
196 {
197 const int64_t rom_size = 32 * KiB;
198 g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
199 struct boot_file_head *head = (struct boot_file_head *)buffer;
200
201 if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
202 error_setg(&error_fatal, "%s: failed to read BlockBackend data",
203 __func__);
204 return false;
205 }
206
207 /* we only check the magic string here. */
208 if (memcmp(head->magic, BOOT0_MAGIC, sizeof(head->magic))) {
209 return false;
210 }
211
212 /*
213 * Simulate the behavior of the bootROM, it will change the boot_media
214 * flag to indicate where the chip is booting from. R40 can boot from
215 * mmc0 or mmc2, the default value of boot_media is zero
216 * (SUNXI_BOOTED_FROM_MMC0), let's fix this flag when it is booting from
217 * the others.
218 */
219 if (unit == 2) {
220 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC2);
221 } else {
222 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC0);
223 }
224
225 rom_add_blob("allwinner-r40.bootrom", buffer, rom_size,
226 rom_size, s->memmap[AW_R40_DEV_SRAM_A1],
227 NULL, NULL, NULL, NULL, false);
228 return true;
229 }
230
231 static void allwinner_r40_init(Object *obj)
232 {
233 static const char *mmc_names[AW_R40_NUM_MMCS] = {
234 "mmc0", "mmc1", "mmc2", "mmc3"
235 };
236 AwR40State *s = AW_R40(obj);
237
238 s->memmap = allwinner_r40_memmap;
239
240 for (int i = 0; i < AW_R40_NUM_CPUS; i++) {
241 object_initialize_child(obj, "cpu[*]", &s->cpus[i],
242 ARM_CPU_TYPE_NAME("cortex-a7"));
243 }
244
245 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
246
247 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
248 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
249 "clk0-freq");
250 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
251 "clk1-freq");
252
253 object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_R40_CCU);
254
255 for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
256 object_initialize_child(obj, mmc_names[i], &s->mmc[i],
257 TYPE_AW_SDHOST_SUN5I);
258 }
259 }
260
261 static void allwinner_r40_realize(DeviceState *dev, Error **errp)
262 {
263 AwR40State *s = AW_R40(dev);
264 unsigned i;
265
266 /* CPUs */
267 for (i = 0; i < AW_R40_NUM_CPUS; i++) {
268
269 /*
270 * Disable secondary CPUs. Guest EL3 firmware will start
271 * them via CPU reset control registers.
272 */
273 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
274 i > 0);
275
276 /* All exception levels required */
277 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
278 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
279
280 /* Mark realized */
281 qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal);
282 }
283
284 /* Generic Interrupt Controller */
285 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_R40_GIC_NUM_SPI +
286 GIC_INTERNAL);
287 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
288 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_R40_NUM_CPUS);
289 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
290 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
291 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
292
293 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_R40_DEV_GIC_DIST]);
294 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_R40_DEV_GIC_CPU]);
295 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_R40_DEV_GIC_HYP]);
296 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_R40_DEV_GIC_VCPU]);
297
298 /*
299 * Wire the outputs from each CPU's generic timer and the GICv2
300 * maintenance interrupt signal to the appropriate GIC PPI inputs,
301 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
302 */
303 for (i = 0; i < AW_R40_NUM_CPUS; i++) {
304 DeviceState *cpudev = DEVICE(&s->cpus[i]);
305 int ppibase = AW_R40_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
306 int irq;
307 /*
308 * Mapping from the output timer irq lines from the CPU to the
309 * GIC PPI inputs used for this board.
310 */
311 const int timer_irq[] = {
312 [GTIMER_PHYS] = AW_R40_GIC_PPI_PHYSTIMER,
313 [GTIMER_VIRT] = AW_R40_GIC_PPI_VIRTTIMER,
314 [GTIMER_HYP] = AW_R40_GIC_PPI_HYPTIMER,
315 [GTIMER_SEC] = AW_R40_GIC_PPI_SECTIMER,
316 };
317
318 /* Connect CPU timer outputs to GIC PPI inputs */
319 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
320 qdev_connect_gpio_out(cpudev, irq,
321 qdev_get_gpio_in(DEVICE(&s->gic),
322 ppibase + timer_irq[irq]));
323 }
324
325 /* Connect GIC outputs to CPU interrupt inputs */
326 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
327 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
328 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_R40_NUM_CPUS,
329 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
330 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_R40_NUM_CPUS),
331 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
332 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_R40_NUM_CPUS),
333 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
334
335 /* GIC maintenance signal */
336 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_R40_NUM_CPUS),
337 qdev_get_gpio_in(DEVICE(&s->gic),
338 ppibase + AW_R40_GIC_PPI_MAINT));
339 }
340
341 /* Timer */
342 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
343 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_R40_DEV_PIT]);
344 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
345 qdev_get_gpio_in(DEVICE(&s->gic),
346 AW_R40_GIC_SPI_TIMER0));
347 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
348 qdev_get_gpio_in(DEVICE(&s->gic),
349 AW_R40_GIC_SPI_TIMER1));
350
351 /* SRAM */
352 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
353 16 * KiB, &error_abort);
354 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
355 16 * KiB, &error_abort);
356 memory_region_init_ram(&s->sram_a3, OBJECT(dev), "sram A3",
357 13 * KiB, &error_abort);
358 memory_region_init_ram(&s->sram_a4, OBJECT(dev), "sram A4",
359 3 * KiB, &error_abort);
360 memory_region_add_subregion(get_system_memory(),
361 s->memmap[AW_R40_DEV_SRAM_A1], &s->sram_a1);
362 memory_region_add_subregion(get_system_memory(),
363 s->memmap[AW_R40_DEV_SRAM_A2], &s->sram_a2);
364 memory_region_add_subregion(get_system_memory(),
365 s->memmap[AW_R40_DEV_SRAM_A3], &s->sram_a3);
366 memory_region_add_subregion(get_system_memory(),
367 s->memmap[AW_R40_DEV_SRAM_A4], &s->sram_a4);
368
369 /* Clock Control Unit */
370 sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
371 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]);
372
373 /* SD/MMC */
374 for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
375 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->gic),
376 AW_R40_GIC_SPI_MMC0 + i);
377 const hwaddr addr = s->memmap[AW_R40_DEV_MMC0 + i];
378
379 object_property_set_link(OBJECT(&s->mmc[i]), "dma-memory",
380 OBJECT(get_system_memory()), &error_fatal);
381 sysbus_realize(SYS_BUS_DEVICE(&s->mmc[i]), &error_fatal);
382 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc[i]), 0, addr);
383 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc[i]), 0, irq);
384 }
385
386 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
387 serial_mm_init(get_system_memory(), s->memmap[AW_R40_DEV_UART0], 2,
388 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_UART0),
389 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
390
391 /* Unimplemented devices */
392 for (i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) {
393 create_unimplemented_device(r40_unimplemented[i].device_name,
394 r40_unimplemented[i].base,
395 r40_unimplemented[i].size);
396 }
397 }
398
399 static void allwinner_r40_class_init(ObjectClass *oc, void *data)
400 {
401 DeviceClass *dc = DEVICE_CLASS(oc);
402
403 dc->realize = allwinner_r40_realize;
404 /* Reason: uses serial_hd() in realize function */
405 dc->user_creatable = false;
406 }
407
408 static const TypeInfo allwinner_r40_type_info = {
409 .name = TYPE_AW_R40,
410 .parent = TYPE_DEVICE,
411 .instance_size = sizeof(AwR40State),
412 .instance_init = allwinner_r40_init,
413 .class_init = allwinner_r40_class_init,
414 };
415
416 static void allwinner_r40_register_types(void)
417 {
418 type_register_static(&allwinner_r40_type_info);
419 }
420
421 type_init(allwinner_r40_register_types)
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