2 * Luminary Micro Stellaris peripherals
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/sysbus.h"
13 #include "hw/ssi/ssi.h"
14 #include "hw/arm/arm.h"
15 #include "hw/devices.h"
16 #include "qemu/timer.h"
17 #include "hw/i2c/i2c.h"
19 #include "hw/boards.h"
21 #include "exec/address-spaces.h"
22 #include "sysemu/sysemu.h"
23 #include "hw/char/pl011.h"
24 #include "hw/misc/unimp.h"
34 #define BP_OLED_I2C 0x01
35 #define BP_OLED_SSI 0x02
36 #define BP_GAMEPAD 0x04
38 #define NUM_IRQ_LINES 64
40 typedef const struct {
50 } stellaris_board_info
;
52 /* General purpose timer module. */
54 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
55 #define STELLARIS_GPTM(obj) \
56 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM)
58 typedef struct gptm_state
{
59 SysBusDevice parent_obj
;
70 uint32_t match_prescale
[2];
73 struct gptm_state
*opaque
[2];
75 /* The timers have an alternate output used to trigger the ADC. */
80 static void gptm_update_irq(gptm_state
*s
)
83 level
= (s
->state
& s
->mask
) != 0;
84 qemu_set_irq(s
->irq
, level
);
87 static void gptm_stop(gptm_state
*s
, int n
)
89 timer_del(s
->timer
[n
]);
92 static void gptm_reload(gptm_state
*s
, int n
, int reset
)
96 tick
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
100 if (s
->config
== 0) {
101 /* 32-bit CountDown. */
103 count
= s
->load
[0] | (s
->load
[1] << 16);
104 tick
+= (int64_t)count
* system_clock_scale
;
105 } else if (s
->config
== 1) {
106 /* 32-bit RTC. 1Hz tick. */
107 tick
+= NANOSECONDS_PER_SECOND
;
108 } else if (s
->mode
[n
] == 0xa) {
109 /* PWM mode. Not implemented. */
111 hw_error("TODO: 16-bit timer mode 0x%x\n", s
->mode
[n
]);
114 timer_mod(s
->timer
[n
], tick
);
117 static void gptm_tick(void *opaque
)
119 gptm_state
**p
= (gptm_state
**)opaque
;
125 if (s
->config
== 0) {
127 if ((s
->control
& 0x20)) {
128 /* Output trigger. */
129 qemu_irq_pulse(s
->trigger
);
131 if (s
->mode
[0] & 1) {
136 gptm_reload(s
, 0, 0);
138 } else if (s
->config
== 1) {
142 match
= s
->match
[0] | (s
->match
[1] << 16);
148 gptm_reload(s
, 0, 0);
149 } else if (s
->mode
[n
] == 0xa) {
150 /* PWM mode. Not implemented. */
152 hw_error("TODO: 16-bit timer mode 0x%x\n", s
->mode
[n
]);
157 static uint64_t gptm_read(void *opaque
, hwaddr offset
,
160 gptm_state
*s
= (gptm_state
*)opaque
;
165 case 0x04: /* TAMR */
167 case 0x08: /* TBMR */
176 return s
->state
& s
->mask
;
179 case 0x28: /* TAILR */
180 return s
->load
[0] | ((s
->config
< 4) ? (s
->load
[1] << 16) : 0);
181 case 0x2c: /* TBILR */
183 case 0x30: /* TAMARCHR */
184 return s
->match
[0] | ((s
->config
< 4) ? (s
->match
[1] << 16) : 0);
185 case 0x34: /* TBMATCHR */
187 case 0x38: /* TAPR */
188 return s
->prescale
[0];
189 case 0x3c: /* TBPR */
190 return s
->prescale
[1];
191 case 0x40: /* TAPMR */
192 return s
->match_prescale
[0];
193 case 0x44: /* TBPMR */
194 return s
->match_prescale
[1];
196 if (s
->config
== 1) {
199 qemu_log_mask(LOG_UNIMP
,
200 "GPTM: read of TAR but timer read not supported");
203 qemu_log_mask(LOG_UNIMP
,
204 "GPTM: read of TBR but timer read not supported");
207 qemu_log_mask(LOG_GUEST_ERROR
,
208 "GPTM: read at bad offset 0x%x\n", (int)offset
);
213 static void gptm_write(void *opaque
, hwaddr offset
,
214 uint64_t value
, unsigned size
)
216 gptm_state
*s
= (gptm_state
*)opaque
;
219 /* The timers should be disabled before changing the configuration.
220 We take advantage of this and defer everything until the timer
226 case 0x04: /* TAMR */
229 case 0x08: /* TBMR */
235 /* TODO: Implement pause. */
236 if ((oldval
^ value
) & 1) {
238 gptm_reload(s
, 0, 1);
243 if (((oldval
^ value
) & 0x100) && s
->config
>= 4) {
245 gptm_reload(s
, 1, 1);
252 s
->mask
= value
& 0x77;
258 case 0x28: /* TAILR */
259 s
->load
[0] = value
& 0xffff;
261 s
->load
[1] = value
>> 16;
264 case 0x2c: /* TBILR */
265 s
->load
[1] = value
& 0xffff;
267 case 0x30: /* TAMARCHR */
268 s
->match
[0] = value
& 0xffff;
270 s
->match
[1] = value
>> 16;
273 case 0x34: /* TBMATCHR */
274 s
->match
[1] = value
>> 16;
276 case 0x38: /* TAPR */
277 s
->prescale
[0] = value
;
279 case 0x3c: /* TBPR */
280 s
->prescale
[1] = value
;
282 case 0x40: /* TAPMR */
283 s
->match_prescale
[0] = value
;
285 case 0x44: /* TBPMR */
286 s
->match_prescale
[0] = value
;
289 hw_error("gptm_write: Bad offset 0x%x\n", (int)offset
);
294 static const MemoryRegionOps gptm_ops
= {
297 .endianness
= DEVICE_NATIVE_ENDIAN
,
300 static const VMStateDescription vmstate_stellaris_gptm
= {
301 .name
= "stellaris_gptm",
303 .minimum_version_id
= 1,
304 .fields
= (VMStateField
[]) {
305 VMSTATE_UINT32(config
, gptm_state
),
306 VMSTATE_UINT32_ARRAY(mode
, gptm_state
, 2),
307 VMSTATE_UINT32(control
, gptm_state
),
308 VMSTATE_UINT32(state
, gptm_state
),
309 VMSTATE_UINT32(mask
, gptm_state
),
311 VMSTATE_UINT32_ARRAY(load
, gptm_state
, 2),
312 VMSTATE_UINT32_ARRAY(match
, gptm_state
, 2),
313 VMSTATE_UINT32_ARRAY(prescale
, gptm_state
, 2),
314 VMSTATE_UINT32_ARRAY(match_prescale
, gptm_state
, 2),
315 VMSTATE_UINT32(rtc
, gptm_state
),
316 VMSTATE_INT64_ARRAY(tick
, gptm_state
, 2),
317 VMSTATE_TIMER_PTR_ARRAY(timer
, gptm_state
, 2),
318 VMSTATE_END_OF_LIST()
322 static void stellaris_gptm_init(Object
*obj
)
324 DeviceState
*dev
= DEVICE(obj
);
325 gptm_state
*s
= STELLARIS_GPTM(obj
);
326 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
328 sysbus_init_irq(sbd
, &s
->irq
);
329 qdev_init_gpio_out(dev
, &s
->trigger
, 1);
331 memory_region_init_io(&s
->iomem
, obj
, &gptm_ops
, s
,
333 sysbus_init_mmio(sbd
, &s
->iomem
);
335 s
->opaque
[0] = s
->opaque
[1] = s
;
336 s
->timer
[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL
, gptm_tick
, &s
->opaque
[0]);
337 s
->timer
[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL
, gptm_tick
, &s
->opaque
[1]);
341 /* System controller. */
360 stellaris_board_info
*board
;
363 static void ssys_update(ssys_state
*s
)
365 qemu_set_irq(s
->irq
, (s
->int_status
& s
->int_mask
) != 0);
368 static uint32_t pllcfg_sandstorm
[16] = {
370 0x1ae0, /* 1.8432 Mhz */
372 0xd573, /* 2.4576 Mhz */
373 0x37a6, /* 3.57954 Mhz */
374 0x1ae2, /* 3.6864 Mhz */
376 0x98bc, /* 4.906 Mhz */
377 0x935b, /* 4.9152 Mhz */
379 0x4dee, /* 5.12 Mhz */
381 0x75db, /* 6.144 Mhz */
382 0x1ae6, /* 7.3728 Mhz */
384 0x585b /* 8.192 Mhz */
387 static uint32_t pllcfg_fury
[16] = {
389 0x1b20, /* 1.8432 Mhz */
391 0xf42b, /* 2.4576 Mhz */
392 0x37e3, /* 3.57954 Mhz */
393 0x1b21, /* 3.6864 Mhz */
395 0x98ee, /* 4.906 Mhz */
396 0xd5b4, /* 4.9152 Mhz */
398 0x4e27, /* 5.12 Mhz */
400 0xec1c, /* 6.144 Mhz */
401 0x1b23, /* 7.3728 Mhz */
403 0xb11c /* 8.192 Mhz */
406 #define DID0_VER_MASK 0x70000000
407 #define DID0_VER_0 0x00000000
408 #define DID0_VER_1 0x10000000
410 #define DID0_CLASS_MASK 0x00FF0000
411 #define DID0_CLASS_SANDSTORM 0x00000000
412 #define DID0_CLASS_FURY 0x00010000
414 static int ssys_board_class(const ssys_state
*s
)
416 uint32_t did0
= s
->board
->did0
;
417 switch (did0
& DID0_VER_MASK
) {
419 return DID0_CLASS_SANDSTORM
;
421 switch (did0
& DID0_CLASS_MASK
) {
422 case DID0_CLASS_SANDSTORM
:
423 case DID0_CLASS_FURY
:
424 return did0
& DID0_CLASS_MASK
;
426 /* for unknown classes, fall through */
428 hw_error("ssys_board_class: Unknown class 0x%08x\n", did0
);
432 static uint64_t ssys_read(void *opaque
, hwaddr offset
,
435 ssys_state
*s
= (ssys_state
*)opaque
;
438 case 0x000: /* DID0 */
439 return s
->board
->did0
;
440 case 0x004: /* DID1 */
441 return s
->board
->did1
;
442 case 0x008: /* DC0 */
443 return s
->board
->dc0
;
444 case 0x010: /* DC1 */
445 return s
->board
->dc1
;
446 case 0x014: /* DC2 */
447 return s
->board
->dc2
;
448 case 0x018: /* DC3 */
449 return s
->board
->dc3
;
450 case 0x01c: /* DC4 */
451 return s
->board
->dc4
;
452 case 0x030: /* PBORCTL */
454 case 0x034: /* LDOPCTL */
456 case 0x040: /* SRCR0 */
458 case 0x044: /* SRCR1 */
460 case 0x048: /* SRCR2 */
462 case 0x050: /* RIS */
463 return s
->int_status
;
464 case 0x054: /* IMC */
466 case 0x058: /* MISC */
467 return s
->int_status
& s
->int_mask
;
468 case 0x05c: /* RESC */
470 case 0x060: /* RCC */
472 case 0x064: /* PLLCFG */
475 xtal
= (s
->rcc
>> 6) & 0xf;
476 switch (ssys_board_class(s
)) {
477 case DID0_CLASS_FURY
:
478 return pllcfg_fury
[xtal
];
479 case DID0_CLASS_SANDSTORM
:
480 return pllcfg_sandstorm
[xtal
];
482 hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
486 case 0x070: /* RCC2 */
488 case 0x100: /* RCGC0 */
490 case 0x104: /* RCGC1 */
492 case 0x108: /* RCGC2 */
494 case 0x110: /* SCGC0 */
496 case 0x114: /* SCGC1 */
498 case 0x118: /* SCGC2 */
500 case 0x120: /* DCGC0 */
502 case 0x124: /* DCGC1 */
504 case 0x128: /* DCGC2 */
506 case 0x150: /* CLKVCLR */
508 case 0x160: /* LDOARST */
510 case 0x1e0: /* USER0 */
512 case 0x1e4: /* USER1 */
515 hw_error("ssys_read: Bad offset 0x%x\n", (int)offset
);
520 static bool ssys_use_rcc2(ssys_state
*s
)
522 return (s
->rcc2
>> 31) & 0x1;
526 * Caculate the sys. clock period in ms.
528 static void ssys_calculate_system_clock(ssys_state
*s
)
530 if (ssys_use_rcc2(s
)) {
531 system_clock_scale
= 5 * (((s
->rcc2
>> 23) & 0x3f) + 1);
533 system_clock_scale
= 5 * (((s
->rcc
>> 23) & 0xf) + 1);
537 static void ssys_write(void *opaque
, hwaddr offset
,
538 uint64_t value
, unsigned size
)
540 ssys_state
*s
= (ssys_state
*)opaque
;
543 case 0x030: /* PBORCTL */
544 s
->pborctl
= value
& 0xffff;
546 case 0x034: /* LDOPCTL */
547 s
->ldopctl
= value
& 0x1f;
549 case 0x040: /* SRCR0 */
550 case 0x044: /* SRCR1 */
551 case 0x048: /* SRCR2 */
552 fprintf(stderr
, "Peripheral reset not implemented\n");
554 case 0x054: /* IMC */
555 s
->int_mask
= value
& 0x7f;
557 case 0x058: /* MISC */
558 s
->int_status
&= ~value
;
560 case 0x05c: /* RESC */
561 s
->resc
= value
& 0x3f;
563 case 0x060: /* RCC */
564 if ((s
->rcc
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
566 s
->int_status
|= (1 << 6);
569 ssys_calculate_system_clock(s
);
571 case 0x070: /* RCC2 */
572 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
576 if ((s
->rcc2
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
578 s
->int_status
|= (1 << 6);
581 ssys_calculate_system_clock(s
);
583 case 0x100: /* RCGC0 */
586 case 0x104: /* RCGC1 */
589 case 0x108: /* RCGC2 */
592 case 0x110: /* SCGC0 */
595 case 0x114: /* SCGC1 */
598 case 0x118: /* SCGC2 */
601 case 0x120: /* DCGC0 */
604 case 0x124: /* DCGC1 */
607 case 0x128: /* DCGC2 */
610 case 0x150: /* CLKVCLR */
613 case 0x160: /* LDOARST */
617 hw_error("ssys_write: Bad offset 0x%x\n", (int)offset
);
622 static const MemoryRegionOps ssys_ops
= {
625 .endianness
= DEVICE_NATIVE_ENDIAN
,
628 static void ssys_reset(void *opaque
)
630 ssys_state
*s
= (ssys_state
*)opaque
;
635 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
638 s
->rcc2
= 0x07802810;
643 ssys_calculate_system_clock(s
);
646 static int stellaris_sys_post_load(void *opaque
, int version_id
)
648 ssys_state
*s
= opaque
;
650 ssys_calculate_system_clock(s
);
655 static const VMStateDescription vmstate_stellaris_sys
= {
656 .name
= "stellaris_sys",
658 .minimum_version_id
= 1,
659 .post_load
= stellaris_sys_post_load
,
660 .fields
= (VMStateField
[]) {
661 VMSTATE_UINT32(pborctl
, ssys_state
),
662 VMSTATE_UINT32(ldopctl
, ssys_state
),
663 VMSTATE_UINT32(int_mask
, ssys_state
),
664 VMSTATE_UINT32(int_status
, ssys_state
),
665 VMSTATE_UINT32(resc
, ssys_state
),
666 VMSTATE_UINT32(rcc
, ssys_state
),
667 VMSTATE_UINT32_V(rcc2
, ssys_state
, 2),
668 VMSTATE_UINT32_ARRAY(rcgc
, ssys_state
, 3),
669 VMSTATE_UINT32_ARRAY(scgc
, ssys_state
, 3),
670 VMSTATE_UINT32_ARRAY(dcgc
, ssys_state
, 3),
671 VMSTATE_UINT32(clkvclr
, ssys_state
),
672 VMSTATE_UINT32(ldoarst
, ssys_state
),
673 VMSTATE_END_OF_LIST()
677 static int stellaris_sys_init(uint32_t base
, qemu_irq irq
,
678 stellaris_board_info
* board
,
683 s
= g_new0(ssys_state
, 1);
686 /* Most devices come preprogrammed with a MAC address in the user data. */
687 s
->user0
= macaddr
[0] | (macaddr
[1] << 8) | (macaddr
[2] << 16);
688 s
->user1
= macaddr
[3] | (macaddr
[4] << 8) | (macaddr
[5] << 16);
690 memory_region_init_io(&s
->iomem
, NULL
, &ssys_ops
, s
, "ssys", 0x00001000);
691 memory_region_add_subregion(get_system_memory(), base
, &s
->iomem
);
693 vmstate_register(NULL
, -1, &vmstate_stellaris_sys
, s
);
698 /* I2C controller. */
700 #define TYPE_STELLARIS_I2C "stellaris-i2c"
701 #define STELLARIS_I2C(obj) \
702 OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C)
705 SysBusDevice parent_obj
;
717 } stellaris_i2c_state
;
719 #define STELLARIS_I2C_MCS_BUSY 0x01
720 #define STELLARIS_I2C_MCS_ERROR 0x02
721 #define STELLARIS_I2C_MCS_ADRACK 0x04
722 #define STELLARIS_I2C_MCS_DATACK 0x08
723 #define STELLARIS_I2C_MCS_ARBLST 0x10
724 #define STELLARIS_I2C_MCS_IDLE 0x20
725 #define STELLARIS_I2C_MCS_BUSBSY 0x40
727 static uint64_t stellaris_i2c_read(void *opaque
, hwaddr offset
,
730 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
736 /* We don't emulate timing, so the controller is never busy. */
737 return s
->mcs
| STELLARIS_I2C_MCS_IDLE
;
740 case 0x0c: /* MTPR */
742 case 0x10: /* MIMR */
744 case 0x14: /* MRIS */
746 case 0x18: /* MMIS */
747 return s
->mris
& s
->mimr
;
751 hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset
);
756 static void stellaris_i2c_update(stellaris_i2c_state
*s
)
760 level
= (s
->mris
& s
->mimr
) != 0;
761 qemu_set_irq(s
->irq
, level
);
764 static void stellaris_i2c_write(void *opaque
, hwaddr offset
,
765 uint64_t value
, unsigned size
)
767 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
771 s
->msa
= value
& 0xff;
774 if ((s
->mcr
& 0x10) == 0) {
775 /* Disabled. Do nothing. */
778 /* Grab the bus if this is starting a transfer. */
779 if ((value
& 2) && (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
780 if (i2c_start_transfer(s
->bus
, s
->msa
>> 1, s
->msa
& 1)) {
781 s
->mcs
|= STELLARIS_I2C_MCS_ARBLST
;
783 s
->mcs
&= ~STELLARIS_I2C_MCS_ARBLST
;
784 s
->mcs
|= STELLARIS_I2C_MCS_BUSBSY
;
787 /* If we don't have the bus then indicate an error. */
788 if (!i2c_bus_busy(s
->bus
)
789 || (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
790 s
->mcs
|= STELLARIS_I2C_MCS_ERROR
;
793 s
->mcs
&= ~STELLARIS_I2C_MCS_ERROR
;
795 /* Transfer a byte. */
796 /* TODO: Handle errors. */
799 s
->mdr
= i2c_recv(s
->bus
) & 0xff;
802 i2c_send(s
->bus
, s
->mdr
);
804 /* Raise an interrupt. */
808 /* Finish transfer. */
809 i2c_end_transfer(s
->bus
);
810 s
->mcs
&= ~STELLARIS_I2C_MCS_BUSBSY
;
814 s
->mdr
= value
& 0xff;
816 case 0x0c: /* MTPR */
817 s
->mtpr
= value
& 0xff;
819 case 0x10: /* MIMR */
822 case 0x1c: /* MICR */
828 "stellaris_i2c_write: Loopback not implemented\n");
831 "stellaris_i2c_write: Slave mode not implemented\n");
832 s
->mcr
= value
& 0x31;
835 hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
838 stellaris_i2c_update(s
);
841 static void stellaris_i2c_reset(stellaris_i2c_state
*s
)
843 if (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
)
844 i2c_end_transfer(s
->bus
);
853 stellaris_i2c_update(s
);
856 static const MemoryRegionOps stellaris_i2c_ops
= {
857 .read
= stellaris_i2c_read
,
858 .write
= stellaris_i2c_write
,
859 .endianness
= DEVICE_NATIVE_ENDIAN
,
862 static const VMStateDescription vmstate_stellaris_i2c
= {
863 .name
= "stellaris_i2c",
865 .minimum_version_id
= 1,
866 .fields
= (VMStateField
[]) {
867 VMSTATE_UINT32(msa
, stellaris_i2c_state
),
868 VMSTATE_UINT32(mcs
, stellaris_i2c_state
),
869 VMSTATE_UINT32(mdr
, stellaris_i2c_state
),
870 VMSTATE_UINT32(mtpr
, stellaris_i2c_state
),
871 VMSTATE_UINT32(mimr
, stellaris_i2c_state
),
872 VMSTATE_UINT32(mris
, stellaris_i2c_state
),
873 VMSTATE_UINT32(mcr
, stellaris_i2c_state
),
874 VMSTATE_END_OF_LIST()
878 static void stellaris_i2c_init(Object
*obj
)
880 DeviceState
*dev
= DEVICE(obj
);
881 stellaris_i2c_state
*s
= STELLARIS_I2C(obj
);
882 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
885 sysbus_init_irq(sbd
, &s
->irq
);
886 bus
= i2c_init_bus(dev
, "i2c");
889 memory_region_init_io(&s
->iomem
, obj
, &stellaris_i2c_ops
, s
,
891 sysbus_init_mmio(sbd
, &s
->iomem
);
892 /* ??? For now we only implement the master interface. */
893 stellaris_i2c_reset(s
);
896 /* Analogue to Digital Converter. This is only partially implemented,
897 enough for applications that use a combined ADC and timer tick. */
899 #define STELLARIS_ADC_EM_CONTROLLER 0
900 #define STELLARIS_ADC_EM_COMP 1
901 #define STELLARIS_ADC_EM_EXTERNAL 4
902 #define STELLARIS_ADC_EM_TIMER 5
903 #define STELLARIS_ADC_EM_PWM0 6
904 #define STELLARIS_ADC_EM_PWM1 7
905 #define STELLARIS_ADC_EM_PWM2 8
907 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
908 #define STELLARIS_ADC_FIFO_FULL 0x1000
910 #define TYPE_STELLARIS_ADC "stellaris-adc"
911 #define STELLARIS_ADC(obj) \
912 OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC)
914 typedef struct StellarisADCState
{
915 SysBusDevice parent_obj
;
934 } stellaris_adc_state
;
936 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state
*s
, int n
)
940 tail
= s
->fifo
[n
].state
& 0xf;
941 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_EMPTY
) {
944 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf) | ((tail
+ 1) & 0xf);
945 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_FULL
;
946 if (tail
+ 1 == ((s
->fifo
[n
].state
>> 4) & 0xf))
947 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_EMPTY
;
949 return s
->fifo
[n
].data
[tail
];
952 static void stellaris_adc_fifo_write(stellaris_adc_state
*s
, int n
,
957 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
958 FIFO fir each sequencer. */
959 head
= (s
->fifo
[n
].state
>> 4) & 0xf;
960 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_FULL
) {
964 s
->fifo
[n
].data
[head
] = value
;
965 head
= (head
+ 1) & 0xf;
966 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_EMPTY
;
967 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf0) | (head
<< 4);
968 if ((s
->fifo
[n
].state
& 0xf) == head
)
969 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_FULL
;
972 static void stellaris_adc_update(stellaris_adc_state
*s
)
977 for (n
= 0; n
< 4; n
++) {
978 level
= (s
->ris
& s
->im
& (1 << n
)) != 0;
979 qemu_set_irq(s
->irq
[n
], level
);
983 static void stellaris_adc_trigger(void *opaque
, int irq
, int level
)
985 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
988 for (n
= 0; n
< 4; n
++) {
989 if ((s
->actss
& (1 << n
)) == 0) {
993 if (((s
->emux
>> (n
* 4)) & 0xff) != 5) {
997 /* Some applications use the ADC as a random number source, so introduce
998 some variation into the signal. */
999 s
->noise
= s
->noise
* 314159 + 1;
1000 /* ??? actual inputs not implemented. Return an arbitrary value. */
1001 stellaris_adc_fifo_write(s
, n
, 0x200 + ((s
->noise
>> 16) & 7));
1003 stellaris_adc_update(s
);
1007 static void stellaris_adc_reset(stellaris_adc_state
*s
)
1011 for (n
= 0; n
< 4; n
++) {
1014 s
->fifo
[n
].state
= STELLARIS_ADC_FIFO_EMPTY
;
1018 static uint64_t stellaris_adc_read(void *opaque
, hwaddr offset
,
1021 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1023 /* TODO: Implement this. */
1024 if (offset
>= 0x40 && offset
< 0xc0) {
1026 n
= (offset
- 0x40) >> 5;
1027 switch (offset
& 0x1f) {
1028 case 0x00: /* SSMUX */
1030 case 0x04: /* SSCTL */
1032 case 0x08: /* SSFIFO */
1033 return stellaris_adc_fifo_read(s
, n
);
1034 case 0x0c: /* SSFSTAT */
1035 return s
->fifo
[n
].state
;
1041 case 0x00: /* ACTSS */
1043 case 0x04: /* RIS */
1047 case 0x0c: /* ISC */
1048 return s
->ris
& s
->im
;
1049 case 0x10: /* OSTAT */
1051 case 0x14: /* EMUX */
1053 case 0x18: /* USTAT */
1055 case 0x20: /* SSPRI */
1057 case 0x30: /* SAC */
1060 hw_error("strllaris_adc_read: Bad offset 0x%x\n",
1066 static void stellaris_adc_write(void *opaque
, hwaddr offset
,
1067 uint64_t value
, unsigned size
)
1069 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1071 /* TODO: Implement this. */
1072 if (offset
>= 0x40 && offset
< 0xc0) {
1074 n
= (offset
- 0x40) >> 5;
1075 switch (offset
& 0x1f) {
1076 case 0x00: /* SSMUX */
1077 s
->ssmux
[n
] = value
& 0x33333333;
1079 case 0x04: /* SSCTL */
1081 hw_error("ADC: Unimplemented sequence %" PRIx64
"\n",
1084 s
->ssctl
[n
] = value
;
1091 case 0x00: /* ACTSS */
1092 s
->actss
= value
& 0xf;
1097 case 0x0c: /* ISC */
1100 case 0x10: /* OSTAT */
1103 case 0x14: /* EMUX */
1106 case 0x18: /* USTAT */
1109 case 0x20: /* SSPRI */
1112 case 0x28: /* PSSI */
1113 hw_error("Not implemented: ADC sample initiate\n");
1115 case 0x30: /* SAC */
1119 hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset
);
1121 stellaris_adc_update(s
);
1124 static const MemoryRegionOps stellaris_adc_ops
= {
1125 .read
= stellaris_adc_read
,
1126 .write
= stellaris_adc_write
,
1127 .endianness
= DEVICE_NATIVE_ENDIAN
,
1130 static const VMStateDescription vmstate_stellaris_adc
= {
1131 .name
= "stellaris_adc",
1133 .minimum_version_id
= 1,
1134 .fields
= (VMStateField
[]) {
1135 VMSTATE_UINT32(actss
, stellaris_adc_state
),
1136 VMSTATE_UINT32(ris
, stellaris_adc_state
),
1137 VMSTATE_UINT32(im
, stellaris_adc_state
),
1138 VMSTATE_UINT32(emux
, stellaris_adc_state
),
1139 VMSTATE_UINT32(ostat
, stellaris_adc_state
),
1140 VMSTATE_UINT32(ustat
, stellaris_adc_state
),
1141 VMSTATE_UINT32(sspri
, stellaris_adc_state
),
1142 VMSTATE_UINT32(sac
, stellaris_adc_state
),
1143 VMSTATE_UINT32(fifo
[0].state
, stellaris_adc_state
),
1144 VMSTATE_UINT32_ARRAY(fifo
[0].data
, stellaris_adc_state
, 16),
1145 VMSTATE_UINT32(ssmux
[0], stellaris_adc_state
),
1146 VMSTATE_UINT32(ssctl
[0], stellaris_adc_state
),
1147 VMSTATE_UINT32(fifo
[1].state
, stellaris_adc_state
),
1148 VMSTATE_UINT32_ARRAY(fifo
[1].data
, stellaris_adc_state
, 16),
1149 VMSTATE_UINT32(ssmux
[1], stellaris_adc_state
),
1150 VMSTATE_UINT32(ssctl
[1], stellaris_adc_state
),
1151 VMSTATE_UINT32(fifo
[2].state
, stellaris_adc_state
),
1152 VMSTATE_UINT32_ARRAY(fifo
[2].data
, stellaris_adc_state
, 16),
1153 VMSTATE_UINT32(ssmux
[2], stellaris_adc_state
),
1154 VMSTATE_UINT32(ssctl
[2], stellaris_adc_state
),
1155 VMSTATE_UINT32(fifo
[3].state
, stellaris_adc_state
),
1156 VMSTATE_UINT32_ARRAY(fifo
[3].data
, stellaris_adc_state
, 16),
1157 VMSTATE_UINT32(ssmux
[3], stellaris_adc_state
),
1158 VMSTATE_UINT32(ssctl
[3], stellaris_adc_state
),
1159 VMSTATE_UINT32(noise
, stellaris_adc_state
),
1160 VMSTATE_END_OF_LIST()
1164 static void stellaris_adc_init(Object
*obj
)
1166 DeviceState
*dev
= DEVICE(obj
);
1167 stellaris_adc_state
*s
= STELLARIS_ADC(obj
);
1168 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1171 for (n
= 0; n
< 4; n
++) {
1172 sysbus_init_irq(sbd
, &s
->irq
[n
]);
1175 memory_region_init_io(&s
->iomem
, obj
, &stellaris_adc_ops
, s
,
1177 sysbus_init_mmio(sbd
, &s
->iomem
);
1178 stellaris_adc_reset(s
);
1179 qdev_init_gpio_in(dev
, stellaris_adc_trigger
, 1);
1183 void do_sys_reset(void *opaque
, int n
, int level
)
1186 qemu_system_reset_request();
1191 static stellaris_board_info stellaris_boards
[] = {
1195 0x001f001f, /* dc0 */
1205 0x00ff007f, /* dc0 */
1210 BP_OLED_SSI
| BP_GAMEPAD
1214 static void stellaris_init(const char *kernel_filename
, const char *cpu_model
,
1215 stellaris_board_info
*board
)
1217 static const int uart_irq
[] = {5, 6, 33, 34};
1218 static const int timer_irq
[] = {19, 21, 23, 35};
1219 static const uint32_t gpio_addr
[7] =
1220 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1221 0x40024000, 0x40025000, 0x40026000};
1222 static const int gpio_irq
[7] = {0, 1, 2, 3, 4, 30, 31};
1224 /* Memory map of SoC devices, from
1225 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
1226 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
1228 * 40000000 wdtimer (unimplemented)
1229 * 40002000 i2c (unimplemented)
1239 * 40021000 i2c (unimplemented)
1243 * 40028000 PWM (unimplemented)
1244 * 4002c000 QEI (unimplemented)
1245 * 4002d000 QEI (unimplemented)
1251 * 4003c000 analogue comparator (unimplemented)
1253 * 400fc000 hibernation module (unimplemented)
1254 * 400fd000 flash memory control (unimplemented)
1255 * 400fe000 system control
1258 DeviceState
*gpio_dev
[7], *nvic
;
1259 qemu_irq gpio_in
[7][8];
1260 qemu_irq gpio_out
[7][8];
1269 MemoryRegion
*sram
= g_new(MemoryRegion
, 1);
1270 MemoryRegion
*flash
= g_new(MemoryRegion
, 1);
1271 MemoryRegion
*system_memory
= get_system_memory();
1273 flash_size
= (((board
->dc0
& 0xffff) + 1) << 1) * 1024;
1274 sram_size
= ((board
->dc0
>> 18) + 1) * 1024;
1276 /* Flash programming is done via the SCU, so pretend it is ROM. */
1277 memory_region_init_ram(flash
, NULL
, "stellaris.flash", flash_size
,
1279 vmstate_register_ram_global(flash
);
1280 memory_region_set_readonly(flash
, true);
1281 memory_region_add_subregion(system_memory
, 0, flash
);
1283 memory_region_init_ram(sram
, NULL
, "stellaris.sram", sram_size
,
1285 vmstate_register_ram_global(sram
);
1286 memory_region_add_subregion(system_memory
, 0x20000000, sram
);
1288 nvic
= armv7m_init(system_memory
, flash_size
, NUM_IRQ_LINES
,
1289 kernel_filename
, cpu_model
);
1291 qdev_connect_gpio_out_named(nvic
, "SYSRESETREQ", 0,
1292 qemu_allocate_irq(&do_sys_reset
, NULL
, 0));
1294 if (board
->dc1
& (1 << 16)) {
1295 dev
= sysbus_create_varargs(TYPE_STELLARIS_ADC
, 0x40038000,
1296 qdev_get_gpio_in(nvic
, 14),
1297 qdev_get_gpio_in(nvic
, 15),
1298 qdev_get_gpio_in(nvic
, 16),
1299 qdev_get_gpio_in(nvic
, 17),
1301 adc
= qdev_get_gpio_in(dev
, 0);
1305 for (i
= 0; i
< 4; i
++) {
1306 if (board
->dc2
& (0x10000 << i
)) {
1307 dev
= sysbus_create_simple(TYPE_STELLARIS_GPTM
,
1308 0x40030000 + i
* 0x1000,
1309 qdev_get_gpio_in(nvic
, timer_irq
[i
]));
1310 /* TODO: This is incorrect, but we get away with it because
1311 the ADC output is only ever pulsed. */
1312 qdev_connect_gpio_out(dev
, 0, adc
);
1316 stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic
, 28),
1317 board
, nd_table
[0].macaddr
.a
);
1319 for (i
= 0; i
< 7; i
++) {
1320 if (board
->dc4
& (1 << i
)) {
1321 gpio_dev
[i
] = sysbus_create_simple("pl061_luminary", gpio_addr
[i
],
1322 qdev_get_gpio_in(nvic
,
1324 for (j
= 0; j
< 8; j
++) {
1325 gpio_in
[i
][j
] = qdev_get_gpio_in(gpio_dev
[i
], j
);
1326 gpio_out
[i
][j
] = NULL
;
1331 if (board
->dc2
& (1 << 12)) {
1332 dev
= sysbus_create_simple(TYPE_STELLARIS_I2C
, 0x40020000,
1333 qdev_get_gpio_in(nvic
, 8));
1334 i2c
= (I2CBus
*)qdev_get_child_bus(dev
, "i2c");
1335 if (board
->peripherals
& BP_OLED_I2C
) {
1336 i2c_create_slave(i2c
, "ssd0303", 0x3d);
1340 for (i
= 0; i
< 4; i
++) {
1341 if (board
->dc2
& (1 << i
)) {
1342 pl011_luminary_create(0x4000c000 + i
* 0x1000,
1343 qdev_get_gpio_in(nvic
, uart_irq
[i
]),
1347 if (board
->dc2
& (1 << 4)) {
1348 dev
= sysbus_create_simple("pl022", 0x40008000,
1349 qdev_get_gpio_in(nvic
, 7));
1350 if (board
->peripherals
& BP_OLED_SSI
) {
1353 DeviceState
*ssddev
;
1355 /* Some boards have both an OLED controller and SD card connected to
1356 * the same SSI port, with the SD card chip select connected to a
1357 * GPIO pin. Technically the OLED chip select is connected to the
1358 * SSI Fss pin. We do not bother emulating that as both devices
1359 * should never be selected simultaneously, and our OLED controller
1360 * ignores stray 0xff commands that occur when deselecting the SD
1363 bus
= qdev_get_child_bus(dev
, "ssi");
1365 sddev
= ssi_create_slave(bus
, "ssi-sd");
1366 ssddev
= ssi_create_slave(bus
, "ssd0323");
1367 gpio_out
[GPIO_D
][0] = qemu_irq_split(
1368 qdev_get_gpio_in_named(sddev
, SSI_GPIO_CS
, 0),
1369 qdev_get_gpio_in_named(ssddev
, SSI_GPIO_CS
, 0));
1370 gpio_out
[GPIO_C
][7] = qdev_get_gpio_in(ssddev
, 0);
1372 /* Make sure the select pin is high. */
1373 qemu_irq_raise(gpio_out
[GPIO_D
][0]);
1376 if (board
->dc4
& (1 << 28)) {
1379 qemu_check_nic_model(&nd_table
[0], "stellaris");
1381 enet
= qdev_create(NULL
, "stellaris_enet");
1382 qdev_set_nic_properties(enet
, &nd_table
[0]);
1383 qdev_init_nofail(enet
);
1384 sysbus_mmio_map(SYS_BUS_DEVICE(enet
), 0, 0x40048000);
1385 sysbus_connect_irq(SYS_BUS_DEVICE(enet
), 0, qdev_get_gpio_in(nvic
, 42));
1387 if (board
->peripherals
& BP_GAMEPAD
) {
1388 qemu_irq gpad_irq
[5];
1389 static const int gpad_keycode
[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1391 gpad_irq
[0] = qemu_irq_invert(gpio_in
[GPIO_E
][0]); /* up */
1392 gpad_irq
[1] = qemu_irq_invert(gpio_in
[GPIO_E
][1]); /* down */
1393 gpad_irq
[2] = qemu_irq_invert(gpio_in
[GPIO_E
][2]); /* left */
1394 gpad_irq
[3] = qemu_irq_invert(gpio_in
[GPIO_E
][3]); /* right */
1395 gpad_irq
[4] = qemu_irq_invert(gpio_in
[GPIO_F
][1]); /* select */
1397 stellaris_gamepad_init(5, gpad_irq
, gpad_keycode
);
1399 for (i
= 0; i
< 7; i
++) {
1400 if (board
->dc4
& (1 << i
)) {
1401 for (j
= 0; j
< 8; j
++) {
1402 if (gpio_out
[i
][j
]) {
1403 qdev_connect_gpio_out(gpio_dev
[i
], j
, gpio_out
[i
][j
]);
1409 /* Add dummy regions for the devices we don't implement yet,
1410 * so guest accesses don't cause unlogged crashes.
1412 create_unimplemented_device("wdtimer", 0x40000000, 0x1000);
1413 create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1414 create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1415 create_unimplemented_device("PWM", 0x40028000, 0x1000);
1416 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1417 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1418 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1419 create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1420 create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1423 /* FIXME: Figure out how to generate these from stellaris_boards. */
1424 static void lm3s811evb_init(MachineState
*machine
)
1426 const char *cpu_model
= machine
->cpu_model
;
1427 const char *kernel_filename
= machine
->kernel_filename
;
1428 stellaris_init(kernel_filename
, cpu_model
, &stellaris_boards
[0]);
1431 static void lm3s6965evb_init(MachineState
*machine
)
1433 const char *cpu_model
= machine
->cpu_model
;
1434 const char *kernel_filename
= machine
->kernel_filename
;
1435 stellaris_init(kernel_filename
, cpu_model
, &stellaris_boards
[1]);
1438 static void lm3s811evb_class_init(ObjectClass
*oc
, void *data
)
1440 MachineClass
*mc
= MACHINE_CLASS(oc
);
1442 mc
->desc
= "Stellaris LM3S811EVB";
1443 mc
->init
= lm3s811evb_init
;
1446 static const TypeInfo lm3s811evb_type
= {
1447 .name
= MACHINE_TYPE_NAME("lm3s811evb"),
1448 .parent
= TYPE_MACHINE
,
1449 .class_init
= lm3s811evb_class_init
,
1452 static void lm3s6965evb_class_init(ObjectClass
*oc
, void *data
)
1454 MachineClass
*mc
= MACHINE_CLASS(oc
);
1456 mc
->desc
= "Stellaris LM3S6965EVB";
1457 mc
->init
= lm3s6965evb_init
;
1460 static const TypeInfo lm3s6965evb_type
= {
1461 .name
= MACHINE_TYPE_NAME("lm3s6965evb"),
1462 .parent
= TYPE_MACHINE
,
1463 .class_init
= lm3s6965evb_class_init
,
1466 static void stellaris_machine_init(void)
1468 type_register_static(&lm3s811evb_type
);
1469 type_register_static(&lm3s6965evb_type
);
1472 type_init(stellaris_machine_init
)
1474 static void stellaris_i2c_class_init(ObjectClass
*klass
, void *data
)
1476 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1478 dc
->vmsd
= &vmstate_stellaris_i2c
;
1481 static const TypeInfo stellaris_i2c_info
= {
1482 .name
= TYPE_STELLARIS_I2C
,
1483 .parent
= TYPE_SYS_BUS_DEVICE
,
1484 .instance_size
= sizeof(stellaris_i2c_state
),
1485 .instance_init
= stellaris_i2c_init
,
1486 .class_init
= stellaris_i2c_class_init
,
1489 static void stellaris_gptm_class_init(ObjectClass
*klass
, void *data
)
1491 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1493 dc
->vmsd
= &vmstate_stellaris_gptm
;
1496 static const TypeInfo stellaris_gptm_info
= {
1497 .name
= TYPE_STELLARIS_GPTM
,
1498 .parent
= TYPE_SYS_BUS_DEVICE
,
1499 .instance_size
= sizeof(gptm_state
),
1500 .instance_init
= stellaris_gptm_init
,
1501 .class_init
= stellaris_gptm_class_init
,
1504 static void stellaris_adc_class_init(ObjectClass
*klass
, void *data
)
1506 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1508 dc
->vmsd
= &vmstate_stellaris_adc
;
1511 static const TypeInfo stellaris_adc_info
= {
1512 .name
= TYPE_STELLARIS_ADC
,
1513 .parent
= TYPE_SYS_BUS_DEVICE
,
1514 .instance_size
= sizeof(stellaris_adc_state
),
1515 .instance_init
= stellaris_adc_init
,
1516 .class_init
= stellaris_adc_class_init
,
1519 static void stellaris_register_types(void)
1521 type_register_static(&stellaris_i2c_info
);
1522 type_register_static(&stellaris_gptm_info
);
1523 type_register_static(&stellaris_adc_info
);
1526 type_init(stellaris_register_types
)