2 * Luminary Micro Stellaris peripherals
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/sysbus.h"
13 #include "hw/ssi/ssi.h"
14 #include "hw/arm/arm.h"
15 #include "hw/devices.h"
16 #include "qemu/timer.h"
17 #include "hw/i2c/i2c.h"
19 #include "hw/boards.h"
20 #include "exec/address-spaces.h"
21 #include "sysemu/sysemu.h"
31 #define BP_OLED_I2C 0x01
32 #define BP_OLED_SSI 0x02
33 #define BP_GAMEPAD 0x04
35 #define NUM_IRQ_LINES 64
37 typedef const struct {
47 } stellaris_board_info
;
49 /* General purpose timer module. */
51 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
52 #define STELLARIS_GPTM(obj) \
53 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM)
55 typedef struct gptm_state
{
56 SysBusDevice parent_obj
;
67 uint32_t match_prescale
[2];
70 struct gptm_state
*opaque
[2];
72 /* The timers have an alternate output used to trigger the ADC. */
77 static void gptm_update_irq(gptm_state
*s
)
80 level
= (s
->state
& s
->mask
) != 0;
81 qemu_set_irq(s
->irq
, level
);
84 static void gptm_stop(gptm_state
*s
, int n
)
86 timer_del(s
->timer
[n
]);
89 static void gptm_reload(gptm_state
*s
, int n
, int reset
)
93 tick
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
98 /* 32-bit CountDown. */
100 count
= s
->load
[0] | (s
->load
[1] << 16);
101 tick
+= (int64_t)count
* system_clock_scale
;
102 } else if (s
->config
== 1) {
103 /* 32-bit RTC. 1Hz tick. */
104 tick
+= NANOSECONDS_PER_SECOND
;
105 } else if (s
->mode
[n
] == 0xa) {
106 /* PWM mode. Not implemented. */
108 hw_error("TODO: 16-bit timer mode 0x%x\n", s
->mode
[n
]);
111 timer_mod(s
->timer
[n
], tick
);
114 static void gptm_tick(void *opaque
)
116 gptm_state
**p
= (gptm_state
**)opaque
;
122 if (s
->config
== 0) {
124 if ((s
->control
& 0x20)) {
125 /* Output trigger. */
126 qemu_irq_pulse(s
->trigger
);
128 if (s
->mode
[0] & 1) {
133 gptm_reload(s
, 0, 0);
135 } else if (s
->config
== 1) {
139 match
= s
->match
[0] | (s
->match
[1] << 16);
145 gptm_reload(s
, 0, 0);
146 } else if (s
->mode
[n
] == 0xa) {
147 /* PWM mode. Not implemented. */
149 hw_error("TODO: 16-bit timer mode 0x%x\n", s
->mode
[n
]);
154 static uint64_t gptm_read(void *opaque
, hwaddr offset
,
157 gptm_state
*s
= (gptm_state
*)opaque
;
162 case 0x04: /* TAMR */
164 case 0x08: /* TBMR */
173 return s
->state
& s
->mask
;
176 case 0x28: /* TAILR */
177 return s
->load
[0] | ((s
->config
< 4) ? (s
->load
[1] << 16) : 0);
178 case 0x2c: /* TBILR */
180 case 0x30: /* TAMARCHR */
181 return s
->match
[0] | ((s
->config
< 4) ? (s
->match
[1] << 16) : 0);
182 case 0x34: /* TBMATCHR */
184 case 0x38: /* TAPR */
185 return s
->prescale
[0];
186 case 0x3c: /* TBPR */
187 return s
->prescale
[1];
188 case 0x40: /* TAPMR */
189 return s
->match_prescale
[0];
190 case 0x44: /* TBPMR */
191 return s
->match_prescale
[1];
193 if (s
->config
== 1) {
196 qemu_log_mask(LOG_UNIMP
,
197 "GPTM: read of TAR but timer read not supported");
200 qemu_log_mask(LOG_UNIMP
,
201 "GPTM: read of TBR but timer read not supported");
204 qemu_log_mask(LOG_GUEST_ERROR
,
205 "GPTM: read at bad offset 0x%x\n", (int)offset
);
210 static void gptm_write(void *opaque
, hwaddr offset
,
211 uint64_t value
, unsigned size
)
213 gptm_state
*s
= (gptm_state
*)opaque
;
216 /* The timers should be disabled before changing the configuration.
217 We take advantage of this and defer everything until the timer
223 case 0x04: /* TAMR */
226 case 0x08: /* TBMR */
232 /* TODO: Implement pause. */
233 if ((oldval
^ value
) & 1) {
235 gptm_reload(s
, 0, 1);
240 if (((oldval
^ value
) & 0x100) && s
->config
>= 4) {
242 gptm_reload(s
, 1, 1);
249 s
->mask
= value
& 0x77;
255 case 0x28: /* TAILR */
256 s
->load
[0] = value
& 0xffff;
258 s
->load
[1] = value
>> 16;
261 case 0x2c: /* TBILR */
262 s
->load
[1] = value
& 0xffff;
264 case 0x30: /* TAMARCHR */
265 s
->match
[0] = value
& 0xffff;
267 s
->match
[1] = value
>> 16;
270 case 0x34: /* TBMATCHR */
271 s
->match
[1] = value
>> 16;
273 case 0x38: /* TAPR */
274 s
->prescale
[0] = value
;
276 case 0x3c: /* TBPR */
277 s
->prescale
[1] = value
;
279 case 0x40: /* TAPMR */
280 s
->match_prescale
[0] = value
;
282 case 0x44: /* TBPMR */
283 s
->match_prescale
[0] = value
;
286 hw_error("gptm_write: Bad offset 0x%x\n", (int)offset
);
291 static const MemoryRegionOps gptm_ops
= {
294 .endianness
= DEVICE_NATIVE_ENDIAN
,
297 static const VMStateDescription vmstate_stellaris_gptm
= {
298 .name
= "stellaris_gptm",
300 .minimum_version_id
= 1,
301 .fields
= (VMStateField
[]) {
302 VMSTATE_UINT32(config
, gptm_state
),
303 VMSTATE_UINT32_ARRAY(mode
, gptm_state
, 2),
304 VMSTATE_UINT32(control
, gptm_state
),
305 VMSTATE_UINT32(state
, gptm_state
),
306 VMSTATE_UINT32(mask
, gptm_state
),
308 VMSTATE_UINT32_ARRAY(load
, gptm_state
, 2),
309 VMSTATE_UINT32_ARRAY(match
, gptm_state
, 2),
310 VMSTATE_UINT32_ARRAY(prescale
, gptm_state
, 2),
311 VMSTATE_UINT32_ARRAY(match_prescale
, gptm_state
, 2),
312 VMSTATE_UINT32(rtc
, gptm_state
),
313 VMSTATE_INT64_ARRAY(tick
, gptm_state
, 2),
314 VMSTATE_TIMER_PTR_ARRAY(timer
, gptm_state
, 2),
315 VMSTATE_END_OF_LIST()
319 static int stellaris_gptm_init(SysBusDevice
*sbd
)
321 DeviceState
*dev
= DEVICE(sbd
);
322 gptm_state
*s
= STELLARIS_GPTM(dev
);
324 sysbus_init_irq(sbd
, &s
->irq
);
325 qdev_init_gpio_out(dev
, &s
->trigger
, 1);
327 memory_region_init_io(&s
->iomem
, OBJECT(s
), &gptm_ops
, s
,
329 sysbus_init_mmio(sbd
, &s
->iomem
);
331 s
->opaque
[0] = s
->opaque
[1] = s
;
332 s
->timer
[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL
, gptm_tick
, &s
->opaque
[0]);
333 s
->timer
[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL
, gptm_tick
, &s
->opaque
[1]);
334 vmstate_register(dev
, -1, &vmstate_stellaris_gptm
, s
);
339 /* System controller. */
358 stellaris_board_info
*board
;
361 static void ssys_update(ssys_state
*s
)
363 qemu_set_irq(s
->irq
, (s
->int_status
& s
->int_mask
) != 0);
366 static uint32_t pllcfg_sandstorm
[16] = {
368 0x1ae0, /* 1.8432 Mhz */
370 0xd573, /* 2.4576 Mhz */
371 0x37a6, /* 3.57954 Mhz */
372 0x1ae2, /* 3.6864 Mhz */
374 0x98bc, /* 4.906 Mhz */
375 0x935b, /* 4.9152 Mhz */
377 0x4dee, /* 5.12 Mhz */
379 0x75db, /* 6.144 Mhz */
380 0x1ae6, /* 7.3728 Mhz */
382 0x585b /* 8.192 Mhz */
385 static uint32_t pllcfg_fury
[16] = {
387 0x1b20, /* 1.8432 Mhz */
389 0xf42b, /* 2.4576 Mhz */
390 0x37e3, /* 3.57954 Mhz */
391 0x1b21, /* 3.6864 Mhz */
393 0x98ee, /* 4.906 Mhz */
394 0xd5b4, /* 4.9152 Mhz */
396 0x4e27, /* 5.12 Mhz */
398 0xec1c, /* 6.144 Mhz */
399 0x1b23, /* 7.3728 Mhz */
401 0xb11c /* 8.192 Mhz */
404 #define DID0_VER_MASK 0x70000000
405 #define DID0_VER_0 0x00000000
406 #define DID0_VER_1 0x10000000
408 #define DID0_CLASS_MASK 0x00FF0000
409 #define DID0_CLASS_SANDSTORM 0x00000000
410 #define DID0_CLASS_FURY 0x00010000
412 static int ssys_board_class(const ssys_state
*s
)
414 uint32_t did0
= s
->board
->did0
;
415 switch (did0
& DID0_VER_MASK
) {
417 return DID0_CLASS_SANDSTORM
;
419 switch (did0
& DID0_CLASS_MASK
) {
420 case DID0_CLASS_SANDSTORM
:
421 case DID0_CLASS_FURY
:
422 return did0
& DID0_CLASS_MASK
;
424 /* for unknown classes, fall through */
426 hw_error("ssys_board_class: Unknown class 0x%08x\n", did0
);
430 static uint64_t ssys_read(void *opaque
, hwaddr offset
,
433 ssys_state
*s
= (ssys_state
*)opaque
;
436 case 0x000: /* DID0 */
437 return s
->board
->did0
;
438 case 0x004: /* DID1 */
439 return s
->board
->did1
;
440 case 0x008: /* DC0 */
441 return s
->board
->dc0
;
442 case 0x010: /* DC1 */
443 return s
->board
->dc1
;
444 case 0x014: /* DC2 */
445 return s
->board
->dc2
;
446 case 0x018: /* DC3 */
447 return s
->board
->dc3
;
448 case 0x01c: /* DC4 */
449 return s
->board
->dc4
;
450 case 0x030: /* PBORCTL */
452 case 0x034: /* LDOPCTL */
454 case 0x040: /* SRCR0 */
456 case 0x044: /* SRCR1 */
458 case 0x048: /* SRCR2 */
460 case 0x050: /* RIS */
461 return s
->int_status
;
462 case 0x054: /* IMC */
464 case 0x058: /* MISC */
465 return s
->int_status
& s
->int_mask
;
466 case 0x05c: /* RESC */
468 case 0x060: /* RCC */
470 case 0x064: /* PLLCFG */
473 xtal
= (s
->rcc
>> 6) & 0xf;
474 switch (ssys_board_class(s
)) {
475 case DID0_CLASS_FURY
:
476 return pllcfg_fury
[xtal
];
477 case DID0_CLASS_SANDSTORM
:
478 return pllcfg_sandstorm
[xtal
];
480 hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
484 case 0x070: /* RCC2 */
486 case 0x100: /* RCGC0 */
488 case 0x104: /* RCGC1 */
490 case 0x108: /* RCGC2 */
492 case 0x110: /* SCGC0 */
494 case 0x114: /* SCGC1 */
496 case 0x118: /* SCGC2 */
498 case 0x120: /* DCGC0 */
500 case 0x124: /* DCGC1 */
502 case 0x128: /* DCGC2 */
504 case 0x150: /* CLKVCLR */
506 case 0x160: /* LDOARST */
508 case 0x1e0: /* USER0 */
510 case 0x1e4: /* USER1 */
513 hw_error("ssys_read: Bad offset 0x%x\n", (int)offset
);
518 static bool ssys_use_rcc2(ssys_state
*s
)
520 return (s
->rcc2
>> 31) & 0x1;
524 * Caculate the sys. clock period in ms.
526 static void ssys_calculate_system_clock(ssys_state
*s
)
528 if (ssys_use_rcc2(s
)) {
529 system_clock_scale
= 5 * (((s
->rcc2
>> 23) & 0x3f) + 1);
531 system_clock_scale
= 5 * (((s
->rcc
>> 23) & 0xf) + 1);
535 static void ssys_write(void *opaque
, hwaddr offset
,
536 uint64_t value
, unsigned size
)
538 ssys_state
*s
= (ssys_state
*)opaque
;
541 case 0x030: /* PBORCTL */
542 s
->pborctl
= value
& 0xffff;
544 case 0x034: /* LDOPCTL */
545 s
->ldopctl
= value
& 0x1f;
547 case 0x040: /* SRCR0 */
548 case 0x044: /* SRCR1 */
549 case 0x048: /* SRCR2 */
550 fprintf(stderr
, "Peripheral reset not implemented\n");
552 case 0x054: /* IMC */
553 s
->int_mask
= value
& 0x7f;
555 case 0x058: /* MISC */
556 s
->int_status
&= ~value
;
558 case 0x05c: /* RESC */
559 s
->resc
= value
& 0x3f;
561 case 0x060: /* RCC */
562 if ((s
->rcc
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
564 s
->int_status
|= (1 << 6);
567 ssys_calculate_system_clock(s
);
569 case 0x070: /* RCC2 */
570 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
574 if ((s
->rcc2
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
576 s
->int_status
|= (1 << 6);
579 ssys_calculate_system_clock(s
);
581 case 0x100: /* RCGC0 */
584 case 0x104: /* RCGC1 */
587 case 0x108: /* RCGC2 */
590 case 0x110: /* SCGC0 */
593 case 0x114: /* SCGC1 */
596 case 0x118: /* SCGC2 */
599 case 0x120: /* DCGC0 */
602 case 0x124: /* DCGC1 */
605 case 0x128: /* DCGC2 */
608 case 0x150: /* CLKVCLR */
611 case 0x160: /* LDOARST */
615 hw_error("ssys_write: Bad offset 0x%x\n", (int)offset
);
620 static const MemoryRegionOps ssys_ops
= {
623 .endianness
= DEVICE_NATIVE_ENDIAN
,
626 static void ssys_reset(void *opaque
)
628 ssys_state
*s
= (ssys_state
*)opaque
;
633 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
636 s
->rcc2
= 0x07802810;
641 ssys_calculate_system_clock(s
);
644 static int stellaris_sys_post_load(void *opaque
, int version_id
)
646 ssys_state
*s
= opaque
;
648 ssys_calculate_system_clock(s
);
653 static const VMStateDescription vmstate_stellaris_sys
= {
654 .name
= "stellaris_sys",
656 .minimum_version_id
= 1,
657 .post_load
= stellaris_sys_post_load
,
658 .fields
= (VMStateField
[]) {
659 VMSTATE_UINT32(pborctl
, ssys_state
),
660 VMSTATE_UINT32(ldopctl
, ssys_state
),
661 VMSTATE_UINT32(int_mask
, ssys_state
),
662 VMSTATE_UINT32(int_status
, ssys_state
),
663 VMSTATE_UINT32(resc
, ssys_state
),
664 VMSTATE_UINT32(rcc
, ssys_state
),
665 VMSTATE_UINT32_V(rcc2
, ssys_state
, 2),
666 VMSTATE_UINT32_ARRAY(rcgc
, ssys_state
, 3),
667 VMSTATE_UINT32_ARRAY(scgc
, ssys_state
, 3),
668 VMSTATE_UINT32_ARRAY(dcgc
, ssys_state
, 3),
669 VMSTATE_UINT32(clkvclr
, ssys_state
),
670 VMSTATE_UINT32(ldoarst
, ssys_state
),
671 VMSTATE_END_OF_LIST()
675 static int stellaris_sys_init(uint32_t base
, qemu_irq irq
,
676 stellaris_board_info
* board
,
681 s
= g_new0(ssys_state
, 1);
684 /* Most devices come preprogrammed with a MAC address in the user data. */
685 s
->user0
= macaddr
[0] | (macaddr
[1] << 8) | (macaddr
[2] << 16);
686 s
->user1
= macaddr
[3] | (macaddr
[4] << 8) | (macaddr
[5] << 16);
688 memory_region_init_io(&s
->iomem
, NULL
, &ssys_ops
, s
, "ssys", 0x00001000);
689 memory_region_add_subregion(get_system_memory(), base
, &s
->iomem
);
691 vmstate_register(NULL
, -1, &vmstate_stellaris_sys
, s
);
696 /* I2C controller. */
698 #define TYPE_STELLARIS_I2C "stellaris-i2c"
699 #define STELLARIS_I2C(obj) \
700 OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C)
703 SysBusDevice parent_obj
;
715 } stellaris_i2c_state
;
717 #define STELLARIS_I2C_MCS_BUSY 0x01
718 #define STELLARIS_I2C_MCS_ERROR 0x02
719 #define STELLARIS_I2C_MCS_ADRACK 0x04
720 #define STELLARIS_I2C_MCS_DATACK 0x08
721 #define STELLARIS_I2C_MCS_ARBLST 0x10
722 #define STELLARIS_I2C_MCS_IDLE 0x20
723 #define STELLARIS_I2C_MCS_BUSBSY 0x40
725 static uint64_t stellaris_i2c_read(void *opaque
, hwaddr offset
,
728 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
734 /* We don't emulate timing, so the controller is never busy. */
735 return s
->mcs
| STELLARIS_I2C_MCS_IDLE
;
738 case 0x0c: /* MTPR */
740 case 0x10: /* MIMR */
742 case 0x14: /* MRIS */
744 case 0x18: /* MMIS */
745 return s
->mris
& s
->mimr
;
749 hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset
);
754 static void stellaris_i2c_update(stellaris_i2c_state
*s
)
758 level
= (s
->mris
& s
->mimr
) != 0;
759 qemu_set_irq(s
->irq
, level
);
762 static void stellaris_i2c_write(void *opaque
, hwaddr offset
,
763 uint64_t value
, unsigned size
)
765 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
769 s
->msa
= value
& 0xff;
772 if ((s
->mcr
& 0x10) == 0) {
773 /* Disabled. Do nothing. */
776 /* Grab the bus if this is starting a transfer. */
777 if ((value
& 2) && (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
778 if (i2c_start_transfer(s
->bus
, s
->msa
>> 1, s
->msa
& 1)) {
779 s
->mcs
|= STELLARIS_I2C_MCS_ARBLST
;
781 s
->mcs
&= ~STELLARIS_I2C_MCS_ARBLST
;
782 s
->mcs
|= STELLARIS_I2C_MCS_BUSBSY
;
785 /* If we don't have the bus then indicate an error. */
786 if (!i2c_bus_busy(s
->bus
)
787 || (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
788 s
->mcs
|= STELLARIS_I2C_MCS_ERROR
;
791 s
->mcs
&= ~STELLARIS_I2C_MCS_ERROR
;
793 /* Transfer a byte. */
794 /* TODO: Handle errors. */
797 s
->mdr
= i2c_recv(s
->bus
) & 0xff;
800 i2c_send(s
->bus
, s
->mdr
);
802 /* Raise an interrupt. */
806 /* Finish transfer. */
807 i2c_end_transfer(s
->bus
);
808 s
->mcs
&= ~STELLARIS_I2C_MCS_BUSBSY
;
812 s
->mdr
= value
& 0xff;
814 case 0x0c: /* MTPR */
815 s
->mtpr
= value
& 0xff;
817 case 0x10: /* MIMR */
820 case 0x1c: /* MICR */
826 "stellaris_i2c_write: Loopback not implemented\n");
829 "stellaris_i2c_write: Slave mode not implemented\n");
830 s
->mcr
= value
& 0x31;
833 hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
836 stellaris_i2c_update(s
);
839 static void stellaris_i2c_reset(stellaris_i2c_state
*s
)
841 if (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
)
842 i2c_end_transfer(s
->bus
);
851 stellaris_i2c_update(s
);
854 static const MemoryRegionOps stellaris_i2c_ops
= {
855 .read
= stellaris_i2c_read
,
856 .write
= stellaris_i2c_write
,
857 .endianness
= DEVICE_NATIVE_ENDIAN
,
860 static const VMStateDescription vmstate_stellaris_i2c
= {
861 .name
= "stellaris_i2c",
863 .minimum_version_id
= 1,
864 .fields
= (VMStateField
[]) {
865 VMSTATE_UINT32(msa
, stellaris_i2c_state
),
866 VMSTATE_UINT32(mcs
, stellaris_i2c_state
),
867 VMSTATE_UINT32(mdr
, stellaris_i2c_state
),
868 VMSTATE_UINT32(mtpr
, stellaris_i2c_state
),
869 VMSTATE_UINT32(mimr
, stellaris_i2c_state
),
870 VMSTATE_UINT32(mris
, stellaris_i2c_state
),
871 VMSTATE_UINT32(mcr
, stellaris_i2c_state
),
872 VMSTATE_END_OF_LIST()
876 static int stellaris_i2c_init(SysBusDevice
*sbd
)
878 DeviceState
*dev
= DEVICE(sbd
);
879 stellaris_i2c_state
*s
= STELLARIS_I2C(dev
);
882 sysbus_init_irq(sbd
, &s
->irq
);
883 bus
= i2c_init_bus(dev
, "i2c");
886 memory_region_init_io(&s
->iomem
, OBJECT(s
), &stellaris_i2c_ops
, s
,
888 sysbus_init_mmio(sbd
, &s
->iomem
);
889 /* ??? For now we only implement the master interface. */
890 stellaris_i2c_reset(s
);
891 vmstate_register(dev
, -1, &vmstate_stellaris_i2c
, s
);
895 /* Analogue to Digital Converter. This is only partially implemented,
896 enough for applications that use a combined ADC and timer tick. */
898 #define STELLARIS_ADC_EM_CONTROLLER 0
899 #define STELLARIS_ADC_EM_COMP 1
900 #define STELLARIS_ADC_EM_EXTERNAL 4
901 #define STELLARIS_ADC_EM_TIMER 5
902 #define STELLARIS_ADC_EM_PWM0 6
903 #define STELLARIS_ADC_EM_PWM1 7
904 #define STELLARIS_ADC_EM_PWM2 8
906 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
907 #define STELLARIS_ADC_FIFO_FULL 0x1000
909 #define TYPE_STELLARIS_ADC "stellaris-adc"
910 #define STELLARIS_ADC(obj) \
911 OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC)
913 typedef struct StellarisADCState
{
914 SysBusDevice parent_obj
;
933 } stellaris_adc_state
;
935 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state
*s
, int n
)
939 tail
= s
->fifo
[n
].state
& 0xf;
940 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_EMPTY
) {
943 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf) | ((tail
+ 1) & 0xf);
944 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_FULL
;
945 if (tail
+ 1 == ((s
->fifo
[n
].state
>> 4) & 0xf))
946 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_EMPTY
;
948 return s
->fifo
[n
].data
[tail
];
951 static void stellaris_adc_fifo_write(stellaris_adc_state
*s
, int n
,
956 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
957 FIFO fir each sequencer. */
958 head
= (s
->fifo
[n
].state
>> 4) & 0xf;
959 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_FULL
) {
963 s
->fifo
[n
].data
[head
] = value
;
964 head
= (head
+ 1) & 0xf;
965 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_EMPTY
;
966 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf0) | (head
<< 4);
967 if ((s
->fifo
[n
].state
& 0xf) == head
)
968 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_FULL
;
971 static void stellaris_adc_update(stellaris_adc_state
*s
)
976 for (n
= 0; n
< 4; n
++) {
977 level
= (s
->ris
& s
->im
& (1 << n
)) != 0;
978 qemu_set_irq(s
->irq
[n
], level
);
982 static void stellaris_adc_trigger(void *opaque
, int irq
, int level
)
984 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
987 for (n
= 0; n
< 4; n
++) {
988 if ((s
->actss
& (1 << n
)) == 0) {
992 if (((s
->emux
>> (n
* 4)) & 0xff) != 5) {
996 /* Some applications use the ADC as a random number source, so introduce
997 some variation into the signal. */
998 s
->noise
= s
->noise
* 314159 + 1;
999 /* ??? actual inputs not implemented. Return an arbitrary value. */
1000 stellaris_adc_fifo_write(s
, n
, 0x200 + ((s
->noise
>> 16) & 7));
1002 stellaris_adc_update(s
);
1006 static void stellaris_adc_reset(stellaris_adc_state
*s
)
1010 for (n
= 0; n
< 4; n
++) {
1013 s
->fifo
[n
].state
= STELLARIS_ADC_FIFO_EMPTY
;
1017 static uint64_t stellaris_adc_read(void *opaque
, hwaddr offset
,
1020 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1022 /* TODO: Implement this. */
1023 if (offset
>= 0x40 && offset
< 0xc0) {
1025 n
= (offset
- 0x40) >> 5;
1026 switch (offset
& 0x1f) {
1027 case 0x00: /* SSMUX */
1029 case 0x04: /* SSCTL */
1031 case 0x08: /* SSFIFO */
1032 return stellaris_adc_fifo_read(s
, n
);
1033 case 0x0c: /* SSFSTAT */
1034 return s
->fifo
[n
].state
;
1040 case 0x00: /* ACTSS */
1042 case 0x04: /* RIS */
1046 case 0x0c: /* ISC */
1047 return s
->ris
& s
->im
;
1048 case 0x10: /* OSTAT */
1050 case 0x14: /* EMUX */
1052 case 0x18: /* USTAT */
1054 case 0x20: /* SSPRI */
1056 case 0x30: /* SAC */
1059 hw_error("strllaris_adc_read: Bad offset 0x%x\n",
1065 static void stellaris_adc_write(void *opaque
, hwaddr offset
,
1066 uint64_t value
, unsigned size
)
1068 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1070 /* TODO: Implement this. */
1071 if (offset
>= 0x40 && offset
< 0xc0) {
1073 n
= (offset
- 0x40) >> 5;
1074 switch (offset
& 0x1f) {
1075 case 0x00: /* SSMUX */
1076 s
->ssmux
[n
] = value
& 0x33333333;
1078 case 0x04: /* SSCTL */
1080 hw_error("ADC: Unimplemented sequence %" PRIx64
"\n",
1083 s
->ssctl
[n
] = value
;
1090 case 0x00: /* ACTSS */
1091 s
->actss
= value
& 0xf;
1096 case 0x0c: /* ISC */
1099 case 0x10: /* OSTAT */
1102 case 0x14: /* EMUX */
1105 case 0x18: /* USTAT */
1108 case 0x20: /* SSPRI */
1111 case 0x28: /* PSSI */
1112 hw_error("Not implemented: ADC sample initiate\n");
1114 case 0x30: /* SAC */
1118 hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset
);
1120 stellaris_adc_update(s
);
1123 static const MemoryRegionOps stellaris_adc_ops
= {
1124 .read
= stellaris_adc_read
,
1125 .write
= stellaris_adc_write
,
1126 .endianness
= DEVICE_NATIVE_ENDIAN
,
1129 static const VMStateDescription vmstate_stellaris_adc
= {
1130 .name
= "stellaris_adc",
1132 .minimum_version_id
= 1,
1133 .fields
= (VMStateField
[]) {
1134 VMSTATE_UINT32(actss
, stellaris_adc_state
),
1135 VMSTATE_UINT32(ris
, stellaris_adc_state
),
1136 VMSTATE_UINT32(im
, stellaris_adc_state
),
1137 VMSTATE_UINT32(emux
, stellaris_adc_state
),
1138 VMSTATE_UINT32(ostat
, stellaris_adc_state
),
1139 VMSTATE_UINT32(ustat
, stellaris_adc_state
),
1140 VMSTATE_UINT32(sspri
, stellaris_adc_state
),
1141 VMSTATE_UINT32(sac
, stellaris_adc_state
),
1142 VMSTATE_UINT32(fifo
[0].state
, stellaris_adc_state
),
1143 VMSTATE_UINT32_ARRAY(fifo
[0].data
, stellaris_adc_state
, 16),
1144 VMSTATE_UINT32(ssmux
[0], stellaris_adc_state
),
1145 VMSTATE_UINT32(ssctl
[0], stellaris_adc_state
),
1146 VMSTATE_UINT32(fifo
[1].state
, stellaris_adc_state
),
1147 VMSTATE_UINT32_ARRAY(fifo
[1].data
, stellaris_adc_state
, 16),
1148 VMSTATE_UINT32(ssmux
[1], stellaris_adc_state
),
1149 VMSTATE_UINT32(ssctl
[1], stellaris_adc_state
),
1150 VMSTATE_UINT32(fifo
[2].state
, stellaris_adc_state
),
1151 VMSTATE_UINT32_ARRAY(fifo
[2].data
, stellaris_adc_state
, 16),
1152 VMSTATE_UINT32(ssmux
[2], stellaris_adc_state
),
1153 VMSTATE_UINT32(ssctl
[2], stellaris_adc_state
),
1154 VMSTATE_UINT32(fifo
[3].state
, stellaris_adc_state
),
1155 VMSTATE_UINT32_ARRAY(fifo
[3].data
, stellaris_adc_state
, 16),
1156 VMSTATE_UINT32(ssmux
[3], stellaris_adc_state
),
1157 VMSTATE_UINT32(ssctl
[3], stellaris_adc_state
),
1158 VMSTATE_UINT32(noise
, stellaris_adc_state
),
1159 VMSTATE_END_OF_LIST()
1163 static int stellaris_adc_init(SysBusDevice
*sbd
)
1165 DeviceState
*dev
= DEVICE(sbd
);
1166 stellaris_adc_state
*s
= STELLARIS_ADC(dev
);
1169 for (n
= 0; n
< 4; n
++) {
1170 sysbus_init_irq(sbd
, &s
->irq
[n
]);
1173 memory_region_init_io(&s
->iomem
, OBJECT(s
), &stellaris_adc_ops
, s
,
1175 sysbus_init_mmio(sbd
, &s
->iomem
);
1176 stellaris_adc_reset(s
);
1177 qdev_init_gpio_in(dev
, stellaris_adc_trigger
, 1);
1178 vmstate_register(dev
, -1, &vmstate_stellaris_adc
, s
);
1183 void do_sys_reset(void *opaque
, int n
, int level
)
1186 qemu_system_reset_request();
1191 static stellaris_board_info stellaris_boards
[] = {
1195 0x001f001f, /* dc0 */
1205 0x00ff007f, /* dc0 */
1210 BP_OLED_SSI
| BP_GAMEPAD
1214 static void stellaris_init(const char *kernel_filename
, const char *cpu_model
,
1215 stellaris_board_info
*board
)
1217 static const int uart_irq
[] = {5, 6, 33, 34};
1218 static const int timer_irq
[] = {19, 21, 23, 35};
1219 static const uint32_t gpio_addr
[7] =
1220 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1221 0x40024000, 0x40025000, 0x40026000};
1222 static const int gpio_irq
[7] = {0, 1, 2, 3, 4, 30, 31};
1224 DeviceState
*gpio_dev
[7], *nvic
;
1225 qemu_irq gpio_in
[7][8];
1226 qemu_irq gpio_out
[7][8];
1235 MemoryRegion
*sram
= g_new(MemoryRegion
, 1);
1236 MemoryRegion
*flash
= g_new(MemoryRegion
, 1);
1237 MemoryRegion
*system_memory
= get_system_memory();
1239 flash_size
= (((board
->dc0
& 0xffff) + 1) << 1) * 1024;
1240 sram_size
= ((board
->dc0
>> 18) + 1) * 1024;
1242 /* Flash programming is done via the SCU, so pretend it is ROM. */
1243 memory_region_init_ram(flash
, NULL
, "stellaris.flash", flash_size
,
1245 vmstate_register_ram_global(flash
);
1246 memory_region_set_readonly(flash
, true);
1247 memory_region_add_subregion(system_memory
, 0, flash
);
1249 memory_region_init_ram(sram
, NULL
, "stellaris.sram", sram_size
,
1251 vmstate_register_ram_global(sram
);
1252 memory_region_add_subregion(system_memory
, 0x20000000, sram
);
1254 nvic
= armv7m_init(system_memory
, flash_size
, NUM_IRQ_LINES
,
1255 kernel_filename
, cpu_model
);
1257 qdev_connect_gpio_out_named(nvic
, "SYSRESETREQ", 0,
1258 qemu_allocate_irq(&do_sys_reset
, NULL
, 0));
1260 if (board
->dc1
& (1 << 16)) {
1261 dev
= sysbus_create_varargs(TYPE_STELLARIS_ADC
, 0x40038000,
1262 qdev_get_gpio_in(nvic
, 14),
1263 qdev_get_gpio_in(nvic
, 15),
1264 qdev_get_gpio_in(nvic
, 16),
1265 qdev_get_gpio_in(nvic
, 17),
1267 adc
= qdev_get_gpio_in(dev
, 0);
1271 for (i
= 0; i
< 4; i
++) {
1272 if (board
->dc2
& (0x10000 << i
)) {
1273 dev
= sysbus_create_simple(TYPE_STELLARIS_GPTM
,
1274 0x40030000 + i
* 0x1000,
1275 qdev_get_gpio_in(nvic
, timer_irq
[i
]));
1276 /* TODO: This is incorrect, but we get away with it because
1277 the ADC output is only ever pulsed. */
1278 qdev_connect_gpio_out(dev
, 0, adc
);
1282 stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic
, 28),
1283 board
, nd_table
[0].macaddr
.a
);
1285 for (i
= 0; i
< 7; i
++) {
1286 if (board
->dc4
& (1 << i
)) {
1287 gpio_dev
[i
] = sysbus_create_simple("pl061_luminary", gpio_addr
[i
],
1288 qdev_get_gpio_in(nvic
,
1290 for (j
= 0; j
< 8; j
++) {
1291 gpio_in
[i
][j
] = qdev_get_gpio_in(gpio_dev
[i
], j
);
1292 gpio_out
[i
][j
] = NULL
;
1297 if (board
->dc2
& (1 << 12)) {
1298 dev
= sysbus_create_simple(TYPE_STELLARIS_I2C
, 0x40020000,
1299 qdev_get_gpio_in(nvic
, 8));
1300 i2c
= (I2CBus
*)qdev_get_child_bus(dev
, "i2c");
1301 if (board
->peripherals
& BP_OLED_I2C
) {
1302 i2c_create_slave(i2c
, "ssd0303", 0x3d);
1306 for (i
= 0; i
< 4; i
++) {
1307 if (board
->dc2
& (1 << i
)) {
1308 sysbus_create_simple("pl011_luminary", 0x4000c000 + i
* 0x1000,
1309 qdev_get_gpio_in(nvic
, uart_irq
[i
]));
1312 if (board
->dc2
& (1 << 4)) {
1313 dev
= sysbus_create_simple("pl022", 0x40008000,
1314 qdev_get_gpio_in(nvic
, 7));
1315 if (board
->peripherals
& BP_OLED_SSI
) {
1318 DeviceState
*ssddev
;
1320 /* Some boards have both an OLED controller and SD card connected to
1321 * the same SSI port, with the SD card chip select connected to a
1322 * GPIO pin. Technically the OLED chip select is connected to the
1323 * SSI Fss pin. We do not bother emulating that as both devices
1324 * should never be selected simultaneously, and our OLED controller
1325 * ignores stray 0xff commands that occur when deselecting the SD
1328 bus
= qdev_get_child_bus(dev
, "ssi");
1330 sddev
= ssi_create_slave(bus
, "ssi-sd");
1331 ssddev
= ssi_create_slave(bus
, "ssd0323");
1332 gpio_out
[GPIO_D
][0] = qemu_irq_split(
1333 qdev_get_gpio_in_named(sddev
, SSI_GPIO_CS
, 0),
1334 qdev_get_gpio_in_named(ssddev
, SSI_GPIO_CS
, 0));
1335 gpio_out
[GPIO_C
][7] = qdev_get_gpio_in(ssddev
, 0);
1337 /* Make sure the select pin is high. */
1338 qemu_irq_raise(gpio_out
[GPIO_D
][0]);
1341 if (board
->dc4
& (1 << 28)) {
1344 qemu_check_nic_model(&nd_table
[0], "stellaris");
1346 enet
= qdev_create(NULL
, "stellaris_enet");
1347 qdev_set_nic_properties(enet
, &nd_table
[0]);
1348 qdev_init_nofail(enet
);
1349 sysbus_mmio_map(SYS_BUS_DEVICE(enet
), 0, 0x40048000);
1350 sysbus_connect_irq(SYS_BUS_DEVICE(enet
), 0, qdev_get_gpio_in(nvic
, 42));
1352 if (board
->peripherals
& BP_GAMEPAD
) {
1353 qemu_irq gpad_irq
[5];
1354 static const int gpad_keycode
[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1356 gpad_irq
[0] = qemu_irq_invert(gpio_in
[GPIO_E
][0]); /* up */
1357 gpad_irq
[1] = qemu_irq_invert(gpio_in
[GPIO_E
][1]); /* down */
1358 gpad_irq
[2] = qemu_irq_invert(gpio_in
[GPIO_E
][2]); /* left */
1359 gpad_irq
[3] = qemu_irq_invert(gpio_in
[GPIO_E
][3]); /* right */
1360 gpad_irq
[4] = qemu_irq_invert(gpio_in
[GPIO_F
][1]); /* select */
1362 stellaris_gamepad_init(5, gpad_irq
, gpad_keycode
);
1364 for (i
= 0; i
< 7; i
++) {
1365 if (board
->dc4
& (1 << i
)) {
1366 for (j
= 0; j
< 8; j
++) {
1367 if (gpio_out
[i
][j
]) {
1368 qdev_connect_gpio_out(gpio_dev
[i
], j
, gpio_out
[i
][j
]);
1375 /* FIXME: Figure out how to generate these from stellaris_boards. */
1376 static void lm3s811evb_init(MachineState
*machine
)
1378 const char *cpu_model
= machine
->cpu_model
;
1379 const char *kernel_filename
= machine
->kernel_filename
;
1380 stellaris_init(kernel_filename
, cpu_model
, &stellaris_boards
[0]);
1383 static void lm3s6965evb_init(MachineState
*machine
)
1385 const char *cpu_model
= machine
->cpu_model
;
1386 const char *kernel_filename
= machine
->kernel_filename
;
1387 stellaris_init(kernel_filename
, cpu_model
, &stellaris_boards
[1]);
1390 static void lm3s811evb_class_init(ObjectClass
*oc
, void *data
)
1392 MachineClass
*mc
= MACHINE_CLASS(oc
);
1394 mc
->desc
= "Stellaris LM3S811EVB";
1395 mc
->init
= lm3s811evb_init
;
1398 static const TypeInfo lm3s811evb_type
= {
1399 .name
= MACHINE_TYPE_NAME("lm3s811evb"),
1400 .parent
= TYPE_MACHINE
,
1401 .class_init
= lm3s811evb_class_init
,
1404 static void lm3s6965evb_class_init(ObjectClass
*oc
, void *data
)
1406 MachineClass
*mc
= MACHINE_CLASS(oc
);
1408 mc
->desc
= "Stellaris LM3S6965EVB";
1409 mc
->init
= lm3s6965evb_init
;
1412 static const TypeInfo lm3s6965evb_type
= {
1413 .name
= MACHINE_TYPE_NAME("lm3s6965evb"),
1414 .parent
= TYPE_MACHINE
,
1415 .class_init
= lm3s6965evb_class_init
,
1418 static void stellaris_machine_init(void)
1420 type_register_static(&lm3s811evb_type
);
1421 type_register_static(&lm3s6965evb_type
);
1424 type_init(stellaris_machine_init
)
1426 static void stellaris_i2c_class_init(ObjectClass
*klass
, void *data
)
1428 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
1430 sdc
->init
= stellaris_i2c_init
;
1433 static const TypeInfo stellaris_i2c_info
= {
1434 .name
= TYPE_STELLARIS_I2C
,
1435 .parent
= TYPE_SYS_BUS_DEVICE
,
1436 .instance_size
= sizeof(stellaris_i2c_state
),
1437 .class_init
= stellaris_i2c_class_init
,
1440 static void stellaris_gptm_class_init(ObjectClass
*klass
, void *data
)
1442 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
1444 sdc
->init
= stellaris_gptm_init
;
1447 static const TypeInfo stellaris_gptm_info
= {
1448 .name
= TYPE_STELLARIS_GPTM
,
1449 .parent
= TYPE_SYS_BUS_DEVICE
,
1450 .instance_size
= sizeof(gptm_state
),
1451 .class_init
= stellaris_gptm_class_init
,
1454 static void stellaris_adc_class_init(ObjectClass
*klass
, void *data
)
1456 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
1458 sdc
->init
= stellaris_adc_init
;
1461 static const TypeInfo stellaris_adc_info
= {
1462 .name
= TYPE_STELLARIS_ADC
,
1463 .parent
= TYPE_SYS_BUS_DEVICE
,
1464 .instance_size
= sizeof(stellaris_adc_state
),
1465 .class_init
= stellaris_adc_class_init
,
1468 static void stellaris_register_types(void)
1470 type_register_static(&stellaris_i2c_info
);
1471 type_register_static(&stellaris_gptm_info
);
1472 type_register_static(&stellaris_adc_info
);
1475 type_init(stellaris_register_types
)