2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/runstate.h"
48 #include "sysemu/tpm.h"
49 #include "sysemu/tcg.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "sysemu/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/error-report.h"
57 #include "qemu/module.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/arm/fdt.h"
64 #include "hw/intc/arm_gic.h"
65 #include "hw/intc/arm_gicv3_common.h"
66 #include "hw/intc/arm_gicv3_its_common.h"
69 #include "hw/firmware/smbios.h"
70 #include "qapi/visitor.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "qapi/qmp/qlist.h"
73 #include "standard-headers/linux/input.h"
74 #include "hw/arm/smmuv3.h"
75 #include "hw/acpi/acpi.h"
76 #include "target/arm/internals.h"
77 #include "hw/mem/pc-dimm.h"
78 #include "hw/mem/nvdimm.h"
79 #include "hw/acpi/generic_event_device.h"
80 #include "hw/virtio/virtio-md-pci.h"
81 #include "hw/virtio/virtio-iommu.h"
82 #include "hw/char/pl011.h"
83 #include "qemu/guest-random.h"
85 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
86 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
89 MachineClass *mc = MACHINE_CLASS(oc); \
90 virt_machine_##major##_##minor##_options(mc); \
91 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
96 static const TypeInfo machvirt_##major##_##minor##_info = { \
97 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
98 .parent = TYPE_VIRT_MACHINE, \
99 .class_init = virt_##major##_##minor##_class_init, \
101 static void machvirt_machine_##major##_##minor##_init(void) \
103 type_register_static(&machvirt_##major##_##minor##_info); \
105 type_init(machvirt_machine_##major##_##minor##_init);
107 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
108 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
109 #define DEFINE_VIRT_MACHINE(major, minor) \
110 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
113 /* Number of external interrupt lines to configure the GIC with */
116 #define PLATFORM_BUS_NUM_IRQS 64
118 /* Legacy RAM limit in GB (< version 4.0) */
119 #define LEGACY_RAMLIMIT_GB 255
120 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
122 /* Addresses and sizes of our components.
123 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
124 * 128MB..256MB is used for miscellaneous device I/O.
125 * 256MB..1GB is reserved for possible future PCI support (ie where the
126 * PCI memory window will go if we add a PCI host controller).
127 * 1GB and up is RAM (which may happily spill over into the
128 * high memory region beyond 4GB).
129 * This represents a compromise between how much RAM can be given to
130 * a 32 bit VM and leaving space for expansion and in particular for PCI.
131 * Note that devices should generally be placed at multiples of 0x10000,
132 * to accommodate guests using 64K pages.
134 static const MemMapEntry base_memmap
[] = {
135 /* Space up to 0x8000000 is reserved for a boot ROM */
136 [VIRT_FLASH
] = { 0, 0x08000000 },
137 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
138 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
139 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
140 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
141 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
142 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
143 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
144 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
145 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
146 /* This redistributor space allows up to 2*64kB*123 CPUs */
147 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
148 [VIRT_UART
] = { 0x09000000, 0x00001000 },
149 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
150 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
151 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
152 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
153 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
154 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
155 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
156 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
157 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
158 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
159 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
160 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
161 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
162 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
163 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
164 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
165 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
166 /* Actual RAM size depends on initial RAM and device memory settings */
167 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
171 * Highmem IO Regions: This memory map is floating, located after the RAM.
172 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
173 * top of the RAM, so that its base get the same alignment as the size,
174 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
175 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
176 * Note the extended_memmap is sized so that it eventually also includes the
177 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
178 * index of base_memmap).
180 * The memory map for these Highmem IO Regions can be in legacy or compact
181 * layout, depending on 'compact-highmem' property. With legacy layout, the
182 * PA space for one specific region is always reserved, even if the region
183 * has been disabled or doesn't fit into the PA space. However, the PA space
184 * for the region won't be reserved in these circumstances with compact layout.
186 static MemMapEntry extended_memmap
[] = {
187 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
188 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
189 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
190 /* Second PCIe window */
191 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
194 static const int a15irqmap
[] = {
197 [VIRT_PCIE
] = 3, /* ... to 6 */
199 [VIRT_SECURE_UART
] = 8,
201 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
202 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
203 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
204 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
207 static const char *valid_cpus
[] = {
209 ARM_CPU_TYPE_NAME("cortex-a7"),
210 ARM_CPU_TYPE_NAME("cortex-a15"),
211 ARM_CPU_TYPE_NAME("cortex-a35"),
212 ARM_CPU_TYPE_NAME("cortex-a55"),
213 ARM_CPU_TYPE_NAME("cortex-a72"),
214 ARM_CPU_TYPE_NAME("cortex-a76"),
215 ARM_CPU_TYPE_NAME("cortex-a710"),
216 ARM_CPU_TYPE_NAME("a64fx"),
217 ARM_CPU_TYPE_NAME("neoverse-n1"),
218 ARM_CPU_TYPE_NAME("neoverse-v1"),
219 ARM_CPU_TYPE_NAME("neoverse-n2"),
221 ARM_CPU_TYPE_NAME("cortex-a53"),
222 ARM_CPU_TYPE_NAME("cortex-a57"),
223 ARM_CPU_TYPE_NAME("host"),
224 ARM_CPU_TYPE_NAME("max"),
227 static bool cpu_type_valid(const char *cpu
)
231 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
232 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
239 static void create_randomness(MachineState
*ms
, const char *node
)
246 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
249 qemu_fdt_setprop_u64(ms
->fdt
, node
, "kaslr-seed", seed
.kaslr
);
250 qemu_fdt_setprop(ms
->fdt
, node
, "rng-seed", seed
.rng
, sizeof(seed
.rng
));
253 static void create_fdt(VirtMachineState
*vms
)
255 MachineState
*ms
= MACHINE(vms
);
256 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
257 void *fdt
= create_device_tree(&vms
->fdt_size
);
260 error_report("create_device_tree() failed");
267 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
268 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
269 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
270 qemu_fdt_setprop_string(fdt
, "/", "model", "linux,dummy-virt");
272 /* /chosen must exist for load_dtb to fill in necessary properties later */
273 qemu_fdt_add_subnode(fdt
, "/chosen");
274 if (vms
->dtb_randomness
) {
275 create_randomness(ms
, "/chosen");
279 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
280 if (vms
->dtb_randomness
) {
281 create_randomness(ms
, "/secure-chosen");
285 /* Clock node, for the benefit of the UART. The kernel device tree
286 * binding documentation claims the PL011 node clock properties are
287 * optional but in practice if you omit them the kernel refuses to
288 * probe for the device.
290 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
291 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
292 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
293 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
294 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
295 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
297 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
299 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
300 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
301 uint32_t *matrix
= g_malloc0(size
);
304 for (i
= 0; i
< nb_numa_nodes
; i
++) {
305 for (j
= 0; j
< nb_numa_nodes
; j
++) {
306 idx
= (i
* nb_numa_nodes
+ j
) * 3;
307 matrix
[idx
+ 0] = cpu_to_be32(i
);
308 matrix
[idx
+ 1] = cpu_to_be32(j
);
310 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
314 qemu_fdt_add_subnode(fdt
, "/distance-map");
315 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
316 "numa-distance-map-v1");
317 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
323 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
325 /* On real hardware these interrupts are level-triggered.
326 * On KVM they were edge-triggered before host kernel version 4.4,
327 * and level-triggered afterwards.
328 * On emulated QEMU they are level-triggered.
330 * Getting the DTB info about them wrong is awkward for some
332 * pre-4.8 ignore the DT and leave the interrupt configured
333 * with whatever the GIC reset value (or the bootloader) left it at
334 * 4.8 before rc6 honour the incorrect data by programming it back
335 * into the GIC, causing problems
336 * 4.8rc6 and later ignore the DT and always write "level triggered"
339 * For backwards-compatibility, virt-2.8 and earlier will continue
340 * to say these are edge-triggered, but later machines will report
341 * the correct information.
344 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
345 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
346 MachineState
*ms
= MACHINE(vms
);
348 if (vmc
->claim_edge_triggered_timers
) {
349 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
352 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
353 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
354 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
355 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
358 qemu_fdt_add_subnode(ms
->fdt
, "/timer");
360 armcpu
= ARM_CPU(qemu_get_cpu(0));
361 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
362 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
363 qemu_fdt_setprop(ms
->fdt
, "/timer", "compatible",
364 compat
, sizeof(compat
));
366 qemu_fdt_setprop_string(ms
->fdt
, "/timer", "compatible",
369 qemu_fdt_setprop(ms
->fdt
, "/timer", "always-on", NULL
, 0);
370 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
371 GIC_FDT_IRQ_TYPE_PPI
,
372 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ
), irqflags
,
373 GIC_FDT_IRQ_TYPE_PPI
,
374 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ
), irqflags
,
375 GIC_FDT_IRQ_TYPE_PPI
,
376 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ
), irqflags
,
377 GIC_FDT_IRQ_TYPE_PPI
,
378 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ
), irqflags
);
381 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
385 const MachineState
*ms
= MACHINE(vms
);
386 const VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
387 int smp_cpus
= ms
->smp
.cpus
;
390 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
391 * On ARM v8 64-bit systems value should be set to 2,
392 * that corresponds to the MPIDR_EL1 register size.
393 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
394 * in the system, #address-cells can be set to 1, since
395 * MPIDR_EL1[63:32] bits are not used for CPUs
398 * Here we actually don't know whether our system is 32- or 64-bit one.
399 * The simplest way to go is to examine affinity IDs of all our CPUs. If
400 * at least one of them has Aff3 populated, we set #address-cells to 2.
402 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
403 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
405 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
411 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
412 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", addr_cells
);
413 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
415 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
416 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
417 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
418 CPUState
*cs
= CPU(armcpu
);
420 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
421 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "cpu");
422 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
423 armcpu
->dtb_compatible
);
425 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
426 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
427 "enable-method", "psci");
430 if (addr_cells
== 2) {
431 qemu_fdt_setprop_u64(ms
->fdt
, nodename
, "reg",
432 armcpu
->mp_affinity
);
434 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "reg",
435 armcpu
->mp_affinity
);
438 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
439 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "numa-node-id",
440 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
443 if (!vmc
->no_cpu_topology
) {
444 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle",
445 qemu_fdt_alloc_phandle(ms
->fdt
));
451 if (!vmc
->no_cpu_topology
) {
453 * Add vCPU topology description through fdt node cpu-map.
455 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
456 * In a SMP system, the hierarchy of CPUs can be defined through
457 * four entities that are used to describe the layout of CPUs in
458 * the system: socket/cluster/core/thread.
460 * A socket node represents the boundary of system physical package
461 * and its child nodes must be one or more cluster nodes. A system
462 * can contain several layers of clustering within a single physical
463 * package and cluster nodes can be contained in parent cluster nodes.
465 * Note: currently we only support one layer of clustering within
466 * each physical package.
468 qemu_fdt_add_subnode(ms
->fdt
, "/cpus/cpu-map");
470 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
471 char *cpu_path
= g_strdup_printf("/cpus/cpu@%d", cpu
);
474 if (ms
->smp
.threads
> 1) {
475 map_path
= g_strdup_printf(
476 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
477 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
),
478 (cpu
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
,
479 (cpu
/ ms
->smp
.threads
) % ms
->smp
.cores
,
480 cpu
% ms
->smp
.threads
);
482 map_path
= g_strdup_printf(
483 "/cpus/cpu-map/socket%d/cluster%d/core%d",
484 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
),
485 (cpu
/ ms
->smp
.cores
) % ms
->smp
.clusters
,
486 cpu
% ms
->smp
.cores
);
488 qemu_fdt_add_path(ms
->fdt
, map_path
);
489 qemu_fdt_setprop_phandle(ms
->fdt
, map_path
, "cpu", cpu_path
);
497 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
500 MachineState
*ms
= MACHINE(vms
);
502 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
503 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
504 vms
->memmap
[VIRT_GIC_ITS
].base
);
505 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
506 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
508 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
509 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#msi-cells", 1);
510 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
511 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
512 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
513 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
517 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
519 MachineState
*ms
= MACHINE(vms
);
522 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
523 vms
->memmap
[VIRT_GIC_V2M
].base
);
524 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
525 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
526 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
527 "arm,gic-v2m-frame");
528 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
529 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
530 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
531 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
532 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
536 static void fdt_add_gic_node(VirtMachineState
*vms
)
538 MachineState
*ms
= MACHINE(vms
);
541 vms
->gic_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
542 qemu_fdt_setprop_cell(ms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
544 nodename
= g_strdup_printf("/intc@%" PRIx64
,
545 vms
->memmap
[VIRT_GIC_DIST
].base
);
546 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
547 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 3);
548 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
549 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 0x2);
550 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 0x2);
551 qemu_fdt_setprop(ms
->fdt
, nodename
, "ranges", NULL
, 0);
552 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
553 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
555 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
558 qemu_fdt_setprop_cell(ms
->fdt
, nodename
,
559 "#redistributor-regions", nb_redist_regions
);
561 if (nb_redist_regions
== 1) {
562 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
563 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
564 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
565 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
566 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
568 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
569 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
570 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
571 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
572 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
573 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
574 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
578 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
579 GIC_FDT_IRQ_TYPE_PPI
,
580 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ
),
581 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
584 /* 'cortex-a15-gic' means 'GIC v2' */
585 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
586 "arm,cortex-a15-gic");
588 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
589 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
590 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
591 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
592 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
594 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
595 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
596 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
597 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
598 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
599 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
600 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
601 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
602 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
603 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
604 GIC_FDT_IRQ_TYPE_PPI
,
605 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ
),
606 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
610 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
614 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
616 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
617 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
618 MachineState
*ms
= MACHINE(vms
);
620 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
621 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
625 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
626 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
627 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
628 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
631 qemu_fdt_add_subnode(ms
->fdt
, "/pmu");
632 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
633 const char compat
[] = "arm,armv8-pmuv3";
634 qemu_fdt_setprop(ms
->fdt
, "/pmu", "compatible",
635 compat
, sizeof(compat
));
636 qemu_fdt_setprop_cells(ms
->fdt
, "/pmu", "interrupts",
637 GIC_FDT_IRQ_TYPE_PPI
,
638 INTID_TO_PPI(VIRTUAL_PMU_IRQ
), irqflags
);
642 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
645 MachineState
*ms
= MACHINE(vms
);
646 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
647 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
650 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
653 if (ms
->nvdimms_state
->is_enabled
) {
654 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
657 dev
= qdev_new(TYPE_ACPI_GED
);
658 qdev_prop_set_uint32(dev
, "ged-event", event
);
659 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
661 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
662 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
663 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
668 static void create_its(VirtMachineState
*vms
)
670 const char *itsclass
= its_class_name();
673 if (!strcmp(itsclass
, "arm-gicv3-its")) {
680 /* Do nothing if not supported */
684 dev
= qdev_new(itsclass
);
686 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
688 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
689 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
691 fdt_add_its_gic_node(vms
);
692 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
695 static void create_v2m(VirtMachineState
*vms
)
698 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
701 dev
= qdev_new("arm-gicv2m");
702 qdev_prop_set_uint32(dev
, "base-spi", irq
);
703 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
704 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
705 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
707 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
708 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
709 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
712 fdt_add_v2m_gic_node(vms
);
713 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
716 static void create_gic(VirtMachineState
*vms
, MemoryRegion
*mem
)
718 MachineState
*ms
= MACHINE(vms
);
719 /* We create a standalone GIC */
720 SysBusDevice
*gicbusdev
;
723 unsigned int smp_cpus
= ms
->smp
.cpus
;
724 uint32_t nb_redist_regions
= 0;
727 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
728 gictype
= gic_class_name();
730 gictype
= gicv3_class_name();
733 switch (vms
->gic_version
) {
734 case VIRT_GIC_VERSION_2
:
737 case VIRT_GIC_VERSION_3
:
740 case VIRT_GIC_VERSION_4
:
744 g_assert_not_reached();
746 vms
->gic
= qdev_new(gictype
);
747 qdev_prop_set_uint32(vms
->gic
, "revision", revision
);
748 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
749 /* Note that the num-irq property counts both internal and external
750 * interrupts; there are always 32 of the former (mandated by GIC spec).
752 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
753 if (!kvm_irqchip_in_kernel()) {
754 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
757 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
758 QList
*redist_region_count
;
759 uint32_t redist0_capacity
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
760 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
762 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
764 redist_region_count
= qlist_new();
765 qlist_append_int(redist_region_count
, redist0_count
);
766 if (nb_redist_regions
== 2) {
767 uint32_t redist1_capacity
=
768 virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
770 qlist_append_int(redist_region_count
,
771 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
773 qdev_prop_set_array(vms
->gic
, "redist-region-count",
774 redist_region_count
);
776 if (!kvm_irqchip_in_kernel()) {
778 object_property_set_link(OBJECT(vms
->gic
), "sysmem",
779 OBJECT(mem
), &error_fatal
);
780 qdev_prop_set_bit(vms
->gic
, "has-lpi", true);
784 if (!kvm_irqchip_in_kernel()) {
785 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
789 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
790 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
791 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
792 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
793 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
794 if (nb_redist_regions
== 2) {
795 sysbus_mmio_map(gicbusdev
, 2,
796 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
799 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
801 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
802 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
806 /* Wire the outputs from each CPU's generic timer and the GICv3
807 * maintenance interrupt signal to the appropriate GIC PPI inputs,
808 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
810 for (i
= 0; i
< smp_cpus
; i
++) {
811 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
812 int intidbase
= NUM_IRQS
+ i
* GIC_INTERNAL
;
813 /* Mapping from the output timer irq lines from the CPU to the
814 * GIC PPI inputs we use for the virt board.
816 const int timer_irq
[] = {
817 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
818 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
819 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
820 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
823 for (unsigned irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
824 qdev_connect_gpio_out(cpudev
, irq
,
825 qdev_get_gpio_in(vms
->gic
,
826 intidbase
+ timer_irq
[irq
]));
829 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
830 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
831 intidbase
+ ARCH_GIC_MAINT_IRQ
);
832 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
834 } else if (vms
->virt
) {
835 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
836 intidbase
+ ARCH_GIC_MAINT_IRQ
);
837 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
840 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
841 qdev_get_gpio_in(vms
->gic
, intidbase
844 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
845 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
846 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
847 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
848 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
849 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
850 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
853 fdt_add_gic_node(vms
);
855 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& vms
->its
) {
857 } else if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
862 static void create_uart(const VirtMachineState
*vms
, int uart
,
863 MemoryRegion
*mem
, Chardev
*chr
)
866 hwaddr base
= vms
->memmap
[uart
].base
;
867 hwaddr size
= vms
->memmap
[uart
].size
;
868 int irq
= vms
->irqmap
[uart
];
869 const char compat
[] = "arm,pl011\0arm,primecell";
870 const char clocknames
[] = "uartclk\0apb_pclk";
871 DeviceState
*dev
= qdev_new(TYPE_PL011
);
872 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
873 MachineState
*ms
= MACHINE(vms
);
875 qdev_prop_set_chr(dev
, "chardev", chr
);
876 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
877 memory_region_add_subregion(mem
, base
,
878 sysbus_mmio_get_region(s
, 0));
879 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
881 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
882 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
883 /* Note that we can't use setprop_string because of the embedded NUL */
884 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible",
885 compat
, sizeof(compat
));
886 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
888 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
889 GIC_FDT_IRQ_TYPE_SPI
, irq
,
890 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
891 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "clocks",
892 vms
->clock_phandle
, vms
->clock_phandle
);
893 qemu_fdt_setprop(ms
->fdt
, nodename
, "clock-names",
894 clocknames
, sizeof(clocknames
));
896 if (uart
== VIRT_UART
) {
897 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", nodename
);
899 /* Mark as not usable by the normal world */
900 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
901 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
903 qemu_fdt_setprop_string(ms
->fdt
, "/secure-chosen", "stdout-path",
910 static void create_rtc(const VirtMachineState
*vms
)
913 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
914 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
915 int irq
= vms
->irqmap
[VIRT_RTC
];
916 const char compat
[] = "arm,pl031\0arm,primecell";
917 MachineState
*ms
= MACHINE(vms
);
919 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
921 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
922 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
923 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
924 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
926 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
927 GIC_FDT_IRQ_TYPE_SPI
, irq
,
928 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
929 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
930 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
934 static DeviceState
*gpio_key_dev
;
935 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
937 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
940 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
942 /* use gpio Pin 3 for power button event */
943 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
947 static void create_gpio_keys(char *fdt
, DeviceState
*pl061_dev
,
950 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
951 qdev_get_gpio_in(pl061_dev
, 3));
953 qemu_fdt_add_subnode(fdt
, "/gpio-keys");
954 qemu_fdt_setprop_string(fdt
, "/gpio-keys", "compatible", "gpio-keys");
956 qemu_fdt_add_subnode(fdt
, "/gpio-keys/poweroff");
957 qemu_fdt_setprop_string(fdt
, "/gpio-keys/poweroff",
958 "label", "GPIO Key Poweroff");
959 qemu_fdt_setprop_cell(fdt
, "/gpio-keys/poweroff", "linux,code",
961 qemu_fdt_setprop_cells(fdt
, "/gpio-keys/poweroff",
962 "gpios", phandle
, 3, 0);
965 #define SECURE_GPIO_POWEROFF 0
966 #define SECURE_GPIO_RESET 1
968 static void create_secure_gpio_pwr(char *fdt
, DeviceState
*pl061_dev
,
971 DeviceState
*gpio_pwr_dev
;
974 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
976 /* connect secure pl061 to gpio-pwr */
977 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
978 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
979 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
980 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
982 qemu_fdt_add_subnode(fdt
, "/gpio-poweroff");
983 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "compatible",
985 qemu_fdt_setprop_cells(fdt
, "/gpio-poweroff",
986 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
987 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "status", "disabled");
988 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "secure-status",
991 qemu_fdt_add_subnode(fdt
, "/gpio-restart");
992 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "compatible",
994 qemu_fdt_setprop_cells(fdt
, "/gpio-restart",
995 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
996 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "status", "disabled");
997 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "secure-status",
1001 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
1005 DeviceState
*pl061_dev
;
1006 hwaddr base
= vms
->memmap
[gpio
].base
;
1007 hwaddr size
= vms
->memmap
[gpio
].size
;
1008 int irq
= vms
->irqmap
[gpio
];
1009 const char compat
[] = "arm,pl061\0arm,primecell";
1011 MachineState
*ms
= MACHINE(vms
);
1013 pl061_dev
= qdev_new("pl061");
1014 /* Pull lines down to 0 if not driven by the PL061 */
1015 qdev_prop_set_uint32(pl061_dev
, "pullups", 0);
1016 qdev_prop_set_uint32(pl061_dev
, "pulldowns", 0xff);
1017 s
= SYS_BUS_DEVICE(pl061_dev
);
1018 sysbus_realize_and_unref(s
, &error_fatal
);
1019 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
1020 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
1022 uint32_t phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1023 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
1024 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1025 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1027 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
1028 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#gpio-cells", 2);
1029 qemu_fdt_setprop(ms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
1030 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1031 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1032 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
1033 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
1034 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
1035 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", phandle
);
1037 if (gpio
!= VIRT_GPIO
) {
1038 /* Mark as not usable by the normal world */
1039 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1040 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1044 /* Child gpio devices */
1045 if (gpio
== VIRT_GPIO
) {
1046 create_gpio_keys(ms
->fdt
, pl061_dev
, phandle
);
1048 create_secure_gpio_pwr(ms
->fdt
, pl061_dev
, phandle
);
1052 static void create_virtio_devices(const VirtMachineState
*vms
)
1055 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
1056 MachineState
*ms
= MACHINE(vms
);
1058 /* We create the transports in forwards order. Since qbus_realize()
1059 * prepends (not appends) new child buses, the incrementing loop below will
1060 * create a list of virtio-mmio buses with decreasing base addresses.
1062 * When a -device option is processed from the command line,
1063 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1064 * order. The upshot is that -device options in increasing command line
1065 * order are mapped to virtio-mmio buses with decreasing base addresses.
1067 * When this code was originally written, that arrangement ensured that the
1068 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1069 * the first -device on the command line. (The end-to-end order is a
1070 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1071 * guest kernel's name-to-address assignment strategy.)
1073 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1074 * the message, if not necessarily the code, of commit 70161ff336.
1075 * Therefore the loop now establishes the inverse of the original intent.
1077 * Unfortunately, we can't counteract the kernel change by reversing the
1078 * loop; it would break existing command lines.
1080 * In any case, the kernel makes no guarantee about the stability of
1081 * enumeration order of virtio devices (as demonstrated by it changing
1082 * between kernel versions). For reliable and stable identification
1083 * of disks users must use UUIDs or similar mechanisms.
1085 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
1086 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1087 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1089 sysbus_create_simple("virtio-mmio", base
,
1090 qdev_get_gpio_in(vms
->gic
, irq
));
1093 /* We add dtb nodes in reverse order so that they appear in the finished
1094 * device tree lowest address first.
1096 * Note that this mapping is independent of the loop above. The previous
1097 * loop influences virtio device to virtio transport assignment, whereas
1098 * this loop controls how virtio transports are laid out in the dtb.
1100 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
1102 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1103 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1105 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
1106 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1107 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1108 "compatible", "virtio,mmio");
1109 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1111 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1112 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1113 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1114 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1119 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1121 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
1123 const char *alias_prop_name
)
1126 * Create a single flash device. We use the same parameters as
1127 * the flash devices on the Versatile Express board.
1129 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1131 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1132 qdev_prop_set_uint8(dev
, "width", 4);
1133 qdev_prop_set_uint8(dev
, "device-width", 2);
1134 qdev_prop_set_bit(dev
, "big-endian", false);
1135 qdev_prop_set_uint16(dev
, "id0", 0x89);
1136 qdev_prop_set_uint16(dev
, "id1", 0x18);
1137 qdev_prop_set_uint16(dev
, "id2", 0x00);
1138 qdev_prop_set_uint16(dev
, "id3", 0x00);
1139 qdev_prop_set_string(dev
, "name", name
);
1140 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1141 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1142 OBJECT(dev
), "drive");
1143 return PFLASH_CFI01(dev
);
1146 static void virt_flash_create(VirtMachineState
*vms
)
1148 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1149 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1152 static void virt_flash_map1(PFlashCFI01
*flash
,
1153 hwaddr base
, hwaddr size
,
1154 MemoryRegion
*sysmem
)
1156 DeviceState
*dev
= DEVICE(flash
);
1158 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1159 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1160 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1161 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1163 memory_region_add_subregion(sysmem
, base
,
1164 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1168 static void virt_flash_map(VirtMachineState
*vms
,
1169 MemoryRegion
*sysmem
,
1170 MemoryRegion
*secure_sysmem
)
1173 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1174 * sysmem is the system memory space. secure_sysmem is the secure view
1175 * of the system, and the first flash device should be made visible only
1176 * there. The second flash device is visible to both secure and nonsecure.
1177 * If sysmem == secure_sysmem this means there is no separate Secure
1178 * address space and both flash devices are generally visible.
1180 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1181 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1183 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1185 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1189 static void virt_flash_fdt(VirtMachineState
*vms
,
1190 MemoryRegion
*sysmem
,
1191 MemoryRegion
*secure_sysmem
)
1193 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1194 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1195 MachineState
*ms
= MACHINE(vms
);
1198 if (sysmem
== secure_sysmem
) {
1199 /* Report both flash devices as a single node in the DT */
1200 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1201 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1202 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1203 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1204 2, flashbase
, 2, flashsize
,
1205 2, flashbase
+ flashsize
, 2, flashsize
);
1206 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1210 * Report the devices as separate nodes so we can mark one as
1211 * only visible to the secure world.
1213 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1214 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1215 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1216 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1217 2, flashbase
, 2, flashsize
);
1218 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1219 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1220 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1223 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
+ flashsize
);
1224 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1225 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1226 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1227 2, flashbase
+ flashsize
, 2, flashsize
);
1228 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1233 static bool virt_firmware_init(VirtMachineState
*vms
,
1234 MemoryRegion
*sysmem
,
1235 MemoryRegion
*secure_sysmem
)
1238 const char *bios_name
;
1239 BlockBackend
*pflash_blk0
;
1241 /* Map legacy -drive if=pflash to machine properties */
1242 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1243 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1244 drive_get(IF_PFLASH
, 0, i
));
1247 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1249 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1251 bios_name
= MACHINE(vms
)->firmware
;
1258 error_report("The contents of the first flash device may be "
1259 "specified with -bios or with -drive if=pflash... "
1260 "but you cannot use both options at once");
1264 /* Fall back to -bios */
1266 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1268 error_report("Could not find ROM image '%s'", bios_name
);
1271 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1272 image_size
= load_image_mr(fname
, mr
);
1274 if (image_size
< 0) {
1275 error_report("Could not load ROM image '%s'", bios_name
);
1280 return pflash_blk0
|| bios_name
;
1283 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1285 MachineState
*ms
= MACHINE(vms
);
1286 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1287 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1291 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1292 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1294 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1295 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1296 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1297 "compatible", "qemu,fw-cfg-mmio");
1298 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1300 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1305 static void create_pcie_irq_map(const MachineState
*ms
,
1306 uint32_t gic_phandle
,
1307 int first_irq
, const char *nodename
)
1310 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1311 uint32_t *irq_map
= full_irq_map
;
1313 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1314 for (pin
= 0; pin
< 4; pin
++) {
1315 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1316 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1317 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1321 devfn
<< 8, 0, 0, /* devfn */
1322 pin
+ 1, /* PCI pin */
1323 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1325 /* Convert map to big endian */
1326 for (i
= 0; i
< 10; i
++) {
1327 irq_map
[i
] = cpu_to_be32(map
[i
]);
1333 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-map",
1334 full_irq_map
, sizeof(full_irq_map
));
1336 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupt-map-mask",
1337 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1342 static void create_smmu(const VirtMachineState
*vms
,
1346 const char compat
[] = "arm,smmu-v3";
1347 int irq
= vms
->irqmap
[VIRT_SMMU
];
1349 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1350 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1351 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1353 MachineState
*ms
= MACHINE(vms
);
1355 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1359 dev
= qdev_new(TYPE_ARM_SMMUV3
);
1361 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1363 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1364 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1365 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1366 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1367 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1370 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1371 qemu_fdt_add_subnode(ms
->fdt
, node
);
1372 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1373 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg", 2, base
, 2, size
);
1375 qemu_fdt_setprop_cells(ms
->fdt
, node
, "interrupts",
1376 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1377 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1378 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1379 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1381 qemu_fdt_setprop(ms
->fdt
, node
, "interrupt-names", irq_names
,
1384 qemu_fdt_setprop(ms
->fdt
, node
, "dma-coherent", NULL
, 0);
1386 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1388 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1392 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1394 const char compat
[] = "virtio,pci-iommu\0pci1af4,1057";
1395 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1396 MachineState
*ms
= MACHINE(vms
);
1399 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1401 node
= g_strdup_printf("%s/virtio_iommu@%x,%x", vms
->pciehb_nodename
,
1402 PCI_SLOT(bdf
), PCI_FUNC(bdf
));
1403 qemu_fdt_add_subnode(ms
->fdt
, node
);
1404 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1405 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg",
1406 1, bdf
<< 8, 1, 0, 1, 0,
1409 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1410 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1413 qemu_fdt_setprop_cells(ms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1414 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1415 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1418 static void create_pcie(VirtMachineState
*vms
)
1420 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1421 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1422 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1423 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1424 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1425 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1426 hwaddr base_ecam
, size_ecam
;
1427 hwaddr base
= base_mmio
;
1429 int irq
= vms
->irqmap
[VIRT_PCIE
];
1430 MemoryRegion
*mmio_alias
;
1431 MemoryRegion
*mmio_reg
;
1432 MemoryRegion
*ecam_alias
;
1433 MemoryRegion
*ecam_reg
;
1438 MachineState
*ms
= MACHINE(vms
);
1439 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
1441 dev
= qdev_new(TYPE_GPEX_HOST
);
1442 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1444 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1445 base_ecam
= vms
->memmap
[ecam_id
].base
;
1446 size_ecam
= vms
->memmap
[ecam_id
].size
;
1447 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1448 /* Map only the first size_ecam bytes of ECAM space */
1449 ecam_alias
= g_new0(MemoryRegion
, 1);
1450 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1451 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1452 ecam_reg
, 0, size_ecam
);
1453 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1455 /* Map the MMIO window into system address space so as to expose
1456 * the section of PCI MMIO space which starts at the same base address
1457 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1460 mmio_alias
= g_new0(MemoryRegion
, 1);
1461 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1462 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1463 mmio_reg
, base_mmio
, size_mmio
);
1464 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1466 if (vms
->highmem_mmio
) {
1467 /* Map high MMIO space */
1468 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1470 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1471 mmio_reg
, base_mmio_high
, size_mmio_high
);
1472 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1476 /* Map IO port space */
1477 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1479 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1480 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1481 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1482 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1485 pci
= PCI_HOST_BRIDGE(dev
);
1486 pci
->bypass_iommu
= vms
->default_bus_bypass_iommu
;
1487 vms
->bus
= pci
->bus
;
1489 for (i
= 0; i
< nb_nics
; i
++) {
1490 pci_nic_init_nofail(&nd_table
[i
], pci
->bus
, mc
->default_nic
, NULL
);
1494 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1495 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1496 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1497 "compatible", "pci-host-ecam-generic");
1498 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "pci");
1499 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 3);
1500 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 2);
1501 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "linux,pci-domain", 0);
1502 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "bus-range", 0,
1504 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1506 if (vms
->msi_phandle
) {
1507 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "msi-map",
1508 0, vms
->msi_phandle
, 0, 0x10000);
1511 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1512 2, base_ecam
, 2, size_ecam
);
1514 if (vms
->highmem_mmio
) {
1515 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1516 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1517 2, base_pio
, 2, size_pio
,
1518 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1519 2, base_mmio
, 2, size_mmio
,
1520 1, FDT_PCI_RANGE_MMIO_64BIT
,
1522 2, base_mmio_high
, 2, size_mmio_high
);
1524 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1525 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1526 2, base_pio
, 2, size_pio
,
1527 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1528 2, base_mmio
, 2, size_mmio
);
1531 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 1);
1532 create_pcie_irq_map(ms
, vms
->gic_phandle
, irq
, nodename
);
1535 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1537 switch (vms
->iommu
) {
1538 case VIRT_IOMMU_SMMUV3
:
1539 create_smmu(vms
, vms
->bus
);
1540 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "iommu-map",
1541 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1544 g_assert_not_reached();
1549 static void create_platform_bus(VirtMachineState
*vms
)
1554 MemoryRegion
*sysmem
= get_system_memory();
1556 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1557 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1558 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1559 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1560 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1561 vms
->platform_bus_dev
= dev
;
1563 s
= SYS_BUS_DEVICE(dev
);
1564 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1565 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1566 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1569 memory_region_add_subregion(sysmem
,
1570 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1571 sysbus_mmio_get_region(s
, 0));
1574 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1575 hwaddr base
, hwaddr size
,
1578 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1580 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1581 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1584 static void create_secure_ram(VirtMachineState
*vms
,
1585 MemoryRegion
*secure_sysmem
,
1586 MemoryRegion
*secure_tag_sysmem
)
1588 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1590 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1591 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1592 MachineState
*ms
= MACHINE(vms
);
1594 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1596 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1598 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1599 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1600 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "memory");
1601 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1602 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1603 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1605 if (secure_tag_sysmem
) {
1606 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1612 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1614 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1616 MachineState
*ms
= MACHINE(board
);
1619 *fdt_size
= board
->fdt_size
;
1623 static void virt_build_smbios(VirtMachineState
*vms
)
1625 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1626 MachineState
*ms
= MACHINE(vms
);
1627 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1628 uint8_t *smbios_tables
, *smbios_anchor
;
1629 size_t smbios_tables_len
, smbios_anchor_len
;
1630 struct smbios_phys_mem_area mem_array
;
1631 const char *product
= "QEMU Virtual Machine";
1633 if (kvm_enabled()) {
1634 product
= "KVM Virtual Machine";
1637 smbios_set_defaults("QEMU", product
,
1638 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1639 true, SMBIOS_ENTRY_POINT_TYPE_64
);
1641 /* build the array of physical mem area from base_memmap */
1642 mem_array
.address
= vms
->memmap
[VIRT_MEM
].base
;
1643 mem_array
.length
= ms
->ram_size
;
1645 smbios_get_tables(ms
, &mem_array
, 1,
1646 &smbios_tables
, &smbios_tables_len
,
1647 &smbios_anchor
, &smbios_anchor_len
,
1650 if (smbios_anchor
) {
1651 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1652 smbios_tables
, smbios_tables_len
);
1653 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1654 smbios_anchor
, smbios_anchor_len
);
1659 void virt_machine_done(Notifier
*notifier
, void *data
)
1661 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1663 MachineState
*ms
= MACHINE(vms
);
1664 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1665 struct arm_boot_info
*info
= &vms
->bootinfo
;
1666 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1669 * If the user provided a dtb, we assume the dynamic sysbus nodes
1670 * already are integrated there. This corresponds to a use case where
1671 * the dynamic sysbus nodes are complex and their generation is not yet
1672 * supported. In that case the user can take charge of the guest dt
1673 * while qemu takes charge of the qom stuff.
1675 if (info
->dtb_filename
== NULL
) {
1676 platform_bus_add_all_fdt_nodes(ms
->fdt
, "/intc",
1677 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1678 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1679 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1681 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1685 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1687 virt_acpi_setup(vms
);
1688 virt_build_smbios(vms
);
1691 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1693 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1694 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1696 if (!vmc
->disallow_affinity_adjustment
) {
1697 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1698 * GIC's target-list limitations. 32-bit KVM hosts currently
1699 * always create clusters of 4 CPUs, but that is expected to
1700 * change when they gain support for gicv3. When KVM is enabled
1701 * it will override the changes we make here, therefore our
1702 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1703 * and to improve SGI efficiency.
1705 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
1706 clustersz
= GIC_TARGETLIST_BITS
;
1708 clustersz
= GICV3_TARGETLIST_BITS
;
1711 return arm_cpu_mp_affinity(idx
, clustersz
);
1714 static inline bool *virt_get_high_memmap_enabled(VirtMachineState
*vms
,
1717 bool *enabled_array
[] = {
1718 &vms
->highmem_redists
,
1723 assert(ARRAY_SIZE(extended_memmap
) - VIRT_LOWMEMMAP_LAST
==
1724 ARRAY_SIZE(enabled_array
));
1725 assert(index
- VIRT_LOWMEMMAP_LAST
< ARRAY_SIZE(enabled_array
));
1727 return enabled_array
[index
- VIRT_LOWMEMMAP_LAST
];
1730 static void virt_set_high_memmap(VirtMachineState
*vms
,
1731 hwaddr base
, int pa_bits
)
1733 hwaddr region_base
, region_size
;
1734 bool *region_enabled
, fits
;
1737 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1738 region_enabled
= virt_get_high_memmap_enabled(vms
, i
);
1739 region_base
= ROUND_UP(base
, extended_memmap
[i
].size
);
1740 region_size
= extended_memmap
[i
].size
;
1742 vms
->memmap
[i
].base
= region_base
;
1743 vms
->memmap
[i
].size
= region_size
;
1746 * Check each device to see if it fits in the PA space,
1747 * moving highest_gpa as we go. For compatibility, move
1748 * highest_gpa for disabled fitting devices as well, if
1749 * the compact layout has been disabled.
1751 * For each device that doesn't fit, disable it.
1753 fits
= (region_base
+ region_size
) <= BIT_ULL(pa_bits
);
1754 *region_enabled
&= fits
;
1755 if (vms
->highmem_compact
&& !*region_enabled
) {
1759 base
= region_base
+ region_size
;
1761 vms
->highest_gpa
= base
- 1;
1766 static void virt_set_memmap(VirtMachineState
*vms
, int pa_bits
)
1768 MachineState
*ms
= MACHINE(vms
);
1769 hwaddr base
, device_memory_base
, device_memory_size
, memtop
;
1772 vms
->memmap
= extended_memmap
;
1774 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1775 vms
->memmap
[i
] = base_memmap
[i
];
1778 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1779 error_report("unsupported number of memory slots: %"PRIu64
,
1785 * !highmem is exactly the same as limiting the PA space to 32bit,
1786 * irrespective of the underlying capabilities of the HW.
1788 if (!vms
->highmem
) {
1793 * We compute the base of the high IO region depending on the
1794 * amount of initial and device memory. The device memory start/size
1795 * is aligned on 1GiB. We never put the high IO region below 256GiB
1796 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1797 * The device region size assumes 1GiB page max alignment per slot.
1799 device_memory_base
=
1800 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1801 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1803 /* Base address of the high IO region */
1804 memtop
= base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1805 if (memtop
> BIT_ULL(pa_bits
)) {
1806 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
1807 pa_bits
, memtop
- BIT_ULL(pa_bits
));
1810 if (base
< device_memory_base
) {
1811 error_report("maxmem/slots too huge");
1814 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1815 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1818 /* We know for sure that at least the memory fits in the PA space */
1819 vms
->highest_gpa
= memtop
- 1;
1821 virt_set_high_memmap(vms
, base
, pa_bits
);
1823 if (device_memory_size
> 0) {
1824 machine_memory_devices_init(ms
, device_memory_base
, device_memory_size
);
1828 static VirtGICType
finalize_gic_version_do(const char *accel_name
,
1829 VirtGICType gic_version
,
1831 unsigned int max_cpus
)
1833 /* Convert host/max/nosel to GIC version number */
1834 switch (gic_version
) {
1835 case VIRT_GIC_VERSION_HOST
:
1836 if (!kvm_enabled()) {
1837 error_report("gic-version=host requires KVM");
1841 /* For KVM, gic-version=host means gic-version=max */
1842 return finalize_gic_version_do(accel_name
, VIRT_GIC_VERSION_MAX
,
1843 gics_supported
, max_cpus
);
1844 case VIRT_GIC_VERSION_MAX
:
1845 if (gics_supported
& VIRT_GIC_VERSION_4_MASK
) {
1846 gic_version
= VIRT_GIC_VERSION_4
;
1847 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1848 gic_version
= VIRT_GIC_VERSION_3
;
1850 gic_version
= VIRT_GIC_VERSION_2
;
1853 case VIRT_GIC_VERSION_NOSEL
:
1854 if ((gics_supported
& VIRT_GIC_VERSION_2_MASK
) &&
1855 max_cpus
<= GIC_NCPU
) {
1856 gic_version
= VIRT_GIC_VERSION_2
;
1857 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1859 * in case the host does not support v2 emulation or
1860 * the end-user requested more than 8 VCPUs we now default
1861 * to v3. In any case defaulting to v2 would be broken.
1863 gic_version
= VIRT_GIC_VERSION_3
;
1864 } else if (max_cpus
> GIC_NCPU
) {
1865 error_report("%s only supports GICv2 emulation but more than 8 "
1866 "vcpus are requested", accel_name
);
1870 case VIRT_GIC_VERSION_2
:
1871 case VIRT_GIC_VERSION_3
:
1872 case VIRT_GIC_VERSION_4
:
1876 /* Check chosen version is effectively supported */
1877 switch (gic_version
) {
1878 case VIRT_GIC_VERSION_2
:
1879 if (!(gics_supported
& VIRT_GIC_VERSION_2_MASK
)) {
1880 error_report("%s does not support GICv2 emulation", accel_name
);
1884 case VIRT_GIC_VERSION_3
:
1885 if (!(gics_supported
& VIRT_GIC_VERSION_3_MASK
)) {
1886 error_report("%s does not support GICv3 emulation", accel_name
);
1890 case VIRT_GIC_VERSION_4
:
1891 if (!(gics_supported
& VIRT_GIC_VERSION_4_MASK
)) {
1892 error_report("%s does not support GICv4 emulation, is virtualization=on?",
1898 error_report("logic error in finalize_gic_version");
1907 * finalize_gic_version - Determines the final gic_version
1908 * according to the gic-version property
1910 * Default GIC type is v2
1912 static void finalize_gic_version(VirtMachineState
*vms
)
1914 const char *accel_name
= current_accel_name();
1915 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1916 int gics_supported
= 0;
1918 /* Determine which GIC versions the current environment supports */
1919 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1920 int probe_bitmap
= kvm_arm_vgic_probe();
1922 if (!probe_bitmap
) {
1923 error_report("Unable to determine GIC version supported by host");
1927 if (probe_bitmap
& KVM_ARM_VGIC_V2
) {
1928 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1930 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1931 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
1933 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
1934 /* KVM w/o kernel irqchip can only deal with GICv2 */
1935 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1936 accel_name
= "KVM with kernel-irqchip=off";
1937 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
1938 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1939 if (module_object_class_by_name("arm-gicv3")) {
1940 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
1942 /* GICv4 only makes sense if CPU has EL2 */
1943 gics_supported
|= VIRT_GIC_VERSION_4_MASK
;
1947 error_report("Unsupported accelerator, can not determine GIC support");
1952 * Then convert helpers like host/max to concrete GIC versions and ensure
1953 * the desired version is supported
1955 vms
->gic_version
= finalize_gic_version_do(accel_name
, vms
->gic_version
,
1956 gics_supported
, max_cpus
);
1960 * virt_cpu_post_init() must be called after the CPUs have
1961 * been realized and the GIC has been created.
1963 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
1965 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1966 bool aarch64
, pmu
, steal_time
;
1969 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
1970 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
1971 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
1972 "kvm-steal-time", NULL
);
1974 if (kvm_enabled()) {
1975 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
1976 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
1979 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
1980 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
1982 /* The memory region size must be a multiple of host page size. */
1983 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
1985 if (pvtime_size
> pvtime_reg_size
) {
1986 error_report("pvtime requires a %" HWADDR_PRId
1987 " byte memory region for %d CPUs,"
1988 " but only %" HWADDR_PRId
" has been reserved",
1989 pvtime_size
, max_cpus
, pvtime_reg_size
);
1993 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
1994 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
1999 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
2000 if (kvm_irqchip_in_kernel()) {
2001 kvm_arm_pmu_set_irq(cpu
, VIRTUAL_PMU_IRQ
);
2003 kvm_arm_pmu_init(cpu
);
2006 kvm_arm_pvtime_init(ARM_CPU(cpu
), pvtime_reg_base
2008 * PVTIME_SIZE_PER_CPU
);
2012 if (aarch64
&& vms
->highmem
) {
2013 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2014 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
2016 if (pamax
< requested_pa_size
) {
2017 error_report("VCPU supports less PA bits (%d) than "
2018 "requested by the memory map (%d)",
2019 pamax
, requested_pa_size
);
2026 static void machvirt_init(MachineState
*machine
)
2028 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
2029 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
2030 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2031 const CPUArchIdList
*possible_cpus
;
2032 MemoryRegion
*sysmem
= get_system_memory();
2033 MemoryRegion
*secure_sysmem
= NULL
;
2034 MemoryRegion
*tag_sysmem
= NULL
;
2035 MemoryRegion
*secure_tag_sysmem
= NULL
;
2036 int n
, virt_max_cpus
;
2037 bool firmware_loaded
;
2038 bool aarch64
= true;
2039 bool has_ged
= !vmc
->no_ged
;
2040 unsigned int smp_cpus
= machine
->smp
.cpus
;
2041 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2043 if (!cpu_type_valid(machine
->cpu_type
)) {
2044 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
2048 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2051 * In accelerated mode, the memory map is computed earlier in kvm_type()
2052 * to create a VM with the right number of IPA bits.
2060 * Instantiate a temporary CPU object to find out about what
2061 * we are about to deal with. Once this is done, get rid of
2064 cpuobj
= object_new(possible_cpus
->cpus
[0].type
);
2065 armcpu
= ARM_CPU(cpuobj
);
2067 pa_bits
= arm_pamax(armcpu
);
2069 object_unref(cpuobj
);
2071 virt_set_memmap(vms
, pa_bits
);
2074 /* We can probe only here because during property set
2075 * KVM is not available yet
2077 finalize_gic_version(vms
);
2081 * The Secure view of the world is the same as the NonSecure,
2082 * but with a few extra devices. Create it as a container region
2083 * containing the system memory at low priority; any secure-only
2084 * devices go in at higher priority and take precedence.
2086 secure_sysmem
= g_new(MemoryRegion
, 1);
2087 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
2089 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
2092 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
2093 secure_sysmem
?: sysmem
);
2095 /* If we have an EL3 boot ROM then the assumption is that it will
2096 * implement PSCI itself, so disable QEMU's internal implementation
2097 * so it doesn't get in the way. Instead of starting secondary
2098 * CPUs in PSCI powerdown state we will start them all running and
2099 * let the boot ROM sort them out.
2100 * The usual case is that we do use QEMU's PSCI implementation;
2101 * if the guest has EL2 then we will use SMC as the conduit,
2102 * and otherwise we will use HVC (for backwards compatibility and
2103 * because if we're using KVM then we must use HVC).
2105 if (vms
->secure
&& firmware_loaded
) {
2106 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
2107 } else if (vms
->virt
) {
2108 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
2110 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
2114 * The maximum number of CPUs depends on the GIC version, or on how
2115 * many redistributors we can fit into the memory map (which in turn
2116 * depends on whether this is a GICv3 or v4).
2118 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
2119 virt_max_cpus
= GIC_NCPU
;
2121 virt_max_cpus
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
2122 if (vms
->highmem_redists
) {
2123 virt_max_cpus
+= virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
2127 if (max_cpus
> virt_max_cpus
) {
2128 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2129 "supported by machine 'mach-virt' (%d)",
2130 max_cpus
, virt_max_cpus
);
2131 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& !vms
->highmem_redists
) {
2132 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2138 if (vms
->secure
&& (kvm_enabled() || hvf_enabled())) {
2139 error_report("mach-virt: %s does not support providing "
2140 "Security extensions (TrustZone) to the guest CPU",
2141 current_accel_name());
2145 if (vms
->virt
&& (kvm_enabled() || hvf_enabled())) {
2146 error_report("mach-virt: %s does not support providing "
2147 "Virtualization extensions to the guest CPU",
2148 current_accel_name());
2152 if (vms
->mte
&& (kvm_enabled() || hvf_enabled())) {
2153 error_report("mach-virt: %s does not support providing "
2154 "MTE to the guest CPU",
2155 current_accel_name());
2161 assert(possible_cpus
->len
== max_cpus
);
2162 for (n
= 0; n
< possible_cpus
->len
; n
++) {
2166 if (n
>= smp_cpus
) {
2170 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
2171 object_property_set_int(cpuobj
, "mp-affinity",
2172 possible_cpus
->cpus
[n
].arch_id
, NULL
);
2177 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
2180 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
2183 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
2186 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
2187 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
2190 if (vmc
->kvm_no_adjvtime
&&
2191 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
2192 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
2195 if (vmc
->no_kvm_steal_time
&&
2196 object_property_find(cpuobj
, "kvm-steal-time")) {
2197 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
2200 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
2201 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
2204 if (vmc
->no_tcg_lpa2
&& object_property_find(cpuobj
, "lpa2")) {
2205 object_property_set_bool(cpuobj
, "lpa2", false, NULL
);
2208 if (object_property_find(cpuobj
, "reset-cbar")) {
2209 object_property_set_int(cpuobj
, "reset-cbar",
2210 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
2214 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
2217 object_property_set_link(cpuobj
, "secure-memory",
2218 OBJECT(secure_sysmem
), &error_abort
);
2222 /* Create the memory region only once, but link to all cpus. */
2225 * The property exists only if MemTag is supported.
2226 * If it is, we must allocate the ram to back that up.
2228 if (!object_property_find(cpuobj
, "tag-memory")) {
2229 error_report("MTE requested, but not supported "
2230 "by the guest CPU");
2234 tag_sysmem
= g_new(MemoryRegion
, 1);
2235 memory_region_init(tag_sysmem
, OBJECT(machine
),
2236 "tag-memory", UINT64_MAX
/ 32);
2239 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
2240 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
2241 "secure-tag-memory", UINT64_MAX
/ 32);
2243 /* As with ram, secure-tag takes precedence over tag. */
2244 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2249 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2252 object_property_set_link(cpuobj
, "secure-tag-memory",
2253 OBJECT(secure_tag_sysmem
),
2258 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2259 object_unref(cpuobj
);
2261 fdt_add_timer_nodes(vms
);
2262 fdt_add_cpu_nodes(vms
);
2264 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2267 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2269 create_gic(vms
, sysmem
);
2271 virt_cpu_post_init(vms
, sysmem
);
2273 fdt_add_pmu_nodes(vms
);
2275 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
2278 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2279 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
2283 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2284 machine
->ram_size
, "mach-virt.tag");
2287 vms
->highmem_ecam
&= (!firmware_loaded
|| aarch64
);
2293 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2294 vms
->acpi_dev
= create_acpi_ged(vms
);
2296 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2299 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2300 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2303 /* connect powerdown request */
2304 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2305 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2307 /* Create mmio transports, so the user can create virtio backends
2308 * (which will be automatically plugged in to the transports). If
2309 * no backend is created the transport will just sit harmlessly idle.
2311 create_virtio_devices(vms
);
2313 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2314 rom_set_fw(vms
->fw_cfg
);
2316 create_platform_bus(vms
);
2318 if (machine
->nvdimms_state
->is_enabled
) {
2319 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2320 .space_id
= AML_AS_SYSTEM_MEMORY
,
2321 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2322 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2325 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2326 arm_virt_nvdimm_acpi_dsmio
,
2327 vms
->fw_cfg
, OBJECT(vms
));
2330 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2331 vms
->bootinfo
.board_id
= -1;
2332 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2333 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2334 vms
->bootinfo
.skip_dtb_autoload
= true;
2335 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2336 vms
->bootinfo
.psci_conduit
= vms
->psci_conduit
;
2337 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2339 vms
->machine_done
.notify
= virt_machine_done
;
2340 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2343 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2345 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2350 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2352 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2354 vms
->secure
= value
;
2357 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2359 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2364 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2366 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2371 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2373 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2375 return vms
->highmem
;
2378 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2380 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2382 vms
->highmem
= value
;
2385 static bool virt_get_compact_highmem(Object
*obj
, Error
**errp
)
2387 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2389 return vms
->highmem_compact
;
2392 static void virt_set_compact_highmem(Object
*obj
, bool value
, Error
**errp
)
2394 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2396 vms
->highmem_compact
= value
;
2399 static bool virt_get_highmem_redists(Object
*obj
, Error
**errp
)
2401 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2403 return vms
->highmem_redists
;
2406 static void virt_set_highmem_redists(Object
*obj
, bool value
, Error
**errp
)
2408 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2410 vms
->highmem_redists
= value
;
2413 static bool virt_get_highmem_ecam(Object
*obj
, Error
**errp
)
2415 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2417 return vms
->highmem_ecam
;
2420 static void virt_set_highmem_ecam(Object
*obj
, bool value
, Error
**errp
)
2422 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2424 vms
->highmem_ecam
= value
;
2427 static bool virt_get_highmem_mmio(Object
*obj
, Error
**errp
)
2429 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2431 return vms
->highmem_mmio
;
2434 static void virt_set_highmem_mmio(Object
*obj
, bool value
, Error
**errp
)
2436 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2438 vms
->highmem_mmio
= value
;
2442 static bool virt_get_its(Object
*obj
, Error
**errp
)
2444 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2449 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2451 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2456 static bool virt_get_dtb_randomness(Object
*obj
, Error
**errp
)
2458 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2460 return vms
->dtb_randomness
;
2463 static void virt_set_dtb_randomness(Object
*obj
, bool value
, Error
**errp
)
2465 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2467 vms
->dtb_randomness
= value
;
2470 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2472 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2474 return g_strdup(vms
->oem_id
);
2477 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2479 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2480 size_t len
= strlen(value
);
2484 "User specified oem-id value is bigger than 6 bytes in size");
2488 strncpy(vms
->oem_id
, value
, 6);
2491 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2493 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2495 return g_strdup(vms
->oem_table_id
);
2498 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2501 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2502 size_t len
= strlen(value
);
2506 "User specified oem-table-id value is bigger than 8 bytes in size");
2509 strncpy(vms
->oem_table_id
, value
, 8);
2513 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2515 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2521 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2522 void *opaque
, Error
**errp
)
2524 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2525 OnOffAuto acpi
= vms
->acpi
;
2527 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2530 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2531 void *opaque
, Error
**errp
)
2533 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2535 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2538 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2540 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2545 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2547 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2552 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2554 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2559 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2561 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2566 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2568 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2571 switch (vms
->gic_version
) {
2572 case VIRT_GIC_VERSION_4
:
2575 case VIRT_GIC_VERSION_3
:
2582 return g_strdup(val
);
2585 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2587 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2589 if (!strcmp(value
, "4")) {
2590 vms
->gic_version
= VIRT_GIC_VERSION_4
;
2591 } else if (!strcmp(value
, "3")) {
2592 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2593 } else if (!strcmp(value
, "2")) {
2594 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2595 } else if (!strcmp(value
, "host")) {
2596 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2597 } else if (!strcmp(value
, "max")) {
2598 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2600 error_setg(errp
, "Invalid gic-version value");
2601 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2605 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2607 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2609 switch (vms
->iommu
) {
2610 case VIRT_IOMMU_NONE
:
2611 return g_strdup("none");
2612 case VIRT_IOMMU_SMMUV3
:
2613 return g_strdup("smmuv3");
2615 g_assert_not_reached();
2619 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2621 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2623 if (!strcmp(value
, "smmuv3")) {
2624 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2625 } else if (!strcmp(value
, "none")) {
2626 vms
->iommu
= VIRT_IOMMU_NONE
;
2628 error_setg(errp
, "Invalid iommu value");
2629 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2633 static bool virt_get_default_bus_bypass_iommu(Object
*obj
, Error
**errp
)
2635 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2637 return vms
->default_bus_bypass_iommu
;
2640 static void virt_set_default_bus_bypass_iommu(Object
*obj
, bool value
,
2643 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2645 vms
->default_bus_bypass_iommu
= value
;
2648 static CpuInstanceProperties
2649 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2651 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2652 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2654 assert(cpu_index
< possible_cpus
->len
);
2655 return possible_cpus
->cpus
[cpu_index
].props
;
2658 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2660 int64_t socket_id
= ms
->possible_cpus
->cpus
[idx
].props
.socket_id
;
2662 return socket_id
% ms
->numa_state
->num_nodes
;
2665 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2668 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2669 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2670 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2672 if (ms
->possible_cpus
) {
2673 assert(ms
->possible_cpus
->len
== max_cpus
);
2674 return ms
->possible_cpus
;
2677 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2678 sizeof(CPUArchId
) * max_cpus
);
2679 ms
->possible_cpus
->len
= max_cpus
;
2680 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2681 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2682 ms
->possible_cpus
->cpus
[n
].arch_id
=
2683 virt_cpu_mp_affinity(vms
, n
);
2685 assert(!mc
->smp_props
.dies_supported
);
2686 ms
->possible_cpus
->cpus
[n
].props
.has_socket_id
= true;
2687 ms
->possible_cpus
->cpus
[n
].props
.socket_id
=
2688 n
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
);
2689 ms
->possible_cpus
->cpus
[n
].props
.has_cluster_id
= true;
2690 ms
->possible_cpus
->cpus
[n
].props
.cluster_id
=
2691 (n
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
;
2692 ms
->possible_cpus
->cpus
[n
].props
.has_core_id
= true;
2693 ms
->possible_cpus
->cpus
[n
].props
.core_id
=
2694 (n
/ ms
->smp
.threads
) % ms
->smp
.cores
;
2695 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2696 ms
->possible_cpus
->cpus
[n
].props
.thread_id
=
2697 n
% ms
->smp
.threads
;
2699 return ms
->possible_cpus
;
2702 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2705 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2706 const MachineState
*ms
= MACHINE(hotplug_dev
);
2707 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2709 if (!vms
->acpi_dev
) {
2711 "memory hotplug is not enabled: missing acpi-ged device");
2716 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2720 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2721 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2725 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2728 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2729 DeviceState
*dev
, Error
**errp
)
2731 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2732 MachineState
*ms
= MACHINE(hotplug_dev
);
2733 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2735 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2738 nvdimm_plug(ms
->nvdimms_state
);
2741 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2745 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2746 DeviceState
*dev
, Error
**errp
)
2748 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2750 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2751 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2752 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2753 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2754 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2755 hwaddr db_start
= 0, db_end
= 0;
2756 QList
*reserved_regions
;
2757 char *resv_prop_str
;
2759 if (vms
->iommu
!= VIRT_IOMMU_NONE
) {
2760 error_setg(errp
, "virt machine does not support multiple IOMMUs");
2764 switch (vms
->msi_controller
) {
2765 case VIRT_MSI_CTRL_NONE
:
2767 case VIRT_MSI_CTRL_ITS
:
2768 /* GITS_TRANSLATER page */
2769 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2770 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2771 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2773 case VIRT_MSI_CTRL_GICV2M
:
2774 /* MSI_SETSPI_NS page */
2775 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2776 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2779 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2781 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2783 reserved_regions
= qlist_new();
2784 qlist_append_str(reserved_regions
, resv_prop_str
);
2785 qdev_prop_set_array(dev
, "reserved-regions", reserved_regions
);
2786 g_free(resv_prop_str
);
2790 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2791 DeviceState
*dev
, Error
**errp
)
2793 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2795 if (vms
->platform_bus_dev
) {
2796 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2798 if (device_is_dynamic_sysbus(mc
, dev
)) {
2799 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2800 SYS_BUS_DEVICE(dev
));
2804 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2805 virt_memory_plug(hotplug_dev
, dev
, errp
);
2806 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2807 virtio_md_pci_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2810 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2811 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2813 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2814 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2815 create_virtio_iommu_dt_bindings(vms
);
2819 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2820 DeviceState
*dev
, Error
**errp
)
2822 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2824 if (!vms
->acpi_dev
) {
2826 "memory hotplug is not enabled: missing acpi-ged device");
2830 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2831 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
2835 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2839 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2840 DeviceState
*dev
, Error
**errp
)
2842 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2843 Error
*local_err
= NULL
;
2845 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2850 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2851 qdev_unrealize(dev
);
2854 error_propagate(errp
, local_err
);
2857 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2858 DeviceState
*dev
, Error
**errp
)
2860 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2861 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2862 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2863 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
),
2866 error_setg(errp
, "device unplug request for unsupported device"
2867 " type: %s", object_get_typename(OBJECT(dev
)));
2871 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2872 DeviceState
*dev
, Error
**errp
)
2874 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2875 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2876 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2877 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2879 error_setg(errp
, "virt: device unplug for unsupported device"
2880 " type: %s", object_get_typename(OBJECT(dev
)));
2884 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2887 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2889 if (device_is_dynamic_sysbus(mc
, dev
) ||
2890 object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2891 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
) ||
2892 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2893 return HOTPLUG_HANDLER(machine
);
2899 * for arm64 kvm_type [7-0] encodes the requested number of bits
2900 * in the IPA address space
2902 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2904 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2905 int max_vm_pa_size
, requested_pa_size
;
2908 max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
, &fixed_ipa
);
2910 /* we freeze the memory map to compute the highest gpa */
2911 virt_set_memmap(vms
, max_vm_pa_size
);
2913 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2916 * KVM requires the IPA size to be at least 32 bits.
2918 if (requested_pa_size
< 32) {
2919 requested_pa_size
= 32;
2922 if (requested_pa_size
> max_vm_pa_size
) {
2923 error_report("-m and ,maxmem option values "
2924 "require an IPA range (%d bits) larger than "
2925 "the one supported by the host (%d bits)",
2926 requested_pa_size
, max_vm_pa_size
);
2930 * We return the requested PA log size, unless KVM only supports
2931 * the implicit legacy 40b IPA setting, in which case the kvm_type
2934 return fixed_ipa
? 0 : requested_pa_size
;
2937 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2939 MachineClass
*mc
= MACHINE_CLASS(oc
);
2940 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2942 mc
->init
= machvirt_init
;
2943 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2944 * The value may be reduced later when we have more information about the
2945 * configuration of the particular instance.
2948 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
2949 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
2950 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
2951 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
2953 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
2955 mc
->block_default_type
= IF_VIRTIO
;
2957 mc
->pci_allow_0_address
= true;
2958 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2959 mc
->minimum_page_bits
= 12;
2960 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
2961 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
2963 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
2965 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("max");
2967 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
2968 mc
->kvm_type
= virt_kvm_type
;
2969 assert(!mc
->get_hotplug_handler
);
2970 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
2971 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
2972 hc
->plug
= virt_machine_device_plug_cb
;
2973 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
2974 hc
->unplug
= virt_machine_device_unplug_cb
;
2975 mc
->nvdimm_supported
= true;
2976 mc
->smp_props
.clusters_supported
= true;
2977 mc
->auto_enable_numa_with_memhp
= true;
2978 mc
->auto_enable_numa_with_memdev
= true;
2979 /* platform instead of architectural choice */
2980 mc
->cpu_cluster_has_numa_boundary
= true;
2981 mc
->default_ram_id
= "mach-virt.ram";
2982 mc
->default_nic
= "virtio-net-pci";
2984 object_class_property_add(oc
, "acpi", "OnOffAuto",
2985 virt_get_acpi
, virt_set_acpi
,
2987 object_class_property_set_description(oc
, "acpi",
2989 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
2991 object_class_property_set_description(oc
, "secure",
2992 "Set on/off to enable/disable the ARM "
2993 "Security Extensions (TrustZone)");
2995 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
2997 object_class_property_set_description(oc
, "virtualization",
2998 "Set on/off to enable/disable emulating a "
2999 "guest CPU which implements the ARM "
3000 "Virtualization Extensions");
3002 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
3004 object_class_property_set_description(oc
, "highmem",
3005 "Set on/off to enable/disable using "
3006 "physical address space above 32 bits");
3008 object_class_property_add_bool(oc
, "compact-highmem",
3009 virt_get_compact_highmem
,
3010 virt_set_compact_highmem
);
3011 object_class_property_set_description(oc
, "compact-highmem",
3012 "Set on/off to enable/disable compact "
3013 "layout for high memory regions");
3015 object_class_property_add_bool(oc
, "highmem-redists",
3016 virt_get_highmem_redists
,
3017 virt_set_highmem_redists
);
3018 object_class_property_set_description(oc
, "highmem-redists",
3019 "Set on/off to enable/disable high "
3020 "memory region for GICv3 or GICv4 "
3023 object_class_property_add_bool(oc
, "highmem-ecam",
3024 virt_get_highmem_ecam
,
3025 virt_set_highmem_ecam
);
3026 object_class_property_set_description(oc
, "highmem-ecam",
3027 "Set on/off to enable/disable high "
3028 "memory region for PCI ECAM");
3030 object_class_property_add_bool(oc
, "highmem-mmio",
3031 virt_get_highmem_mmio
,
3032 virt_set_highmem_mmio
);
3033 object_class_property_set_description(oc
, "highmem-mmio",
3034 "Set on/off to enable/disable high "
3035 "memory region for PCI MMIO");
3037 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
3038 virt_set_gic_version
);
3039 object_class_property_set_description(oc
, "gic-version",
3041 "Valid values are 2, 3, 4, host and max");
3043 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
3044 object_class_property_set_description(oc
, "iommu",
3045 "Set the IOMMU type. "
3046 "Valid values are none and smmuv3");
3048 object_class_property_add_bool(oc
, "default-bus-bypass-iommu",
3049 virt_get_default_bus_bypass_iommu
,
3050 virt_set_default_bus_bypass_iommu
);
3051 object_class_property_set_description(oc
, "default-bus-bypass-iommu",
3052 "Set on/off to enable/disable "
3053 "bypass_iommu for default root bus");
3055 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
3057 object_class_property_set_description(oc
, "ras",
3058 "Set on/off to enable/disable reporting host memory errors "
3059 "to a KVM guest using ACPI and guest external abort exceptions");
3061 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
3062 object_class_property_set_description(oc
, "mte",
3063 "Set on/off to enable/disable emulating a "
3064 "guest CPU which implements the ARM "
3065 "Memory Tagging Extension");
3067 object_class_property_add_bool(oc
, "its", virt_get_its
,
3069 object_class_property_set_description(oc
, "its",
3070 "Set on/off to enable/disable "
3071 "ITS instantiation");
3073 object_class_property_add_bool(oc
, "dtb-randomness",
3074 virt_get_dtb_randomness
,
3075 virt_set_dtb_randomness
);
3076 object_class_property_set_description(oc
, "dtb-randomness",
3077 "Set off to disable passing random or "
3078 "non-deterministic dtb nodes to guest");
3080 object_class_property_add_bool(oc
, "dtb-kaslr-seed",
3081 virt_get_dtb_randomness
,
3082 virt_set_dtb_randomness
);
3083 object_class_property_set_description(oc
, "dtb-kaslr-seed",
3084 "Deprecated synonym of dtb-randomness");
3086 object_class_property_add_str(oc
, "x-oem-id",
3089 object_class_property_set_description(oc
, "x-oem-id",
3090 "Override the default value of field OEMID "
3091 "in ACPI table header."
3092 "The string may be up to 6 bytes in size");
3095 object_class_property_add_str(oc
, "x-oem-table-id",
3096 virt_get_oem_table_id
,
3097 virt_set_oem_table_id
);
3098 object_class_property_set_description(oc
, "x-oem-table-id",
3099 "Override the default value of field OEM Table ID "
3100 "in ACPI table header."
3101 "The string may be up to 8 bytes in size");
3105 static void virt_instance_init(Object
*obj
)
3107 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
3108 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
3110 /* EL3 is disabled by default on virt: this makes us consistent
3111 * between KVM and TCG for this board, and it also allows us to
3112 * boot UEFI blobs which assume no TrustZone support.
3114 vms
->secure
= false;
3116 /* EL2 is also disabled by default, for similar reasons */
3119 /* High memory is enabled by default */
3120 vms
->highmem
= true;
3121 vms
->highmem_compact
= !vmc
->no_highmem_compact
;
3122 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
3124 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
3125 vms
->highmem_mmio
= true;
3126 vms
->highmem_redists
= true;
3131 /* Default allows ITS instantiation */
3134 if (vmc
->no_tcg_its
) {
3135 vms
->tcg_its
= false;
3137 vms
->tcg_its
= true;
3141 /* Default disallows iommu instantiation */
3142 vms
->iommu
= VIRT_IOMMU_NONE
;
3144 /* The default root bus is attached to iommu by default */
3145 vms
->default_bus_bypass_iommu
= false;
3147 /* Default disallows RAS instantiation */
3150 /* MTE is disabled by default. */
3153 /* Supply kaslr-seed and rng-seed by default */
3154 vms
->dtb_randomness
= true;
3156 vms
->irqmap
= a15irqmap
;
3158 virt_flash_create(vms
);
3160 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
3161 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
3164 static const TypeInfo virt_machine_info
= {
3165 .name
= TYPE_VIRT_MACHINE
,
3166 .parent
= TYPE_MACHINE
,
3168 .instance_size
= sizeof(VirtMachineState
),
3169 .class_size
= sizeof(VirtMachineClass
),
3170 .class_init
= virt_machine_class_init
,
3171 .instance_init
= virt_instance_init
,
3172 .interfaces
= (InterfaceInfo
[]) {
3173 { TYPE_HOTPLUG_HANDLER
},
3178 static void machvirt_machine_init(void)
3180 type_register_static(&virt_machine_info
);
3182 type_init(machvirt_machine_init
);
3184 static void virt_machine_8_2_options(MachineClass
*mc
)
3187 DEFINE_VIRT_MACHINE_AS_LATEST(8, 2)
3189 static void virt_machine_8_1_options(MachineClass
*mc
)
3191 virt_machine_8_2_options(mc
);
3192 compat_props_add(mc
->compat_props
, hw_compat_8_1
, hw_compat_8_1_len
);
3194 DEFINE_VIRT_MACHINE(8, 1)
3196 static void virt_machine_8_0_options(MachineClass
*mc
)
3198 virt_machine_8_1_options(mc
);
3199 compat_props_add(mc
->compat_props
, hw_compat_8_0
, hw_compat_8_0_len
);
3201 DEFINE_VIRT_MACHINE(8, 0)
3203 static void virt_machine_7_2_options(MachineClass
*mc
)
3205 virt_machine_8_0_options(mc
);
3206 compat_props_add(mc
->compat_props
, hw_compat_7_2
, hw_compat_7_2_len
);
3208 DEFINE_VIRT_MACHINE(7, 2)
3210 static void virt_machine_7_1_options(MachineClass
*mc
)
3212 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3214 virt_machine_7_2_options(mc
);
3215 compat_props_add(mc
->compat_props
, hw_compat_7_1
, hw_compat_7_1_len
);
3216 /* Compact layout for high memory regions was introduced with 7.2 */
3217 vmc
->no_highmem_compact
= true;
3219 DEFINE_VIRT_MACHINE(7, 1)
3221 static void virt_machine_7_0_options(MachineClass
*mc
)
3223 virt_machine_7_1_options(mc
);
3224 compat_props_add(mc
->compat_props
, hw_compat_7_0
, hw_compat_7_0_len
);
3226 DEFINE_VIRT_MACHINE(7, 0)
3228 static void virt_machine_6_2_options(MachineClass
*mc
)
3230 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3232 virt_machine_7_0_options(mc
);
3233 compat_props_add(mc
->compat_props
, hw_compat_6_2
, hw_compat_6_2_len
);
3234 vmc
->no_tcg_lpa2
= true;
3236 DEFINE_VIRT_MACHINE(6, 2)
3238 static void virt_machine_6_1_options(MachineClass
*mc
)
3240 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3242 virt_machine_6_2_options(mc
);
3243 compat_props_add(mc
->compat_props
, hw_compat_6_1
, hw_compat_6_1_len
);
3244 mc
->smp_props
.prefer_sockets
= true;
3245 vmc
->no_cpu_topology
= true;
3247 /* qemu ITS was introduced with 6.2 */
3248 vmc
->no_tcg_its
= true;
3250 DEFINE_VIRT_MACHINE(6, 1)
3252 static void virt_machine_6_0_options(MachineClass
*mc
)
3254 virt_machine_6_1_options(mc
);
3255 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
3257 DEFINE_VIRT_MACHINE(6, 0)
3259 static void virt_machine_5_2_options(MachineClass
*mc
)
3261 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3263 virt_machine_6_0_options(mc
);
3264 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
3265 vmc
->no_secure_gpio
= true;
3267 DEFINE_VIRT_MACHINE(5, 2)
3269 static void virt_machine_5_1_options(MachineClass
*mc
)
3271 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3273 virt_machine_5_2_options(mc
);
3274 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
3275 vmc
->no_kvm_steal_time
= true;
3277 DEFINE_VIRT_MACHINE(5, 1)
3279 static void virt_machine_5_0_options(MachineClass
*mc
)
3281 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3283 virt_machine_5_1_options(mc
);
3284 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
3285 mc
->numa_mem_supported
= true;
3286 vmc
->acpi_expose_flash
= true;
3287 mc
->auto_enable_numa_with_memdev
= false;
3289 DEFINE_VIRT_MACHINE(5, 0)
3291 static void virt_machine_4_2_options(MachineClass
*mc
)
3293 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3295 virt_machine_5_0_options(mc
);
3296 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
3297 vmc
->kvm_no_adjvtime
= true;
3299 DEFINE_VIRT_MACHINE(4, 2)
3301 static void virt_machine_4_1_options(MachineClass
*mc
)
3303 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3305 virt_machine_4_2_options(mc
);
3306 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
3308 mc
->auto_enable_numa_with_memhp
= false;
3310 DEFINE_VIRT_MACHINE(4, 1)
3312 static void virt_machine_4_0_options(MachineClass
*mc
)
3314 virt_machine_4_1_options(mc
);
3315 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
3317 DEFINE_VIRT_MACHINE(4, 0)
3319 static void virt_machine_3_1_options(MachineClass
*mc
)
3321 virt_machine_4_0_options(mc
);
3322 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
3324 DEFINE_VIRT_MACHINE(3, 1)
3326 static void virt_machine_3_0_options(MachineClass
*mc
)
3328 virt_machine_3_1_options(mc
);
3329 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
3331 DEFINE_VIRT_MACHINE(3, 0)
3333 static void virt_machine_2_12_options(MachineClass
*mc
)
3335 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3337 virt_machine_3_0_options(mc
);
3338 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
3339 vmc
->no_highmem_ecam
= true;
3342 DEFINE_VIRT_MACHINE(2, 12)
3344 static void virt_machine_2_11_options(MachineClass
*mc
)
3346 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3348 virt_machine_2_12_options(mc
);
3349 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
3350 vmc
->smbios_old_sys_ver
= true;
3352 DEFINE_VIRT_MACHINE(2, 11)
3354 static void virt_machine_2_10_options(MachineClass
*mc
)
3356 virt_machine_2_11_options(mc
);
3357 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
3358 /* before 2.11 we never faulted accesses to bad addresses */
3359 mc
->ignore_memory_transaction_failures
= true;
3361 DEFINE_VIRT_MACHINE(2, 10)
3363 static void virt_machine_2_9_options(MachineClass
*mc
)
3365 virt_machine_2_10_options(mc
);
3366 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
3368 DEFINE_VIRT_MACHINE(2, 9)
3370 static void virt_machine_2_8_options(MachineClass
*mc
)
3372 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3374 virt_machine_2_9_options(mc
);
3375 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
3376 /* For 2.8 and earlier we falsely claimed in the DT that
3377 * our timers were edge-triggered, not level-triggered.
3379 vmc
->claim_edge_triggered_timers
= true;
3381 DEFINE_VIRT_MACHINE(2, 8)
3383 static void virt_machine_2_7_options(MachineClass
*mc
)
3385 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3387 virt_machine_2_8_options(mc
);
3388 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
3389 /* ITS was introduced with 2.8 */
3391 /* Stick with 1K pages for migration compatibility */
3392 mc
->minimum_page_bits
= 0;
3394 DEFINE_VIRT_MACHINE(2, 7)
3396 static void virt_machine_2_6_options(MachineClass
*mc
)
3398 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3400 virt_machine_2_7_options(mc
);
3401 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
3402 vmc
->disallow_affinity_adjustment
= true;
3403 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3406 DEFINE_VIRT_MACHINE(2, 6)