2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 controller, MPCore distributed interrupt controller and ARMv7-M
12 Nested Vectored Interrupt Controller. */
17 #define DPRINTF(fmt, ...) \
18 do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0)
20 #define DPRINTF(fmt, ...) do {} while(0)
24 static const uint8_t gic_id
[] =
25 { 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
26 /* The NVIC has 16 internal vectors. However these are not exposed
27 through the normal GIC interface. */
28 #define GIC_BASE_IRQ 32
30 static const uint8_t gic_id
[] =
31 { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
32 #define GIC_BASE_IRQ 0
35 #define FROM_SYSBUSGIC(type, dev) \
36 DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev))
38 typedef struct gic_irq_state
40 /* The enable bits are only banked for per-cpu interrupts. */
41 unsigned enabled
:NCPU
;
42 unsigned pending
:NCPU
;
45 unsigned model
:1; /* 0 = N:N, 1 = 1:N */
46 unsigned trigger
:1; /* nonzero = edge triggered. */
49 #define ALL_CPU_MASK ((1 << NCPU) - 1)
51 #define NUM_CPU(s) ((s)->num_cpu)
56 #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
57 #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
58 #define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
59 #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
60 #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
61 #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
62 #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
63 #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
64 #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
65 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
66 #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
67 #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
68 #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
69 #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
70 #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
71 #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
72 #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
73 #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
74 #define GIC_GET_PRIORITY(irq, cpu) \
75 (((irq) < 32) ? s->priority1[irq][cpu] : s->priority2[(irq) - 32])
77 #define GIC_TARGET(irq) 1
79 #define GIC_TARGET(irq) s->irq_target[irq]
82 typedef struct gic_state
85 qemu_irq parent_irq
[NCPU
];
87 int cpu_enabled
[NCPU
];
89 gic_irq_state irq_state
[GIC_NIRQ
];
91 int irq_target
[GIC_NIRQ
];
93 int priority1
[32][NCPU
];
94 int priority2
[GIC_NIRQ
- 32];
95 int last_active
[GIC_NIRQ
][NCPU
];
97 int priority_mask
[NCPU
];
98 int running_irq
[NCPU
];
99 int running_priority
[NCPU
];
100 int current_pending
[NCPU
];
109 /* TODO: Many places that call this routine could be optimized. */
110 /* Update interrupt status after enabled or pending bits have been changed. */
111 static void gic_update(gic_state
*s
)
120 for (cpu
= 0; cpu
< NUM_CPU(s
); cpu
++) {
122 s
->current_pending
[cpu
] = 1023;
123 if (!s
->enabled
|| !s
->cpu_enabled
[cpu
]) {
124 qemu_irq_lower(s
->parent_irq
[cpu
]);
129 for (irq
= 0; irq
< GIC_NIRQ
; irq
++) {
130 if (GIC_TEST_ENABLED(irq
, cm
) && GIC_TEST_PENDING(irq
, cm
)) {
131 if (GIC_GET_PRIORITY(irq
, cpu
) < best_prio
) {
132 best_prio
= GIC_GET_PRIORITY(irq
, cpu
);
138 if (best_prio
<= s
->priority_mask
[cpu
]) {
139 s
->current_pending
[cpu
] = best_irq
;
140 if (best_prio
< s
->running_priority
[cpu
]) {
141 DPRINTF("Raised pending IRQ %d\n", best_irq
);
145 qemu_set_irq(s
->parent_irq
[cpu
], level
);
149 static void __attribute__((unused
))
150 gic_set_pending_private(gic_state
*s
, int cpu
, int irq
)
154 if (GIC_TEST_PENDING(irq
, cm
))
157 DPRINTF("Set %d pending cpu %d\n", irq
, cpu
);
158 GIC_SET_PENDING(irq
, cm
);
162 /* Process a change in an external IRQ input. */
163 static void gic_set_irq(void *opaque
, int irq
, int level
)
165 gic_state
*s
= (gic_state
*)opaque
;
166 /* The first external input line is internal interrupt 32. */
168 if (level
== GIC_TEST_LEVEL(irq
, ALL_CPU_MASK
))
172 GIC_SET_LEVEL(irq
, ALL_CPU_MASK
);
173 if (GIC_TEST_TRIGGER(irq
) || GIC_TEST_ENABLED(irq
, ALL_CPU_MASK
)) {
174 DPRINTF("Set %d pending mask %x\n", irq
, GIC_TARGET(irq
));
175 GIC_SET_PENDING(irq
, GIC_TARGET(irq
));
178 GIC_CLEAR_LEVEL(irq
, ALL_CPU_MASK
);
183 static void gic_set_running_irq(gic_state
*s
, int cpu
, int irq
)
185 s
->running_irq
[cpu
] = irq
;
187 s
->running_priority
[cpu
] = 0x100;
189 s
->running_priority
[cpu
] = GIC_GET_PRIORITY(irq
, cpu
);
194 static uint32_t gic_acknowledge_irq(gic_state
*s
, int cpu
)
198 new_irq
= s
->current_pending
[cpu
];
200 || GIC_GET_PRIORITY(new_irq
, cpu
) >= s
->running_priority
[cpu
]) {
201 DPRINTF("ACK no pending IRQ\n");
204 s
->last_active
[new_irq
][cpu
] = s
->running_irq
[cpu
];
205 /* Clear pending flags for both level and edge triggered interrupts.
206 Level triggered IRQs will be reasserted once they become inactive. */
207 GIC_CLEAR_PENDING(new_irq
, GIC_TEST_MODEL(new_irq
) ? ALL_CPU_MASK
: cm
);
208 gic_set_running_irq(s
, cpu
, new_irq
);
209 DPRINTF("ACK %d\n", new_irq
);
213 static void gic_complete_irq(gic_state
* s
, int cpu
, int irq
)
217 DPRINTF("EOI %d\n", irq
);
218 if (s
->running_irq
[cpu
] == 1023)
219 return; /* No active IRQ. */
221 /* Mark level triggered interrupts as pending if they are still
223 if (!GIC_TEST_TRIGGER(irq
) && GIC_TEST_ENABLED(irq
, cm
)
224 && GIC_TEST_LEVEL(irq
, cm
) && (GIC_TARGET(irq
) & cm
) != 0) {
225 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
226 GIC_SET_PENDING(irq
, cm
);
230 if (irq
!= s
->running_irq
[cpu
]) {
231 /* Complete an IRQ that is not currently running. */
232 int tmp
= s
->running_irq
[cpu
];
233 while (s
->last_active
[tmp
][cpu
] != 1023) {
234 if (s
->last_active
[tmp
][cpu
] == irq
) {
235 s
->last_active
[tmp
][cpu
] = s
->last_active
[irq
][cpu
];
238 tmp
= s
->last_active
[tmp
][cpu
];
244 /* Complete the current running IRQ. */
245 gic_set_running_irq(s
, cpu
, s
->last_active
[s
->running_irq
[cpu
]][cpu
]);
249 static uint32_t gic_dist_readb(void *opaque
, target_phys_addr_t offset
)
251 gic_state
*s
= (gic_state
*)opaque
;
259 cpu
= gic_get_current_cpu();
261 if (offset
< 0x100) {
266 return ((GIC_NIRQ
/ 32) - 1) | ((NUM_CPU(s
) - 1) << 5);
271 } else if (offset
< 0x200) {
272 /* Interrupt Set/Clear Enable. */
274 irq
= (offset
- 0x100) * 8;
276 irq
= (offset
- 0x180) * 8;
281 for (i
= 0; i
< 8; i
++) {
282 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
286 } else if (offset
< 0x300) {
287 /* Interrupt Set/Clear Pending. */
289 irq
= (offset
- 0x200) * 8;
291 irq
= (offset
- 0x280) * 8;
296 mask
= (irq
< 32) ? cm
: ALL_CPU_MASK
;
297 for (i
= 0; i
< 8; i
++) {
298 if (GIC_TEST_PENDING(irq
+ i
, mask
)) {
302 } else if (offset
< 0x400) {
303 /* Interrupt Active. */
304 irq
= (offset
- 0x300) * 8 + GIC_BASE_IRQ
;
308 mask
= (irq
< 32) ? cm
: ALL_CPU_MASK
;
309 for (i
= 0; i
< 8; i
++) {
310 if (GIC_TEST_ACTIVE(irq
+ i
, mask
)) {
314 } else if (offset
< 0x800) {
315 /* Interrupt Priority. */
316 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
319 res
= GIC_GET_PRIORITY(irq
, cpu
);
321 } else if (offset
< 0xc00) {
322 /* Interrupt CPU Target. */
323 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
326 if (irq
>= 29 && irq
<= 31) {
329 res
= GIC_TARGET(irq
);
331 } else if (offset
< 0xf00) {
332 /* Interrupt Configuration. */
333 irq
= (offset
- 0xc00) * 2 + GIC_BASE_IRQ
;
337 for (i
= 0; i
< 4; i
++) {
338 if (GIC_TEST_MODEL(irq
+ i
))
339 res
|= (1 << (i
* 2));
340 if (GIC_TEST_TRIGGER(irq
+ i
))
341 res
|= (2 << (i
* 2));
344 } else if (offset
< 0xfe0) {
346 } else /* offset >= 0xfe0 */ {
350 res
= gic_id
[(offset
- 0xfe0) >> 2];
355 hw_error("gic_dist_readb: Bad offset %x\n", (int)offset
);
359 static uint32_t gic_dist_readw(void *opaque
, target_phys_addr_t offset
)
362 val
= gic_dist_readb(opaque
, offset
);
363 val
|= gic_dist_readb(opaque
, offset
+ 1) << 8;
367 static uint32_t gic_dist_readl(void *opaque
, target_phys_addr_t offset
)
371 gic_state
*s
= (gic_state
*)opaque
;
374 if (addr
< 0x100 || addr
> 0xd00)
375 return nvic_readl(s
, addr
);
377 val
= gic_dist_readw(opaque
, offset
);
378 val
|= gic_dist_readw(opaque
, offset
+ 2) << 16;
382 static void gic_dist_writeb(void *opaque
, target_phys_addr_t offset
,
385 gic_state
*s
= (gic_state
*)opaque
;
390 cpu
= gic_get_current_cpu();
391 if (offset
< 0x100) {
396 s
->enabled
= (value
& 1);
397 DPRINTF("Distribution %sabled\n", s
->enabled
? "En" : "Dis");
398 } else if (offset
< 4) {
404 } else if (offset
< 0x180) {
405 /* Interrupt Set Enable. */
406 irq
= (offset
- 0x100) * 8 + GIC_BASE_IRQ
;
411 for (i
= 0; i
< 8; i
++) {
412 if (value
& (1 << i
)) {
413 int mask
= (irq
< 32) ? (1 << cpu
) : GIC_TARGET(irq
);
414 int cm
= (irq
< 32) ? (1 << cpu
) : ALL_CPU_MASK
;
416 if (!GIC_TEST_ENABLED(irq
+ i
, cm
)) {
417 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
419 GIC_SET_ENABLED(irq
+ i
, cm
);
420 /* If a raised level triggered IRQ enabled then mark
422 if (GIC_TEST_LEVEL(irq
+ i
, mask
)
423 && !GIC_TEST_TRIGGER(irq
+ i
)) {
424 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
425 GIC_SET_PENDING(irq
+ i
, mask
);
429 } else if (offset
< 0x200) {
430 /* Interrupt Clear Enable. */
431 irq
= (offset
- 0x180) * 8 + GIC_BASE_IRQ
;
436 for (i
= 0; i
< 8; i
++) {
437 if (value
& (1 << i
)) {
438 int cm
= (irq
< 32) ? (1 << cpu
) : ALL_CPU_MASK
;
440 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
441 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
443 GIC_CLEAR_ENABLED(irq
+ i
, cm
);
446 } else if (offset
< 0x280) {
447 /* Interrupt Set Pending. */
448 irq
= (offset
- 0x200) * 8 + GIC_BASE_IRQ
;
454 for (i
= 0; i
< 8; i
++) {
455 if (value
& (1 << i
)) {
456 GIC_SET_PENDING(irq
+ i
, GIC_TARGET(irq
));
459 } else if (offset
< 0x300) {
460 /* Interrupt Clear Pending. */
461 irq
= (offset
- 0x280) * 8 + GIC_BASE_IRQ
;
464 for (i
= 0; i
< 8; i
++) {
465 /* ??? This currently clears the pending bit for all CPUs, even
466 for per-CPU interrupts. It's unclear whether this is the
468 if (value
& (1 << i
)) {
469 GIC_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
472 } else if (offset
< 0x400) {
473 /* Interrupt Active. */
475 } else if (offset
< 0x800) {
476 /* Interrupt Priority. */
477 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
481 s
->priority1
[irq
][cpu
] = value
;
483 s
->priority2
[irq
- 32] = value
;
486 } else if (offset
< 0xc00) {
487 /* Interrupt CPU Target. */
488 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
494 value
= ALL_CPU_MASK
;
495 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
496 } else if (offset
< 0xf00) {
497 /* Interrupt Configuration. */
498 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
503 for (i
= 0; i
< 4; i
++) {
504 if (value
& (1 << (i
* 2))) {
505 GIC_SET_MODEL(irq
+ i
);
507 GIC_CLEAR_MODEL(irq
+ i
);
509 if (value
& (2 << (i
* 2))) {
510 GIC_SET_TRIGGER(irq
+ i
);
512 GIC_CLEAR_TRIGGER(irq
+ i
);
517 /* 0xf00 is only handled for 32-bit writes. */
523 hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset
);
526 static void gic_dist_writew(void *opaque
, target_phys_addr_t offset
,
529 gic_dist_writeb(opaque
, offset
, value
& 0xff);
530 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8);
533 static void gic_dist_writel(void *opaque
, target_phys_addr_t offset
,
536 gic_state
*s
= (gic_state
*)opaque
;
540 if (addr
< 0x100 || (addr
> 0xd00 && addr
!= 0xf00)) {
541 nvic_writel(s
, addr
, value
);
545 if (offset
== 0xf00) {
550 cpu
= gic_get_current_cpu();
552 switch ((value
>> 24) & 3) {
554 mask
= (value
>> 16) & ALL_CPU_MASK
;
557 mask
= ALL_CPU_MASK
^ (1 << cpu
);
563 DPRINTF("Bad Soft Int target filter\n");
567 GIC_SET_PENDING(irq
, mask
);
571 gic_dist_writew(opaque
, offset
, value
& 0xffff);
572 gic_dist_writew(opaque
, offset
+ 2, value
>> 16);
575 static const MemoryRegionOps gic_dist_ops
= {
577 .read
= { gic_dist_readb
, gic_dist_readw
, gic_dist_readl
, },
578 .write
= { gic_dist_writeb
, gic_dist_writew
, gic_dist_writel
, },
580 .endianness
= DEVICE_NATIVE_ENDIAN
,
584 static uint32_t gic_cpu_read(gic_state
*s
, int cpu
, int offset
)
587 case 0x00: /* Control */
588 return s
->cpu_enabled
[cpu
];
589 case 0x04: /* Priority mask */
590 return s
->priority_mask
[cpu
];
591 case 0x08: /* Binary Point */
592 /* ??? Not implemented. */
594 case 0x0c: /* Acknowledge */
595 return gic_acknowledge_irq(s
, cpu
);
596 case 0x14: /* Runing Priority */
597 return s
->running_priority
[cpu
];
598 case 0x18: /* Highest Pending Interrupt */
599 return s
->current_pending
[cpu
];
601 hw_error("gic_cpu_read: Bad offset %x\n", (int)offset
);
606 static void gic_cpu_write(gic_state
*s
, int cpu
, int offset
, uint32_t value
)
609 case 0x00: /* Control */
610 s
->cpu_enabled
[cpu
] = (value
& 1);
611 DPRINTF("CPU %d %sabled\n", cpu
, s
->cpu_enabled
? "En" : "Dis");
613 case 0x04: /* Priority mask */
614 s
->priority_mask
[cpu
] = (value
& 0xff);
616 case 0x08: /* Binary Point */
617 /* ??? Not implemented. */
619 case 0x10: /* End Of Interrupt */
620 return gic_complete_irq(s
, cpu
, value
& 0x3ff);
622 hw_error("gic_cpu_write: Bad offset %x\n", (int)offset
);
629 static void gic_reset(gic_state
*s
)
632 memset(s
->irq_state
, 0, GIC_NIRQ
* sizeof(gic_irq_state
));
633 for (i
= 0 ; i
< NUM_CPU(s
); i
++) {
634 s
->priority_mask
[i
] = 0xf0;
635 s
->current_pending
[i
] = 1023;
636 s
->running_irq
[i
] = 1023;
637 s
->running_priority
[i
] = 0x100;
639 /* The NVIC doesn't have per-cpu interfaces, so enable by default. */
640 s
->cpu_enabled
[i
] = 1;
642 s
->cpu_enabled
[i
] = 0;
645 for (i
= 0; i
< 16; i
++) {
646 GIC_SET_ENABLED(i
, ALL_CPU_MASK
);
650 /* The NVIC is always enabled. */
657 static void gic_save(QEMUFile
*f
, void *opaque
)
659 gic_state
*s
= (gic_state
*)opaque
;
663 qemu_put_be32(f
, s
->enabled
);
664 for (i
= 0; i
< NUM_CPU(s
); i
++) {
665 qemu_put_be32(f
, s
->cpu_enabled
[i
]);
666 for (j
= 0; j
< 32; j
++)
667 qemu_put_be32(f
, s
->priority1
[j
][i
]);
668 for (j
= 0; j
< GIC_NIRQ
; j
++)
669 qemu_put_be32(f
, s
->last_active
[j
][i
]);
670 qemu_put_be32(f
, s
->priority_mask
[i
]);
671 qemu_put_be32(f
, s
->running_irq
[i
]);
672 qemu_put_be32(f
, s
->running_priority
[i
]);
673 qemu_put_be32(f
, s
->current_pending
[i
]);
675 for (i
= 0; i
< GIC_NIRQ
- 32; i
++) {
676 qemu_put_be32(f
, s
->priority2
[i
]);
678 for (i
= 0; i
< GIC_NIRQ
; i
++) {
680 qemu_put_be32(f
, s
->irq_target
[i
]);
682 qemu_put_byte(f
, s
->irq_state
[i
].enabled
);
683 qemu_put_byte(f
, s
->irq_state
[i
].pending
);
684 qemu_put_byte(f
, s
->irq_state
[i
].active
);
685 qemu_put_byte(f
, s
->irq_state
[i
].level
);
686 qemu_put_byte(f
, s
->irq_state
[i
].model
);
687 qemu_put_byte(f
, s
->irq_state
[i
].trigger
);
691 static int gic_load(QEMUFile
*f
, void *opaque
, int version_id
)
693 gic_state
*s
= (gic_state
*)opaque
;
700 s
->enabled
= qemu_get_be32(f
);
701 for (i
= 0; i
< NUM_CPU(s
); i
++) {
702 s
->cpu_enabled
[i
] = qemu_get_be32(f
);
703 for (j
= 0; j
< 32; j
++)
704 s
->priority1
[j
][i
] = qemu_get_be32(f
);
705 for (j
= 0; j
< GIC_NIRQ
; j
++)
706 s
->last_active
[j
][i
] = qemu_get_be32(f
);
707 s
->priority_mask
[i
] = qemu_get_be32(f
);
708 s
->running_irq
[i
] = qemu_get_be32(f
);
709 s
->running_priority
[i
] = qemu_get_be32(f
);
710 s
->current_pending
[i
] = qemu_get_be32(f
);
712 for (i
= 0; i
< GIC_NIRQ
- 32; i
++) {
713 s
->priority2
[i
] = qemu_get_be32(f
);
715 for (i
= 0; i
< GIC_NIRQ
; i
++) {
717 s
->irq_target
[i
] = qemu_get_be32(f
);
719 s
->irq_state
[i
].enabled
= qemu_get_byte(f
);
720 s
->irq_state
[i
].pending
= qemu_get_byte(f
);
721 s
->irq_state
[i
].active
= qemu_get_byte(f
);
722 s
->irq_state
[i
].level
= qemu_get_byte(f
);
723 s
->irq_state
[i
].model
= qemu_get_byte(f
);
724 s
->irq_state
[i
].trigger
= qemu_get_byte(f
);
731 static void gic_init(gic_state
*s
, int num_cpu
)
733 static void gic_init(gic_state
*s
)
739 s
->num_cpu
= num_cpu
;
741 qdev_init_gpio_in(&s
->busdev
.qdev
, gic_set_irq
, GIC_NIRQ
- 32);
742 for (i
= 0; i
< NUM_CPU(s
); i
++) {
743 sysbus_init_irq(&s
->busdev
, &s
->parent_irq
[i
]);
745 memory_region_init_io(&s
->iomem
, &gic_dist_ops
, s
, "gic_dist", 0x1000);
747 register_savevm(NULL
, "arm_gic", -1, 2, gic_save
, gic_load
, s
);