2 * ARM dummy L210, L220, PL310 cache controller.
4 * Copyright (c) 2010-2012 Calxeda
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or any later version, as published by the Free Software
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
24 #define CACHE_ID 0x410000c8
26 typedef struct l2x0_state
{
34 uint32_t filter_start
;
38 static const VMStateDescription vmstate_l2x0
= {
41 .minimum_version_id
= 1,
42 .fields
= (VMStateField
[]) {
43 VMSTATE_UINT32(ctrl
, l2x0_state
),
44 VMSTATE_UINT32(aux_ctrl
, l2x0_state
),
45 VMSTATE_UINT32(data_ctrl
, l2x0_state
),
46 VMSTATE_UINT32(tag_ctrl
, l2x0_state
),
47 VMSTATE_UINT32(filter_start
, l2x0_state
),
48 VMSTATE_UINT32(filter_end
, l2x0_state
),
54 static uint64_t l2x0_priv_read(void *opaque
, target_phys_addr_t offset
,
58 l2x0_state
*s
= (l2x0_state
*)opaque
;
60 if (offset
>= 0x730 && offset
< 0x800) {
61 return 0; /* cache ops complete */
67 /* aux_ctrl values affect cache_type values */
68 cache_data
= (s
->aux_ctrl
& (7 << 17)) >> 15;
69 cache_data
|= (s
->aux_ctrl
& (1 << 16)) >> 16;
70 return s
->cache_type
|= (cache_data
<< 18) | (cache_data
<< 6);
80 return s
->filter_start
;
90 fprintf(stderr
, "l2x0_priv_read: Bad offset %x\n", (int)offset
);
96 static void l2x0_priv_write(void *opaque
, target_phys_addr_t offset
,
97 uint64_t value
, unsigned size
)
99 l2x0_state
*s
= (l2x0_state
*)opaque
;
101 if (offset
>= 0x730 && offset
< 0x800) {
116 s
->data_ctrl
= value
;
119 s
->filter_start
= value
;
122 s
->filter_end
= value
;
131 fprintf(stderr
, "l2x0_priv_write: Bad offset %x\n", (int)offset
);
136 static void l2x0_priv_reset(DeviceState
*dev
)
138 l2x0_state
*s
= DO_UPCAST(l2x0_state
, busdev
.qdev
, dev
);
141 s
->aux_ctrl
= 0x02020000;
148 static const MemoryRegionOps l2x0_mem_ops
= {
149 .read
= l2x0_priv_read
,
150 .write
= l2x0_priv_write
,
151 .endianness
= DEVICE_NATIVE_ENDIAN
,
154 static int l2x0_priv_init(SysBusDevice
*dev
)
156 l2x0_state
*s
= FROM_SYSBUS(l2x0_state
, dev
);
158 memory_region_init_io(&s
->iomem
, &l2x0_mem_ops
, s
, "l2x0_cc", 0x1000);
159 sysbus_init_mmio(dev
, &s
->iomem
);
163 static SysBusDeviceInfo l2x0_info
= {
164 .init
= l2x0_priv_init
,
166 .qdev
.size
= sizeof(l2x0_state
),
167 .qdev
.vmsd
= &vmstate_l2x0
,
169 .qdev
.props
= (Property
[]) {
170 DEFINE_PROP_UINT32("type", l2x0_state
, cache_type
, 0x1c100100),
171 DEFINE_PROP_END_OF_LIST(),
173 .qdev
.reset
= l2x0_priv_reset
,
176 static void l2x0_register_device(void)
178 sysbus_register_withprop(&l2x0_info
);
181 device_init(l2x0_register_device
)