2 * QEMU model for the AXIS devboard 88.
4 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
44 static struct nand_state_t nand_state
;
45 static uint32_t nand_readl (void *opaque
, target_phys_addr_t addr
)
47 struct nand_state_t
*s
= opaque
;
51 r
= nand_getio(s
->nand
);
52 nand_getpins(s
->nand
, &rdy
);
55 DNAND(printf("%s addr=%x r=%x\n", __func__
, addr
, r
));
60 nand_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
62 struct nand_state_t
*s
= opaque
;
65 DNAND(printf("%s addr=%x v=%x\n", __func__
, addr
, value
));
66 nand_setpins(s
->nand
, s
->cle
, s
->ale
, s
->ce
, 1, 0);
67 nand_setio(s
->nand
, value
);
68 nand_getpins(s
->nand
, &rdy
);
72 static CPUReadMemoryFunc
*nand_read
[] = {
78 static CPUWriteMemoryFunc
*nand_write
[] = {
87 unsigned int shiftreg
;
96 static void tempsensor_clkedge(struct tempsensor_t
*s
,
97 unsigned int clk
, unsigned int data_in
)
99 D(printf("%s clk=%d state=%d sr=%x\n", __func__
,
100 clk
, s
->state
, s
->shiftreg
));
107 /* Output reg is clocked at negedge. */
129 /* Indata is sampled at posedge. */
133 s
->shiftreg
|= data_in
& 1;
135 D(printf("%s cfgreg=%x\n", __func__
, s
->shiftreg
));
136 s
->regs
[0] = s
->shiftreg
;
140 if ((s
->regs
[0] & 0xff) == 0) {
141 /* 25 degrees celcius. */
142 s
->shiftreg
= 0x0b9f;
143 } else if ((s
->regs
[0] & 0xff) == 0xff) {
144 /* Sensor ID, 0x8100 LM70. */
145 s
->shiftreg
= 0x8100;
147 printf("Invalid tempsens state %x\n", s
->regs
[0]);
155 #define RW_PA_DOUT 0x00
156 #define R_PA_DIN 0x01
157 #define RW_PA_OE 0x02
158 #define RW_PD_DOUT 0x10
159 #define R_PD_DIN 0x11
160 #define RW_PD_OE 0x12
162 static struct gpio_state_t
164 struct nand_state_t
*nand
;
165 struct tempsensor_t tempsensor
;
166 uint32_t regs
[0x5c / 4];
169 static uint32_t gpio_readl (void *opaque
, target_phys_addr_t addr
)
171 struct gpio_state_t
*s
= opaque
;
178 r
= s
->regs
[RW_PA_DOUT
] & s
->regs
[RW_PA_OE
];
180 /* Encode pins from the nand. */
181 r
|= s
->nand
->rdy
<< 7;
184 r
= s
->regs
[RW_PD_DOUT
] & s
->regs
[RW_PD_OE
];
186 /* Encode temp sensor pins. */
187 r
|= (!!(s
->tempsensor
.shiftreg
& 0x10000)) << 4;
195 D(printf("%s %x=%x\n", __func__
, addr
, r
));
198 static void gpio_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
200 struct gpio_state_t
*s
= opaque
;
201 D(printf("%s %x=%x\n", __func__
, addr
, value
));
207 /* Decode nand pins. */
208 s
->nand
->ale
= !!(value
& (1 << 6));
209 s
->nand
->cle
= !!(value
& (1 << 5));
210 s
->nand
->ce
= !!(value
& (1 << 4));
212 s
->regs
[addr
] = value
;
216 /* Temp sensor clk. */
217 if ((s
->regs
[addr
] ^ value
) & 2)
218 tempsensor_clkedge(&s
->tempsensor
, !!(value
& 2),
220 s
->regs
[addr
] = value
;
224 s
->regs
[addr
] = value
;
229 static CPUReadMemoryFunc
*gpio_read
[] = {
234 static CPUWriteMemoryFunc
*gpio_write
[] = {
239 #define INTMEM_SIZE (128 * 1024)
241 static uint32_t bootstrap_pc
;
242 static void main_cpu_reset(void *opaque
)
244 CPUState
*env
= opaque
;
247 env
->pc
= bootstrap_pc
;
251 void axisdev88_init (ram_addr_t ram_size
,
252 const char *boot_device
,
253 const char *kernel_filename
, const char *kernel_cmdline
,
254 const char *initrd_filename
, const char *cpu_model
)
259 struct etraxfs_dma_client
*eth
[2] = {NULL
, NULL
};
265 ram_addr_t phys_intmem
;
268 if (cpu_model
== NULL
) {
269 cpu_model
= "crisv32";
271 env
= cpu_init(cpu_model
);
272 qemu_register_reset(main_cpu_reset
, env
);
275 phys_ram
= qemu_ram_alloc(ram_size
);
276 cpu_register_physical_memory(0x40000000, ram_size
, phys_ram
| IO_MEM_RAM
);
278 /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
280 phys_intmem
= qemu_ram_alloc(INTMEM_SIZE
);
281 cpu_register_physical_memory(0x38000000, INTMEM_SIZE
,
282 phys_intmem
| IO_MEM_RAM
);
285 /* Attach a NAND flash to CS1. */
286 nand_state
.nand
= nand_init(NAND_MFR_STMICRO
, 0x39);
287 nand_regs
= cpu_register_io_memory(0, nand_read
, nand_write
, &nand_state
);
288 cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs
);
290 gpio_state
.nand
= &nand_state
;
291 gpio_regs
= cpu_register_io_memory(0, gpio_read
, gpio_write
, &gpio_state
);
292 cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs
);
295 irq
= etraxfs_pic_init(env
, 0x3001c000);
298 etraxfs_dmac
= etraxfs_dmac_init(env
, 0x30000000, 10);
299 for (i
= 0; i
< 10; i
++) {
300 /* On ETRAX, odd numbered channels are inputs. */
301 etraxfs_dmac_connect(etraxfs_dmac
, i
, irq
+ 7 + i
, i
& 1);
304 /* Add the two ethernet blocks. */
305 eth
[0] = etraxfs_eth_init(&nd_table
[0], env
, irq
+ 25, 0x30034000, 1);
307 eth
[1] = etraxfs_eth_init(&nd_table
[1], env
,
308 irq
+ 26, 0x30036000, 2);
310 /* The DMA Connector block is missing, hardwire things for now. */
311 etraxfs_dmac_connect_client(etraxfs_dmac
, 0, eth
[0]);
312 etraxfs_dmac_connect_client(etraxfs_dmac
, 1, eth
[0] + 1);
314 etraxfs_dmac_connect_client(etraxfs_dmac
, 6, eth
[1]);
315 etraxfs_dmac_connect_client(etraxfs_dmac
, 7, eth
[1] + 1);
319 etraxfs_timer_init(env
, irq
+ 0x1b, nmi
+ 1, 0x3001e000);
320 etraxfs_timer_init(env
, irq
+ 0x1b, nmi
+ 1, 0x3005e000);
322 for (i
= 0; i
< 4; i
++) {
323 sysbus_create_simple("etraxfs,serial", 0x30026000 + i
* 0x2000,
327 if (kernel_filename
) {
328 uint64_t entry
, high
;
331 /* Boots a kernel elf binary, os/linux-2.6/vmlinux from the axis
333 kernel_size
= load_elf(kernel_filename
, -0x80000000LL
,
334 &entry
, NULL
, &high
);
335 bootstrap_pc
= entry
;
336 if (kernel_size
< 0) {
337 /* Takes a kimage from the axis devboard SDK. */
338 kernel_size
= load_image_targphys(kernel_filename
, 0x40004000,
340 bootstrap_pc
= 0x40004000;
341 env
->regs
[9] = 0x40004000 + kernel_size
;
343 env
->regs
[8] = 0x56902387; /* RAM init magic. */
345 if (kernel_cmdline
&& (kcmdline_len
= strlen(kernel_cmdline
))) {
346 if (kcmdline_len
> 256) {
347 fprintf(stderr
, "Too long CRIS kernel cmdline (max 256)\n");
350 /* Let the kernel know we are modifying the cmdline. */
351 env
->regs
[10] = 0x87109563;
352 env
->regs
[11] = 0x40000000;
353 pstrcpy_targphys(env
->regs
[11], 256, kernel_cmdline
);
356 env
->pc
= bootstrap_pc
;
358 printf ("pc =%x\n", env
->pc
);
359 printf ("ram size =%ld\n", ram_size
);
362 QEMUMachine axisdev88_machine
= {
363 .name
= "axis-dev88",
364 .desc
= "AXIS devboard 88",
365 .init
= axisdev88_init
,