hw/cxl/cxl-mailbox-utils.c

   1 /*
   2  * CXL Utility library for mailbox interface
   3  *
   4  * Copyright(C) 2020 Intel Corporation.
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/cxl/cxl.h"
  12 #include "hw/pci/pci.h"
  13 #include "qemu/cutils.h"
  14 #include "qemu/log.h"
  15 #include "qemu/units.h"
  16 #include "qemu/uuid.h"
  17
  18 #define CXL_CAPACITY_MULTIPLIER   (256 * MiB)
  19
  20 /*
  21  * How to add a new command, example. The command set FOO, with cmd BAR.
  22  *  1. Add the command set and cmd to the enum.
  23  *     FOO    = 0x7f,
  24  *          #define BAR 0
  25  *  2. Implement the handler
  26  *    static ret_code cmd_foo_bar(struct cxl_cmd *cmd,
  27  *                                  CXLDeviceState *cxl_dstate, uint16_t *len)
  28  *  3. Add the command to the cxl_cmd_set[][]
  29  *    [FOO][BAR] = { "FOO_BAR", cmd_foo_bar, x, y },
  30  *  4. Implement your handler
  31  *     define_mailbox_handler(FOO_BAR) { ... return CXL_MBOX_SUCCESS; }
  32  *
  33  *
  34  *  Writing the handler:
  35  *    The handler will provide the &struct cxl_cmd, the &CXLDeviceState, and the
  36  *    in/out length of the payload. The handler is responsible for consuming the
  37  *    payload from cmd->payload and operating upon it as necessary. It must then
  38  *    fill the output data into cmd->payload (overwriting what was there),
  39  *    setting the length, and returning a valid return code.
  40  *
  41  *  XXX: The handler need not worry about endianess. The payload is read out of
  42  *  a register interface that already deals with it.
  43  */
  44
  45 enum {
  46     EVENTS      = 0x01,
  47         #define GET_RECORDS   0x0
  48         #define CLEAR_RECORDS   0x1
  49         #define GET_INTERRUPT_POLICY   0x2
  50         #define SET_INTERRUPT_POLICY   0x3
  51     FIRMWARE_UPDATE = 0x02,
  52         #define GET_INFO      0x0
  53     TIMESTAMP   = 0x03,
  54         #define GET           0x0
  55         #define SET           0x1
  56     LOGS        = 0x04,
  57         #define GET_SUPPORTED 0x0
  58         #define GET_LOG       0x1
  59     IDENTIFY    = 0x40,
  60         #define MEMORY_DEVICE 0x0
  61     CCLS        = 0x41,
  62         #define GET_PARTITION_INFO     0x0
  63         #define GET_LSA       0x2
  64         #define SET_LSA       0x3
  65 };
  66
  67 /* 8.2.8.4.5.1 Command Return Codes */
  68 typedef enum {
  69     CXL_MBOX_SUCCESS = 0x0,
  70     CXL_MBOX_BG_STARTED = 0x1,
  71     CXL_MBOX_INVALID_INPUT = 0x2,
  72     CXL_MBOX_UNSUPPORTED = 0x3,
  73     CXL_MBOX_INTERNAL_ERROR = 0x4,
  74     CXL_MBOX_RETRY_REQUIRED = 0x5,
  75     CXL_MBOX_BUSY = 0x6,
  76     CXL_MBOX_MEDIA_DISABLED = 0x7,
  77     CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8,
  78     CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9,
  79     CXL_MBOX_FW_AUTH_FAILED = 0xa,
  80     CXL_MBOX_FW_INVALID_SLOT = 0xb,
  81     CXL_MBOX_FW_ROLLEDBACK = 0xc,
  82     CXL_MBOX_FW_REST_REQD = 0xd,
  83     CXL_MBOX_INVALID_HANDLE = 0xe,
  84     CXL_MBOX_INVALID_PA = 0xf,
  85     CXL_MBOX_INJECT_POISON_LIMIT = 0x10,
  86     CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11,
  87     CXL_MBOX_ABORTED = 0x12,
  88     CXL_MBOX_INVALID_SECURITY_STATE = 0x13,
  89     CXL_MBOX_INCORRECT_PASSPHRASE = 0x14,
  90     CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15,
  91     CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16,
  92     CXL_MBOX_MAX = 0x17
  93 } ret_code;
  94
  95 struct cxl_cmd;
  96 typedef ret_code (*opcode_handler)(struct cxl_cmd *cmd,
  97                                    CXLDeviceState *cxl_dstate, uint16_t *len);
  98 struct cxl_cmd {
  99     const char *name;
 100     opcode_handler handler;
 101     ssize_t in;
 102     uint16_t effect; /* Reported in CEL */
 103     uint8_t *payload;
 104 };
 105
 106 #define DEFINE_MAILBOX_HANDLER_ZEROED(name, size)                         \
 107     uint16_t __zero##name = size;                                         \
 108     static ret_code cmd_##name(struct cxl_cmd *cmd,                       \
 109                                CXLDeviceState *cxl_dstate, uint16_t *len) \
 110     {                                                                     \
 111         *len = __zero##name;                                              \
 112         memset(cmd->payload, 0, *len);                                    \
 113         return CXL_MBOX_SUCCESS;                                          \
 114     }
 115 #define DEFINE_MAILBOX_HANDLER_NOP(name)                                  \
 116     static ret_code cmd_##name(struct cxl_cmd *cmd,                       \
 117                                CXLDeviceState *cxl_dstate, uint16_t *len) \
 118     {                                                                     \
 119         return CXL_MBOX_SUCCESS;                                          \
 120     }
 121
 122 DEFINE_MAILBOX_HANDLER_ZEROED(events_get_records, 0x20);
 123 DEFINE_MAILBOX_HANDLER_NOP(events_clear_records);
 124 DEFINE_MAILBOX_HANDLER_ZEROED(events_get_interrupt_policy, 4);
 125 DEFINE_MAILBOX_HANDLER_NOP(events_set_interrupt_policy);
 126
 127 /* 8.2.9.2.1 */
 128 static ret_code cmd_firmware_update_get_info(struct cxl_cmd *cmd,
 129                                              CXLDeviceState *cxl_dstate,
 130                                              uint16_t *len)
 131 {
 132     struct {
 133         uint8_t slots_supported;
 134         uint8_t slot_info;
 135         uint8_t caps;
 136         uint8_t rsvd[0xd];
 137         char fw_rev1[0x10];
 138         char fw_rev2[0x10];
 139         char fw_rev3[0x10];
 140         char fw_rev4[0x10];
 141     } QEMU_PACKED *fw_info;
 142     QEMU_BUILD_BUG_ON(sizeof(*fw_info) != 0x50);
 143
 144     if (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER) {
 145         return CXL_MBOX_INTERNAL_ERROR;
 146     }
 147
 148     fw_info = (void *)cmd->payload;
 149     memset(fw_info, 0, sizeof(*fw_info));
 150
 151     fw_info->slots_supported = 2;
 152     fw_info->slot_info = BIT(0) | BIT(3);
 153     fw_info->caps = 0;
 154     pstrcpy(fw_info->fw_rev1, sizeof(fw_info->fw_rev1), "BWFW VERSION 0");
 155
 156     *len = sizeof(*fw_info);
 157     return CXL_MBOX_SUCCESS;
 158 }
 159
 160 /* 8.2.9.3.1 */
 161 static ret_code cmd_timestamp_get(struct cxl_cmd *cmd,
 162                                   CXLDeviceState *cxl_dstate,
 163                                   uint16_t *len)
 164 {
 165     uint64_t time, delta;
 166     uint64_t final_time = 0;
 167
 168     if (cxl_dstate->timestamp.set) {
 169         /* First find the delta from the last time the host set the time. */
 170         time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 171         delta = time - cxl_dstate->timestamp.last_set;
 172         final_time = cxl_dstate->timestamp.host_set + delta;
 173     }
 174
 175     /* Then adjust the actual time */
 176     stq_le_p(cmd->payload, final_time);
 177     *len = 8;
 178
 179     return CXL_MBOX_SUCCESS;
 180 }
 181
 182 /* 8.2.9.3.2 */
 183 static ret_code cmd_timestamp_set(struct cxl_cmd *cmd,
 184                                   CXLDeviceState *cxl_dstate,
 185                                   uint16_t *len)
 186 {
 187     cxl_dstate->timestamp.set = true;
 188     cxl_dstate->timestamp.last_set = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 189
 190     cxl_dstate->timestamp.host_set = le64_to_cpu(*(uint64_t *)cmd->payload);
 191
 192     *len = 0;
 193     return CXL_MBOX_SUCCESS;
 194 }
 195
 196 /* CXL 3.0 8.2.9.5.2.1 Command Effects Log (CEL) */
 197 static const QemuUUID cel_uuid = {
 198     .data = UUID(0x0da9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79,
 199                  0x96, 0xb1, 0x62, 0x3b, 0x3f, 0x17)
 200 };
 201
 202 /* 8.2.9.4.1 */
 203 static ret_code cmd_logs_get_supported(struct cxl_cmd *cmd,
 204                                        CXLDeviceState *cxl_dstate,
 205                                        uint16_t *len)
 206 {
 207     struct {
 208         uint16_t entries;
 209         uint8_t rsvd[6];
 210         struct {
 211             QemuUUID uuid;
 212             uint32_t size;
 213         } log_entries[1];
 214     } QEMU_PACKED *supported_logs = (void *)cmd->payload;
 215     QEMU_BUILD_BUG_ON(sizeof(*supported_logs) != 0x1c);
 216
 217     supported_logs->entries = 1;
 218     supported_logs->log_entries[0].uuid = cel_uuid;
 219     supported_logs->log_entries[0].size = 4 * cxl_dstate->cel_size;
 220
 221     *len = sizeof(*supported_logs);
 222     return CXL_MBOX_SUCCESS;
 223 }
 224
 225 /* 8.2.9.4.2 */
 226 static ret_code cmd_logs_get_log(struct cxl_cmd *cmd,
 227                                  CXLDeviceState *cxl_dstate,
 228                                  uint16_t *len)
 229 {
 230     struct {
 231         QemuUUID uuid;
 232         uint32_t offset;
 233         uint32_t length;
 234     } QEMU_PACKED QEMU_ALIGNED(16) *get_log = (void *)cmd->payload;
 235
 236     /*
 237      * 8.2.9.4.2
 238      *   The device shall return Invalid Parameter if the Offset or Length
 239      *   fields attempt to access beyond the size of the log as reported by Get
 240      *   Supported Logs.
 241      *
 242      * XXX: Spec is wrong, "Invalid Parameter" isn't a thing.
 243      * XXX: Spec doesn't address incorrect UUID incorrectness.
 244      *
 245      * The CEL buffer is large enough to fit all commands in the emulation, so
 246      * the only possible failure would be if the mailbox itself isn't big
 247      * enough.
 248      */
 249     if (get_log->offset + get_log->length > cxl_dstate->payload_size) {
 250         return CXL_MBOX_INVALID_INPUT;
 251     }
 252
 253     if (!qemu_uuid_is_equal(&get_log->uuid, &cel_uuid)) {
 254         return CXL_MBOX_UNSUPPORTED;
 255     }
 256
 257     /* Store off everything to local variables so we can wipe out the payload */
 258     *len = get_log->length;
 259
 260     memmove(cmd->payload, cxl_dstate->cel_log + get_log->offset,
 261            get_log->length);
 262
 263     return CXL_MBOX_SUCCESS;
 264 }
 265
 266 /* 8.2.9.5.1.1 */
 267 static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd,
 268                                            CXLDeviceState *cxl_dstate,
 269                                            uint16_t *len)
 270 {
 271     struct {
 272         char fw_revision[0x10];
 273         uint64_t total_capacity;
 274         uint64_t volatile_capacity;
 275         uint64_t persistent_capacity;
 276         uint64_t partition_align;
 277         uint16_t info_event_log_size;
 278         uint16_t warning_event_log_size;
 279         uint16_t failure_event_log_size;
 280         uint16_t fatal_event_log_size;
 281         uint32_t lsa_size;
 282         uint8_t poison_list_max_mer[3];
 283         uint16_t inject_poison_limit;
 284         uint8_t poison_caps;
 285         uint8_t qos_telemetry_caps;
 286     } QEMU_PACKED *id;
 287     QEMU_BUILD_BUG_ON(sizeof(*id) != 0x43);
 288
 289     CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
 290     CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d);
 291     uint64_t size = cxl_dstate->pmem_size;
 292
 293     if (!QEMU_IS_ALIGNED(size, CXL_CAPACITY_MULTIPLIER)) {
 294         return CXL_MBOX_INTERNAL_ERROR;
 295     }
 296
 297     id = (void *)cmd->payload;
 298     memset(id, 0, sizeof(*id));
 299
 300     /* PMEM only */
 301     snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0);
 302
 303     id->total_capacity = size / CXL_CAPACITY_MULTIPLIER;
 304     id->persistent_capacity = size / CXL_CAPACITY_MULTIPLIER;
 305     id->lsa_size = cvc->get_lsa_size(ct3d);
 306
 307     *len = sizeof(*id);
 308     return CXL_MBOX_SUCCESS;
 309 }
 310
 311 static ret_code cmd_ccls_get_partition_info(struct cxl_cmd *cmd,
 312                                            CXLDeviceState *cxl_dstate,
 313                                            uint16_t *len)
 314 {
 315     struct {
 316         uint64_t active_vmem;
 317         uint64_t active_pmem;
 318         uint64_t next_vmem;
 319         uint64_t next_pmem;
 320     } QEMU_PACKED *part_info = (void *)cmd->payload;
 321     QEMU_BUILD_BUG_ON(sizeof(*part_info) != 0x20);
 322     uint64_t size = cxl_dstate->pmem_size;
 323
 324     if (!QEMU_IS_ALIGNED(size, CXL_CAPACITY_MULTIPLIER)) {
 325         return CXL_MBOX_INTERNAL_ERROR;
 326     }
 327
 328     /* PMEM only */
 329     part_info->active_vmem = 0;
 330     part_info->next_vmem = 0;
 331     part_info->active_pmem = size / CXL_CAPACITY_MULTIPLIER;
 332     part_info->next_pmem = 0;
 333
 334     *len = sizeof(*part_info);
 335     return CXL_MBOX_SUCCESS;
 336 }
 337
 338 static ret_code cmd_ccls_get_lsa(struct cxl_cmd *cmd,
 339                                  CXLDeviceState *cxl_dstate,
 340                                  uint16_t *len)
 341 {
 342     struct {
 343         uint32_t offset;
 344         uint32_t length;
 345     } QEMU_PACKED *get_lsa;
 346     CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
 347     CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d);
 348     uint32_t offset, length;
 349
 350     get_lsa = (void *)cmd->payload;
 351     offset = get_lsa->offset;
 352     length = get_lsa->length;
 353
 354     if (offset + length > cvc->get_lsa_size(ct3d)) {
 355         *len = 0;
 356         return CXL_MBOX_INVALID_INPUT;
 357     }
 358
 359     *len = cvc->get_lsa(ct3d, get_lsa, length, offset);
 360     return CXL_MBOX_SUCCESS;
 361 }
 362
 363 static ret_code cmd_ccls_set_lsa(struct cxl_cmd *cmd,
 364                                  CXLDeviceState *cxl_dstate,
 365                                  uint16_t *len)
 366 {
 367     struct set_lsa_pl {
 368         uint32_t offset;
 369         uint32_t rsvd;
 370         uint8_t data[];
 371     } QEMU_PACKED;
 372     struct set_lsa_pl *set_lsa_payload = (void *)cmd->payload;
 373     CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
 374     CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d);
 375     const size_t hdr_len = offsetof(struct set_lsa_pl, data);
 376     uint16_t plen = *len;
 377
 378     *len = 0;
 379     if (!plen) {
 380         return CXL_MBOX_SUCCESS;
 381     }
 382
 383     if (set_lsa_payload->offset + plen > cvc->get_lsa_size(ct3d) + hdr_len) {
 384         return CXL_MBOX_INVALID_INPUT;
 385     }
 386     plen -= hdr_len;
 387
 388     cvc->set_lsa(ct3d, set_lsa_payload->data, plen, set_lsa_payload->offset);
 389     return CXL_MBOX_SUCCESS;
 390 }
 391
 392 #define IMMEDIATE_CONFIG_CHANGE (1 << 1)
 393 #define IMMEDIATE_DATA_CHANGE (1 << 2)
 394 #define IMMEDIATE_POLICY_CHANGE (1 << 3)
 395 #define IMMEDIATE_LOG_CHANGE (1 << 4)
 396
 397 static struct cxl_cmd cxl_cmd_set[256][256] = {
 398     [EVENTS][GET_RECORDS] = { "EVENTS_GET_RECORDS",
 399         cmd_events_get_records, 1, 0 },
 400     [EVENTS][CLEAR_RECORDS] = { "EVENTS_CLEAR_RECORDS",
 401         cmd_events_clear_records, ~0, IMMEDIATE_LOG_CHANGE },
 402     [EVENTS][GET_INTERRUPT_POLICY] = { "EVENTS_GET_INTERRUPT_POLICY",
 403         cmd_events_get_interrupt_policy, 0, 0 },
 404     [EVENTS][SET_INTERRUPT_POLICY] = { "EVENTS_SET_INTERRUPT_POLICY",
 405         cmd_events_set_interrupt_policy, 4, IMMEDIATE_CONFIG_CHANGE },
 406     [FIRMWARE_UPDATE][GET_INFO] = { "FIRMWARE_UPDATE_GET_INFO",
 407         cmd_firmware_update_get_info, 0, 0 },
 408     [TIMESTAMP][GET] = { "TIMESTAMP_GET", cmd_timestamp_get, 0, 0 },
 409     [TIMESTAMP][SET] = { "TIMESTAMP_SET", cmd_timestamp_set, 8, IMMEDIATE_POLICY_CHANGE },
 410     [LOGS][GET_SUPPORTED] = { "LOGS_GET_SUPPORTED", cmd_logs_get_supported, 0, 0 },
 411     [LOGS][GET_LOG] = { "LOGS_GET_LOG", cmd_logs_get_log, 0x18, 0 },
 412     [IDENTIFY][MEMORY_DEVICE] = { "IDENTIFY_MEMORY_DEVICE",
 413         cmd_identify_memory_device, 0, 0 },
 414     [CCLS][GET_PARTITION_INFO] = { "CCLS_GET_PARTITION_INFO",
 415         cmd_ccls_get_partition_info, 0, 0 },
 416     [CCLS][GET_LSA] = { "CCLS_GET_LSA", cmd_ccls_get_lsa, 8, 0 },
 417     [CCLS][SET_LSA] = { "CCLS_SET_LSA", cmd_ccls_set_lsa,
 418         ~0, IMMEDIATE_CONFIG_CHANGE | IMMEDIATE_DATA_CHANGE },
 419 };
 420
 421 void cxl_process_mailbox(CXLDeviceState *cxl_dstate)
 422 {
 423     uint16_t ret = CXL_MBOX_SUCCESS;
 424     struct cxl_cmd *cxl_cmd;
 425     uint64_t status_reg;
 426     opcode_handler h;
 427     uint64_t command_reg = cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD];
 428
 429     uint8_t set = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET);
 430     uint8_t cmd = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND);
 431     uint16_t len = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH);
 432     cxl_cmd = &cxl_cmd_set[set][cmd];
 433     h = cxl_cmd->handler;
 434     if (h) {
 435         if (len == cxl_cmd->in || cxl_cmd->in == ~0) {
 436             cxl_cmd->payload = cxl_dstate->mbox_reg_state +
 437                 A_CXL_DEV_CMD_PAYLOAD;
 438             ret = (*h)(cxl_cmd, cxl_dstate, &len);
 439             assert(len <= cxl_dstate->payload_size);
 440         } else {
 441             ret = CXL_MBOX_INVALID_PAYLOAD_LENGTH;
 442         }
 443     } else {
 444         qemu_log_mask(LOG_UNIMP, "Command %04xh not implemented\n",
 445                       set << 8 | cmd);
 446         ret = CXL_MBOX_UNSUPPORTED;
 447     }
 448
 449     /* Set the return code */
 450     status_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_STS, ERRNO, ret);
 451
 452     /* Set the return length */
 453     command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET, 0);
 454     command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND, 0);
 455     command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH, len);
 456
 457     cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD] = command_reg;
 458     cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_STS] = status_reg;
 459
 460     /* Tell the host we're done */
 461     ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL,
 462                      DOORBELL, 0);
 463 }
 464
 465 void cxl_initialize_mailbox(CXLDeviceState *cxl_dstate)
 466 {
 467     for (int set = 0; set < 256; set++) {
 468         for (int cmd = 0; cmd < 256; cmd++) {
 469             if (cxl_cmd_set[set][cmd].handler) {
 470                 struct cxl_cmd *c = &cxl_cmd_set[set][cmd];
 471                 struct cel_log *log =
 472                     &cxl_dstate->cel_log[cxl_dstate->cel_size];
 473
 474                 log->opcode = (set << 8) | cmd;
 475                 log->effect = c->effect;
 476                 cxl_dstate->cel_size++;
 477             }
 478         }
 479     }
 480 }