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1 /*
2 * CXL Utility library for mailbox interface
3 *
4 * Copyright(C) 2020 Intel Corporation.
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2. See the
7 * COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "hw/cxl/cxl.h"
12 #include "hw/pci/pci.h"
13 #include "qemu/log.h"
14 #include "qemu/uuid.h"
15
16 /*
17 * How to add a new command, example. The command set FOO, with cmd BAR.
18 * 1. Add the command set and cmd to the enum.
19 * FOO = 0x7f,
20 * #define BAR 0
21 * 2. Implement the handler
22 * static ret_code cmd_foo_bar(struct cxl_cmd *cmd,
23 * CXLDeviceState *cxl_dstate, uint16_t *len)
24 * 3. Add the command to the cxl_cmd_set[][]
25 * [FOO][BAR] = { "FOO_BAR", cmd_foo_bar, x, y },
26 * 4. Implement your handler
27 * define_mailbox_handler(FOO_BAR) { ... return CXL_MBOX_SUCCESS; }
28 *
29 *
30 * Writing the handler:
31 * The handler will provide the &struct cxl_cmd, the &CXLDeviceState, and the
32 * in/out length of the payload. The handler is responsible for consuming the
33 * payload from cmd->payload and operating upon it as necessary. It must then
34 * fill the output data into cmd->payload (overwriting what was there),
35 * setting the length, and returning a valid return code.
36 *
37 * XXX: The handler need not worry about endianess. The payload is read out of
38 * a register interface that already deals with it.
39 */
40
41 enum {
42 EVENTS = 0x01,
43 #define GET_RECORDS 0x0
44 #define CLEAR_RECORDS 0x1
45 #define GET_INTERRUPT_POLICY 0x2
46 #define SET_INTERRUPT_POLICY 0x3
47 TIMESTAMP = 0x03,
48 #define GET 0x0
49 #define SET 0x1
50 LOGS = 0x04,
51 #define GET_SUPPORTED 0x0
52 #define GET_LOG 0x1
53 IDENTIFY = 0x40,
54 #define MEMORY_DEVICE 0x0
55 };
56
57 /* 8.2.8.4.5.1 Command Return Codes */
58 typedef enum {
59 CXL_MBOX_SUCCESS = 0x0,
60 CXL_MBOX_BG_STARTED = 0x1,
61 CXL_MBOX_INVALID_INPUT = 0x2,
62 CXL_MBOX_UNSUPPORTED = 0x3,
63 CXL_MBOX_INTERNAL_ERROR = 0x4,
64 CXL_MBOX_RETRY_REQUIRED = 0x5,
65 CXL_MBOX_BUSY = 0x6,
66 CXL_MBOX_MEDIA_DISABLED = 0x7,
67 CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8,
68 CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9,
69 CXL_MBOX_FW_AUTH_FAILED = 0xa,
70 CXL_MBOX_FW_INVALID_SLOT = 0xb,
71 CXL_MBOX_FW_ROLLEDBACK = 0xc,
72 CXL_MBOX_FW_REST_REQD = 0xd,
73 CXL_MBOX_INVALID_HANDLE = 0xe,
74 CXL_MBOX_INVALID_PA = 0xf,
75 CXL_MBOX_INJECT_POISON_LIMIT = 0x10,
76 CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11,
77 CXL_MBOX_ABORTED = 0x12,
78 CXL_MBOX_INVALID_SECURITY_STATE = 0x13,
79 CXL_MBOX_INCORRECT_PASSPHRASE = 0x14,
80 CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15,
81 CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16,
82 CXL_MBOX_MAX = 0x17
83 } ret_code;
84
85 struct cxl_cmd;
86 typedef ret_code (*opcode_handler)(struct cxl_cmd *cmd,
87 CXLDeviceState *cxl_dstate, uint16_t *len);
88 struct cxl_cmd {
89 const char *name;
90 opcode_handler handler;
91 ssize_t in;
92 uint16_t effect; /* Reported in CEL */
93 uint8_t *payload;
94 };
95
96 #define DEFINE_MAILBOX_HANDLER_ZEROED(name, size) \
97 uint16_t __zero##name = size; \
98 static ret_code cmd_##name(struct cxl_cmd *cmd, \
99 CXLDeviceState *cxl_dstate, uint16_t *len) \
100 { \
101 *len = __zero##name; \
102 memset(cmd->payload, 0, *len); \
103 return CXL_MBOX_SUCCESS; \
104 }
105 #define DEFINE_MAILBOX_HANDLER_NOP(name) \
106 static ret_code cmd_##name(struct cxl_cmd *cmd, \
107 CXLDeviceState *cxl_dstate, uint16_t *len) \
108 { \
109 return CXL_MBOX_SUCCESS; \
110 }
111
112 DEFINE_MAILBOX_HANDLER_ZEROED(events_get_records, 0x20);
113 DEFINE_MAILBOX_HANDLER_NOP(events_clear_records);
114 DEFINE_MAILBOX_HANDLER_ZEROED(events_get_interrupt_policy, 4);
115 DEFINE_MAILBOX_HANDLER_NOP(events_set_interrupt_policy);
116
117 /* 8.2.9.3.1 */
118 static ret_code cmd_timestamp_get(struct cxl_cmd *cmd,
119 CXLDeviceState *cxl_dstate,
120 uint16_t *len)
121 {
122 uint64_t time, delta;
123 uint64_t final_time = 0;
124
125 if (cxl_dstate->timestamp.set) {
126 /* First find the delta from the last time the host set the time. */
127 time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
128 delta = time - cxl_dstate->timestamp.last_set;
129 final_time = cxl_dstate->timestamp.host_set + delta;
130 }
131
132 /* Then adjust the actual time */
133 stq_le_p(cmd->payload, final_time);
134 *len = 8;
135
136 return CXL_MBOX_SUCCESS;
137 }
138
139 /* 8.2.9.3.2 */
140 static ret_code cmd_timestamp_set(struct cxl_cmd *cmd,
141 CXLDeviceState *cxl_dstate,
142 uint16_t *len)
143 {
144 cxl_dstate->timestamp.set = true;
145 cxl_dstate->timestamp.last_set = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
146
147 cxl_dstate->timestamp.host_set = le64_to_cpu(*(uint64_t *)cmd->payload);
148
149 *len = 0;
150 return CXL_MBOX_SUCCESS;
151 }
152
153 static QemuUUID cel_uuid;
154
155 /* 8.2.9.4.1 */
156 static ret_code cmd_logs_get_supported(struct cxl_cmd *cmd,
157 CXLDeviceState *cxl_dstate,
158 uint16_t *len)
159 {
160 struct {
161 uint16_t entries;
162 uint8_t rsvd[6];
163 struct {
164 QemuUUID uuid;
165 uint32_t size;
166 } log_entries[1];
167 } QEMU_PACKED *supported_logs = (void *)cmd->payload;
168 QEMU_BUILD_BUG_ON(sizeof(*supported_logs) != 0x1c);
169
170 supported_logs->entries = 1;
171 supported_logs->log_entries[0].uuid = cel_uuid;
172 supported_logs->log_entries[0].size = 4 * cxl_dstate->cel_size;
173
174 *len = sizeof(*supported_logs);
175 return CXL_MBOX_SUCCESS;
176 }
177
178 /* 8.2.9.4.2 */
179 static ret_code cmd_logs_get_log(struct cxl_cmd *cmd,
180 CXLDeviceState *cxl_dstate,
181 uint16_t *len)
182 {
183 struct {
184 QemuUUID uuid;
185 uint32_t offset;
186 uint32_t length;
187 } QEMU_PACKED QEMU_ALIGNED(16) *get_log = (void *)cmd->payload;
188
189 /*
190 * 8.2.9.4.2
191 * The device shall return Invalid Parameter if the Offset or Length
192 * fields attempt to access beyond the size of the log as reported by Get
193 * Supported Logs.
194 *
195 * XXX: Spec is wrong, "Invalid Parameter" isn't a thing.
196 * XXX: Spec doesn't address incorrect UUID incorrectness.
197 *
198 * The CEL buffer is large enough to fit all commands in the emulation, so
199 * the only possible failure would be if the mailbox itself isn't big
200 * enough.
201 */
202 if (get_log->offset + get_log->length > cxl_dstate->payload_size) {
203 return CXL_MBOX_INVALID_INPUT;
204 }
205
206 if (!qemu_uuid_is_equal(&get_log->uuid, &cel_uuid)) {
207 return CXL_MBOX_UNSUPPORTED;
208 }
209
210 /* Store off everything to local variables so we can wipe out the payload */
211 *len = get_log->length;
212
213 memmove(cmd->payload, cxl_dstate->cel_log + get_log->offset,
214 get_log->length);
215
216 return CXL_MBOX_SUCCESS;
217 }
218
219 /* 8.2.9.5.1.1 */
220 static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd,
221 CXLDeviceState *cxl_dstate,
222 uint16_t *len)
223 {
224 struct {
225 char fw_revision[0x10];
226 uint64_t total_capacity;
227 uint64_t volatile_capacity;
228 uint64_t persistent_capacity;
229 uint64_t partition_align;
230 uint16_t info_event_log_size;
231 uint16_t warning_event_log_size;
232 uint16_t failure_event_log_size;
233 uint16_t fatal_event_log_size;
234 uint32_t lsa_size;
235 uint8_t poison_list_max_mer[3];
236 uint16_t inject_poison_limit;
237 uint8_t poison_caps;
238 uint8_t qos_telemetry_caps;
239 } QEMU_PACKED *id;
240 QEMU_BUILD_BUG_ON(sizeof(*id) != 0x43);
241
242 uint64_t size = cxl_dstate->pmem_size;
243
244 if (!QEMU_IS_ALIGNED(size, 256 << 20)) {
245 return CXL_MBOX_INTERNAL_ERROR;
246 }
247
248 id = (void *)cmd->payload;
249 memset(id, 0, sizeof(*id));
250
251 /* PMEM only */
252 snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0);
253
254 id->total_capacity = size / (256 << 20);
255 id->persistent_capacity = size / (256 << 20);
256
257 *len = sizeof(*id);
258 return CXL_MBOX_SUCCESS;
259 }
260
261 #define IMMEDIATE_CONFIG_CHANGE (1 << 1)
262 #define IMMEDIATE_POLICY_CHANGE (1 << 3)
263 #define IMMEDIATE_LOG_CHANGE (1 << 4)
264
265 static struct cxl_cmd cxl_cmd_set[256][256] = {
266 [EVENTS][GET_RECORDS] = { "EVENTS_GET_RECORDS",
267 cmd_events_get_records, 1, 0 },
268 [EVENTS][CLEAR_RECORDS] = { "EVENTS_CLEAR_RECORDS",
269 cmd_events_clear_records, ~0, IMMEDIATE_LOG_CHANGE },
270 [EVENTS][GET_INTERRUPT_POLICY] = { "EVENTS_GET_INTERRUPT_POLICY",
271 cmd_events_get_interrupt_policy, 0, 0 },
272 [EVENTS][SET_INTERRUPT_POLICY] = { "EVENTS_SET_INTERRUPT_POLICY",
273 cmd_events_set_interrupt_policy, 4, IMMEDIATE_CONFIG_CHANGE },
274 [TIMESTAMP][GET] = { "TIMESTAMP_GET", cmd_timestamp_get, 0, 0 },
275 [TIMESTAMP][SET] = { "TIMESTAMP_SET", cmd_timestamp_set, 8, IMMEDIATE_POLICY_CHANGE },
276 [LOGS][GET_SUPPORTED] = { "LOGS_GET_SUPPORTED", cmd_logs_get_supported, 0, 0 },
277 [LOGS][GET_LOG] = { "LOGS_GET_LOG", cmd_logs_get_log, 0x18, 0 },
278 [IDENTIFY][MEMORY_DEVICE] = { "IDENTIFY_MEMORY_DEVICE",
279 cmd_identify_memory_device, 0, 0 },
280 };
281
282 void cxl_process_mailbox(CXLDeviceState *cxl_dstate)
283 {
284 uint16_t ret = CXL_MBOX_SUCCESS;
285 struct cxl_cmd *cxl_cmd;
286 uint64_t status_reg;
287 opcode_handler h;
288 uint64_t command_reg = cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD];
289
290 uint8_t set = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET);
291 uint8_t cmd = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND);
292 uint16_t len = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH);
293 cxl_cmd = &cxl_cmd_set[set][cmd];
294 h = cxl_cmd->handler;
295 if (h) {
296 if (len == cxl_cmd->in) {
297 cxl_cmd->payload = cxl_dstate->mbox_reg_state +
298 A_CXL_DEV_CMD_PAYLOAD;
299 ret = (*h)(cxl_cmd, cxl_dstate, &len);
300 assert(len <= cxl_dstate->payload_size);
301 } else {
302 ret = CXL_MBOX_INVALID_PAYLOAD_LENGTH;
303 }
304 } else {
305 qemu_log_mask(LOG_UNIMP, "Command %04xh not implemented\n",
306 set << 8 | cmd);
307 ret = CXL_MBOX_UNSUPPORTED;
308 }
309
310 /* Set the return code */
311 status_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_STS, ERRNO, ret);
312
313 /* Set the return length */
314 command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET, 0);
315 command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND, 0);
316 command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH, len);
317
318 cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD] = command_reg;
319 cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_STS] = status_reg;
320
321 /* Tell the host we're done */
322 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL,
323 DOORBELL, 0);
324 }
325
326 int cxl_initialize_mailbox(CXLDeviceState *cxl_dstate)
327 {
328 /* CXL 2.0: Table 169 Get Supported Logs Log Entry */
329 const char *cel_uuidstr = "0da9c0b5-bf41-4b78-8f79-96b1623b3f17";
330
331 for (int set = 0; set < 256; set++) {
332 for (int cmd = 0; cmd < 256; cmd++) {
333 if (cxl_cmd_set[set][cmd].handler) {
334 struct cxl_cmd *c = &cxl_cmd_set[set][cmd];
335 struct cel_log *log =
336 &cxl_dstate->cel_log[cxl_dstate->cel_size];
337
338 log->opcode = (set << 8) | cmd;
339 log->effect = c->effect;
340 cxl_dstate->cel_size++;
341 }
342 }
343 }
344
345 return qemu_uuid_parse(cel_uuidstr, &cel_uuid);
346 }