2 * QEMU i8255x (PRO100) emulation
4 * Copyright (c) 2006-2007 Stefan Weil
6 * Portions of the code are copies from grub / etherboot eepro100.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
22 * Tested features (i82559):
23 * PXE boot (i386) no valid link
24 * Linux networking (i386) ok
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
36 #if defined(TARGET_I386)
37 # warning "PXE boot still not working!"
40 #include <stddef.h> /* offsetof */
45 #include "eeprom93xx.h"
47 /* Common declarations for all PCI devices. */
49 #define PCI_CONFIG_8(offset, value) \
50 (pci_conf[offset] = (value))
51 #define PCI_CONFIG_16(offset, value) \
52 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
53 #define PCI_CONFIG_32(offset, value) \
54 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
58 /* Debug EEPRO100 card. */
59 //~ #define DEBUG_EEPRO100
62 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
64 #define logout(fmt, ...) ((void)0)
67 /* Set flags to 0 to disable debug output. */
68 #define INT 1 /* interrupt related actions */
69 #define MDI 1 /* mdi related actions */
72 #define EEPROM 1 /* eeprom related actions */
74 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
76 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
78 #define MAX_ETH_FRAME_SIZE 1514
80 /* This driver supports several different devices which are declared here. */
81 #define i82550 0x82550
82 #define i82551 0x82551
83 #define i82557A 0x82557a
84 #define i82557B 0x82557b
85 #define i82557C 0x82557c
86 #define i82558A 0x82558a
87 #define i82558B 0x82558b
88 #define i82559A 0x82559a
89 #define i82559B 0x82559b
90 #define i82559C 0x82559c
91 #define i82559ER 0x82559e
92 #define i82562 0x82562
94 /* Use 64 word EEPROM. TODO: could be a runtime option. */
95 #define EEPROM_SIZE 64
97 #define PCI_MEM_SIZE (4 * KiB)
98 #define PCI_IO_SIZE 64
99 #define PCI_FLASH_SIZE (128 * KiB)
101 #define BIT(n) (1 << (n))
102 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
104 /* The SCB accepts the following controls for the Tx and Rx units: */
105 #define CU_NOP 0x0000 /* No operation. */
106 #define CU_START 0x0010 /* CU start. */
107 #define CU_RESUME 0x0020 /* CU resume. */
108 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
109 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
110 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
111 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
112 #define CU_SRESUME 0x00a0 /* CU static resume. */
114 #define RU_NOP 0x0000
115 #define RX_START 0x0001
116 #define RX_RESUME 0x0002
117 #define RX_ABORT 0x0004
118 #define RX_ADDR_LOAD 0x0006
119 #define RX_RESUMENR 0x0007
120 #define INT_MASK 0x0100
121 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
123 /* Offsets to the various registers.
124 All accesses need not be longword aligned. */
125 enum speedo_offsets
{
128 SCBCmd
= 2, /* Rx/Command Unit command and status. */
130 SCBPointer
= 4, /* General purpose pointer. */
131 SCBPort
= 8, /* Misc. commands and operands. */
132 SCBflash
= 12, SCBeeprom
= 14, /* EEPROM and flash memory control. */
133 SCBCtrlMDI
= 16, /* MDI interface control. */
134 SCBEarlyRx
= 20, /* Early receive byte count. */
138 /* A speedo3 transmit buffer descriptor with two buffers... */
142 uint32_t link
; /* void * */
143 uint32_t tx_desc_addr
; /* transmit buffer decsriptor array address. */
144 uint16_t tcb_bytes
; /* transmit command block byte count (in lower 14 bits */
145 uint8_t tx_threshold
; /* transmit threshold */
146 uint8_t tbd_count
; /* TBD number */
147 //~ /* This constitutes two "TBD" entries: hdr and data */
148 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
149 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
150 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
151 //~ int32_t tx_buf_size1; /* Length of Tx data. */
154 /* Receive frame descriptor. */
158 uint32_t link
; /* struct RxFD * */
159 uint32_t rx_buf_addr
; /* void * */
162 char packet
[MAX_ETH_FRAME_SIZE
+ 4];
166 uint32_t tx_good_frames
, tx_max_collisions
, tx_late_collisions
,
167 tx_underruns
, tx_lost_crs
, tx_deferred
, tx_single_collisions
,
168 tx_multiple_collisions
, tx_total_collisions
;
169 uint32_t rx_good_frames
, rx_crc_errors
, rx_alignment_errors
,
170 rx_resource_errors
, rx_overrun_errors
, rx_cdt_errors
,
171 rx_short_frame_errors
;
172 uint32_t fc_xmt_pause
, fc_rcv_pause
, fc_rcv_unsupported
;
173 uint16_t xmt_tco_frames
, rcv_tco_frames
;
194 uint8_t mult
[8]; /* multicast mask array */
198 uint8_t scb_stat
; /* SCB stat/ack byte */
199 uint8_t int_stat
; /* PCI interrupt status */
200 /* region must not be saved by nic_save. */
201 uint32_t region
[3]; /* PCI region addresses */
204 uint32_t device
; /* device variant */
206 /* (cu_base + cu_offset) address the next command block in the command block list. */
207 uint32_t cu_base
; /* CU base address */
208 uint32_t cu_offset
; /* CU address offset */
209 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
210 uint32_t ru_base
; /* RU base address */
211 uint32_t ru_offset
; /* RU address offset */
212 uint32_t statsaddr
; /* pointer to eepro100_stats_t */
213 eepro100_stats_t statistics
; /* statistical counters */
218 /* Configuration bytes. */
219 uint8_t configuration
[22];
221 /* Data in mem is always in the byte order of the controller (le). */
222 uint8_t mem
[PCI_MEM_SIZE
];
223 /* vmstate for each particular nic */
224 VMStateDescription
*vmstate
;
227 /* Default values for MDI (PHY) registers */
228 static const uint16_t eepro100_mdi_default
[] = {
229 /* MDI Registers 0 - 6, 7 */
230 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
231 /* MDI Registers 8 - 15 */
232 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
233 /* MDI Registers 16 - 31 */
234 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
235 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
238 /* Readonly mask for MDI (PHY) registers */
239 static const uint16_t eepro100_mdi_mask
[] = {
240 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
241 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
242 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
243 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
246 #define POLYNOMIAL 0x04c11db6
250 static int compute_mcast_idx(const uint8_t * ep
)
257 for (i
= 0; i
< 6; i
++) {
259 for (j
= 0; j
< 8; j
++) {
260 carry
= ((crc
& 0x80000000L
) ? 1 : 0) ^ (b
& 0x01);
264 crc
= ((crc
^ POLYNOMIAL
) | carry
);
271 #if defined(DEBUG_EEPRO100)
272 static const char *nic_dump(const uint8_t * buf
, unsigned size
)
274 static char dump
[3 * 16 + 1];
280 p
+= sprintf(p
, " %02x", *buf
++);
284 #endif /* DEBUG_EEPRO100 */
287 stat_ack_not_ours
= 0x00,
288 stat_ack_sw_gen
= 0x04,
290 stat_ack_cu_idle
= 0x20,
291 stat_ack_frame_rx
= 0x40,
292 stat_ack_cu_cmd_done
= 0x80,
293 stat_ack_not_present
= 0xFF,
294 stat_ack_rx
= (stat_ack_sw_gen
| stat_ack_rnr
| stat_ack_frame_rx
),
295 stat_ack_tx
= (stat_ack_cu_idle
| stat_ack_cu_cmd_done
),
298 static void disable_interrupt(EEPRO100State
* s
)
301 TRACE(INT
, logout("interrupt disabled\n"));
302 qemu_irq_lower(s
->dev
.irq
[0]);
307 static void enable_interrupt(EEPRO100State
* s
)
310 TRACE(INT
, logout("interrupt enabled\n"));
311 qemu_irq_raise(s
->dev
.irq
[0]);
316 static void eepro100_acknowledge(EEPRO100State
* s
)
318 s
->scb_stat
&= ~s
->mem
[SCBAck
];
319 s
->mem
[SCBAck
] = s
->scb_stat
;
320 if (s
->scb_stat
== 0) {
321 disable_interrupt(s
);
325 static void eepro100_interrupt(EEPRO100State
* s
, uint8_t stat
)
327 uint8_t mask
= ~s
->mem
[SCBIntmask
];
328 s
->mem
[SCBAck
] |= stat
;
329 stat
= s
->scb_stat
= s
->mem
[SCBAck
];
330 stat
&= (mask
| 0x0f);
331 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
332 if (stat
&& (mask
& 0x01)) {
333 /* SCB mask and SCB Bit M do not disable interrupt. */
335 } else if (s
->int_stat
) {
336 disable_interrupt(s
);
340 static void eepro100_cx_interrupt(EEPRO100State
* s
)
342 /* CU completed action command. */
343 /* Transmit not ok (82557 only, not in emulation). */
344 eepro100_interrupt(s
, 0x80);
347 static void eepro100_cna_interrupt(EEPRO100State
* s
)
349 /* CU left the active state. */
350 eepro100_interrupt(s
, 0x20);
353 static void eepro100_fr_interrupt(EEPRO100State
* s
)
355 /* RU received a complete frame. */
356 eepro100_interrupt(s
, 0x40);
360 static void eepro100_rnr_interrupt(EEPRO100State
* s
)
362 /* RU is not ready. */
363 eepro100_interrupt(s
, 0x10);
367 static void eepro100_mdi_interrupt(EEPRO100State
* s
)
369 /* MDI completed read or write cycle. */
370 eepro100_interrupt(s
, 0x08);
373 static void eepro100_swi_interrupt(EEPRO100State
* s
)
375 /* Software has requested an interrupt. */
376 eepro100_interrupt(s
, 0x04);
380 static void eepro100_fcp_interrupt(EEPRO100State
* s
)
382 /* Flow control pause interrupt (82558 and later). */
383 eepro100_interrupt(s
, 0x01);
387 static void pci_reset(EEPRO100State
* s
)
389 uint32_t device
= s
->device
;
390 uint8_t *pci_conf
= s
->dev
.config
;
392 TRACE(OTHER
, logout("%p\n", s
));
395 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
396 /* PCI Device ID depends on device and is set below. */
398 PCI_CONFIG_16(PCI_COMMAND
, 0x0000);
400 PCI_CONFIG_16(PCI_STATUS
, 0x2800);
401 /* PCI Revision ID */
402 PCI_CONFIG_8(PCI_REVISION_ID
, 0x08);
404 PCI_CONFIG_8(0x09, 0x00);
405 pci_config_set_class(pci_conf
, PCI_CLASS_NETWORK_ETHERNET
);
406 /* PCI Cache Line Size */
407 /* check cache line size!!! */
408 //~ PCI_CONFIG_8(0x0c, 0x00);
409 /* PCI Latency Timer */
410 PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks
411 /* PCI Header Type */
412 /* BIST (built-in self test) */
413 #if defined(TARGET_I386)
414 // !!! workaround for buggy bios
415 //~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0
418 /* PCI Base Address Registers */
419 /* CSR Memory Mapped Base Address */
420 PCI_CONFIG_32(PCI_BASE_ADDRESS_0
,
421 PCI_ADDRESS_SPACE_MEM
| PCI_ADDRESS_SPACE_MEM_PREFETCH
);
422 /* CSR I/O Mapped Base Address */
423 PCI_CONFIG_32(PCI_BASE_ADDRESS_1
, PCI_ADDRESS_SPACE_IO
);
425 /* Flash Memory Mapped Base Address */
426 PCI_CONFIG_32(PCI_BASE_ADDRESS_2
, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM
);
429 /* Expansion ROM Base Address (depends on boot disable!!!) */
430 PCI_CONFIG_32(0x30, 0x00000000);
431 /* Capability Pointer */
432 PCI_CONFIG_8(0x34, 0xdc);
435 PCI_CONFIG_8(0x3d, 1); // interrupt pin 0
437 PCI_CONFIG_8(0x3e, 0x08);
438 /* Maximum Latency */
439 PCI_CONFIG_8(0x3f, 0x18);
440 /* Power Management Capabilities / Next Item Pointer / Capability ID */
441 PCI_CONFIG_32(0xdc, 0x7e210001);
445 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82551IT
);
446 PCI_CONFIG_8(PCI_REVISION_ID
, 0x0f);
449 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
450 PCI_CONFIG_8(PCI_REVISION_ID
, 0x02);
453 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
454 PCI_CONFIG_8(PCI_REVISION_ID
, 0x03);
457 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
458 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
459 PCI_CONFIG_8(PCI_REVISION_ID
, 0x05);
462 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
463 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
464 //~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
467 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82551IT
);
468 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
469 PCI_CONFIG_8(PCI_REVISION_ID
, 0x09);
471 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029);
472 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */
474 logout("Device %X is undefined!\n", device
);
477 if (device
== i82557C
|| device
== i82558B
|| device
== i82559C
) {
478 logout("Get device id and revision from EEPROM!!!\n");
482 static void nic_selective_reset(EEPRO100State
* s
)
485 uint16_t *eeprom_contents
= eeprom93xx_data(s
->eeprom
);
486 //~ eeprom93xx_reset(s->eeprom);
487 memcpy(eeprom_contents
, s
->conf
.macaddr
.a
, 6);
488 eeprom_contents
[0xa] = 0x4000;
489 if (s
->device
== i82557B
|| s
->device
== i82557C
)
490 eeprom_contents
[5] = 0x0100;
492 for (i
= 0; i
< EEPROM_SIZE
- 1; i
++) {
493 sum
+= eeprom_contents
[i
];
495 eeprom_contents
[EEPROM_SIZE
- 1] = 0xbaba - sum
;
496 TRACE(EEPROM
, logout("checksum=0x%04x\n", eeprom_contents
[EEPROM_SIZE
- 1]));
498 memset(s
->mem
, 0, sizeof(s
->mem
));
499 uint32_t val
= BIT(21);
500 memcpy(&s
->mem
[SCBCtrlMDI
], &val
, sizeof(val
));
502 assert(sizeof(s
->mdimem
) == sizeof(eepro100_mdi_default
));
503 memcpy(&s
->mdimem
[0], &eepro100_mdi_default
[0], sizeof(s
->mdimem
));
506 static void nic_reset(void *opaque
)
508 EEPRO100State
*s
= opaque
;
509 TRACE(OTHER
, logout("%p\n", s
));
510 nic_selective_reset(s
);
513 #if defined(DEBUG_EEPRO100)
514 static const char * const reg
[PCI_IO_SIZE
/ 4] = {
518 "EEPROM/Flash Control",
520 "Receive DMA Byte Count",
522 "General Status/Control"
525 static char *regname(uint32_t addr
)
528 if (addr
< PCI_IO_SIZE
) {
529 const char *r
= reg
[addr
/ 4];
531 snprintf(buf
, sizeof(buf
), "%s+%u", r
, addr
% 4);
533 snprintf(buf
, sizeof(buf
), "0x%02x", addr
);
536 snprintf(buf
, sizeof(buf
), "??? 0x%08x", addr
);
540 #endif /* DEBUG_EEPRO100 */
543 static uint16_t eepro100_read_status(EEPRO100State
* s
)
545 uint16_t val
= s
->status
;
546 TRACE(OTHER
, logout("val=0x%04x\n", val
));
550 static void eepro100_write_status(EEPRO100State
* s
, uint16_t val
)
552 TRACE(OTHER
, logout("val=0x%04x\n", val
));
557 /*****************************************************************************
561 ****************************************************************************/
564 static uint16_t eepro100_read_command(EEPRO100State
* s
)
566 uint16_t val
= 0xffff;
567 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
572 static bool device_supports_eTxCB(EEPRO100State
* s
)
574 return (s
->device
!= i82557B
&& s
->device
!= i82557C
);
577 /* Commands that can be put in a command list entry. */
582 CmdMulticastList
= 3,
584 CmdTDR
= 5, /* load microcode */
588 /* And some extra flags: */
589 CmdSuspend
= 0x4000, /* Suspend after completion. */
590 CmdIntr
= 0x2000, /* Interrupt after completion. */
591 CmdTxFlex
= 0x0008, /* Use "Flexible mode" for CmdTx command. */
594 static cu_state_t
get_cu_state(EEPRO100State
* s
)
596 return ((s
->mem
[SCBStatus
] >> 6) & 0x03);
599 static void set_cu_state(EEPRO100State
* s
, cu_state_t state
)
601 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & 0x3f) + (state
<< 6);
604 static ru_state_t
get_ru_state(EEPRO100State
* s
)
606 return ((s
->mem
[SCBStatus
] >> 2) & 0x0f);
609 static void set_ru_state(EEPRO100State
* s
, ru_state_t state
)
611 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & 0xc3) + (state
<< 2);
614 static void dump_statistics(EEPRO100State
* s
)
616 /* Dump statistical data. Most data is never changed by the emulation
617 * and always 0, so we first just copy the whole block and then those
618 * values which really matter.
619 * Number of data should check configuration!!!
621 cpu_physical_memory_write(s
->statsaddr
, (uint8_t *) & s
->statistics
, 64);
622 stl_phys(s
->statsaddr
+ 0, s
->statistics
.tx_good_frames
);
623 stl_phys(s
->statsaddr
+ 36, s
->statistics
.rx_good_frames
);
624 stl_phys(s
->statsaddr
+ 48, s
->statistics
.rx_resource_errors
);
625 stl_phys(s
->statsaddr
+ 60, s
->statistics
.rx_short_frame_errors
);
626 //~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
627 //~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
628 //~ missing("CU dump statistical counters");
631 static void action_command(EEPRO100State
*s
)
634 uint32_t cb_address
= s
->cu_base
+ s
->cu_offset
;
636 cpu_physical_memory_read(cb_address
, (uint8_t *) & tx
, sizeof(tx
));
637 uint16_t status
= le16_to_cpu(tx
.status
);
638 uint16_t command
= le16_to_cpu(tx
.command
);
640 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
641 val
, status
, command
, tx
.link
);
642 bool bit_el
= ((command
& 0x8000) != 0);
643 bool bit_s
= ((command
& 0x4000) != 0);
644 bool bit_i
= ((command
& 0x2000) != 0);
645 bool bit_nc
= ((command
& 0x0010) != 0);
647 //~ bool bit_sf = ((command & 0x0008) != 0);
648 uint16_t cmd
= command
& 0x0007;
649 s
->cu_offset
= le32_to_cpu(tx
.link
);
655 cpu_physical_memory_read(cb_address
+ 8, &s
->conf
.macaddr
.a
[0], 6);
656 TRACE(OTHER
, logout("macaddr: %s\n", nic_dump(&s
->macaddr
[0], 6)));
659 cpu_physical_memory_read(cb_address
+ 8, &s
->configuration
[0],
660 sizeof(s
->configuration
));
661 TRACE(OTHER
, logout("configuration: %s\n", nic_dump(&s
->configuration
[0], 16)));
663 case CmdMulticastList
:
664 //~ missing("multicast list");
668 uint32_t tbd_array
= le32_to_cpu(tx
.tx_desc_addr
);
669 uint16_t tcb_bytes
= (le16_to_cpu(tx
.tcb_bytes
) & 0x3fff);
671 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
672 tbd_array
, tcb_bytes
, tx
.tbd_count
));
675 missing("CmdTx: NC = 0");
680 if (tcb_bytes
> 2600) {
681 logout("TCB byte count too large, using 2600\n");
684 /* Next assertion fails for local configuration. */
685 //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
686 if (!((tcb_bytes
> 0) || (tbd_array
!= 0xffffffff))) {
688 ("illegal values of TBD array address and TCB byte count!\n");
690 // sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes
693 uint32_t tbd_address
= cb_address
+ 0x10;
694 assert(tcb_bytes
<= sizeof(buf
));
695 while (size
< tcb_bytes
) {
696 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
697 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
698 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
701 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
702 tx_buffer_address
, tx_buffer_size
));
703 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
704 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
706 size
+= tx_buffer_size
;
708 if (tbd_array
== 0xffffffff) {
709 /* Simplified mode. Was already handled by code above. */
712 uint8_t tbd_count
= 0;
713 if (device_supports_eTxCB(s
) && !(s
->configuration
[6] & BIT(4))) {
714 /* Extended Flexible TCB. */
715 for (; tbd_count
< 2; tbd_count
++) {
716 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
717 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
718 uint16_t tx_buffer_el
= lduw_phys(tbd_address
+ 6);
721 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
722 tx_buffer_address
, tx_buffer_size
));
723 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
724 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
726 size
+= tx_buffer_size
;
727 if (tx_buffer_el
& 1) {
732 tbd_address
= tbd_array
;
733 for (; tbd_count
< tx
.tbd_count
; tbd_count
++) {
734 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
735 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
736 uint16_t tx_buffer_el
= lduw_phys(tbd_address
+ 6);
739 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
740 tx_buffer_address
, tx_buffer_size
));
741 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
742 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
744 size
+= tx_buffer_size
;
745 if (tx_buffer_el
& 1) {
750 TRACE(RXTX
, logout("%p sending frame, len=%d,%s\n", s
, size
, nic_dump(buf
, size
)));
751 qemu_send_packet(s
->vc
, buf
, size
);
752 s
->statistics
.tx_good_frames
++;
753 /* Transmit with bad status would raise an CX/TNO interrupt.
754 * (82557 only). Emulation never has bad status. */
755 //~ eepro100_cx_interrupt(s);
758 TRACE(OTHER
, logout("load microcode\n"));
759 /* Starting with offset 8, the command contains
760 * 64 dwords microcode which we just ignore here. */
763 missing("undefined command");
767 /* Write new status. */
768 stw_phys(cb_address
, status
| 0x8000 | (success
? 0x2000 : 0));
770 /* CU completed action. */
771 eepro100_cx_interrupt(s
);
774 /* CU becomes idle. Terminate command loop. */
775 set_cu_state(s
, cu_idle
);
776 eepro100_cna_interrupt(s
);
779 /* CU becomes suspended. Terminate command loop. */
780 set_cu_state(s
, cu_suspended
);
781 eepro100_cna_interrupt(s
);
784 /* More entries in list. */
785 TRACE(OTHER
, logout("CU list with at least one more entry\n"));
788 TRACE(OTHER
, logout("CU list empty\n"));
789 /* List is empty. Now CU is idle or suspended. */
792 static void eepro100_cu_command(EEPRO100State
* s
, uint8_t val
)
799 if (get_cu_state(s
) != cu_idle
) {
800 /* Intel documentation says that CU must be idle for the CU
801 * start command. Intel driver for Linux also starts the CU
802 * from suspended state. */
803 logout("CU state is %u, should be %u\n", get_cu_state(s
), cu_idle
);
804 //~ assert(!"wrong CU state");
806 set_cu_state(s
, cu_active
);
807 s
->cu_offset
= s
->pointer
;
811 if (get_cu_state(s
) != cu_suspended
) {
812 logout("bad CU resume from CU state %u\n", get_cu_state(s
));
813 /* Workaround for bad Linux eepro100 driver which resumes
814 * from idle state. */
815 //~ missing("cu resume");
816 set_cu_state(s
, cu_suspended
);
818 if (get_cu_state(s
) == cu_suspended
) {
819 TRACE(OTHER
, logout("CU resuming\n"));
820 set_cu_state(s
, cu_active
);
825 /* Load dump counters address. */
826 s
->statsaddr
= s
->pointer
;
827 TRACE(OTHER
, logout("val=0x%02x (status address)\n", val
));
830 /* Dump statistical counters. */
831 TRACE(OTHER
, logout("val=0x%02x (dump stats)\n", val
));
836 TRACE(OTHER
, logout("val=0x%02x (CU base address)\n", val
));
837 s
->cu_base
= s
->pointer
;
840 /* Dump and reset statistical counters. */
841 TRACE(OTHER
, logout("val=0x%02x (dump stats and reset)\n", val
));
843 memset(&s
->statistics
, 0, sizeof(s
->statistics
));
846 /* CU static resume. */
847 missing("CU static resume");
850 missing("Undefined CU command");
854 static void eepro100_ru_command(EEPRO100State
* s
, uint8_t val
)
862 if (get_ru_state(s
) != ru_idle
) {
863 logout("RU state is %u, should be %u\n", get_ru_state(s
), ru_idle
);
864 //~ assert(!"wrong RU state");
866 set_ru_state(s
, ru_ready
);
867 s
->ru_offset
= s
->pointer
;
868 TRACE(OTHER
, logout("val=0x%02x (rx start)\n", val
));
872 if (get_ru_state(s
) != ru_suspended
) {
873 logout("RU state is %u, should be %u\n", get_ru_state(s
),
875 //~ assert(!"wrong RU state");
877 set_ru_state(s
, ru_ready
);
881 TRACE(OTHER
, logout("val=0x%02x (RU base address)\n", val
));
882 s
->ru_base
= s
->pointer
;
885 logout("val=0x%02x (undefined RU command)\n", val
);
886 missing("Undefined SU command");
890 static void eepro100_write_command(EEPRO100State
* s
, uint8_t val
)
892 eepro100_ru_command(s
, val
& 0x0f);
893 eepro100_cu_command(s
, val
& 0xf0);
895 TRACE(OTHER
, logout("val=0x%02x\n", val
));
897 /* Clear command byte after command was accepted. */
901 /*****************************************************************************
905 ****************************************************************************/
907 #define EEPROM_CS 0x02
908 #define EEPROM_SK 0x01
909 #define EEPROM_DI 0x04
910 #define EEPROM_DO 0x08
912 static uint16_t eepro100_read_eeprom(EEPRO100State
* s
)
915 memcpy(&val
, &s
->mem
[SCBeeprom
], sizeof(val
));
916 if (eeprom93xx_read(s
->eeprom
)) {
921 TRACE(EEPROM
, logout("val=0x%04x\n", val
));
925 static void eepro100_write_eeprom(eeprom_t
* eeprom
, uint8_t val
)
927 TRACE(EEPROM
, logout("val=0x%02x\n", val
));
929 /* mask unwriteable bits */
930 //~ val = SET_MASKED(val, 0x31, eeprom->value);
932 int eecs
= ((val
& EEPROM_CS
) != 0);
933 int eesk
= ((val
& EEPROM_SK
) != 0);
934 int eedi
= ((val
& EEPROM_DI
) != 0);
935 eeprom93xx_write(eeprom
, eecs
, eesk
, eedi
);
938 static void eepro100_write_pointer(EEPRO100State
* s
, uint32_t val
)
940 s
->pointer
= le32_to_cpu(val
);
941 TRACE(OTHER
, logout("val=0x%08x\n", val
));
944 /*****************************************************************************
948 ****************************************************************************/
950 #if defined(DEBUG_EEPRO100)
951 static const char * const mdi_op_name
[] = {
958 static const char * const mdi_reg_name
[] = {
961 "PHY Identification (Word 1)",
962 "PHY Identification (Word 2)",
963 "Auto-Negotiation Advertisement",
964 "Auto-Negotiation Link Partner Ability",
965 "Auto-Negotiation Expansion"
968 static const char *reg2name(uint8_t reg
)
970 static char buffer
[10];
971 const char *p
= buffer
;
972 if (reg
< ARRAY_SIZE(mdi_reg_name
)) {
973 p
= mdi_reg_name
[reg
];
975 snprintf(buffer
, sizeof(buffer
), "reg=0x%02x", reg
);
979 #endif /* DEBUG_EEPRO100 */
981 static uint32_t eepro100_read_mdi(EEPRO100State
* s
)
984 memcpy(&val
, &s
->mem
[0x10], sizeof(val
));
986 #ifdef DEBUG_EEPRO100
987 uint8_t raiseint
= (val
& BIT(29)) >> 29;
988 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
989 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
990 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
991 uint16_t data
= (val
& BITS(15, 0));
993 /* Emulation takes no time to finish MDI transaction. */
995 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
996 val
, raiseint
, mdi_op_name
[opcode
], phy
,
997 reg2name(reg
), data
));
1001 static void eepro100_write_mdi(EEPRO100State
* s
, uint32_t val
)
1003 uint8_t raiseint
= (val
& BIT(29)) >> 29;
1004 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
1005 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
1006 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
1007 uint16_t data
= (val
& BITS(15, 0));
1008 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1009 val
, raiseint
, mdi_op_name
[opcode
], phy
, reg2name(reg
), data
));
1011 /* Unsupported PHY address. */
1012 //~ logout("phy must be 1 but is %u\n", phy);
1014 } else if (opcode
!= 1 && opcode
!= 2) {
1015 /* Unsupported opcode. */
1016 logout("opcode must be 1 or 2 but is %u\n", opcode
);
1018 } else if (reg
> 6) {
1019 /* Unsupported register. */
1020 logout("register must be 0...6 but is %u\n", reg
);
1023 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1024 val
, raiseint
, mdi_op_name
[opcode
], phy
,
1025 reg2name(reg
), data
));
1029 case 0: /* Control Register */
1030 if (data
& 0x8000) {
1031 /* Reset status and control registers to default. */
1032 s
->mdimem
[0] = eepro100_mdi_default
[0];
1033 s
->mdimem
[1] = eepro100_mdi_default
[1];
1034 data
= s
->mdimem
[reg
];
1036 /* Restart Auto Configuration = Normal Operation */
1040 case 1: /* Status Register */
1041 missing("not writable");
1042 data
= s
->mdimem
[reg
];
1044 case 2: /* PHY Identification Register (Word 1) */
1045 case 3: /* PHY Identification Register (Word 2) */
1046 missing("not implemented");
1048 case 4: /* Auto-Negotiation Advertisement Register */
1049 case 5: /* Auto-Negotiation Link Partner Ability Register */
1051 case 6: /* Auto-Negotiation Expansion Register */
1053 missing("not implemented");
1055 s
->mdimem
[reg
] = data
;
1056 } else if (opcode
== 2) {
1059 case 0: /* Control Register */
1060 if (data
& 0x8000) {
1061 /* Reset status and control registers to default. */
1062 s
->mdimem
[0] = eepro100_mdi_default
[0];
1063 s
->mdimem
[1] = eepro100_mdi_default
[1];
1066 case 1: /* Status Register */
1067 s
->mdimem
[reg
] |= 0x0020;
1069 case 2: /* PHY Identification Register (Word 1) */
1070 case 3: /* PHY Identification Register (Word 2) */
1071 case 4: /* Auto-Negotiation Advertisement Register */
1073 case 5: /* Auto-Negotiation Link Partner Ability Register */
1074 s
->mdimem
[reg
] = 0x41fe;
1076 case 6: /* Auto-Negotiation Expansion Register */
1077 s
->mdimem
[reg
] = 0x0001;
1080 data
= s
->mdimem
[reg
];
1082 /* Emulation takes no time to finish MDI transaction.
1083 * Set MDI bit in SCB status register. */
1084 s
->mem
[SCBAck
] |= 0x08;
1087 eepro100_mdi_interrupt(s
);
1090 val
= (val
& 0xffff0000) + data
;
1091 memcpy(&s
->mem
[0x10], &val
, sizeof(val
));
1094 /*****************************************************************************
1098 ****************************************************************************/
1100 #define PORT_SOFTWARE_RESET 0
1101 #define PORT_SELFTEST 1
1102 #define PORT_SELECTIVE_RESET 2
1104 #define PORT_SELECTION_MASK 3
1107 uint32_t st_sign
; /* Self Test Signature */
1108 uint32_t st_result
; /* Self Test Results */
1109 } eepro100_selftest_t
;
1111 static uint32_t eepro100_read_port(EEPRO100State
* s
)
1116 static void eepro100_write_port(EEPRO100State
* s
, uint32_t val
)
1118 val
= le32_to_cpu(val
);
1119 uint32_t address
= (val
& ~PORT_SELECTION_MASK
);
1120 uint8_t selection
= (val
& PORT_SELECTION_MASK
);
1121 switch (selection
) {
1122 case PORT_SOFTWARE_RESET
:
1126 TRACE(OTHER
, logout("selftest address=0x%08x\n", address
));
1127 eepro100_selftest_t data
;
1128 cpu_physical_memory_read(address
, (uint8_t *) & data
, sizeof(data
));
1129 data
.st_sign
= 0xffffffff;
1131 cpu_physical_memory_write(address
, (uint8_t *) & data
, sizeof(data
));
1133 case PORT_SELECTIVE_RESET
:
1134 TRACE(OTHER
, logout("selective reset, selftest address=0x%08x\n", address
));
1135 nic_selective_reset(s
);
1138 logout("val=0x%08x\n", val
);
1139 missing("unknown port selection");
1143 /*****************************************************************************
1145 * General hardware emulation.
1147 ****************************************************************************/
1149 static uint8_t eepro100_read1(EEPRO100State
* s
, uint32_t addr
)
1152 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1153 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1158 //~ val = eepro100_read_status(s);
1159 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1162 //~ val = eepro100_read_status(s);
1163 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1166 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1167 //~ val = eepro100_read_command(s);
1170 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1173 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1176 val
= eepro100_read_eeprom(s
);
1178 case 0x1b: /* PMDR (power management driver register) */
1180 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1182 case 0x1d: /* general status register */
1183 /* 100 Mbps full duplex, valid link */
1185 TRACE(OTHER
, logout("addr=General Status val=%02x\n", val
));
1188 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1189 missing("unknown byte read");
1194 static uint16_t eepro100_read2(EEPRO100State
* s
, uint32_t addr
)
1197 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1198 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1203 //~ val = eepro100_read_status(s);
1205 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1208 val
= eepro100_read_eeprom(s
);
1209 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1212 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1213 missing("unknown word read");
1218 static uint32_t eepro100_read4(EEPRO100State
* s
, uint32_t addr
)
1221 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1222 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1227 //~ val = eepro100_read_status(s);
1228 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1231 //~ val = eepro100_read_pointer(s);
1232 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1235 val
= eepro100_read_port(s
);
1236 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1239 val
= eepro100_read_mdi(s
);
1242 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1243 missing("unknown longword read");
1248 static void eepro100_write1(EEPRO100State
* s
, uint32_t addr
, uint8_t val
)
1250 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1251 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1254 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1258 //~ eepro100_write_status(s, val);
1261 eepro100_acknowledge(s
);
1264 eepro100_write_command(s
, val
);
1268 eepro100_swi_interrupt(s
);
1270 eepro100_interrupt(s
, 0);
1273 case SCBFlow
: /* does not exist on 82557 */
1277 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1280 eepro100_write_eeprom(s
->eeprom
, val
);
1283 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1284 missing("unknown byte write");
1288 static void eepro100_write2(EEPRO100State
* s
, uint32_t addr
, uint16_t val
)
1290 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1291 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1294 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1298 //~ eepro100_write_status(s, val);
1299 eepro100_acknowledge(s
);
1302 eepro100_write_command(s
, val
);
1303 eepro100_write1(s
, SCBIntmask
, val
>> 8);
1306 eepro100_write_eeprom(s
->eeprom
, val
);
1309 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1310 missing("unknown word write");
1314 static void eepro100_write4(EEPRO100State
* s
, uint32_t addr
, uint32_t val
)
1316 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1317 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1322 eepro100_write_pointer(s
, val
);
1325 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1326 eepro100_write_port(s
, val
);
1329 eepro100_write_mdi(s
, val
);
1332 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1333 missing("unknown longword write");
1337 /*****************************************************************************
1341 ****************************************************************************/
1343 static uint32_t ioport_read1(void *opaque
, uint32_t addr
)
1345 EEPRO100State
*s
= opaque
;
1346 //~ logout("addr=%s\n", regname(addr));
1347 return eepro100_read1(s
, addr
- s
->region
[1]);
1350 static uint32_t ioport_read2(void *opaque
, uint32_t addr
)
1352 EEPRO100State
*s
= opaque
;
1353 return eepro100_read2(s
, addr
- s
->region
[1]);
1356 static uint32_t ioport_read4(void *opaque
, uint32_t addr
)
1358 EEPRO100State
*s
= opaque
;
1359 return eepro100_read4(s
, addr
- s
->region
[1]);
1362 static void ioport_write1(void *opaque
, uint32_t addr
, uint32_t val
)
1364 EEPRO100State
*s
= opaque
;
1365 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1366 eepro100_write1(s
, addr
- s
->region
[1], val
);
1369 static void ioport_write2(void *opaque
, uint32_t addr
, uint32_t val
)
1371 EEPRO100State
*s
= opaque
;
1372 eepro100_write2(s
, addr
- s
->region
[1], val
);
1375 static void ioport_write4(void *opaque
, uint32_t addr
, uint32_t val
)
1377 EEPRO100State
*s
= opaque
;
1378 eepro100_write4(s
, addr
- s
->region
[1], val
);
1381 /***********************************************************/
1382 /* PCI EEPRO100 definitions */
1384 static void pci_map(PCIDevice
* pci_dev
, int region_num
,
1385 uint32_t addr
, uint32_t size
, int type
)
1387 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1389 TRACE(OTHER
, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1390 region_num
, addr
, size
, type
));
1392 assert(region_num
== 1);
1393 register_ioport_write(addr
, size
, 1, ioport_write1
, s
);
1394 register_ioport_read(addr
, size
, 1, ioport_read1
, s
);
1395 register_ioport_write(addr
, size
, 2, ioport_write2
, s
);
1396 register_ioport_read(addr
, size
, 2, ioport_read2
, s
);
1397 register_ioport_write(addr
, size
, 4, ioport_write4
, s
);
1398 register_ioport_read(addr
, size
, 4, ioport_read4
, s
);
1400 s
->region
[region_num
] = addr
;
1403 /*****************************************************************************
1405 * Memory mapped I/O.
1407 ****************************************************************************/
1409 static void pci_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1411 EEPRO100State
*s
= opaque
;
1412 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1413 eepro100_write1(s
, addr
, val
);
1416 static void pci_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1418 EEPRO100State
*s
= opaque
;
1419 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1420 eepro100_write2(s
, addr
, val
);
1423 static void pci_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1425 EEPRO100State
*s
= opaque
;
1426 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1427 eepro100_write4(s
, addr
, val
);
1430 static uint32_t pci_mmio_readb(void *opaque
, target_phys_addr_t addr
)
1432 EEPRO100State
*s
= opaque
;
1433 //~ logout("addr=%s\n", regname(addr));
1434 return eepro100_read1(s
, addr
);
1437 static uint32_t pci_mmio_readw(void *opaque
, target_phys_addr_t addr
)
1439 EEPRO100State
*s
= opaque
;
1440 //~ logout("addr=%s\n", regname(addr));
1441 return eepro100_read2(s
, addr
);
1444 static uint32_t pci_mmio_readl(void *opaque
, target_phys_addr_t addr
)
1446 EEPRO100State
*s
= opaque
;
1447 //~ logout("addr=%s\n", regname(addr));
1448 return eepro100_read4(s
, addr
);
1451 static CPUWriteMemoryFunc
* const pci_mmio_write
[] = {
1457 static CPUReadMemoryFunc
* const pci_mmio_read
[] = {
1463 static void pci_mmio_map(PCIDevice
* pci_dev
, int region_num
,
1464 uint32_t addr
, uint32_t size
, int type
)
1466 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1468 TRACE(OTHER
, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1469 region_num
, addr
, size
, type
));
1471 if (region_num
== 0) {
1472 /* Map control / status registers. */
1473 cpu_register_physical_memory(addr
, size
, s
->mmio_index
);
1474 s
->region
[region_num
] = addr
;
1478 static int nic_can_receive(VLANClientState
*vc
)
1480 EEPRO100State
*s
= vc
->opaque
;
1481 TRACE(RXTX
, logout("%p\n", s
));
1482 return get_ru_state(s
) == ru_ready
;
1483 //~ return !eepro100_buffer_full(s);
1486 static ssize_t
nic_receive(VLANClientState
*vc
, const uint8_t * buf
, size_t size
)
1489 * - Magic packets should set bit 30 in power management driver register.
1490 * - Interesting packets should set bit 29 in power management driver register.
1492 EEPRO100State
*s
= vc
->opaque
;
1493 uint16_t rfd_status
= 0xa000;
1494 static const uint8_t broadcast_macaddr
[6] =
1495 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1497 /* TODO: check multiple IA bit. */
1498 if (s
->configuration
[20] & BIT(6)) {
1499 missing("Multiple IA bit");
1503 if (s
->configuration
[8] & 0x80) {
1504 /* CSMA is disabled. */
1505 logout("%p received while CSMA is disabled\n", s
);
1507 } else if (size
< 64 && (s
->configuration
[7] & 1)) {
1508 /* Short frame and configuration byte 7/0 (discard short receive) set:
1509 * Short frame is discarded */
1510 logout("%p received short frame (%zu byte)\n", s
, size
);
1511 s
->statistics
.rx_short_frame_errors
++;
1513 } else if ((size
> MAX_ETH_FRAME_SIZE
+ 4) && !(s
->configuration
[18] & 8)) {
1514 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1515 * Long frames are discarded. */
1516 logout("%p received long frame (%zu byte), ignored\n", s
, size
);
1518 } else if (memcmp(buf
, s
->conf
.macaddr
.a
, 6) == 0) { // !!!
1519 /* Frame matches individual address. */
1520 /* TODO: check configuration byte 15/4 (ignore U/L). */
1521 TRACE(RXTX
, logout("%p received frame for me, len=%zu\n", s
, size
));
1522 } else if (memcmp(buf
, broadcast_macaddr
, 6) == 0) {
1523 /* Broadcast frame. */
1524 TRACE(RXTX
, logout("%p received broadcast, len=%zu\n", s
, size
));
1525 rfd_status
|= 0x0002;
1526 } else if (buf
[0] & 0x01) { // !!!
1527 /* Multicast frame. */
1528 TRACE(RXTX
, logout("%p received multicast, len=%zu\n", s
, size
));
1529 /* TODO: check multicast all bit. */
1530 if (s
->configuration
[21] & BIT(3)) {
1531 missing("Multicast All bit");
1533 int mcast_idx
= compute_mcast_idx(buf
);
1534 if (!(s
->mult
[mcast_idx
>> 3] & (1 << (mcast_idx
& 7)))) {
1537 rfd_status
|= 0x0002;
1538 } else if (s
->configuration
[15] & 1) {
1539 /* Promiscuous: receive all. */
1540 TRACE(RXTX
, logout("%p received frame in promiscuous mode, len=%zu\n", s
, size
));
1541 rfd_status
|= 0x0004;
1543 TRACE(RXTX
, logout("%p received frame, ignored, len=%zu,%s\n", s
, size
,
1544 nic_dump(buf
, size
)));
1548 if (get_ru_state(s
) != ru_ready
) {
1549 /* No resources available. */
1550 logout("no resources, state=%u\n", get_ru_state(s
));
1551 s
->statistics
.rx_resource_errors
++;
1552 //~ assert(!"no resources");
1556 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1558 cpu_physical_memory_read(s
->ru_base
+ s
->ru_offset
, (uint8_t *) & rx
,
1559 offsetof(eepro100_rx_t
, packet
));
1560 uint16_t rfd_command
= le16_to_cpu(rx
.command
);
1561 uint16_t rfd_size
= le16_to_cpu(rx
.size
);
1563 if (size
> rfd_size
) {
1564 logout("Receive buffer (%" PRId16
" bytes) too small for data "
1565 "(%zu bytes); data truncated\n", rfd_size
, size
);
1569 rfd_status
|= 0x0080;
1571 TRACE(OTHER
, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1572 rfd_command
, rx
.link
, rx
.rx_buf_addr
, rfd_size
));
1573 stw_phys(s
->ru_base
+ s
->ru_offset
+ offsetof(eepro100_rx_t
, status
),
1575 stw_phys(s
->ru_base
+ s
->ru_offset
+ offsetof(eepro100_rx_t
, count
), size
);
1576 /* Early receive interrupt not supported. */
1577 //~ eepro100_er_interrupt(s);
1578 /* Receive CRC Transfer not supported. */
1579 if (s
->configuration
[18] & 4) {
1580 missing("Receive CRC Transfer");
1583 /* TODO: check stripping enable bit. */
1584 //~ assert(!(s->configuration[17] & 1));
1585 cpu_physical_memory_write(s
->ru_base
+ s
->ru_offset
+
1586 offsetof(eepro100_rx_t
, packet
), buf
, size
);
1587 s
->statistics
.rx_good_frames
++;
1588 eepro100_fr_interrupt(s
);
1589 s
->ru_offset
= le32_to_cpu(rx
.link
);
1590 if (rfd_command
& 0x8000) {
1591 /* EL bit is set, so this was the last frame. */
1592 logout("receive: Running out of frames\n");
1593 set_ru_state(s
, ru_suspended
);
1595 if (rfd_command
& 0x4000) {
1597 set_ru_state(s
, ru_suspended
);
1602 static const VMStateDescription vmstate_eepro100
= {
1604 .minimum_version_id
= 2,
1605 .minimum_version_id_old
= 2,
1606 .fields
= (VMStateField
[]) {
1607 VMSTATE_PCI_DEVICE(dev
, EEPRO100State
),
1609 VMSTATE_BUFFER(mult
, EEPRO100State
),
1610 VMSTATE_BUFFER(mem
, EEPRO100State
),
1611 /* Save all members of struct between scb_stat and mem. */
1612 VMSTATE_UINT8(scb_stat
, EEPRO100State
),
1613 VMSTATE_UINT8(int_stat
, EEPRO100State
),
1614 VMSTATE_UNUSED(3*4),
1615 VMSTATE_MACADDR(conf
.macaddr
, EEPRO100State
),
1616 VMSTATE_UNUSED(19*4),
1617 VMSTATE_UINT16_ARRAY(mdimem
, EEPRO100State
, 32),
1618 /* The eeprom should be saved and restored by its own routines. */
1619 VMSTATE_UINT32(device
, EEPRO100State
),
1620 /* TODO check device. */
1621 VMSTATE_UINT32(pointer
, EEPRO100State
),
1622 VMSTATE_UINT32(cu_base
, EEPRO100State
),
1623 VMSTATE_UINT32(cu_offset
, EEPRO100State
),
1624 VMSTATE_UINT32(ru_base
, EEPRO100State
),
1625 VMSTATE_UINT32(ru_offset
, EEPRO100State
),
1626 VMSTATE_UINT32(statsaddr
, EEPRO100State
),
1627 /* Save epro100_stats_t statistics. */
1628 VMSTATE_UINT32(statistics
.tx_good_frames
, EEPRO100State
),
1629 VMSTATE_UINT32(statistics
.tx_max_collisions
, EEPRO100State
),
1630 VMSTATE_UINT32(statistics
.tx_late_collisions
, EEPRO100State
),
1631 VMSTATE_UINT32(statistics
.tx_underruns
, EEPRO100State
),
1632 VMSTATE_UINT32(statistics
.tx_lost_crs
, EEPRO100State
),
1633 VMSTATE_UINT32(statistics
.tx_deferred
, EEPRO100State
),
1634 VMSTATE_UINT32(statistics
.tx_single_collisions
, EEPRO100State
),
1635 VMSTATE_UINT32(statistics
.tx_multiple_collisions
, EEPRO100State
),
1636 VMSTATE_UINT32(statistics
.tx_total_collisions
, EEPRO100State
),
1637 VMSTATE_UINT32(statistics
.rx_good_frames
, EEPRO100State
),
1638 VMSTATE_UINT32(statistics
.rx_crc_errors
, EEPRO100State
),
1639 VMSTATE_UINT32(statistics
.rx_alignment_errors
, EEPRO100State
),
1640 VMSTATE_UINT32(statistics
.rx_resource_errors
, EEPRO100State
),
1641 VMSTATE_UINT32(statistics
.rx_overrun_errors
, EEPRO100State
),
1642 VMSTATE_UINT32(statistics
.rx_cdt_errors
, EEPRO100State
),
1643 VMSTATE_UINT32(statistics
.rx_short_frame_errors
, EEPRO100State
),
1644 VMSTATE_UINT32(statistics
.fc_xmt_pause
, EEPRO100State
),
1645 VMSTATE_UINT32(statistics
.fc_rcv_pause
, EEPRO100State
),
1646 VMSTATE_UINT32(statistics
.fc_rcv_unsupported
, EEPRO100State
),
1647 VMSTATE_UINT16(statistics
.xmt_tco_frames
, EEPRO100State
),
1648 VMSTATE_UINT16(statistics
.rcv_tco_frames
, EEPRO100State
),
1649 VMSTATE_UINT32(statistics
.complete
, EEPRO100State
),
1651 VMSTATE_UINT16(status
, EEPRO100State
),
1653 /* Configuration bytes. */
1654 VMSTATE_BUFFER(configuration
, EEPRO100State
),
1655 VMSTATE_END_OF_LIST()
1659 static void nic_cleanup(VLANClientState
*vc
)
1661 EEPRO100State
*s
= vc
->opaque
;
1666 static int pci_nic_uninit(PCIDevice
*pci_dev
)
1668 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1670 cpu_unregister_io_memory(s
->mmio_index
);
1671 vmstate_unregister(s
->vmstate
, s
);
1672 eeprom93xx_free(s
->eeprom
);
1673 qemu_del_vlan_client(s
->vc
);
1677 static int nic_init(PCIDevice
*pci_dev
, uint32_t device
)
1679 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1681 TRACE(OTHER
, logout("\n"));
1687 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1688 * i82559 and later support 64 or 256 word EEPROM. */
1689 s
->eeprom
= eeprom93xx_new(EEPROM_SIZE
);
1691 /* Handler for memory-mapped I/O */
1693 cpu_register_io_memory(pci_mmio_read
, pci_mmio_write
, s
);
1695 pci_register_bar(&s
->dev
, 0, PCI_MEM_SIZE
,
1696 PCI_ADDRESS_SPACE_MEM
|
1697 PCI_ADDRESS_SPACE_MEM_PREFETCH
, pci_mmio_map
);
1698 pci_register_bar(&s
->dev
, 1, PCI_IO_SIZE
, PCI_ADDRESS_SPACE_IO
,
1700 pci_register_bar(&s
->dev
, 2, PCI_FLASH_SIZE
, PCI_ADDRESS_SPACE_MEM
,
1703 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
1704 logout("macaddr: %s\n", nic_dump(&s
->macaddr
[0], 6));
1705 assert(s
->region
[1] == 0);
1709 s
->vc
= qemu_new_vlan_client(NET_CLIENT_TYPE_NIC
,
1710 s
->conf
.vlan
, s
->conf
.peer
,
1711 pci_dev
->qdev
.info
->name
, pci_dev
->qdev
.id
,
1712 nic_can_receive
, nic_receive
, NULL
, NULL
,
1715 qemu_format_nic_info_str(s
->vc
, s
->conf
.macaddr
.a
);
1716 TRACE(OTHER
, logout("%s\n", s
->vc
->info_str
));
1718 qemu_register_reset(nic_reset
, s
);
1720 s
->vmstate
= qemu_malloc(sizeof(vmstate_eepro100
));
1721 memcpy(s
->vmstate
, &vmstate_eepro100
, sizeof(vmstate_eepro100
));
1722 s
->vmstate
->name
= s
->vc
->model
;
1723 vmstate_register(-1, s
->vmstate
, s
);
1727 static int pci_i82550_init(PCIDevice
*pci_dev
)
1729 return nic_init(pci_dev
, i82550
);
1732 static int pci_i82551_init(PCIDevice
*pci_dev
)
1734 return nic_init(pci_dev
, i82551
);
1737 static int pci_i82557a_init(PCIDevice
*pci_dev
)
1739 return nic_init(pci_dev
, i82557A
);
1742 static int pci_i82557b_init(PCIDevice
*pci_dev
)
1744 return nic_init(pci_dev
, i82557B
);
1747 static int pci_i82557c_init(PCIDevice
*pci_dev
)
1749 return nic_init(pci_dev
, i82557C
);
1752 static int pci_i82558a_init(PCIDevice
*pci_dev
)
1754 return nic_init(pci_dev
, i82558A
);
1757 static int pci_i82558b_init(PCIDevice
*pci_dev
)
1759 return nic_init(pci_dev
, i82558B
);
1762 static int pci_i82559a_init(PCIDevice
*pci_dev
)
1764 return nic_init(pci_dev
, i82559A
);
1767 static int pci_i82559b_init(PCIDevice
*pci_dev
)
1769 return nic_init(pci_dev
, i82559B
);
1772 static int pci_i82559c_init(PCIDevice
*pci_dev
)
1774 return nic_init(pci_dev
, i82559C
);
1777 static int pci_i82559er_init(PCIDevice
*pci_dev
)
1779 return nic_init(pci_dev
, i82559ER
);
1782 static int pci_i82562_init(PCIDevice
*pci_dev
)
1784 return nic_init(pci_dev
, i82562
);
1787 static PCIDeviceInfo eepro100_info
[] = {
1789 .qdev
.name
= "i82550",
1790 .qdev
.size
= sizeof(EEPRO100State
),
1791 .init
= pci_i82550_init
,
1792 .qdev
.props
= (Property
[]) {
1793 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1794 DEFINE_PROP_END_OF_LIST(),
1797 .qdev
.name
= "i82551",
1798 .qdev
.size
= sizeof(EEPRO100State
),
1799 .init
= pci_i82551_init
,
1800 .exit
= pci_nic_uninit
,
1801 .qdev
.props
= (Property
[]) {
1802 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1803 DEFINE_PROP_END_OF_LIST(),
1806 .qdev
.name
= "i82557a",
1807 .qdev
.size
= sizeof(EEPRO100State
),
1808 .init
= pci_i82557a_init
,
1809 .qdev
.props
= (Property
[]) {
1810 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1811 DEFINE_PROP_END_OF_LIST(),
1814 .qdev
.name
= "i82557b",
1815 .qdev
.size
= sizeof(EEPRO100State
),
1816 .init
= pci_i82557b_init
,
1817 .exit
= pci_nic_uninit
,
1818 .qdev
.props
= (Property
[]) {
1819 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1820 DEFINE_PROP_END_OF_LIST(),
1823 .qdev
.name
= "i82557c",
1824 .qdev
.size
= sizeof(EEPRO100State
),
1825 .init
= pci_i82557c_init
,
1826 .qdev
.props
= (Property
[]) {
1827 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1828 DEFINE_PROP_END_OF_LIST(),
1831 .qdev
.name
= "i82558a",
1832 .qdev
.size
= sizeof(EEPRO100State
),
1833 .init
= pci_i82558a_init
,
1834 .qdev
.props
= (Property
[]) {
1835 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1836 DEFINE_PROP_END_OF_LIST(),
1839 .qdev
.name
= "i82558b",
1840 .qdev
.size
= sizeof(EEPRO100State
),
1841 .init
= pci_i82558b_init
,
1842 .qdev
.props
= (Property
[]) {
1843 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1844 DEFINE_PROP_END_OF_LIST(),
1847 .qdev
.name
= "i82559a",
1848 .qdev
.size
= sizeof(EEPRO100State
),
1849 .init
= pci_i82559a_init
,
1850 .qdev
.props
= (Property
[]) {
1851 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1852 DEFINE_PROP_END_OF_LIST(),
1855 .qdev
.name
= "i82559b",
1856 .qdev
.size
= sizeof(EEPRO100State
),
1857 .init
= pci_i82559b_init
,
1858 .qdev
.props
= (Property
[]) {
1859 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1860 DEFINE_PROP_END_OF_LIST(),
1863 .qdev
.name
= "i82559c",
1864 .qdev
.size
= sizeof(EEPRO100State
),
1865 .init
= pci_i82559c_init
,
1866 .qdev
.props
= (Property
[]) {
1867 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1868 DEFINE_PROP_END_OF_LIST(),
1871 .qdev
.name
= "i82559er",
1872 .qdev
.size
= sizeof(EEPRO100State
),
1873 .init
= pci_i82559er_init
,
1874 .exit
= pci_nic_uninit
,
1875 .qdev
.props
= (Property
[]) {
1876 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1877 DEFINE_PROP_END_OF_LIST(),
1880 .qdev
.name
= "i82562",
1881 .qdev
.size
= sizeof(EEPRO100State
),
1882 .init
= pci_i82562_init
,
1883 .qdev
.props
= (Property
[]) {
1884 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1885 DEFINE_PROP_END_OF_LIST(),
1892 static void eepro100_register_devices(void)
1894 pci_qdev_register_many(eepro100_info
);
1897 device_init(eepro100_register_devices
)