2 * QEMU ESP/NCR53C9x emulation
4 * Copyright (c) 2005-2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
33 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
34 * also produced as NCR89C100. See
35 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
37 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
41 #define DPRINTF(fmt, ...) \
42 do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0)
44 #define DPRINTF(fmt, ...) do {} while (0)
47 #define ESP_ERROR(fmt, ...) \
48 do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
53 typedef struct ESPState ESPState
;
59 uint8_t rregs
[ESP_REGS
];
60 uint8_t wregs
[ESP_REGS
];
62 uint32_t ti_rptr
, ti_wptr
;
63 uint8_t ti_buf
[TI_BUFSZ
];
67 SCSIDevice
*current_dev
;
68 SCSIRequest
*current_req
;
69 uint8_t cmdbuf
[TI_BUFSZ
];
73 /* The amount of data left in the current DMA transfer. */
75 /* The size of the current DMA transfer. Zero if no transfer is in
81 ESPDMAMemoryReadWriteFunc dma_memory_read
;
82 ESPDMAMemoryReadWriteFunc dma_memory_write
;
85 void (*dma_cb
)(ESPState
*s
);
93 #define ESP_WBUSID 0x4
97 #define ESP_WSYNTP 0x6
98 #define ESP_RFLAGS 0x7
101 #define ESP_RRES1 0x9
103 #define ESP_RRES2 0xa
104 #define ESP_WTEST 0xa
115 #define CMD_FLUSH 0x01
116 #define CMD_RESET 0x02
117 #define CMD_BUSRESET 0x03
119 #define CMD_ICCS 0x11
120 #define CMD_MSGACC 0x12
122 #define CMD_SATN 0x1a
124 #define CMD_SELATN 0x42
125 #define CMD_SELATNS 0x43
126 #define CMD_ENSEL 0x44
134 #define STAT_PIO_MASK 0x06
139 #define STAT_INT 0x80
141 #define BUSID_DID 0x07
146 #define INTR_RST 0x80
151 #define CFG1_RESREPT 0x40
153 #define TCHI_FAS100A 0x4
155 static void esp_raise_irq(ESPState
*s
)
157 if (!(s
->rregs
[ESP_RSTAT
] & STAT_INT
)) {
158 s
->rregs
[ESP_RSTAT
] |= STAT_INT
;
159 qemu_irq_raise(s
->irq
);
160 DPRINTF("Raise IRQ\n");
164 static void esp_lower_irq(ESPState
*s
)
166 if (s
->rregs
[ESP_RSTAT
] & STAT_INT
) {
167 s
->rregs
[ESP_RSTAT
] &= ~STAT_INT
;
168 qemu_irq_lower(s
->irq
);
169 DPRINTF("Lower IRQ\n");
173 static void esp_dma_enable(void *opaque
, int irq
, int level
)
175 DeviceState
*d
= opaque
;
176 ESPState
*s
= container_of(d
, ESPState
, busdev
.qdev
);
180 DPRINTF("Raise enable\n");
186 DPRINTF("Lower enable\n");
191 static uint32_t get_cmd(ESPState
*s
, uint8_t *buf
)
196 target
= s
->wregs
[ESP_WBUSID
] & BUSID_DID
;
198 dmalen
= s
->rregs
[ESP_TCLO
] | (s
->rregs
[ESP_TCMID
] << 8);
199 s
->dma_memory_read(s
->dma_opaque
, buf
, dmalen
);
202 memcpy(buf
, s
->ti_buf
, dmalen
);
205 DPRINTF("get_cmd: len %d target %d\n", dmalen
, target
);
211 if (s
->current_dev
) {
212 /* Started a new command before the old one finished. Cancel it. */
213 s
->current_dev
->info
->cancel_io(s
->current_req
);
217 if (target
>= ESP_MAX_DEVS
|| !s
->bus
.devs
[target
]) {
219 s
->rregs
[ESP_RSTAT
] = 0;
220 s
->rregs
[ESP_RINTR
] = INTR_DC
;
221 s
->rregs
[ESP_RSEQ
] = SEQ_0
;
225 s
->current_dev
= s
->bus
.devs
[target
];
229 static void do_busid_cmd(ESPState
*s
, uint8_t *buf
, uint8_t busid
)
234 DPRINTF("do_busid_cmd: busid 0x%x\n", busid
);
236 s
->current_req
= s
->current_dev
->info
->alloc_req(s
->current_dev
, 0, lun
);
237 datalen
= s
->current_dev
->info
->send_command(s
->current_req
, buf
);
238 s
->ti_size
= datalen
;
240 s
->rregs
[ESP_RSTAT
] = STAT_TC
;
244 s
->rregs
[ESP_RSTAT
] |= STAT_DI
;
245 s
->current_dev
->info
->read_data(s
->current_req
);
247 s
->rregs
[ESP_RSTAT
] |= STAT_DO
;
248 s
->current_dev
->info
->write_data(s
->current_req
);
251 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
252 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
256 static void do_cmd(ESPState
*s
, uint8_t *buf
)
258 uint8_t busid
= buf
[0];
260 do_busid_cmd(s
, &buf
[1], busid
);
263 static void handle_satn(ESPState
*s
)
268 if (!s
->dma_enabled
) {
269 s
->dma_cb
= handle_satn
;
272 len
= get_cmd(s
, buf
);
277 static void handle_s_without_atn(ESPState
*s
)
282 if (!s
->dma_enabled
) {
283 s
->dma_cb
= handle_s_without_atn
;
286 len
= get_cmd(s
, buf
);
288 do_busid_cmd(s
, buf
, 0);
292 static void handle_satn_stop(ESPState
*s
)
294 if (!s
->dma_enabled
) {
295 s
->dma_cb
= handle_satn_stop
;
298 s
->cmdlen
= get_cmd(s
, s
->cmdbuf
);
300 DPRINTF("Set ATN & Stop: cmdlen %d\n", s
->cmdlen
);
302 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_CD
;
303 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
304 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
309 static void write_response(ESPState
*s
)
311 DPRINTF("Transfer status (sense=%d)\n", s
->sense
);
312 s
->ti_buf
[0] = s
->sense
;
315 s
->dma_memory_write(s
->dma_opaque
, s
->ti_buf
, 2);
316 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_ST
;
317 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
318 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
323 s
->rregs
[ESP_RFLAGS
] = 2;
328 static void esp_dma_done(ESPState
*s
)
330 s
->rregs
[ESP_RSTAT
] |= STAT_TC
;
331 s
->rregs
[ESP_RINTR
] = INTR_BS
;
332 s
->rregs
[ESP_RSEQ
] = 0;
333 s
->rregs
[ESP_RFLAGS
] = 0;
334 s
->rregs
[ESP_TCLO
] = 0;
335 s
->rregs
[ESP_TCMID
] = 0;
339 static void esp_do_dma(ESPState
*s
)
344 to_device
= (s
->ti_size
< 0);
347 DPRINTF("command len %d + %d\n", s
->cmdlen
, len
);
348 s
->dma_memory_read(s
->dma_opaque
, &s
->cmdbuf
[s
->cmdlen
], len
);
352 do_cmd(s
, s
->cmdbuf
);
355 if (s
->async_len
== 0) {
356 /* Defer until data is available. */
359 if (len
> s
->async_len
) {
363 s
->dma_memory_read(s
->dma_opaque
, s
->async_buf
, len
);
365 s
->dma_memory_write(s
->dma_opaque
, s
->async_buf
, len
);
374 if (s
->async_len
== 0) {
376 // ti_size is negative
377 s
->current_dev
->info
->write_data(s
->current_req
);
379 s
->current_dev
->info
->read_data(s
->current_req
);
380 /* If there is still data to be read from the device then
381 complete the DMA operation immediately. Otherwise defer
382 until the scsi layer has completed. */
383 if (s
->dma_left
== 0 && s
->ti_size
> 0) {
388 /* Partially filled a scsi buffer. Complete immediately. */
393 static void esp_command_complete(SCSIRequest
*req
, int reason
, uint32_t arg
)
395 ESPState
*s
= DO_UPCAST(ESPState
, busdev
.qdev
, req
->bus
->qbus
.parent
);
397 if (reason
== SCSI_REASON_DONE
) {
398 DPRINTF("SCSI Command complete\n");
400 DPRINTF("SCSI command completed unexpectedly\n");
405 DPRINTF("Command failed\n");
407 s
->rregs
[ESP_RSTAT
] = STAT_ST
;
409 if (s
->current_req
) {
410 scsi_req_unref(s
->current_req
);
411 s
->current_req
= NULL
;
412 s
->current_dev
= NULL
;
415 DPRINTF("transfer %d/%d\n", s
->dma_left
, s
->ti_size
);
417 s
->async_buf
= s
->current_dev
->info
->get_buf(req
);
420 } else if (s
->dma_counter
!= 0 && s
->ti_size
<= 0) {
421 /* If this was the last part of a DMA transfer then the
422 completion interrupt is deferred to here. */
428 static void handle_ti(ESPState
*s
)
430 uint32_t dmalen
, minlen
;
432 dmalen
= s
->rregs
[ESP_TCLO
] | (s
->rregs
[ESP_TCMID
] << 8);
436 s
->dma_counter
= dmalen
;
439 minlen
= (dmalen
< 32) ? dmalen
: 32;
440 else if (s
->ti_size
< 0)
441 minlen
= (dmalen
< -s
->ti_size
) ? dmalen
: -s
->ti_size
;
443 minlen
= (dmalen
< s
->ti_size
) ? dmalen
: s
->ti_size
;
444 DPRINTF("Transfer Information len %d\n", minlen
);
446 s
->dma_left
= minlen
;
447 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
449 } else if (s
->do_cmd
) {
450 DPRINTF("command len %d\n", s
->cmdlen
);
454 do_cmd(s
, s
->cmdbuf
);
459 static void esp_hard_reset(DeviceState
*d
)
461 ESPState
*s
= container_of(d
, ESPState
, busdev
.qdev
);
463 memset(s
->rregs
, 0, ESP_REGS
);
464 memset(s
->wregs
, 0, ESP_REGS
);
465 s
->rregs
[ESP_TCHI
] = TCHI_FAS100A
; // Indicate fas100a
473 s
->rregs
[ESP_CFG1
] = 7;
476 static void esp_soft_reset(DeviceState
*d
)
478 ESPState
*s
= container_of(d
, ESPState
, busdev
.qdev
);
480 qemu_irq_lower(s
->irq
);
484 static void parent_esp_reset(void *opaque
, int irq
, int level
)
487 esp_soft_reset(opaque
);
491 static void esp_gpio_demux(void *opaque
, int irq
, int level
)
495 parent_esp_reset(opaque
, irq
, level
);
498 esp_dma_enable(opaque
, irq
, level
);
503 static uint32_t esp_mem_readb(void *opaque
, target_phys_addr_t addr
)
505 ESPState
*s
= opaque
;
506 uint32_t saddr
, old_val
;
508 saddr
= addr
>> s
->it_shift
;
509 DPRINTF("read reg[%d]: 0x%2.2x\n", saddr
, s
->rregs
[saddr
]);
512 if (s
->ti_size
> 0) {
514 if ((s
->rregs
[ESP_RSTAT
] & STAT_PIO_MASK
) == 0) {
516 ESP_ERROR("PIO data read not implemented\n");
517 s
->rregs
[ESP_FIFO
] = 0;
519 s
->rregs
[ESP_FIFO
] = s
->ti_buf
[s
->ti_rptr
++];
523 if (s
->ti_size
== 0) {
529 /* Clear sequence step, interrupt register and all status bits
531 old_val
= s
->rregs
[ESP_RINTR
];
532 s
->rregs
[ESP_RINTR
] = 0;
533 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
534 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
541 return s
->rregs
[saddr
];
544 static void esp_mem_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
546 ESPState
*s
= opaque
;
549 saddr
= addr
>> s
->it_shift
;
550 DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr
, s
->wregs
[saddr
],
555 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
559 s
->cmdbuf
[s
->cmdlen
++] = val
& 0xff;
560 } else if (s
->ti_size
== TI_BUFSZ
- 1) {
561 ESP_ERROR("fifo overrun\n");
564 s
->ti_buf
[s
->ti_wptr
++] = val
& 0xff;
568 s
->rregs
[saddr
] = val
;
571 /* Reload DMA counter. */
572 s
->rregs
[ESP_TCLO
] = s
->wregs
[ESP_TCLO
];
573 s
->rregs
[ESP_TCMID
] = s
->wregs
[ESP_TCMID
];
577 switch(val
& CMD_CMD
) {
579 DPRINTF("NOP (%2.2x)\n", val
);
582 DPRINTF("Flush FIFO (%2.2x)\n", val
);
584 s
->rregs
[ESP_RINTR
] = INTR_FC
;
585 s
->rregs
[ESP_RSEQ
] = 0;
586 s
->rregs
[ESP_RFLAGS
] = 0;
589 DPRINTF("Chip reset (%2.2x)\n", val
);
590 esp_soft_reset(&s
->busdev
.qdev
);
593 DPRINTF("Bus reset (%2.2x)\n", val
);
594 s
->rregs
[ESP_RINTR
] = INTR_RST
;
595 if (!(s
->wregs
[ESP_CFG1
] & CFG1_RESREPT
)) {
603 DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val
);
605 s
->rregs
[ESP_RINTR
] = INTR_FC
;
606 s
->rregs
[ESP_RSTAT
] |= STAT_MI
;
609 DPRINTF("Message Accepted (%2.2x)\n", val
);
610 s
->rregs
[ESP_RINTR
] = INTR_DC
;
611 s
->rregs
[ESP_RSEQ
] = 0;
612 s
->rregs
[ESP_RFLAGS
] = 0;
616 DPRINTF("Transfer padding (%2.2x)\n", val
);
617 s
->rregs
[ESP_RSTAT
] = STAT_TC
;
618 s
->rregs
[ESP_RINTR
] = INTR_FC
;
619 s
->rregs
[ESP_RSEQ
] = 0;
622 DPRINTF("Set ATN (%2.2x)\n", val
);
625 DPRINTF("Select without ATN (%2.2x)\n", val
);
626 handle_s_without_atn(s
);
629 DPRINTF("Select with ATN (%2.2x)\n", val
);
633 DPRINTF("Select with ATN & stop (%2.2x)\n", val
);
637 DPRINTF("Enable selection (%2.2x)\n", val
);
638 s
->rregs
[ESP_RINTR
] = 0;
641 ESP_ERROR("Unhandled ESP command (%2.2x)\n", val
);
645 case ESP_WBUSID
... ESP_WSYNO
:
648 s
->rregs
[saddr
] = val
;
650 case ESP_WCCF
... ESP_WTEST
:
652 case ESP_CFG2
... ESP_RES4
:
653 s
->rregs
[saddr
] = val
;
656 ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val
, saddr
);
659 s
->wregs
[saddr
] = val
;
662 static CPUReadMemoryFunc
* const esp_mem_read
[3] = {
668 static CPUWriteMemoryFunc
* const esp_mem_write
[3] = {
674 static const VMStateDescription vmstate_esp
= {
677 .minimum_version_id
= 3,
678 .minimum_version_id_old
= 3,
679 .fields
= (VMStateField
[]) {
680 VMSTATE_BUFFER(rregs
, ESPState
),
681 VMSTATE_BUFFER(wregs
, ESPState
),
682 VMSTATE_INT32(ti_size
, ESPState
),
683 VMSTATE_UINT32(ti_rptr
, ESPState
),
684 VMSTATE_UINT32(ti_wptr
, ESPState
),
685 VMSTATE_BUFFER(ti_buf
, ESPState
),
686 VMSTATE_UINT32(sense
, ESPState
),
687 VMSTATE_UINT32(dma
, ESPState
),
688 VMSTATE_BUFFER(cmdbuf
, ESPState
),
689 VMSTATE_UINT32(cmdlen
, ESPState
),
690 VMSTATE_UINT32(do_cmd
, ESPState
),
691 VMSTATE_UINT32(dma_left
, ESPState
),
692 VMSTATE_END_OF_LIST()
696 void esp_init(target_phys_addr_t espaddr
, int it_shift
,
697 ESPDMAMemoryReadWriteFunc dma_memory_read
,
698 ESPDMAMemoryReadWriteFunc dma_memory_write
,
699 void *dma_opaque
, qemu_irq irq
, qemu_irq
*reset
,
700 qemu_irq
*dma_enable
)
706 dev
= qdev_create(NULL
, "esp");
707 esp
= DO_UPCAST(ESPState
, busdev
.qdev
, dev
);
708 esp
->dma_memory_read
= dma_memory_read
;
709 esp
->dma_memory_write
= dma_memory_write
;
710 esp
->dma_opaque
= dma_opaque
;
711 esp
->it_shift
= it_shift
;
712 /* XXX for now until rc4030 has been changed to use DMA enable signal */
713 esp
->dma_enabled
= 1;
714 qdev_init_nofail(dev
);
715 s
= sysbus_from_qdev(dev
);
716 sysbus_connect_irq(s
, 0, irq
);
717 sysbus_mmio_map(s
, 0, espaddr
);
718 *reset
= qdev_get_gpio_in(dev
, 0);
719 *dma_enable
= qdev_get_gpio_in(dev
, 1);
722 static const struct SCSIBusOps esp_scsi_ops
= {
723 .complete
= esp_command_complete
726 static int esp_init1(SysBusDevice
*dev
)
728 ESPState
*s
= FROM_SYSBUS(ESPState
, dev
);
731 sysbus_init_irq(dev
, &s
->irq
);
732 assert(s
->it_shift
!= -1);
734 esp_io_memory
= cpu_register_io_memory(esp_mem_read
, esp_mem_write
, s
,
735 DEVICE_NATIVE_ENDIAN
);
736 sysbus_init_mmio(dev
, ESP_REGS
<< s
->it_shift
, esp_io_memory
);
738 qdev_init_gpio_in(&dev
->qdev
, esp_gpio_demux
, 2);
740 scsi_bus_new(&s
->bus
, &dev
->qdev
, 0, ESP_MAX_DEVS
, &esp_scsi_ops
);
741 return scsi_bus_legacy_handle_cmdline(&s
->bus
);
744 static SysBusDeviceInfo esp_info
= {
747 .qdev
.size
= sizeof(ESPState
),
748 .qdev
.vmsd
= &vmstate_esp
,
749 .qdev
.reset
= esp_hard_reset
,
750 .qdev
.props
= (Property
[]) {
755 static void esp_register_devices(void)
757 sysbus_register_withprop(&esp_info
);
760 device_init(esp_register_devices
)