2 * QEMU ESP/NCR53C9x emulation
4 * Copyright (c) 2005-2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
32 * also produced as NCR89C100. See
33 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
35 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
38 #define ESP_ERROR(fmt, ...) \
39 do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
44 typedef struct ESPState ESPState
;
49 uint8_t rregs
[ESP_REGS
];
50 uint8_t wregs
[ESP_REGS
];
55 uint32_t ti_rptr
, ti_wptr
;
58 uint8_t ti_buf
[TI_BUFSZ
];
60 SCSIDevice
*current_dev
;
61 SCSIRequest
*current_req
;
62 uint8_t cmdbuf
[TI_BUFSZ
];
66 /* The amount of data left in the current DMA transfer. */
68 /* The size of the current DMA transfer. Zero if no transfer is in
76 ESPDMAMemoryReadWriteFunc dma_memory_read
;
77 ESPDMAMemoryReadWriteFunc dma_memory_write
;
79 void (*dma_cb
)(ESPState
*s
);
87 #define ESP_WBUSID 0x4
91 #define ESP_WSYNTP 0x6
92 #define ESP_RFLAGS 0x7
109 #define CMD_FLUSH 0x01
110 #define CMD_RESET 0x02
111 #define CMD_BUSRESET 0x03
113 #define CMD_ICCS 0x11
114 #define CMD_MSGACC 0x12
116 #define CMD_SATN 0x1a
117 #define CMD_RSTATN 0x1b
119 #define CMD_SELATN 0x42
120 #define CMD_SELATNS 0x43
121 #define CMD_ENSEL 0x44
122 #define CMD_DISSEL 0x45
130 #define STAT_PIO_MASK 0x06
135 #define STAT_INT 0x80
137 #define BUSID_DID 0x07
142 #define INTR_RST 0x80
147 #define CFG1_RESREPT 0x40
149 #define TCHI_FAS100A 0x4
151 static void esp_raise_irq(ESPState
*s
)
153 if (!(s
->rregs
[ESP_RSTAT
] & STAT_INT
)) {
154 s
->rregs
[ESP_RSTAT
] |= STAT_INT
;
155 qemu_irq_raise(s
->irq
);
156 trace_esp_raise_irq();
160 static void esp_lower_irq(ESPState
*s
)
162 if (s
->rregs
[ESP_RSTAT
] & STAT_INT
) {
163 s
->rregs
[ESP_RSTAT
] &= ~STAT_INT
;
164 qemu_irq_lower(s
->irq
);
165 trace_esp_lower_irq();
169 static void esp_dma_enable(void *opaque
, int irq
, int level
)
171 DeviceState
*d
= opaque
;
172 ESPState
*s
= container_of(d
, ESPState
, busdev
.qdev
);
176 trace_esp_dma_enable();
182 trace_esp_dma_disable();
187 static void esp_request_cancelled(SCSIRequest
*req
)
189 ESPState
*s
= DO_UPCAST(ESPState
, busdev
.qdev
, req
->bus
->qbus
.parent
);
191 if (req
== s
->current_req
) {
192 scsi_req_unref(s
->current_req
);
193 s
->current_req
= NULL
;
194 s
->current_dev
= NULL
;
198 static uint32_t get_cmd(ESPState
*s
, uint8_t *buf
)
203 target
= s
->wregs
[ESP_WBUSID
] & BUSID_DID
;
205 dmalen
= s
->rregs
[ESP_TCLO
] | (s
->rregs
[ESP_TCMID
] << 8);
206 s
->dma_memory_read(s
->dma_opaque
, buf
, dmalen
);
209 memcpy(buf
, s
->ti_buf
, dmalen
);
210 buf
[0] = buf
[2] >> 5;
212 trace_esp_get_cmd(dmalen
, target
);
218 if (s
->current_req
) {
219 /* Started a new command before the old one finished. Cancel it. */
220 scsi_req_cancel(s
->current_req
);
224 s
->current_dev
= scsi_device_find(&s
->bus
, 0, target
, 0);
225 if (!s
->current_dev
) {
227 s
->rregs
[ESP_RSTAT
] = 0;
228 s
->rregs
[ESP_RINTR
] = INTR_DC
;
229 s
->rregs
[ESP_RSEQ
] = SEQ_0
;
236 static void do_busid_cmd(ESPState
*s
, uint8_t *buf
, uint8_t busid
)
240 SCSIDevice
*current_lun
;
242 trace_esp_do_busid_cmd(busid
);
244 current_lun
= scsi_device_find(&s
->bus
, 0, s
->current_dev
->id
, lun
);
245 s
->current_req
= scsi_req_new(current_lun
, 0, lun
, buf
, NULL
);
246 datalen
= scsi_req_enqueue(s
->current_req
);
247 s
->ti_size
= datalen
;
249 s
->rregs
[ESP_RSTAT
] = STAT_TC
;
253 s
->rregs
[ESP_RSTAT
] |= STAT_DI
;
255 s
->rregs
[ESP_RSTAT
] |= STAT_DO
;
257 scsi_req_continue(s
->current_req
);
259 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
260 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
264 static void do_cmd(ESPState
*s
, uint8_t *buf
)
266 uint8_t busid
= buf
[0];
268 do_busid_cmd(s
, &buf
[1], busid
);
271 static void handle_satn(ESPState
*s
)
276 if (s
->dma
&& !s
->dma_enabled
) {
277 s
->dma_cb
= handle_satn
;
280 len
= get_cmd(s
, buf
);
285 static void handle_s_without_atn(ESPState
*s
)
290 if (s
->dma
&& !s
->dma_enabled
) {
291 s
->dma_cb
= handle_s_without_atn
;
294 len
= get_cmd(s
, buf
);
296 do_busid_cmd(s
, buf
, 0);
300 static void handle_satn_stop(ESPState
*s
)
302 if (s
->dma
&& !s
->dma_enabled
) {
303 s
->dma_cb
= handle_satn_stop
;
306 s
->cmdlen
= get_cmd(s
, s
->cmdbuf
);
308 trace_esp_handle_satn_stop(s
->cmdlen
);
310 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_CD
;
311 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
312 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
317 static void write_response(ESPState
*s
)
319 trace_esp_write_response(s
->status
);
320 s
->ti_buf
[0] = s
->status
;
323 s
->dma_memory_write(s
->dma_opaque
, s
->ti_buf
, 2);
324 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_ST
;
325 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
326 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
331 s
->rregs
[ESP_RFLAGS
] = 2;
336 static void esp_dma_done(ESPState
*s
)
338 s
->rregs
[ESP_RSTAT
] |= STAT_TC
;
339 s
->rregs
[ESP_RINTR
] = INTR_BS
;
340 s
->rregs
[ESP_RSEQ
] = 0;
341 s
->rregs
[ESP_RFLAGS
] = 0;
342 s
->rregs
[ESP_TCLO
] = 0;
343 s
->rregs
[ESP_TCMID
] = 0;
347 static void esp_do_dma(ESPState
*s
)
352 to_device
= (s
->ti_size
< 0);
355 trace_esp_do_dma(s
->cmdlen
, len
);
356 s
->dma_memory_read(s
->dma_opaque
, &s
->cmdbuf
[s
->cmdlen
], len
);
360 do_cmd(s
, s
->cmdbuf
);
363 if (s
->async_len
== 0) {
364 /* Defer until data is available. */
367 if (len
> s
->async_len
) {
371 s
->dma_memory_read(s
->dma_opaque
, s
->async_buf
, len
);
373 s
->dma_memory_write(s
->dma_opaque
, s
->async_buf
, len
);
382 if (s
->async_len
== 0) {
383 scsi_req_continue(s
->current_req
);
384 /* If there is still data to be read from the device then
385 complete the DMA operation immediately. Otherwise defer
386 until the scsi layer has completed. */
387 if (to_device
|| s
->dma_left
!= 0 || s
->ti_size
== 0) {
392 /* Partially filled a scsi buffer. Complete immediately. */
396 static void esp_command_complete(SCSIRequest
*req
, uint32_t status
,
399 ESPState
*s
= DO_UPCAST(ESPState
, busdev
.qdev
, req
->bus
->qbus
.parent
);
401 trace_esp_command_complete();
402 if (s
->ti_size
!= 0) {
403 trace_esp_command_complete_unexpected();
409 trace_esp_command_complete_fail();
412 s
->rregs
[ESP_RSTAT
] = STAT_ST
;
414 if (s
->current_req
) {
415 scsi_req_unref(s
->current_req
);
416 s
->current_req
= NULL
;
417 s
->current_dev
= NULL
;
421 static void esp_transfer_data(SCSIRequest
*req
, uint32_t len
)
423 ESPState
*s
= DO_UPCAST(ESPState
, busdev
.qdev
, req
->bus
->qbus
.parent
);
425 trace_esp_transfer_data(s
->dma_left
, s
->ti_size
);
427 s
->async_buf
= scsi_req_get_buf(req
);
430 } else if (s
->dma_counter
!= 0 && s
->ti_size
<= 0) {
431 /* If this was the last part of a DMA transfer then the
432 completion interrupt is deferred to here. */
437 static void handle_ti(ESPState
*s
)
439 uint32_t dmalen
, minlen
;
441 if (s
->dma
&& !s
->dma_enabled
) {
442 s
->dma_cb
= handle_ti
;
446 dmalen
= s
->rregs
[ESP_TCLO
] | (s
->rregs
[ESP_TCMID
] << 8);
450 s
->dma_counter
= dmalen
;
453 minlen
= (dmalen
< 32) ? dmalen
: 32;
454 else if (s
->ti_size
< 0)
455 minlen
= (dmalen
< -s
->ti_size
) ? dmalen
: -s
->ti_size
;
457 minlen
= (dmalen
< s
->ti_size
) ? dmalen
: s
->ti_size
;
458 trace_esp_handle_ti(minlen
);
460 s
->dma_left
= minlen
;
461 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
463 } else if (s
->do_cmd
) {
464 trace_esp_handle_ti_cmd(s
->cmdlen
);
468 do_cmd(s
, s
->cmdbuf
);
473 static void esp_hard_reset(DeviceState
*d
)
475 ESPState
*s
= container_of(d
, ESPState
, busdev
.qdev
);
477 memset(s
->rregs
, 0, ESP_REGS
);
478 memset(s
->wregs
, 0, ESP_REGS
);
479 s
->rregs
[ESP_TCHI
] = s
->chip_id
;
487 s
->rregs
[ESP_CFG1
] = 7;
490 static void esp_soft_reset(DeviceState
*d
)
492 ESPState
*s
= container_of(d
, ESPState
, busdev
.qdev
);
494 qemu_irq_lower(s
->irq
);
498 static void parent_esp_reset(void *opaque
, int irq
, int level
)
501 esp_soft_reset(opaque
);
505 static void esp_gpio_demux(void *opaque
, int irq
, int level
)
509 parent_esp_reset(opaque
, irq
, level
);
512 esp_dma_enable(opaque
, irq
, level
);
517 static uint64_t esp_mem_read(void *opaque
, target_phys_addr_t addr
,
520 ESPState
*s
= opaque
;
521 uint32_t saddr
, old_val
;
523 saddr
= addr
>> s
->it_shift
;
524 trace_esp_mem_readb(saddr
, s
->rregs
[saddr
]);
527 if (s
->ti_size
> 0) {
529 if ((s
->rregs
[ESP_RSTAT
] & STAT_PIO_MASK
) == 0) {
531 ESP_ERROR("PIO data read not implemented\n");
532 s
->rregs
[ESP_FIFO
] = 0;
534 s
->rregs
[ESP_FIFO
] = s
->ti_buf
[s
->ti_rptr
++];
538 if (s
->ti_size
== 0) {
544 /* Clear sequence step, interrupt register and all status bits
546 old_val
= s
->rregs
[ESP_RINTR
];
547 s
->rregs
[ESP_RINTR
] = 0;
548 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
549 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
556 return s
->rregs
[saddr
];
559 static void esp_mem_write(void *opaque
, target_phys_addr_t addr
,
560 uint64_t val
, unsigned size
)
562 ESPState
*s
= opaque
;
565 saddr
= addr
>> s
->it_shift
;
566 trace_esp_mem_writeb(saddr
, s
->wregs
[saddr
], val
);
570 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
574 s
->cmdbuf
[s
->cmdlen
++] = val
& 0xff;
575 } else if (s
->ti_size
== TI_BUFSZ
- 1) {
576 ESP_ERROR("fifo overrun\n");
579 s
->ti_buf
[s
->ti_wptr
++] = val
& 0xff;
583 s
->rregs
[saddr
] = val
;
586 /* Reload DMA counter. */
587 s
->rregs
[ESP_TCLO
] = s
->wregs
[ESP_TCLO
];
588 s
->rregs
[ESP_TCMID
] = s
->wregs
[ESP_TCMID
];
592 switch(val
& CMD_CMD
) {
594 trace_esp_mem_writeb_cmd_nop(val
);
597 trace_esp_mem_writeb_cmd_flush(val
);
599 s
->rregs
[ESP_RINTR
] = INTR_FC
;
600 s
->rregs
[ESP_RSEQ
] = 0;
601 s
->rregs
[ESP_RFLAGS
] = 0;
604 trace_esp_mem_writeb_cmd_reset(val
);
605 esp_soft_reset(&s
->busdev
.qdev
);
608 trace_esp_mem_writeb_cmd_bus_reset(val
);
609 s
->rregs
[ESP_RINTR
] = INTR_RST
;
610 if (!(s
->wregs
[ESP_CFG1
] & CFG1_RESREPT
)) {
618 trace_esp_mem_writeb_cmd_iccs(val
);
620 s
->rregs
[ESP_RINTR
] = INTR_FC
;
621 s
->rregs
[ESP_RSTAT
] |= STAT_MI
;
624 trace_esp_mem_writeb_cmd_msgacc(val
);
625 s
->rregs
[ESP_RINTR
] = INTR_DC
;
626 s
->rregs
[ESP_RSEQ
] = 0;
627 s
->rregs
[ESP_RFLAGS
] = 0;
631 trace_esp_mem_writeb_cmd_pad(val
);
632 s
->rregs
[ESP_RSTAT
] = STAT_TC
;
633 s
->rregs
[ESP_RINTR
] = INTR_FC
;
634 s
->rregs
[ESP_RSEQ
] = 0;
637 trace_esp_mem_writeb_cmd_satn(val
);
640 trace_esp_mem_writeb_cmd_rstatn(val
);
643 trace_esp_mem_writeb_cmd_sel(val
);
644 handle_s_without_atn(s
);
647 trace_esp_mem_writeb_cmd_selatn(val
);
651 trace_esp_mem_writeb_cmd_selatns(val
);
655 trace_esp_mem_writeb_cmd_ensel(val
);
656 s
->rregs
[ESP_RINTR
] = 0;
659 trace_esp_mem_writeb_cmd_dissel(val
);
660 s
->rregs
[ESP_RINTR
] = 0;
664 ESP_ERROR("Unhandled ESP command (%2.2x)\n", (unsigned)val
);
668 case ESP_WBUSID
... ESP_WSYNO
:
671 s
->rregs
[saddr
] = val
;
673 case ESP_WCCF
... ESP_WTEST
:
675 case ESP_CFG2
... ESP_RES4
:
676 s
->rregs
[saddr
] = val
;
679 ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", (unsigned)val
, saddr
);
682 s
->wregs
[saddr
] = val
;
685 static bool esp_mem_accepts(void *opaque
, target_phys_addr_t addr
,
686 unsigned size
, bool is_write
)
688 return (size
== 1) || (is_write
&& size
== 4);
691 static const MemoryRegionOps esp_mem_ops
= {
692 .read
= esp_mem_read
,
693 .write
= esp_mem_write
,
694 .endianness
= DEVICE_NATIVE_ENDIAN
,
695 .valid
.accepts
= esp_mem_accepts
,
698 static const VMStateDescription vmstate_esp
= {
701 .minimum_version_id
= 3,
702 .minimum_version_id_old
= 3,
703 .fields
= (VMStateField
[]) {
704 VMSTATE_BUFFER(rregs
, ESPState
),
705 VMSTATE_BUFFER(wregs
, ESPState
),
706 VMSTATE_INT32(ti_size
, ESPState
),
707 VMSTATE_UINT32(ti_rptr
, ESPState
),
708 VMSTATE_UINT32(ti_wptr
, ESPState
),
709 VMSTATE_BUFFER(ti_buf
, ESPState
),
710 VMSTATE_UINT32(status
, ESPState
),
711 VMSTATE_UINT32(dma
, ESPState
),
712 VMSTATE_BUFFER(cmdbuf
, ESPState
),
713 VMSTATE_UINT32(cmdlen
, ESPState
),
714 VMSTATE_UINT32(do_cmd
, ESPState
),
715 VMSTATE_UINT32(dma_left
, ESPState
),
716 VMSTATE_END_OF_LIST()
720 void esp_init(target_phys_addr_t espaddr
, int it_shift
,
721 ESPDMAMemoryReadWriteFunc dma_memory_read
,
722 ESPDMAMemoryReadWriteFunc dma_memory_write
,
723 void *dma_opaque
, qemu_irq irq
, qemu_irq
*reset
,
724 qemu_irq
*dma_enable
)
730 dev
= qdev_create(NULL
, "esp");
731 esp
= DO_UPCAST(ESPState
, busdev
.qdev
, dev
);
732 esp
->dma_memory_read
= dma_memory_read
;
733 esp
->dma_memory_write
= dma_memory_write
;
734 esp
->dma_opaque
= dma_opaque
;
735 esp
->it_shift
= it_shift
;
736 /* XXX for now until rc4030 has been changed to use DMA enable signal */
737 esp
->dma_enabled
= 1;
738 qdev_init_nofail(dev
);
739 s
= sysbus_from_qdev(dev
);
740 sysbus_connect_irq(s
, 0, irq
);
741 sysbus_mmio_map(s
, 0, espaddr
);
742 *reset
= qdev_get_gpio_in(dev
, 0);
743 *dma_enable
= qdev_get_gpio_in(dev
, 1);
746 static const struct SCSIBusInfo esp_scsi_info
= {
748 .max_target
= ESP_MAX_DEVS
,
751 .transfer_data
= esp_transfer_data
,
752 .complete
= esp_command_complete
,
753 .cancel
= esp_request_cancelled
756 static int esp_init1(SysBusDevice
*dev
)
758 ESPState
*s
= FROM_SYSBUS(ESPState
, dev
);
760 sysbus_init_irq(dev
, &s
->irq
);
761 assert(s
->it_shift
!= -1);
763 s
->chip_id
= TCHI_FAS100A
;
764 memory_region_init_io(&s
->iomem
, &esp_mem_ops
, s
,
765 "esp", ESP_REGS
<< s
->it_shift
);
766 sysbus_init_mmio(dev
, &s
->iomem
);
768 qdev_init_gpio_in(&dev
->qdev
, esp_gpio_demux
, 2);
770 scsi_bus_new(&s
->bus
, &dev
->qdev
, &esp_scsi_info
);
771 return scsi_bus_legacy_handle_cmdline(&s
->bus
);
774 static Property esp_properties
[] = {
778 static void esp_class_init(ObjectClass
*klass
, void *data
)
780 DeviceClass
*dc
= DEVICE_CLASS(klass
);
781 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
784 dc
->reset
= esp_hard_reset
;
785 dc
->vmsd
= &vmstate_esp
;
786 dc
->props
= esp_properties
;
789 static TypeInfo esp_info
= {
791 .parent
= TYPE_SYS_BUS_DEVICE
,
792 .instance_size
= sizeof(ESPState
),
793 .class_init
= esp_class_init
,
796 static void esp_register_types(void)
798 type_register_static(&esp_info
);
801 type_init(esp_register_types
)