hw/flash.h

   1 #include "memory.h"
   2
   3 /* NOR flash devices */
   4 typedef struct pflash_t pflash_t;
   5
   6 /* pflash_cfi01.c */
   7 extern const MemoryRegionOps pflash_cfi01_ops_be;
   8 extern const MemoryRegionOps pflash_cfi01_ops_le;
   9 extern const MemoryRegionOps pflash_cfi02_ops_be;
  10 extern const MemoryRegionOps pflash_cfi02_ops_le;
  11
  12 pflash_t *pflash_cfi01_register(target_phys_addr_t base, MemoryRegion *mem,
  13                                 BlockDriverState *bs,
  14                                 uint32_t sector_len, int nb_blocs, int width,
  15                                 uint16_t id0, uint16_t id1,
  16                                 uint16_t id2, uint16_t id3);
  17
  18 /* pflash_cfi02.c */
  19 pflash_t *pflash_cfi02_register(target_phys_addr_t base, MemoryRegion *mem,
  20                                 BlockDriverState *bs, uint32_t sector_len,
  21                                 int nb_blocs, int nb_mappings, int width,
  22                                 uint16_t id0, uint16_t id1,
  23                                 uint16_t id2, uint16_t id3,
  24                                 uint16_t unlock_addr0, uint16_t unlock_addr1);
  25
  26 /* nand.c */
  27 DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id);
  28 void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
  29                   uint8_t ce, uint8_t wp, uint8_t gnd);
  30 void nand_getpins(DeviceState *dev, int *rb);
  31 void nand_setio(DeviceState *dev, uint32_t value);
  32 uint32_t nand_getio(DeviceState *dev);
  33 uint32_t nand_getbuswidth(DeviceState *dev);
  34
  35 #define NAND_MFR_TOSHIBA        0x98
  36 #define NAND_MFR_SAMSUNG        0xec
  37 #define NAND_MFR_FUJITSU        0x04
  38 #define NAND_MFR_NATIONAL       0x8f
  39 #define NAND_MFR_RENESAS        0x07
  40 #define NAND_MFR_STMICRO        0x20
  41 #define NAND_MFR_HYNIX          0xad
  42 #define NAND_MFR_MICRON         0x2c
  43
  44 /* onenand.c */
  45 void onenand_base_update(void *opaque, target_phys_addr_t new);
  46 void onenand_base_unmap(void *opaque);
  47 void *onenand_init(BlockDriverState *bdrv,
  48                 uint16_t man_id, uint16_t dev_id, uint16_t ver_id,
  49                 int regshift, qemu_irq irq);
  50 void *onenand_raw_otp(void *opaque);
  51
  52 /* ecc.c */
  53 typedef struct {
  54     uint8_t cp;         /* Column parity */
  55     uint16_t lp[2];     /* Line parity */
  56     uint16_t count;
  57 } ECCState;
  58
  59 uint8_t ecc_digest(ECCState *s, uint8_t sample);
  60 void ecc_reset(ECCState *s);
  61 extern VMStateDescription vmstate_ecc_state;