2 * TI OMAP processors GPIO emulation.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2009 Nokia Corporation
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "hw/qdev-properties.h"
24 #include "hw/arm/omap.h"
25 #include "hw/sysbus.h"
26 #include "qemu/error-report.h"
27 #include "qemu/module.h"
28 #include "qapi/error.h"
43 #define TYPE_OMAP1_GPIO "omap-gpio"
44 #define OMAP1_GPIO(obj) \
45 OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO)
48 SysBusDevice parent_obj
;
53 struct omap_gpio_s omap1
;
56 /* General-Purpose I/O of OMAP1 */
57 static void omap_gpio_set(void *opaque
, int line
, int level
)
59 struct omap_gpio_s
*s
= &((struct omap_gpif_s
*) opaque
)->omap1
;
60 uint16_t prev
= s
->inputs
;
63 s
->inputs
|= 1 << line
;
65 s
->inputs
&= ~(1 << line
);
67 if (((s
->edge
& s
->inputs
& ~prev
) | (~s
->edge
& ~s
->inputs
& prev
)) &
68 (1 << line
) & s
->dir
& ~s
->mask
) {
70 qemu_irq_raise(s
->irq
);
74 static uint64_t omap_gpio_read(void *opaque
, hwaddr addr
,
77 struct omap_gpio_s
*s
= (struct omap_gpio_s
*) opaque
;
78 int offset
= addr
& OMAP_MPUI_REG_MASK
;
81 return omap_badwidth_read16(opaque
, addr
);
85 case 0x00: /* DATA_INPUT */
86 return s
->inputs
& s
->pins
;
88 case 0x04: /* DATA_OUTPUT */
91 case 0x08: /* DIRECTION_CONTROL */
94 case 0x0c: /* INTERRUPT_CONTROL */
97 case 0x10: /* INTERRUPT_MASK */
100 case 0x14: /* INTERRUPT_STATUS */
103 case 0x18: /* PIN_CONTROL (not in OMAP310) */
112 static void omap_gpio_write(void *opaque
, hwaddr addr
,
113 uint64_t value
, unsigned size
)
115 struct omap_gpio_s
*s
= (struct omap_gpio_s
*) opaque
;
116 int offset
= addr
& OMAP_MPUI_REG_MASK
;
121 omap_badwidth_write16(opaque
, addr
, value
);
126 case 0x00: /* DATA_INPUT */
130 case 0x04: /* DATA_OUTPUT */
131 diff
= (s
->outputs
^ value
) & ~s
->dir
;
133 while ((ln
= ctz32(diff
)) != 32) {
135 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
140 case 0x08: /* DIRECTION_CONTROL */
141 diff
= s
->outputs
& (s
->dir
^ value
);
144 value
= s
->outputs
& ~s
->dir
;
145 while ((ln
= ctz32(diff
)) != 32) {
147 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
152 case 0x0c: /* INTERRUPT_CONTROL */
156 case 0x10: /* INTERRUPT_MASK */
160 case 0x14: /* INTERRUPT_STATUS */
163 qemu_irq_lower(s
->irq
);
166 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
177 /* *Some* sources say the memory region is 32-bit. */
178 static const MemoryRegionOps omap_gpio_ops
= {
179 .read
= omap_gpio_read
,
180 .write
= omap_gpio_write
,
181 .endianness
= DEVICE_NATIVE_ENDIAN
,
184 static void omap_gpio_reset(struct omap_gpio_s
*s
)
195 struct omap2_gpio_s
{
215 #define TYPE_OMAP2_GPIO "omap2-gpio"
216 #define OMAP2_GPIO(obj) \
217 OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO)
219 struct omap2_gpif_s
{
220 SysBusDevice parent_obj
;
227 struct omap2_gpio_s
*modules
;
233 /* General-Purpose Interface of OMAP2/3 */
234 static inline void omap2_gpio_module_int_update(struct omap2_gpio_s
*s
,
237 qemu_set_irq(s
->irq
[line
], s
->ints
[line
] & s
->mask
[line
]);
240 static void omap2_gpio_module_wake(struct omap2_gpio_s
*s
, int line
)
242 if (!(s
->config
[0] & (1 << 2))) /* ENAWAKEUP */
244 if (!(s
->config
[0] & (3 << 3))) /* Force Idle */
246 if (!(s
->wumask
& (1 << line
)))
249 qemu_irq_raise(s
->wkup
);
252 static inline void omap2_gpio_module_out_update(struct omap2_gpio_s
*s
,
259 while ((ln
= ctz32(diff
)) != 32) {
260 qemu_set_irq(s
->handler
[ln
], (s
->outputs
>> ln
) & 1);
265 static void omap2_gpio_module_level_update(struct omap2_gpio_s
*s
, int line
)
267 s
->ints
[line
] |= s
->dir
&
268 ((s
->inputs
& s
->level
[1]) | (~s
->inputs
& s
->level
[0]));
269 omap2_gpio_module_int_update(s
, line
);
272 static inline void omap2_gpio_module_int(struct omap2_gpio_s
*s
, int line
)
274 s
->ints
[0] |= 1 << line
;
275 omap2_gpio_module_int_update(s
, 0);
276 s
->ints
[1] |= 1 << line
;
277 omap2_gpio_module_int_update(s
, 1);
278 omap2_gpio_module_wake(s
, line
);
281 static void omap2_gpio_set(void *opaque
, int line
, int level
)
283 struct omap2_gpif_s
*p
= opaque
;
284 struct omap2_gpio_s
*s
= &p
->modules
[line
>> 5];
288 if (s
->dir
& (1 << line
) & ((~s
->inputs
& s
->edge
[0]) | s
->level
[1]))
289 omap2_gpio_module_int(s
, line
);
290 s
->inputs
|= 1 << line
;
292 if (s
->dir
& (1 << line
) & ((s
->inputs
& s
->edge
[1]) | s
->level
[0]))
293 omap2_gpio_module_int(s
, line
);
294 s
->inputs
&= ~(1 << line
);
298 static void omap2_gpio_module_reset(struct omap2_gpio_s
*s
)
316 static uint32_t omap2_gpio_module_read(void *opaque
, hwaddr addr
)
318 struct omap2_gpio_s
*s
= (struct omap2_gpio_s
*) opaque
;
321 case 0x00: /* GPIO_REVISION */
324 case 0x10: /* GPIO_SYSCONFIG */
327 case 0x14: /* GPIO_SYSSTATUS */
330 case 0x18: /* GPIO_IRQSTATUS1 */
333 case 0x1c: /* GPIO_IRQENABLE1 */
334 case 0x60: /* GPIO_CLEARIRQENABLE1 */
335 case 0x64: /* GPIO_SETIRQENABLE1 */
338 case 0x20: /* GPIO_WAKEUPENABLE */
339 case 0x80: /* GPIO_CLEARWKUENA */
340 case 0x84: /* GPIO_SETWKUENA */
343 case 0x28: /* GPIO_IRQSTATUS2 */
346 case 0x2c: /* GPIO_IRQENABLE2 */
347 case 0x70: /* GPIO_CLEARIRQENABLE2 */
348 case 0x74: /* GPIO_SETIREQNEABLE2 */
351 case 0x30: /* GPIO_CTRL */
354 case 0x34: /* GPIO_OE */
357 case 0x38: /* GPIO_DATAIN */
360 case 0x3c: /* GPIO_DATAOUT */
361 case 0x90: /* GPIO_CLEARDATAOUT */
362 case 0x94: /* GPIO_SETDATAOUT */
365 case 0x40: /* GPIO_LEVELDETECT0 */
368 case 0x44: /* GPIO_LEVELDETECT1 */
371 case 0x48: /* GPIO_RISINGDETECT */
374 case 0x4c: /* GPIO_FALLINGDETECT */
377 case 0x50: /* GPIO_DEBOUNCENABLE */
380 case 0x54: /* GPIO_DEBOUNCINGTIME */
388 static void omap2_gpio_module_write(void *opaque
, hwaddr addr
,
391 struct omap2_gpio_s
*s
= (struct omap2_gpio_s
*) opaque
;
396 case 0x00: /* GPIO_REVISION */
397 case 0x14: /* GPIO_SYSSTATUS */
398 case 0x38: /* GPIO_DATAIN */
402 case 0x10: /* GPIO_SYSCONFIG */
403 if (((value
>> 3) & 3) == 3)
404 fprintf(stderr
, "%s: bad IDLEMODE value\n", __func__
);
406 omap2_gpio_module_reset(s
);
407 s
->config
[0] = value
& 0x1d;
410 case 0x18: /* GPIO_IRQSTATUS1 */
411 if (s
->ints
[0] & value
) {
412 s
->ints
[0] &= ~value
;
413 omap2_gpio_module_level_update(s
, 0);
417 case 0x1c: /* GPIO_IRQENABLE1 */
419 omap2_gpio_module_int_update(s
, 0);
422 case 0x20: /* GPIO_WAKEUPENABLE */
426 case 0x28: /* GPIO_IRQSTATUS2 */
427 if (s
->ints
[1] & value
) {
428 s
->ints
[1] &= ~value
;
429 omap2_gpio_module_level_update(s
, 1);
433 case 0x2c: /* GPIO_IRQENABLE2 */
435 omap2_gpio_module_int_update(s
, 1);
438 case 0x30: /* GPIO_CTRL */
439 s
->config
[1] = value
& 7;
442 case 0x34: /* GPIO_OE */
443 diff
= s
->outputs
& (s
->dir
^ value
);
446 value
= s
->outputs
& ~s
->dir
;
447 while ((ln
= ctz32(diff
)) != 32) {
449 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
452 omap2_gpio_module_level_update(s
, 0);
453 omap2_gpio_module_level_update(s
, 1);
456 case 0x3c: /* GPIO_DATAOUT */
457 omap2_gpio_module_out_update(s
, s
->outputs
^ value
);
460 case 0x40: /* GPIO_LEVELDETECT0 */
462 omap2_gpio_module_level_update(s
, 0);
463 omap2_gpio_module_level_update(s
, 1);
466 case 0x44: /* GPIO_LEVELDETECT1 */
468 omap2_gpio_module_level_update(s
, 0);
469 omap2_gpio_module_level_update(s
, 1);
472 case 0x48: /* GPIO_RISINGDETECT */
476 case 0x4c: /* GPIO_FALLINGDETECT */
480 case 0x50: /* GPIO_DEBOUNCENABLE */
484 case 0x54: /* GPIO_DEBOUNCINGTIME */
488 case 0x60: /* GPIO_CLEARIRQENABLE1 */
489 s
->mask
[0] &= ~value
;
490 omap2_gpio_module_int_update(s
, 0);
493 case 0x64: /* GPIO_SETIRQENABLE1 */
495 omap2_gpio_module_int_update(s
, 0);
498 case 0x70: /* GPIO_CLEARIRQENABLE2 */
499 s
->mask
[1] &= ~value
;
500 omap2_gpio_module_int_update(s
, 1);
503 case 0x74: /* GPIO_SETIREQNEABLE2 */
505 omap2_gpio_module_int_update(s
, 1);
508 case 0x80: /* GPIO_CLEARWKUENA */
512 case 0x84: /* GPIO_SETWKUENA */
516 case 0x90: /* GPIO_CLEARDATAOUT */
517 omap2_gpio_module_out_update(s
, s
->outputs
& value
);
520 case 0x94: /* GPIO_SETDATAOUT */
521 omap2_gpio_module_out_update(s
, ~s
->outputs
& value
);
530 static uint64_t omap2_gpio_module_readp(void *opaque
, hwaddr addr
,
533 return omap2_gpio_module_read(opaque
, addr
& ~3) >> ((addr
& 3) << 3);
536 static void omap2_gpio_module_writep(void *opaque
, hwaddr addr
,
537 uint64_t value
, unsigned size
)
540 uint32_t mask
= 0xffff;
543 omap2_gpio_module_write(opaque
, addr
, value
);
548 case 0x00: /* GPIO_REVISION */
549 case 0x14: /* GPIO_SYSSTATUS */
550 case 0x38: /* GPIO_DATAIN */
554 case 0x10: /* GPIO_SYSCONFIG */
555 case 0x1c: /* GPIO_IRQENABLE1 */
556 case 0x20: /* GPIO_WAKEUPENABLE */
557 case 0x2c: /* GPIO_IRQENABLE2 */
558 case 0x30: /* GPIO_CTRL */
559 case 0x34: /* GPIO_OE */
560 case 0x3c: /* GPIO_DATAOUT */
561 case 0x40: /* GPIO_LEVELDETECT0 */
562 case 0x44: /* GPIO_LEVELDETECT1 */
563 case 0x48: /* GPIO_RISINGDETECT */
564 case 0x4c: /* GPIO_FALLINGDETECT */
565 case 0x50: /* GPIO_DEBOUNCENABLE */
566 case 0x54: /* GPIO_DEBOUNCINGTIME */
567 cur
= omap2_gpio_module_read(opaque
, addr
& ~3) &
568 ~(mask
<< ((addr
& 3) << 3));
571 case 0x18: /* GPIO_IRQSTATUS1 */
572 case 0x28: /* GPIO_IRQSTATUS2 */
573 case 0x60: /* GPIO_CLEARIRQENABLE1 */
574 case 0x64: /* GPIO_SETIRQENABLE1 */
575 case 0x70: /* GPIO_CLEARIRQENABLE2 */
576 case 0x74: /* GPIO_SETIREQNEABLE2 */
577 case 0x80: /* GPIO_CLEARWKUENA */
578 case 0x84: /* GPIO_SETWKUENA */
579 case 0x90: /* GPIO_CLEARDATAOUT */
580 case 0x94: /* GPIO_SETDATAOUT */
581 value
<<= (addr
& 3) << 3;
582 omap2_gpio_module_write(opaque
, addr
, cur
| value
);
591 static const MemoryRegionOps omap2_gpio_module_ops
= {
592 .read
= omap2_gpio_module_readp
,
593 .write
= omap2_gpio_module_writep
,
594 .valid
.min_access_size
= 1,
595 .valid
.max_access_size
= 4,
596 .endianness
= DEVICE_NATIVE_ENDIAN
,
599 static void omap_gpif_reset(DeviceState
*dev
)
601 struct omap_gpif_s
*s
= OMAP1_GPIO(dev
);
603 omap_gpio_reset(&s
->omap1
);
606 static void omap2_gpif_reset(DeviceState
*dev
)
608 struct omap2_gpif_s
*s
= OMAP2_GPIO(dev
);
611 for (i
= 0; i
< s
->modulecount
; i
++) {
612 omap2_gpio_module_reset(&s
->modules
[i
]);
618 static uint64_t omap2_gpif_top_read(void *opaque
, hwaddr addr
,
621 struct omap2_gpif_s
*s
= (struct omap2_gpif_s
*) opaque
;
624 case 0x00: /* IPGENERICOCPSPL_REVISION */
627 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
630 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
633 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
636 case 0x40: /* IPGENERICOCPSPL_GPO */
639 case 0x50: /* IPGENERICOCPSPL_GPI */
647 static void omap2_gpif_top_write(void *opaque
, hwaddr addr
,
648 uint64_t value
, unsigned size
)
650 struct omap2_gpif_s
*s
= (struct omap2_gpif_s
*) opaque
;
653 case 0x00: /* IPGENERICOCPSPL_REVISION */
654 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
655 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
656 case 0x50: /* IPGENERICOCPSPL_GPI */
660 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
661 if (value
& (1 << 1)) /* SOFTRESET */
662 omap2_gpif_reset(DEVICE(s
));
663 s
->autoidle
= value
& 1;
666 case 0x40: /* IPGENERICOCPSPL_GPO */
676 static const MemoryRegionOps omap2_gpif_top_ops
= {
677 .read
= omap2_gpif_top_read
,
678 .write
= omap2_gpif_top_write
,
679 .endianness
= DEVICE_NATIVE_ENDIAN
,
682 static void omap_gpio_init(Object
*obj
)
684 DeviceState
*dev
= DEVICE(obj
);
685 struct omap_gpif_s
*s
= OMAP1_GPIO(obj
);
686 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
688 qdev_init_gpio_in(dev
, omap_gpio_set
, 16);
689 qdev_init_gpio_out(dev
, s
->omap1
.handler
, 16);
690 sysbus_init_irq(sbd
, &s
->omap1
.irq
);
691 memory_region_init_io(&s
->iomem
, obj
, &omap_gpio_ops
, &s
->omap1
,
692 "omap.gpio", 0x1000);
693 sysbus_init_mmio(sbd
, &s
->iomem
);
696 static void omap_gpio_realize(DeviceState
*dev
, Error
**errp
)
698 struct omap_gpif_s
*s
= OMAP1_GPIO(dev
);
701 error_setg(errp
, "omap-gpio: clk not connected");
705 static void omap2_gpio_realize(DeviceState
*dev
, Error
**errp
)
707 struct omap2_gpif_s
*s
= OMAP2_GPIO(dev
);
708 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
712 error_setg(errp
, "omap2-gpio: iclk not connected");
716 s
->modulecount
= s
->mpu_model
< omap2430
? 4
717 : s
->mpu_model
< omap3430
? 5
720 if (s
->mpu_model
< omap3430
) {
721 memory_region_init_io(&s
->iomem
, OBJECT(dev
), &omap2_gpif_top_ops
, s
,
722 "omap2.gpio", 0x1000);
723 sysbus_init_mmio(sbd
, &s
->iomem
);
726 s
->modules
= g_new0(struct omap2_gpio_s
, s
->modulecount
);
727 s
->handler
= g_new0(qemu_irq
, s
->modulecount
* 32);
728 qdev_init_gpio_in(dev
, omap2_gpio_set
, s
->modulecount
* 32);
729 qdev_init_gpio_out(dev
, s
->handler
, s
->modulecount
* 32);
731 for (i
= 0; i
< s
->modulecount
; i
++) {
732 struct omap2_gpio_s
*m
= &s
->modules
[i
];
735 error_setg(errp
, "omap2-gpio: fclk%d not connected", i
);
739 m
->revision
= (s
->mpu_model
< omap3430
) ? 0x18 : 0x25;
740 m
->handler
= &s
->handler
[i
* 32];
741 sysbus_init_irq(sbd
, &m
->irq
[0]); /* mpu irq */
742 sysbus_init_irq(sbd
, &m
->irq
[1]); /* dsp irq */
743 sysbus_init_irq(sbd
, &m
->wkup
);
744 memory_region_init_io(&m
->iomem
, OBJECT(dev
), &omap2_gpio_module_ops
, m
,
745 "omap.gpio-module", 0x1000);
746 sysbus_init_mmio(sbd
, &m
->iomem
);
750 /* Using qdev pointer properties for the clocks is not ideal.
751 * qdev should support a generic means of defining a 'port' with
752 * an arbitrary interface for connecting two devices. Then we
753 * could reframe the omap clock API in terms of clock ports,
754 * and get some type safety. For now the best qdev provides is
755 * passing an arbitrary pointer.
756 * (It's not possible to pass in the string which is the clock
757 * name, because this device does not have the necessary information
758 * (ie the struct omap_mpu_state_s*) to do the clockname to pointer
762 static Property omap_gpio_properties
[] = {
763 DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s
, mpu_model
, 0),
764 DEFINE_PROP_PTR("clk", struct omap_gpif_s
, clk
),
765 DEFINE_PROP_END_OF_LIST(),
768 static void omap_gpio_class_init(ObjectClass
*klass
, void *data
)
770 DeviceClass
*dc
= DEVICE_CLASS(klass
);
772 dc
->realize
= omap_gpio_realize
;
773 dc
->reset
= omap_gpif_reset
;
774 dc
->props
= omap_gpio_properties
;
775 /* Reason: pointer property "clk" */
776 dc
->user_creatable
= false;
779 static const TypeInfo omap_gpio_info
= {
780 .name
= TYPE_OMAP1_GPIO
,
781 .parent
= TYPE_SYS_BUS_DEVICE
,
782 .instance_size
= sizeof(struct omap_gpif_s
),
783 .instance_init
= omap_gpio_init
,
784 .class_init
= omap_gpio_class_init
,
787 static Property omap2_gpio_properties
[] = {
788 DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s
, mpu_model
, 0),
789 DEFINE_PROP_PTR("iclk", struct omap2_gpif_s
, iclk
),
790 DEFINE_PROP_PTR("fclk0", struct omap2_gpif_s
, fclk
[0]),
791 DEFINE_PROP_PTR("fclk1", struct omap2_gpif_s
, fclk
[1]),
792 DEFINE_PROP_PTR("fclk2", struct omap2_gpif_s
, fclk
[2]),
793 DEFINE_PROP_PTR("fclk3", struct omap2_gpif_s
, fclk
[3]),
794 DEFINE_PROP_PTR("fclk4", struct omap2_gpif_s
, fclk
[4]),
795 DEFINE_PROP_PTR("fclk5", struct omap2_gpif_s
, fclk
[5]),
796 DEFINE_PROP_END_OF_LIST(),
799 static void omap2_gpio_class_init(ObjectClass
*klass
, void *data
)
801 DeviceClass
*dc
= DEVICE_CLASS(klass
);
803 dc
->realize
= omap2_gpio_realize
;
804 dc
->reset
= omap2_gpif_reset
;
805 dc
->props
= omap2_gpio_properties
;
806 /* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */
807 dc
->user_creatable
= false;
810 static const TypeInfo omap2_gpio_info
= {
811 .name
= TYPE_OMAP2_GPIO
,
812 .parent
= TYPE_SYS_BUS_DEVICE
,
813 .instance_size
= sizeof(struct omap2_gpif_s
),
814 .class_init
= omap2_gpio_class_init
,
817 static void omap_gpio_register_types(void)
819 type_register_static(&omap_gpio_info
);
820 type_register_static(&omap2_gpio_info
);
823 type_init(omap_gpio_register_types
)