2 * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
4 * Copyright (c) 2006-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 typedef target_phys_addr_t pci_addr_t
;
31 typedef PCIHostState GrackleState
;
33 static void pci_grackle_config_writel (void *opaque
, target_phys_addr_t addr
,
36 GrackleState
*s
= opaque
;
37 #ifdef TARGET_WORDS_BIGENDIAN
43 static uint32_t pci_grackle_config_readl (void *opaque
, target_phys_addr_t addr
)
45 GrackleState
*s
= opaque
;
49 #ifdef TARGET_WORDS_BIGENDIAN
55 static CPUWriteMemoryFunc
*pci_grackle_config_write
[] = {
56 &pci_grackle_config_writel
,
57 &pci_grackle_config_writel
,
58 &pci_grackle_config_writel
,
61 static CPUReadMemoryFunc
*pci_grackle_config_read
[] = {
62 &pci_grackle_config_readl
,
63 &pci_grackle_config_readl
,
64 &pci_grackle_config_readl
,
67 static CPUWriteMemoryFunc
*pci_grackle_write
[] = {
68 &pci_host_data_writeb
,
69 &pci_host_data_writew
,
70 &pci_host_data_writel
,
73 static CPUReadMemoryFunc
*pci_grackle_read
[] = {
79 /* Don't know if this matches real hardware, but it agrees with OHW. */
80 static int pci_grackle_map_irq(PCIDevice
*pci_dev
, int irq_num
)
82 return (irq_num
+ (pci_dev
->devfn
>> 3)) & 3;
85 static void pci_grackle_set_irq(qemu_irq
*pic
, int irq_num
, int level
)
87 qemu_set_irq(pic
[irq_num
+ 0x15], level
);
90 PCIBus
*pci_grackle_init(uint32_t base
, qemu_irq
*pic
)
94 int pci_mem_config
, pci_mem_data
;
96 s
= qemu_mallocz(sizeof(GrackleState
));
97 s
->bus
= pci_register_bus(pci_grackle_set_irq
, pci_grackle_map_irq
,
100 pci_mem_config
= cpu_register_io_memory(0, pci_grackle_config_read
,
101 pci_grackle_config_write
, s
);
102 pci_mem_data
= cpu_register_io_memory(0, pci_grackle_read
,
103 pci_grackle_write
, s
);
104 cpu_register_physical_memory(base
, 0x1000, pci_mem_config
);
105 cpu_register_physical_memory(base
+ 0x00200000, 0x1000, pci_mem_data
);
106 d
= pci_register_device(s
->bus
, "Grackle host bridge", sizeof(PCIDevice
),
108 d
->config
[0x00] = 0x57; // vendor_id
109 d
->config
[0x01] = 0x10;
110 d
->config
[0x02] = 0x02; // device_id
111 d
->config
[0x03] = 0x00;
112 d
->config
[0x08] = 0x00; // revision
113 d
->config
[0x09] = 0x01;
114 d
->config
[0x0a] = 0x00; // class_sub = host
115 d
->config
[0x0b] = 0x06; // class_base = PCI_bridge
116 d
->config
[0x0e] = 0x00; // header_type
118 d
->config
[0x18] = 0x00; // primary_bus
119 d
->config
[0x19] = 0x01; // secondary_bus
120 d
->config
[0x1a] = 0x00; // subordinate_bus
121 d
->config
[0x1c] = 0x00;
122 d
->config
[0x1d] = 0x00;
124 d
->config
[0x20] = 0x00; // memory_base
125 d
->config
[0x21] = 0x00;
126 d
->config
[0x22] = 0x01; // memory_limit
127 d
->config
[0x23] = 0x00;
129 d
->config
[0x24] = 0x00; // prefetchable_memory_base
130 d
->config
[0x25] = 0x00;
131 d
->config
[0x26] = 0x00; // prefetchable_memory_limit
132 d
->config
[0x27] = 0x00;
135 /* PCI2PCI bridge same values as PearPC - check this */
136 d
->config
[0x00] = 0x11; // vendor_id
137 d
->config
[0x01] = 0x10;
138 d
->config
[0x02] = 0x26; // device_id
139 d
->config
[0x03] = 0x00;
140 d
->config
[0x08] = 0x02; // revision
141 d
->config
[0x0a] = 0x04; // class_sub = pci2pci
142 d
->config
[0x0b] = 0x06; // class_base = PCI_bridge
143 d
->config
[0x0e] = 0x01; // header_type
145 d
->config
[0x18] = 0x0; // primary_bus
146 d
->config
[0x19] = 0x1; // secondary_bus
147 d
->config
[0x1a] = 0x1; // subordinate_bus
148 d
->config
[0x1c] = 0x10; // io_base
149 d
->config
[0x1d] = 0x20; // io_limit
151 d
->config
[0x20] = 0x80; // memory_base
152 d
->config
[0x21] = 0x80;
153 d
->config
[0x22] = 0x90; // memory_limit
154 d
->config
[0x23] = 0x80;
156 d
->config
[0x24] = 0x00; // prefetchable_memory_base
157 d
->config
[0x25] = 0x84;
158 d
->config
[0x26] = 0x00; // prefetchable_memory_limit
159 d
->config
[0x27] = 0x85;