hw/i386/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "hw/hw.h"
  28 #include "hw/i386/pc.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/char/parallel.h"
  31 #include "hw/i386/apic.h"
  32 #include "hw/i386/topology.h"
  33 #include "sysemu/cpus.h"
  34 #include "hw/block/fdc.h"
  35 #include "hw/ide.h"
  36 #include "hw/pci/pci.h"
  37 #include "hw/pci/pci_bus.h"
  38 #include "hw/nvram/fw_cfg.h"
  39 #include "hw/timer/hpet.h"
  40 #include "hw/firmware/smbios.h"
  41 #include "hw/loader.h"
  42 #include "elf.h"
  43 #include "multiboot.h"
  44 #include "hw/timer/mc146818rtc.h"
  45 #include "hw/dma/i8257.h"
  46 #include "hw/timer/i8254.h"
  47 #include "hw/input/i8042.h"
  48 #include "hw/audio/pcspk.h"
  49 #include "hw/pci/msi.h"
  50 #include "hw/sysbus.h"
  51 #include "sysemu/sysemu.h"
  52 #include "sysemu/numa.h"
  53 #include "sysemu/kvm.h"
  54 #include "sysemu/qtest.h"
  55 #include "kvm_i386.h"
  56 #include "hw/xen/xen.h"
  57 #include "ui/qemu-spice.h"
  58 #include "exec/memory.h"
  59 #include "exec/address-spaces.h"
  60 #include "sysemu/arch_init.h"
  61 #include "qemu/bitmap.h"
  62 #include "qemu/config-file.h"
  63 #include "qemu/error-report.h"
  64 #include "qemu/option.h"
  65 #include "hw/acpi/acpi.h"
  66 #include "hw/acpi/cpu_hotplug.h"
  67 #include "hw/boards.h"
  68 #include "acpi-build.h"
  69 #include "hw/mem/pc-dimm.h"
  70 #include "qapi/error.h"
  71 #include "qapi/qapi-visit-common.h"
  72 #include "qapi/visitor.h"
  73 #include "qom/cpu.h"
  74 #include "hw/nmi.h"
  75 #include "hw/i386/intel_iommu.h"
  76 #include "hw/net/ne2000-isa.h"
  77
  78 /* debug PC/ISA interrupts */
  79 //#define DEBUG_IRQ
  80
  81 #ifdef DEBUG_IRQ
  82 #define DPRINTF(fmt, ...)                                       \
  83     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  84 #else
  85 #define DPRINTF(fmt, ...)
  86 #endif
  87
  88 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  89 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  90 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  91 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  92 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  93
  94 #define E820_NR_ENTRIES         16
  95
  96 struct e820_entry {
  97     uint64_t address;
  98     uint64_t length;
  99     uint32_t type;
 100 } QEMU_PACKED __attribute((__aligned__(4)));
 101
 102 struct e820_table {
 103     uint32_t count;
 104     struct e820_entry entry[E820_NR_ENTRIES];
 105 } QEMU_PACKED __attribute((__aligned__(4)));
 106
 107 static struct e820_table e820_reserve;
 108 static struct e820_entry *e820_table;
 109 static unsigned e820_entries;
 110 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
 111
 112 GlobalProperty pc_compat_3_1[] = {
 113     {
 114         .driver   = "intel-iommu",
 115         .property = "dma-drain",
 116         .value    = "off",
 117     },
 118 };
 119 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
 120
 121 GlobalProperty pc_compat_3_0[] = {
 122     {
 123         .driver   = TYPE_X86_CPU,
 124         .property = "x-hv-synic-kvm-only",
 125         .value    = "on",
 126     },{
 127         .driver   = "Skylake-Server" "-" TYPE_X86_CPU,
 128         .property = "pku",
 129         .value    = "off",
 130     },{
 131         .driver   = "Skylake-Server-IBRS" "-" TYPE_X86_CPU,
 132         .property = "pku",
 133         .value    = "off",
 134     },
 135 };
 136 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
 137
 138 GlobalProperty pc_compat_2_12[] = {
 139     {
 140         .driver   = TYPE_X86_CPU,
 141         .property = "legacy-cache",
 142         .value    = "on",
 143     },{
 144         .driver   = TYPE_X86_CPU,
 145         .property = "topoext",
 146         .value    = "off",
 147     },{
 148         .driver   = "EPYC-" TYPE_X86_CPU,
 149         .property = "xlevel",
 150         .value    = stringify(0x8000000a),
 151     },{
 152         .driver   = "EPYC-IBPB-" TYPE_X86_CPU,
 153         .property = "xlevel",
 154         .value    = stringify(0x8000000a),
 155     },
 156 };
 157 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
 158
 159 void gsi_handler(void *opaque, int n, int level)
 160 {
 161     GSIState *s = opaque;
 162
 163     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
 164     if (n < ISA_NUM_IRQS) {
 165         qemu_set_irq(s->i8259_irq[n], level);
 166     }
 167     qemu_set_irq(s->ioapic_irq[n], level);
 168 }
 169
 170 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
 171                            unsigned size)
 172 {
 173 }
 174
 175 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
 176 {
 177     return 0xffffffffffffffffULL;
 178 }
 179
 180 /* MSDOS compatibility mode FPU exception support */
 181 static qemu_irq ferr_irq;
 182
 183 void pc_register_ferr_irq(qemu_irq irq)
 184 {
 185     ferr_irq = irq;
 186 }
 187
 188 /* XXX: add IGNNE support */
 189 void cpu_set_ferr(CPUX86State *s)
 190 {
 191     qemu_irq_raise(ferr_irq);
 192 }
 193
 194 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
 195                            unsigned size)
 196 {
 197     qemu_irq_lower(ferr_irq);
 198 }
 199
 200 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
 201 {
 202     return 0xffffffffffffffffULL;
 203 }
 204
 205 /* TSC handling */
 206 uint64_t cpu_get_tsc(CPUX86State *env)
 207 {
 208     return cpu_get_ticks();
 209 }
 210
 211 /* IRQ handling */
 212 int cpu_get_pic_interrupt(CPUX86State *env)
 213 {
 214     X86CPU *cpu = x86_env_get_cpu(env);
 215     int intno;
 216
 217     if (!kvm_irqchip_in_kernel()) {
 218         intno = apic_get_interrupt(cpu->apic_state);
 219         if (intno >= 0) {
 220             return intno;
 221         }
 222         /* read the irq from the PIC */
 223         if (!apic_accept_pic_intr(cpu->apic_state)) {
 224             return -1;
 225         }
 226     }
 227
 228     intno = pic_read_irq(isa_pic);
 229     return intno;
 230 }
 231
 232 static void pic_irq_request(void *opaque, int irq, int level)
 233 {
 234     CPUState *cs = first_cpu;
 235     X86CPU *cpu = X86_CPU(cs);
 236
 237     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 238     if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
 239         CPU_FOREACH(cs) {
 240             cpu = X86_CPU(cs);
 241             if (apic_accept_pic_intr(cpu->apic_state)) {
 242                 apic_deliver_pic_intr(cpu->apic_state, level);
 243             }
 244         }
 245     } else {
 246         if (level) {
 247             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 248         } else {
 249             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 250         }
 251     }
 252 }
 253
 254 /* PC cmos mappings */
 255
 256 #define REG_EQUIPMENT_BYTE          0x14
 257
 258 int cmos_get_fd_drive_type(FloppyDriveType fd0)
 259 {
 260     int val;
 261
 262     switch (fd0) {
 263     case FLOPPY_DRIVE_TYPE_144:
 264         /* 1.44 Mb 3"5 drive */
 265         val = 4;
 266         break;
 267     case FLOPPY_DRIVE_TYPE_288:
 268         /* 2.88 Mb 3"5 drive */
 269         val = 5;
 270         break;
 271     case FLOPPY_DRIVE_TYPE_120:
 272         /* 1.2 Mb 5"5 drive */
 273         val = 2;
 274         break;
 275     case FLOPPY_DRIVE_TYPE_NONE:
 276     default:
 277         val = 0;
 278         break;
 279     }
 280     return val;
 281 }
 282
 283 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 284                          int16_t cylinders, int8_t heads, int8_t sectors)
 285 {
 286     rtc_set_memory(s, type_ofs, 47);
 287     rtc_set_memory(s, info_ofs, cylinders);
 288     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 289     rtc_set_memory(s, info_ofs + 2, heads);
 290     rtc_set_memory(s, info_ofs + 3, 0xff);
 291     rtc_set_memory(s, info_ofs + 4, 0xff);
 292     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 293     rtc_set_memory(s, info_ofs + 6, cylinders);
 294     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 295     rtc_set_memory(s, info_ofs + 8, sectors);
 296 }
 297
 298 /* convert boot_device letter to something recognizable by the bios */
 299 static int boot_device2nibble(char boot_device)
 300 {
 301     switch(boot_device) {
 302     case 'a':
 303     case 'b':
 304         return 0x01; /* floppy boot */
 305     case 'c':
 306         return 0x02; /* hard drive boot */
 307     case 'd':
 308         return 0x03; /* CD-ROM boot */
 309     case 'n':
 310         return 0x04; /* Network boot */
 311     }
 312     return 0;
 313 }
 314
 315 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
 316 {
 317 #define PC_MAX_BOOT_DEVICES 3
 318     int nbds, bds[3] = { 0, };
 319     int i;
 320
 321     nbds = strlen(boot_device);
 322     if (nbds > PC_MAX_BOOT_DEVICES) {
 323         error_setg(errp, "Too many boot devices for PC");
 324         return;
 325     }
 326     for (i = 0; i < nbds; i++) {
 327         bds[i] = boot_device2nibble(boot_device[i]);
 328         if (bds[i] == 0) {
 329             error_setg(errp, "Invalid boot device for PC: '%c'",
 330                        boot_device[i]);
 331             return;
 332         }
 333     }
 334     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 335     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 336 }
 337
 338 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
 339 {
 340     set_boot_dev(opaque, boot_device, errp);
 341 }
 342
 343 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
 344 {
 345     int val, nb, i;
 346     FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
 347                                    FLOPPY_DRIVE_TYPE_NONE };
 348
 349     /* floppy type */
 350     if (floppy) {
 351         for (i = 0; i < 2; i++) {
 352             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 353         }
 354     }
 355     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 356         cmos_get_fd_drive_type(fd_type[1]);
 357     rtc_set_memory(rtc_state, 0x10, val);
 358
 359     val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
 360     nb = 0;
 361     if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
 362         nb++;
 363     }
 364     if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
 365         nb++;
 366     }
 367     switch (nb) {
 368     case 0:
 369         break;
 370     case 1:
 371         val |= 0x01; /* 1 drive, ready for boot */
 372         break;
 373     case 2:
 374         val |= 0x41; /* 2 drives, ready for boot */
 375         break;
 376     }
 377     rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
 378 }
 379
 380 typedef struct pc_cmos_init_late_arg {
 381     ISADevice *rtc_state;
 382     BusState *idebus[2];
 383 } pc_cmos_init_late_arg;
 384
 385 typedef struct check_fdc_state {
 386     ISADevice *floppy;
 387     bool multiple;
 388 } CheckFdcState;
 389
 390 static int check_fdc(Object *obj, void *opaque)
 391 {
 392     CheckFdcState *state = opaque;
 393     Object *fdc;
 394     uint32_t iobase;
 395     Error *local_err = NULL;
 396
 397     fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
 398     if (!fdc) {
 399         return 0;
 400     }
 401
 402     iobase = object_property_get_uint(obj, "iobase", &local_err);
 403     if (local_err || iobase != 0x3f0) {
 404         error_free(local_err);
 405         return 0;
 406     }
 407
 408     if (state->floppy) {
 409         state->multiple = true;
 410     } else {
 411         state->floppy = ISA_DEVICE(obj);
 412     }
 413     return 0;
 414 }
 415
 416 static const char * const fdc_container_path[] = {
 417     "/unattached", "/peripheral", "/peripheral-anon"
 418 };
 419
 420 /*
 421  * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
 422  * and ACPI objects.
 423  */
 424 ISADevice *pc_find_fdc0(void)
 425 {
 426     int i;
 427     Object *container;
 428     CheckFdcState state = { 0 };
 429
 430     for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
 431         container = container_get(qdev_get_machine(), fdc_container_path[i]);
 432         object_child_foreach(container, check_fdc, &state);
 433     }
 434
 435     if (state.multiple) {
 436         warn_report("multiple floppy disk controllers with "
 437                     "iobase=0x3f0 have been found");
 438         error_printf("the one being picked for CMOS setup might not reflect "
 439                      "your intent");
 440     }
 441
 442     return state.floppy;
 443 }
 444
 445 static void pc_cmos_init_late(void *opaque)
 446 {
 447     pc_cmos_init_late_arg *arg = opaque;
 448     ISADevice *s = arg->rtc_state;
 449     int16_t cylinders;
 450     int8_t heads, sectors;
 451     int val;
 452     int i, trans;
 453
 454     val = 0;
 455     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
 456                                            &cylinders, &heads, &sectors) >= 0) {
 457         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 458         val |= 0xf0;
 459     }
 460     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
 461                                            &cylinders, &heads, &sectors) >= 0) {
 462         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 463         val |= 0x0f;
 464     }
 465     rtc_set_memory(s, 0x12, val);
 466
 467     val = 0;
 468     for (i = 0; i < 4; i++) {
 469         /* NOTE: ide_get_geometry() returns the physical
 470            geometry.  It is always such that: 1 <= sects <= 63, 1
 471            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 472            geometry can be different if a translation is done. */
 473         if (arg->idebus[i / 2] &&
 474             ide_get_geometry(arg->idebus[i / 2], i % 2,
 475                              &cylinders, &heads, &sectors) >= 0) {
 476             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 477             assert((trans & ~3) == 0);
 478             val |= trans << (i * 2);
 479         }
 480     }
 481     rtc_set_memory(s, 0x39, val);
 482
 483     pc_cmos_init_floppy(s, pc_find_fdc0());
 484
 485     qemu_unregister_reset(pc_cmos_init_late, opaque);
 486 }
 487
 488 void pc_cmos_init(PCMachineState *pcms,
 489                   BusState *idebus0, BusState *idebus1,
 490                   ISADevice *s)
 491 {
 492     int val;
 493     static pc_cmos_init_late_arg arg;
 494
 495     /* various important CMOS locations needed by PC/Bochs bios */
 496
 497     /* memory size */
 498     /* base memory (first MiB) */
 499     val = MIN(pcms->below_4g_mem_size / KiB, 640);
 500     rtc_set_memory(s, 0x15, val);
 501     rtc_set_memory(s, 0x16, val >> 8);
 502     /* extended memory (next 64MiB) */
 503     if (pcms->below_4g_mem_size > 1 * MiB) {
 504         val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
 505     } else {
 506         val = 0;
 507     }
 508     if (val > 65535)
 509         val = 65535;
 510     rtc_set_memory(s, 0x17, val);
 511     rtc_set_memory(s, 0x18, val >> 8);
 512     rtc_set_memory(s, 0x30, val);
 513     rtc_set_memory(s, 0x31, val >> 8);
 514     /* memory between 16MiB and 4GiB */
 515     if (pcms->below_4g_mem_size > 16 * MiB) {
 516         val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
 517     } else {
 518         val = 0;
 519     }
 520     if (val > 65535)
 521         val = 65535;
 522     rtc_set_memory(s, 0x34, val);
 523     rtc_set_memory(s, 0x35, val >> 8);
 524     /* memory above 4GiB */
 525     val = pcms->above_4g_mem_size / 65536;
 526     rtc_set_memory(s, 0x5b, val);
 527     rtc_set_memory(s, 0x5c, val >> 8);
 528     rtc_set_memory(s, 0x5d, val >> 16);
 529
 530     object_property_add_link(OBJECT(pcms), "rtc_state",
 531                              TYPE_ISA_DEVICE,
 532                              (Object **)&pcms->rtc,
 533                              object_property_allow_set_link,
 534                              OBJ_PROP_LINK_STRONG, &error_abort);
 535     object_property_set_link(OBJECT(pcms), OBJECT(s),
 536                              "rtc_state", &error_abort);
 537
 538     set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
 539
 540     val = 0;
 541     val |= 0x02; /* FPU is there */
 542     val |= 0x04; /* PS/2 mouse installed */
 543     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 544
 545     /* hard drives and FDC */
 546     arg.rtc_state = s;
 547     arg.idebus[0] = idebus0;
 548     arg.idebus[1] = idebus1;
 549     qemu_register_reset(pc_cmos_init_late, &arg);
 550 }
 551
 552 #define TYPE_PORT92 "port92"
 553 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
 554
 555 /* port 92 stuff: could be split off */
 556 typedef struct Port92State {
 557     ISADevice parent_obj;
 558
 559     MemoryRegion io;
 560     uint8_t outport;
 561     qemu_irq a20_out;
 562 } Port92State;
 563
 564 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 565                          unsigned size)
 566 {
 567     Port92State *s = opaque;
 568     int oldval = s->outport;
 569
 570     DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
 571     s->outport = val;
 572     qemu_set_irq(s->a20_out, (val >> 1) & 1);
 573     if ((val & 1) && !(oldval & 1)) {
 574         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 575     }
 576 }
 577
 578 static uint64_t port92_read(void *opaque, hwaddr addr,
 579                             unsigned size)
 580 {
 581     Port92State *s = opaque;
 582     uint32_t ret;
 583
 584     ret = s->outport;
 585     DPRINTF("port92: read 0x%02x\n", ret);
 586     return ret;
 587 }
 588
 589 static void port92_init(ISADevice *dev, qemu_irq a20_out)
 590 {
 591     qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
 592 }
 593
 594 static const VMStateDescription vmstate_port92_isa = {
 595     .name = "port92",
 596     .version_id = 1,
 597     .minimum_version_id = 1,
 598     .fields = (VMStateField[]) {
 599         VMSTATE_UINT8(outport, Port92State),
 600         VMSTATE_END_OF_LIST()
 601     }
 602 };
 603
 604 static void port92_reset(DeviceState *d)
 605 {
 606     Port92State *s = PORT92(d);
 607
 608     s->outport &= ~1;
 609 }
 610
 611 static const MemoryRegionOps port92_ops = {
 612     .read = port92_read,
 613     .write = port92_write,
 614     .impl = {
 615         .min_access_size = 1,
 616         .max_access_size = 1,
 617     },
 618     .endianness = DEVICE_LITTLE_ENDIAN,
 619 };
 620
 621 static void port92_initfn(Object *obj)
 622 {
 623     Port92State *s = PORT92(obj);
 624
 625     memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
 626
 627     s->outport = 0;
 628
 629     qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
 630 }
 631
 632 static void port92_realizefn(DeviceState *dev, Error **errp)
 633 {
 634     ISADevice *isadev = ISA_DEVICE(dev);
 635     Port92State *s = PORT92(dev);
 636
 637     isa_register_ioport(isadev, &s->io, 0x92);
 638 }
 639
 640 static void port92_class_initfn(ObjectClass *klass, void *data)
 641 {
 642     DeviceClass *dc = DEVICE_CLASS(klass);
 643
 644     dc->realize = port92_realizefn;
 645     dc->reset = port92_reset;
 646     dc->vmsd = &vmstate_port92_isa;
 647     /*
 648      * Reason: unlike ordinary ISA devices, this one needs additional
 649      * wiring: its A20 output line needs to be wired up by
 650      * port92_init().
 651      */
 652     dc->user_creatable = false;
 653 }
 654
 655 static const TypeInfo port92_info = {
 656     .name          = TYPE_PORT92,
 657     .parent        = TYPE_ISA_DEVICE,
 658     .instance_size = sizeof(Port92State),
 659     .instance_init = port92_initfn,
 660     .class_init    = port92_class_initfn,
 661 };
 662
 663 static void port92_register_types(void)
 664 {
 665     type_register_static(&port92_info);
 666 }
 667
 668 type_init(port92_register_types)
 669
 670 static void handle_a20_line_change(void *opaque, int irq, int level)
 671 {
 672     X86CPU *cpu = opaque;
 673
 674     /* XXX: send to all CPUs ? */
 675     /* XXX: add logic to handle multiple A20 line sources */
 676     x86_cpu_set_a20(cpu, level);
 677 }
 678
 679 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 680 {
 681     int index = le32_to_cpu(e820_reserve.count);
 682     struct e820_entry *entry;
 683
 684     if (type != E820_RAM) {
 685         /* old FW_CFG_E820_TABLE entry -- reservations only */
 686         if (index >= E820_NR_ENTRIES) {
 687             return -EBUSY;
 688         }
 689         entry = &e820_reserve.entry[index++];
 690
 691         entry->address = cpu_to_le64(address);
 692         entry->length = cpu_to_le64(length);
 693         entry->type = cpu_to_le32(type);
 694
 695         e820_reserve.count = cpu_to_le32(index);
 696     }
 697
 698     /* new "etc/e820" file -- include ram too */
 699     e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
 700     e820_table[e820_entries].address = cpu_to_le64(address);
 701     e820_table[e820_entries].length = cpu_to_le64(length);
 702     e820_table[e820_entries].type = cpu_to_le32(type);
 703     e820_entries++;
 704
 705     return e820_entries;
 706 }
 707
 708 int e820_get_num_entries(void)
 709 {
 710     return e820_entries;
 711 }
 712
 713 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
 714 {
 715     if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
 716         *address = le64_to_cpu(e820_table[idx].address);
 717         *length = le64_to_cpu(e820_table[idx].length);
 718         return true;
 719     }
 720     return false;
 721 }
 722
 723 /* Enables contiguous-apic-ID mode, for compatibility */
 724 static bool compat_apic_id_mode;
 725
 726 void enable_compat_apic_id_mode(void)
 727 {
 728     compat_apic_id_mode = true;
 729 }
 730
 731 /* Calculates initial APIC ID for a specific CPU index
 732  *
 733  * Currently we need to be able to calculate the APIC ID from the CPU index
 734  * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
 735  * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
 736  * all CPUs up to max_cpus.
 737  */
 738 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
 739 {
 740     uint32_t correct_id;
 741     static bool warned;
 742
 743     correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
 744     if (compat_apic_id_mode) {
 745         if (cpu_index != correct_id && !warned && !qtest_enabled()) {
 746             error_report("APIC IDs set in compatibility mode, "
 747                          "CPU topology won't match the configuration");
 748             warned = true;
 749         }
 750         return cpu_index;
 751     } else {
 752         return correct_id;
 753     }
 754 }
 755
 756 static void pc_build_smbios(PCMachineState *pcms)
 757 {
 758     uint8_t *smbios_tables, *smbios_anchor;
 759     size_t smbios_tables_len, smbios_anchor_len;
 760     struct smbios_phys_mem_area *mem_array;
 761     unsigned i, array_count;
 762     MachineState *ms = MACHINE(pcms);
 763     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
 764
 765     /* tell smbios about cpuid version and features */
 766     smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
 767
 768     smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
 769     if (smbios_tables) {
 770         fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 771                          smbios_tables, smbios_tables_len);
 772     }
 773
 774     /* build the array of physical mem area from e820 table */
 775     mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
 776     for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
 777         uint64_t addr, len;
 778
 779         if (e820_get_entry(i, E820_RAM, &addr, &len)) {
 780             mem_array[array_count].address = addr;
 781             mem_array[array_count].length = len;
 782             array_count++;
 783         }
 784     }
 785     smbios_get_tables(mem_array, array_count,
 786                       &smbios_tables, &smbios_tables_len,
 787                       &smbios_anchor, &smbios_anchor_len);
 788     g_free(mem_array);
 789
 790     if (smbios_anchor) {
 791         fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
 792                         smbios_tables, smbios_tables_len);
 793         fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
 794                         smbios_anchor, smbios_anchor_len);
 795     }
 796 }
 797
 798 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
 799 {
 800     FWCfgState *fw_cfg;
 801     uint64_t *numa_fw_cfg;
 802     int i;
 803     const CPUArchIdList *cpus;
 804     MachineClass *mc = MACHINE_GET_CLASS(pcms);
 805
 806     fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
 807     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
 808
 809     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 810      *
 811      * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
 812      * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
 813      * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
 814      * for CPU hotplug also uses APIC ID and not "CPU index".
 815      * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
 816      * but the "limit to the APIC ID values SeaBIOS may see".
 817      *
 818      * So for compatibility reasons with old BIOSes we are stuck with
 819      * "etc/max-cpus" actually being apic_id_limit
 820      */
 821     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
 822     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 823     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 824                      acpi_tables, acpi_tables_len);
 825     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 826
 827     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 828                      &e820_reserve, sizeof(e820_reserve));
 829     fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
 830                     sizeof(struct e820_entry) * e820_entries);
 831
 832     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 833     /* allocate memory for the NUMA channel: one (64bit) word for the number
 834      * of nodes, one word for each VCPU->node and one word for each node to
 835      * hold the amount of memory.
 836      */
 837     numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
 838     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 839     cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
 840     for (i = 0; i < cpus->len; i++) {
 841         unsigned int apic_id = cpus->cpus[i].arch_id;
 842         assert(apic_id < pcms->apic_id_limit);
 843         numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
 844     }
 845     for (i = 0; i < nb_numa_nodes; i++) {
 846         numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
 847             cpu_to_le64(numa_info[i].node_mem);
 848     }
 849     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 850                      (1 + pcms->apic_id_limit + nb_numa_nodes) *
 851                      sizeof(*numa_fw_cfg));
 852
 853     return fw_cfg;
 854 }
 855
 856 static long get_file_size(FILE *f)
 857 {
 858     long where, size;
 859
 860     /* XXX: on Unix systems, using fstat() probably makes more sense */
 861
 862     where = ftell(f);
 863     fseek(f, 0, SEEK_END);
 864     size = ftell(f);
 865     fseek(f, where, SEEK_SET);
 866
 867     return size;
 868 }
 869
 870 /* setup_data types */
 871 #define SETUP_NONE     0
 872 #define SETUP_E820_EXT 1
 873 #define SETUP_DTB      2
 874 #define SETUP_PCI      3
 875 #define SETUP_EFI      4
 876
 877 struct setup_data {
 878     uint64_t next;
 879     uint32_t type;
 880     uint32_t len;
 881     uint8_t data[0];
 882 } __attribute__((packed));
 883
 884 static void load_linux(PCMachineState *pcms,
 885                        FWCfgState *fw_cfg)
 886 {
 887     uint16_t protocol;
 888     int setup_size, kernel_size, cmdline_size;
 889     int dtb_size, setup_data_offset;
 890     uint32_t initrd_max;
 891     uint8_t header[8192], *setup, *kernel;
 892     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 893     FILE *f;
 894     char *vmode;
 895     MachineState *machine = MACHINE(pcms);
 896     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
 897     struct setup_data *setup_data;
 898     const char *kernel_filename = machine->kernel_filename;
 899     const char *initrd_filename = machine->initrd_filename;
 900     const char *dtb_filename = machine->dtb;
 901     const char *kernel_cmdline = machine->kernel_cmdline;
 902
 903     /* Align to 16 bytes as a paranoia measure */
 904     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 905
 906     /* load the kernel header */
 907     f = fopen(kernel_filename, "rb");
 908     if (!f || !(kernel_size = get_file_size(f)) ||
 909         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 910         MIN(ARRAY_SIZE(header), kernel_size)) {
 911         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 912                 kernel_filename, strerror(errno));
 913         exit(1);
 914     }
 915
 916     /* kernel protocol version */
 917 #if 0
 918     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 919 #endif
 920     if (ldl_p(header+0x202) == 0x53726448) {
 921         protocol = lduw_p(header+0x206);
 922     } else {
 923         /* This looks like a multiboot kernel. If it is, let's stop
 924            treating it like a Linux kernel. */
 925         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 926                            kernel_cmdline, kernel_size, header)) {
 927             return;
 928         }
 929         protocol = 0;
 930     }
 931
 932     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 933         /* Low kernel */
 934         real_addr    = 0x90000;
 935         cmdline_addr = 0x9a000 - cmdline_size;
 936         prot_addr    = 0x10000;
 937     } else if (protocol < 0x202) {
 938         /* High but ancient kernel */
 939         real_addr    = 0x90000;
 940         cmdline_addr = 0x9a000 - cmdline_size;
 941         prot_addr    = 0x100000;
 942     } else {
 943         /* High and recent kernel */
 944         real_addr    = 0x10000;
 945         cmdline_addr = 0x20000;
 946         prot_addr    = 0x100000;
 947     }
 948
 949 #if 0
 950     fprintf(stderr,
 951             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 952             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 953             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 954             real_addr,
 955             cmdline_addr,
 956             prot_addr);
 957 #endif
 958
 959     /* highest address for loading the initrd */
 960     if (protocol >= 0x203) {
 961         initrd_max = ldl_p(header+0x22c);
 962     } else {
 963         initrd_max = 0x37ffffff;
 964     }
 965
 966     if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
 967         initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
 968     }
 969
 970     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 971     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 972     fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
 973
 974     if (protocol >= 0x202) {
 975         stl_p(header+0x228, cmdline_addr);
 976     } else {
 977         stw_p(header+0x20, 0xA33F);
 978         stw_p(header+0x22, cmdline_addr-real_addr);
 979     }
 980
 981     /* handle vga= parameter */
 982     vmode = strstr(kernel_cmdline, "vga=");
 983     if (vmode) {
 984         unsigned int video_mode;
 985         /* skip "vga=" */
 986         vmode += 4;
 987         if (!strncmp(vmode, "normal", 6)) {
 988             video_mode = 0xffff;
 989         } else if (!strncmp(vmode, "ext", 3)) {
 990             video_mode = 0xfffe;
 991         } else if (!strncmp(vmode, "ask", 3)) {
 992             video_mode = 0xfffd;
 993         } else {
 994             video_mode = strtol(vmode, NULL, 0);
 995         }
 996         stw_p(header+0x1fa, video_mode);
 997     }
 998
 999     /* loader type */
1000     /* High nybble = B reserved for QEMU; low nybble is revision number.
1001        If this code is substantially changed, you may want to consider
1002        incrementing the revision. */
1003     if (protocol >= 0x200) {
1004         header[0x210] = 0xB0;
1005     }
1006     /* heap */
1007     if (protocol >= 0x201) {
1008         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
1009         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
1010     }
1011
1012     /* load initrd */
1013     if (initrd_filename) {
1014         gsize initrd_size;
1015         gchar *initrd_data;
1016         GError *gerr = NULL;
1017
1018         if (protocol < 0x200) {
1019             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
1020             exit(1);
1021         }
1022
1023         if (!g_file_get_contents(initrd_filename, &initrd_data,
1024                                  &initrd_size, &gerr)) {
1025             fprintf(stderr, "qemu: error reading initrd %s: %s\n",
1026                     initrd_filename, gerr->message);
1027             exit(1);
1028         }
1029         if (initrd_size >= initrd_max) {
1030             fprintf(stderr, "qemu: initrd is too large, cannot support."
1031                     "(max: %"PRIu32", need %"PRId64")\n",
1032                     initrd_max, (uint64_t)initrd_size);
1033             exit(1);
1034         }
1035
1036         initrd_addr = (initrd_max-initrd_size) & ~4095;
1037
1038         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1039         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1040         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
1041
1042         stl_p(header+0x218, initrd_addr);
1043         stl_p(header+0x21c, initrd_size);
1044     }
1045
1046     /* load kernel and setup */
1047     setup_size = header[0x1f1];
1048     if (setup_size == 0) {
1049         setup_size = 4;
1050     }
1051     setup_size = (setup_size+1)*512;
1052     if (setup_size > kernel_size) {
1053         fprintf(stderr, "qemu: invalid kernel header\n");
1054         exit(1);
1055     }
1056     kernel_size -= setup_size;
1057
1058     setup  = g_malloc(setup_size);
1059     kernel = g_malloc(kernel_size);
1060     fseek(f, 0, SEEK_SET);
1061     if (fread(setup, 1, setup_size, f) != setup_size) {
1062         fprintf(stderr, "fread() failed\n");
1063         exit(1);
1064     }
1065     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1066         fprintf(stderr, "fread() failed\n");
1067         exit(1);
1068     }
1069     fclose(f);
1070
1071     /* append dtb to kernel */
1072     if (dtb_filename) {
1073         if (protocol < 0x209) {
1074             fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1075             exit(1);
1076         }
1077
1078         dtb_size = get_image_size(dtb_filename);
1079         if (dtb_size <= 0) {
1080             fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1081                     dtb_filename, strerror(errno));
1082             exit(1);
1083         }
1084
1085         setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1086         kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1087         kernel = g_realloc(kernel, kernel_size);
1088
1089         stq_p(header+0x250, prot_addr + setup_data_offset);
1090
1091         setup_data = (struct setup_data *)(kernel + setup_data_offset);
1092         setup_data->next = 0;
1093         setup_data->type = cpu_to_le32(SETUP_DTB);
1094         setup_data->len = cpu_to_le32(dtb_size);
1095
1096         load_image_size(dtb_filename, setup_data->data, dtb_size);
1097     }
1098
1099     memcpy(setup, header, MIN(sizeof(header), setup_size));
1100
1101     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1102     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1103     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1104
1105     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1106     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1107     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1108
1109     option_rom[nb_option_roms].bootindex = 0;
1110     option_rom[nb_option_roms].name = "linuxboot.bin";
1111     if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
1112         option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1113     }
1114     nb_option_roms++;
1115 }
1116
1117 #define NE2000_NB_MAX 6
1118
1119 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1120                                               0x280, 0x380 };
1121 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1122
1123 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1124 {
1125     static int nb_ne2k = 0;
1126
1127     if (nb_ne2k == NE2000_NB_MAX)
1128         return;
1129     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1130                     ne2000_irq[nb_ne2k], nd);
1131     nb_ne2k++;
1132 }
1133
1134 DeviceState *cpu_get_current_apic(void)
1135 {
1136     if (current_cpu) {
1137         X86CPU *cpu = X86_CPU(current_cpu);
1138         return cpu->apic_state;
1139     } else {
1140         return NULL;
1141     }
1142 }
1143
1144 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1145 {
1146     X86CPU *cpu = opaque;
1147
1148     if (level) {
1149         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1150     }
1151 }
1152
1153 static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
1154 {
1155     Object *cpu = NULL;
1156     Error *local_err = NULL;
1157
1158     cpu = object_new(typename);
1159
1160     object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
1161     object_property_set_bool(cpu, true, "realized", &local_err);
1162
1163     object_unref(cpu);
1164     error_propagate(errp, local_err);
1165 }
1166
1167 void pc_hot_add_cpu(const int64_t id, Error **errp)
1168 {
1169     MachineState *ms = MACHINE(qdev_get_machine());
1170     int64_t apic_id = x86_cpu_apic_id_from_index(id);
1171     Error *local_err = NULL;
1172
1173     if (id < 0) {
1174         error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1175         return;
1176     }
1177
1178     if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1179         error_setg(errp, "Unable to add CPU: %" PRIi64
1180                    ", resulting APIC ID (%" PRIi64 ") is too large",
1181                    id, apic_id);
1182         return;
1183     }
1184
1185     pc_new_cpu(ms->cpu_type, apic_id, &local_err);
1186     if (local_err) {
1187         error_propagate(errp, local_err);
1188         return;
1189     }
1190 }
1191
1192 void pc_cpus_init(PCMachineState *pcms)
1193 {
1194     int i;
1195     const CPUArchIdList *possible_cpus;
1196     MachineState *ms = MACHINE(pcms);
1197     MachineClass *mc = MACHINE_GET_CLASS(pcms);
1198
1199     /* Calculates the limit to CPU APIC ID values
1200      *
1201      * Limit for the APIC ID value, so that all
1202      * CPU APIC IDs are < pcms->apic_id_limit.
1203      *
1204      * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1205      */
1206     pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
1207     possible_cpus = mc->possible_cpu_arch_ids(ms);
1208     for (i = 0; i < smp_cpus; i++) {
1209         pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
1210                    &error_fatal);
1211     }
1212 }
1213
1214 static void pc_build_feature_control_file(PCMachineState *pcms)
1215 {
1216     MachineState *ms = MACHINE(pcms);
1217     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
1218     CPUX86State *env = &cpu->env;
1219     uint32_t unused, ecx, edx;
1220     uint64_t feature_control_bits = 0;
1221     uint64_t *val;
1222
1223     cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1224     if (ecx & CPUID_EXT_VMX) {
1225         feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1226     }
1227
1228     if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1229         (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1230         (env->mcg_cap & MCG_LMCE_P)) {
1231         feature_control_bits |= FEATURE_CONTROL_LMCE;
1232     }
1233
1234     if (!feature_control_bits) {
1235         return;
1236     }
1237
1238     val = g_malloc(sizeof(*val));
1239     *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1240     fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1241 }
1242
1243 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1244 {
1245     if (cpus_count > 0xff) {
1246         /* If the number of CPUs can't be represented in 8 bits, the
1247          * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1248          * to make old BIOSes fail more predictably.
1249          */
1250         rtc_set_memory(rtc, 0x5f, 0);
1251     } else {
1252         rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1253     }
1254 }
1255
1256 static
1257 void pc_machine_done(Notifier *notifier, void *data)
1258 {
1259     PCMachineState *pcms = container_of(notifier,
1260                                         PCMachineState, machine_done);
1261     PCIBus *bus = pcms->bus;
1262
1263     /* set the number of CPUs */
1264     rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1265
1266     if (bus) {
1267         int extra_hosts = 0;
1268
1269         QLIST_FOREACH(bus, &bus->child, sibling) {
1270             /* look for expander root buses */
1271             if (pci_bus_is_root(bus)) {
1272                 extra_hosts++;
1273             }
1274         }
1275         if (extra_hosts && pcms->fw_cfg) {
1276             uint64_t *val = g_malloc(sizeof(*val));
1277             *val = cpu_to_le64(extra_hosts);
1278             fw_cfg_add_file(pcms->fw_cfg,
1279                     "etc/extra-pci-roots", val, sizeof(*val));
1280         }
1281     }
1282
1283     acpi_setup();
1284     if (pcms->fw_cfg) {
1285         pc_build_smbios(pcms);
1286         pc_build_feature_control_file(pcms);
1287         /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1288         fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1289     }
1290
1291     if (pcms->apic_id_limit > 255 && !xen_enabled()) {
1292         IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1293
1294         if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
1295             iommu->intr_eim != ON_OFF_AUTO_ON) {
1296             error_report("current -smp configuration requires "
1297                          "Extended Interrupt Mode enabled. "
1298                          "You can add an IOMMU using: "
1299                          "-device intel-iommu,intremap=on,eim=on");
1300             exit(EXIT_FAILURE);
1301         }
1302     }
1303 }
1304
1305 void pc_guest_info_init(PCMachineState *pcms)
1306 {
1307     int i;
1308
1309     pcms->apic_xrupt_override = kvm_allows_irq0_override();
1310     pcms->numa_nodes = nb_numa_nodes;
1311     pcms->node_mem = g_malloc0(pcms->numa_nodes *
1312                                     sizeof *pcms->node_mem);
1313     for (i = 0; i < nb_numa_nodes; i++) {
1314         pcms->node_mem[i] = numa_info[i].node_mem;
1315     }
1316
1317     pcms->machine_done.notify = pc_machine_done;
1318     qemu_add_machine_init_done_notifier(&pcms->machine_done);
1319 }
1320
1321 /* setup pci memory address space mapping into system address space */
1322 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1323                             MemoryRegion *pci_address_space)
1324 {
1325     /* Set to lower priority than RAM */
1326     memory_region_add_subregion_overlap(system_memory, 0x0,
1327                                         pci_address_space, -1);
1328 }
1329
1330 void pc_acpi_init(const char *default_dsdt)
1331 {
1332     char *filename;
1333
1334     if (acpi_tables != NULL) {
1335         /* manually set via -acpitable, leave it alone */
1336         return;
1337     }
1338
1339     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1340     if (filename == NULL) {
1341         warn_report("failed to find %s", default_dsdt);
1342     } else {
1343         QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1344                                           &error_abort);
1345         Error *err = NULL;
1346
1347         qemu_opt_set(opts, "file", filename, &error_abort);
1348
1349         acpi_table_add_builtin(opts, &err);
1350         if (err) {
1351             warn_reportf_err(err, "failed to load %s: ", filename);
1352         }
1353         g_free(filename);
1354     }
1355 }
1356
1357 void xen_load_linux(PCMachineState *pcms)
1358 {
1359     int i;
1360     FWCfgState *fw_cfg;
1361
1362     assert(MACHINE(pcms)->kernel_filename != NULL);
1363
1364     fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1365     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1366     rom_set_fw(fw_cfg);
1367
1368     load_linux(pcms, fw_cfg);
1369     for (i = 0; i < nb_option_roms; i++) {
1370         assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1371                !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1372                !strcmp(option_rom[i].name, "multiboot.bin"));
1373         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1374     }
1375     pcms->fw_cfg = fw_cfg;
1376 }
1377
1378 void pc_memory_init(PCMachineState *pcms,
1379                     MemoryRegion *system_memory,
1380                     MemoryRegion *rom_memory,
1381                     MemoryRegion **ram_memory)
1382 {
1383     int linux_boot, i;
1384     MemoryRegion *ram, *option_rom_mr;
1385     MemoryRegion *ram_below_4g, *ram_above_4g;
1386     FWCfgState *fw_cfg;
1387     MachineState *machine = MACHINE(pcms);
1388     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1389
1390     assert(machine->ram_size == pcms->below_4g_mem_size +
1391                                 pcms->above_4g_mem_size);
1392
1393     linux_boot = (machine->kernel_filename != NULL);
1394
1395     /* Allocate RAM.  We allocate it as a single memory region and use
1396      * aliases to address portions of it, mostly for backwards compatibility
1397      * with older qemus that used qemu_ram_alloc().
1398      */
1399     ram = g_malloc(sizeof(*ram));
1400     memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1401                                          machine->ram_size);
1402     *ram_memory = ram;
1403     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1404     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1405                              0, pcms->below_4g_mem_size);
1406     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1407     e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1408     if (pcms->above_4g_mem_size > 0) {
1409         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1410         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1411                                  pcms->below_4g_mem_size,
1412                                  pcms->above_4g_mem_size);
1413         memory_region_add_subregion(system_memory, 0x100000000ULL,
1414                                     ram_above_4g);
1415         e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1416     }
1417
1418     if (!pcmc->has_reserved_memory &&
1419         (machine->ram_slots ||
1420          (machine->maxram_size > machine->ram_size))) {
1421         MachineClass *mc = MACHINE_GET_CLASS(machine);
1422
1423         error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1424                      mc->name);
1425         exit(EXIT_FAILURE);
1426     }
1427
1428     /* always allocate the device memory information */
1429     machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1430
1431     /* initialize device memory address space */
1432     if (pcmc->has_reserved_memory &&
1433         (machine->ram_size < machine->maxram_size)) {
1434         ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1435
1436         if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1437             error_report("unsupported amount of memory slots: %"PRIu64,
1438                          machine->ram_slots);
1439             exit(EXIT_FAILURE);
1440         }
1441
1442         if (QEMU_ALIGN_UP(machine->maxram_size,
1443                           TARGET_PAGE_SIZE) != machine->maxram_size) {
1444             error_report("maximum memory size must by aligned to multiple of "
1445                          "%d bytes", TARGET_PAGE_SIZE);
1446             exit(EXIT_FAILURE);
1447         }
1448
1449         machine->device_memory->base =
1450             ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
1451
1452         if (pcmc->enforce_aligned_dimm) {
1453             /* size device region assuming 1G page max alignment per slot */
1454             device_mem_size += (1 * GiB) * machine->ram_slots;
1455         }
1456
1457         if ((machine->device_memory->base + device_mem_size) <
1458             device_mem_size) {
1459             error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1460                          machine->maxram_size);
1461             exit(EXIT_FAILURE);
1462         }
1463
1464         memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1465                            "device-memory", device_mem_size);
1466         memory_region_add_subregion(system_memory, machine->device_memory->base,
1467                                     &machine->device_memory->mr);
1468     }
1469
1470     /* Initialize PC system firmware */
1471     pc_system_firmware_init(rom_memory, !pcmc->pci_enabled);
1472
1473     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1474     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1475                            &error_fatal);
1476     if (pcmc->pci_enabled) {
1477         memory_region_set_readonly(option_rom_mr, true);
1478     }
1479     memory_region_add_subregion_overlap(rom_memory,
1480                                         PC_ROM_MIN_VGA,
1481                                         option_rom_mr,
1482                                         1);
1483
1484     fw_cfg = bochs_bios_init(&address_space_memory, pcms);
1485
1486     rom_set_fw(fw_cfg);
1487
1488     if (pcmc->has_reserved_memory && machine->device_memory->base) {
1489         uint64_t *val = g_malloc(sizeof(*val));
1490         PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1491         uint64_t res_mem_end = machine->device_memory->base;
1492
1493         if (!pcmc->broken_reserved_end) {
1494             res_mem_end += memory_region_size(&machine->device_memory->mr);
1495         }
1496         *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1497         fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1498     }
1499
1500     if (linux_boot) {
1501         load_linux(pcms, fw_cfg);
1502     }
1503
1504     for (i = 0; i < nb_option_roms; i++) {
1505         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1506     }
1507     pcms->fw_cfg = fw_cfg;
1508
1509     /* Init default IOAPIC address space */
1510     pcms->ioapic_as = &address_space_memory;
1511 }
1512
1513 /*
1514  * The 64bit pci hole starts after "above 4G RAM" and
1515  * potentially the space reserved for memory hotplug.
1516  */
1517 uint64_t pc_pci_hole64_start(void)
1518 {
1519     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1520     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1521     MachineState *ms = MACHINE(pcms);
1522     uint64_t hole64_start = 0;
1523
1524     if (pcmc->has_reserved_memory && ms->device_memory->base) {
1525         hole64_start = ms->device_memory->base;
1526         if (!pcmc->broken_reserved_end) {
1527             hole64_start += memory_region_size(&ms->device_memory->mr);
1528         }
1529     } else {
1530         hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1531     }
1532
1533     return ROUND_UP(hole64_start, 1 * GiB);
1534 }
1535
1536 qemu_irq pc_allocate_cpu_irq(void)
1537 {
1538     return qemu_allocate_irq(pic_irq_request, NULL, 0);
1539 }
1540
1541 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1542 {
1543     DeviceState *dev = NULL;
1544
1545     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1546     if (pci_bus) {
1547         PCIDevice *pcidev = pci_vga_init(pci_bus);
1548         dev = pcidev ? &pcidev->qdev : NULL;
1549     } else if (isa_bus) {
1550         ISADevice *isadev = isa_vga_init(isa_bus);
1551         dev = isadev ? DEVICE(isadev) : NULL;
1552     }
1553     rom_reset_order_override();
1554     return dev;
1555 }
1556
1557 static const MemoryRegionOps ioport80_io_ops = {
1558     .write = ioport80_write,
1559     .read = ioport80_read,
1560     .endianness = DEVICE_NATIVE_ENDIAN,
1561     .impl = {
1562         .min_access_size = 1,
1563         .max_access_size = 1,
1564     },
1565 };
1566
1567 static const MemoryRegionOps ioportF0_io_ops = {
1568     .write = ioportF0_write,
1569     .read = ioportF0_read,
1570     .endianness = DEVICE_NATIVE_ENDIAN,
1571     .impl = {
1572         .min_access_size = 1,
1573         .max_access_size = 1,
1574     },
1575 };
1576
1577 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1578 {
1579     int i;
1580     DriveInfo *fd[MAX_FD];
1581     qemu_irq *a20_line;
1582     ISADevice *i8042, *port92, *vmmouse;
1583
1584     serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1585     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1586
1587     for (i = 0; i < MAX_FD; i++) {
1588         fd[i] = drive_get(IF_FLOPPY, 0, i);
1589         create_fdctrl |= !!fd[i];
1590     }
1591     if (create_fdctrl) {
1592         fdctrl_init_isa(isa_bus, fd);
1593     }
1594
1595     i8042 = isa_create_simple(isa_bus, "i8042");
1596     if (!no_vmport) {
1597         vmport_init(isa_bus);
1598         vmmouse = isa_try_create(isa_bus, "vmmouse");
1599     } else {
1600         vmmouse = NULL;
1601     }
1602     if (vmmouse) {
1603         DeviceState *dev = DEVICE(vmmouse);
1604         qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1605         qdev_init_nofail(dev);
1606     }
1607     port92 = isa_create_simple(isa_bus, "port92");
1608
1609     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1610     i8042_setup_a20_line(i8042, a20_line[0]);
1611     port92_init(port92, a20_line[1]);
1612     g_free(a20_line);
1613 }
1614
1615 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1616                           ISADevice **rtc_state,
1617                           bool create_fdctrl,
1618                           bool no_vmport,
1619                           bool has_pit,
1620                           uint32_t hpet_irqs)
1621 {
1622     int i;
1623     DeviceState *hpet = NULL;
1624     int pit_isa_irq = 0;
1625     qemu_irq pit_alt_irq = NULL;
1626     qemu_irq rtc_irq = NULL;
1627     ISADevice *pit = NULL;
1628     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1629     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1630
1631     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1632     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1633
1634     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1635     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1636
1637     /*
1638      * Check if an HPET shall be created.
1639      *
1640      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1641      * when the HPET wants to take over. Thus we have to disable the latter.
1642      */
1643     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1644         /* In order to set property, here not using sysbus_try_create_simple */
1645         hpet = qdev_try_create(NULL, TYPE_HPET);
1646         if (hpet) {
1647             /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1648              * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1649              * IRQ8 and IRQ2.
1650              */
1651             uint8_t compat = object_property_get_uint(OBJECT(hpet),
1652                     HPET_INTCAP, NULL);
1653             if (!compat) {
1654                 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1655             }
1656             qdev_init_nofail(hpet);
1657             sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1658
1659             for (i = 0; i < GSI_NUM_PINS; i++) {
1660                 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1661             }
1662             pit_isa_irq = -1;
1663             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1664             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1665         }
1666     }
1667     *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1668
1669     qemu_register_boot_set(pc_boot_set, *rtc_state);
1670
1671     if (!xen_enabled() && has_pit) {
1672         if (kvm_pit_in_kernel()) {
1673             pit = kvm_pit_init(isa_bus, 0x40);
1674         } else {
1675             pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1676         }
1677         if (hpet) {
1678             /* connect PIT to output control line of the HPET */
1679             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1680         }
1681         pcspk_init(isa_bus, pit);
1682     }
1683
1684     i8257_dma_init(isa_bus, 0);
1685
1686     /* Super I/O */
1687     pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1688 }
1689
1690 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1691 {
1692     int i;
1693
1694     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1695     for (i = 0; i < nb_nics; i++) {
1696         NICInfo *nd = &nd_table[i];
1697         const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1698
1699         if (g_str_equal(model, "ne2k_isa")) {
1700             pc_init_ne2k_isa(isa_bus, nd);
1701         } else {
1702             pci_nic_init_nofail(nd, pci_bus, model, NULL);
1703         }
1704     }
1705     rom_reset_order_override();
1706 }
1707
1708 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1709 {
1710     DeviceState *dev;
1711     SysBusDevice *d;
1712     unsigned int i;
1713
1714     if (kvm_ioapic_in_kernel()) {
1715         dev = qdev_create(NULL, "kvm-ioapic");
1716     } else {
1717         dev = qdev_create(NULL, "ioapic");
1718     }
1719     if (parent_name) {
1720         object_property_add_child(object_resolve_path(parent_name, NULL),
1721                                   "ioapic", OBJECT(dev), NULL);
1722     }
1723     qdev_init_nofail(dev);
1724     d = SYS_BUS_DEVICE(dev);
1725     sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1726
1727     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1728         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1729     }
1730 }
1731
1732 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1733                                Error **errp)
1734 {
1735     const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1736     const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1737     const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1738     const uint64_t legacy_align = TARGET_PAGE_SIZE;
1739
1740     /*
1741      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1742      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1743      * addition to cover this case.
1744      */
1745     if (!pcms->acpi_dev || !acpi_enabled) {
1746         error_setg(errp,
1747                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1748         return;
1749     }
1750
1751     if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) {
1752         error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1753         return;
1754     }
1755
1756     pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1757                      pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1758 }
1759
1760 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1761                            DeviceState *dev, Error **errp)
1762 {
1763     HotplugHandlerClass *hhc;
1764     Error *local_err = NULL;
1765     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1766     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1767
1768     pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1769     if (local_err) {
1770         goto out;
1771     }
1772
1773     if (is_nvdimm) {
1774         nvdimm_plug(&pcms->acpi_nvdimm_state);
1775     }
1776
1777     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1778     hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1779 out:
1780     error_propagate(errp, local_err);
1781 }
1782
1783 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1784                                      DeviceState *dev, Error **errp)
1785 {
1786     HotplugHandlerClass *hhc;
1787     Error *local_err = NULL;
1788     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1789
1790     /*
1791      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1792      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1793      * addition to cover this case.
1794      */
1795     if (!pcms->acpi_dev || !acpi_enabled) {
1796         error_setg(&local_err,
1797                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1798         goto out;
1799     }
1800
1801     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1802         error_setg(&local_err,
1803                    "nvdimm device hot unplug is not supported yet.");
1804         goto out;
1805     }
1806
1807     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1808     hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1809
1810 out:
1811     error_propagate(errp, local_err);
1812 }
1813
1814 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1815                              DeviceState *dev, Error **errp)
1816 {
1817     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1818     HotplugHandlerClass *hhc;
1819     Error *local_err = NULL;
1820
1821     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1822     hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1823
1824     if (local_err) {
1825         goto out;
1826     }
1827
1828     pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1829     object_unparent(OBJECT(dev));
1830
1831  out:
1832     error_propagate(errp, local_err);
1833 }
1834
1835 static int pc_apic_cmp(const void *a, const void *b)
1836 {
1837    CPUArchId *apic_a = (CPUArchId *)a;
1838    CPUArchId *apic_b = (CPUArchId *)b;
1839
1840    return apic_a->arch_id - apic_b->arch_id;
1841 }
1842
1843 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1844  * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1845  * entry corresponding to CPU's apic_id returns NULL.
1846  */
1847 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1848 {
1849     CPUArchId apic_id, *found_cpu;
1850
1851     apic_id.arch_id = id;
1852     found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1853         ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1854         pc_apic_cmp);
1855     if (found_cpu && idx) {
1856         *idx = found_cpu - ms->possible_cpus->cpus;
1857     }
1858     return found_cpu;
1859 }
1860
1861 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1862                         DeviceState *dev, Error **errp)
1863 {
1864     CPUArchId *found_cpu;
1865     HotplugHandlerClass *hhc;
1866     Error *local_err = NULL;
1867     X86CPU *cpu = X86_CPU(dev);
1868     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1869
1870     if (pcms->acpi_dev) {
1871         hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1872         hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1873         if (local_err) {
1874             goto out;
1875         }
1876     }
1877
1878     /* increment the number of CPUs */
1879     pcms->boot_cpus++;
1880     if (pcms->rtc) {
1881         rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1882     }
1883     if (pcms->fw_cfg) {
1884         fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1885     }
1886
1887     found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1888     found_cpu->cpu = OBJECT(dev);
1889 out:
1890     error_propagate(errp, local_err);
1891 }
1892 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1893                                      DeviceState *dev, Error **errp)
1894 {
1895     int idx = -1;
1896     HotplugHandlerClass *hhc;
1897     Error *local_err = NULL;
1898     X86CPU *cpu = X86_CPU(dev);
1899     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1900
1901     if (!pcms->acpi_dev) {
1902         error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1903         goto out;
1904     }
1905
1906     pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1907     assert(idx != -1);
1908     if (idx == 0) {
1909         error_setg(&local_err, "Boot CPU is unpluggable");
1910         goto out;
1911     }
1912
1913     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1914     hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1915
1916     if (local_err) {
1917         goto out;
1918     }
1919
1920  out:
1921     error_propagate(errp, local_err);
1922
1923 }
1924
1925 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1926                              DeviceState *dev, Error **errp)
1927 {
1928     CPUArchId *found_cpu;
1929     HotplugHandlerClass *hhc;
1930     Error *local_err = NULL;
1931     X86CPU *cpu = X86_CPU(dev);
1932     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1933
1934     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1935     hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1936
1937     if (local_err) {
1938         goto out;
1939     }
1940
1941     found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1942     found_cpu->cpu = NULL;
1943     object_unparent(OBJECT(dev));
1944
1945     /* decrement the number of CPUs */
1946     pcms->boot_cpus--;
1947     /* Update the number of CPUs in CMOS */
1948     rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1949     fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1950  out:
1951     error_propagate(errp, local_err);
1952 }
1953
1954 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1955                             DeviceState *dev, Error **errp)
1956 {
1957     int idx;
1958     CPUState *cs;
1959     CPUArchId *cpu_slot;
1960     X86CPUTopoInfo topo;
1961     X86CPU *cpu = X86_CPU(dev);
1962     MachineState *ms = MACHINE(hotplug_dev);
1963     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1964
1965     if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1966         error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1967                    ms->cpu_type);
1968         return;
1969     }
1970
1971     /* if APIC ID is not set, set it based on socket/core/thread properties */
1972     if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1973         int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
1974
1975         if (cpu->socket_id < 0) {
1976             error_setg(errp, "CPU socket-id is not set");
1977             return;
1978         } else if (cpu->socket_id > max_socket) {
1979             error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1980                        cpu->socket_id, max_socket);
1981             return;
1982         }
1983         if (cpu->core_id < 0) {
1984             error_setg(errp, "CPU core-id is not set");
1985             return;
1986         } else if (cpu->core_id > (smp_cores - 1)) {
1987             error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1988                        cpu->core_id, smp_cores - 1);
1989             return;
1990         }
1991         if (cpu->thread_id < 0) {
1992             error_setg(errp, "CPU thread-id is not set");
1993             return;
1994         } else if (cpu->thread_id > (smp_threads - 1)) {
1995             error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1996                        cpu->thread_id, smp_threads - 1);
1997             return;
1998         }
1999
2000         topo.pkg_id = cpu->socket_id;
2001         topo.core_id = cpu->core_id;
2002         topo.smt_id = cpu->thread_id;
2003         cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
2004     }
2005
2006     cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
2007     if (!cpu_slot) {
2008         MachineState *ms = MACHINE(pcms);
2009
2010         x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2011         error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
2012                   " APIC ID %" PRIu32 ", valid index range 0:%d",
2013                    topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
2014                    ms->possible_cpus->len - 1);
2015         return;
2016     }
2017
2018     if (cpu_slot->cpu) {
2019         error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
2020                    idx, cpu->apic_id);
2021         return;
2022     }
2023
2024     /* if 'address' properties socket-id/core-id/thread-id are not set, set them
2025      * so that machine_query_hotpluggable_cpus would show correct values
2026      */
2027     /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2028      * once -smp refactoring is complete and there will be CPU private
2029      * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2030     x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2031     if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
2032         error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
2033             " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
2034         return;
2035     }
2036     cpu->socket_id = topo.pkg_id;
2037
2038     if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
2039         error_setg(errp, "property core-id: %u doesn't match set apic-id:"
2040             " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
2041         return;
2042     }
2043     cpu->core_id = topo.core_id;
2044
2045     if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
2046         error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2047             " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2048         return;
2049     }
2050     cpu->thread_id = topo.smt_id;
2051
2052     if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) {
2053         error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2054         return;
2055     }
2056
2057     cs = CPU(cpu);
2058     cs->cpu_index = idx;
2059
2060     numa_cpu_pre_plug(cpu_slot, dev, errp);
2061 }
2062
2063 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2064                                           DeviceState *dev, Error **errp)
2065 {
2066     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2067         pc_memory_pre_plug(hotplug_dev, dev, errp);
2068     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2069         pc_cpu_pre_plug(hotplug_dev, dev, errp);
2070     }
2071 }
2072
2073 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2074                                       DeviceState *dev, Error **errp)
2075 {
2076     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2077         pc_memory_plug(hotplug_dev, dev, errp);
2078     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2079         pc_cpu_plug(hotplug_dev, dev, errp);
2080     }
2081 }
2082
2083 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2084                                                 DeviceState *dev, Error **errp)
2085 {
2086     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2087         pc_memory_unplug_request(hotplug_dev, dev, errp);
2088     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2089         pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
2090     } else {
2091         error_setg(errp, "acpi: device unplug request for not supported device"
2092                    " type: %s", object_get_typename(OBJECT(dev)));
2093     }
2094 }
2095
2096 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2097                                         DeviceState *dev, Error **errp)
2098 {
2099     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2100         pc_memory_unplug(hotplug_dev, dev, errp);
2101     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2102         pc_cpu_unplug_cb(hotplug_dev, dev, errp);
2103     } else {
2104         error_setg(errp, "acpi: device unplug for not supported device"
2105                    " type: %s", object_get_typename(OBJECT(dev)));
2106     }
2107 }
2108
2109 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
2110                                              DeviceState *dev)
2111 {
2112     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2113         object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2114         return HOTPLUG_HANDLER(machine);
2115     }
2116
2117     return NULL;
2118 }
2119
2120 static void
2121 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2122                                          const char *name, void *opaque,
2123                                          Error **errp)
2124 {
2125     MachineState *ms = MACHINE(obj);
2126     int64_t value = memory_region_size(&ms->device_memory->mr);
2127
2128     visit_type_int(v, name, &value, errp);
2129 }
2130
2131 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
2132                                             const char *name, void *opaque,
2133                                             Error **errp)
2134 {
2135     PCMachineState *pcms = PC_MACHINE(obj);
2136     uint64_t value = pcms->max_ram_below_4g;
2137
2138     visit_type_size(v, name, &value, errp);
2139 }
2140
2141 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
2142                                             const char *name, void *opaque,
2143                                             Error **errp)
2144 {
2145     PCMachineState *pcms = PC_MACHINE(obj);
2146     Error *error = NULL;
2147     uint64_t value;
2148
2149     visit_type_size(v, name, &value, &error);
2150     if (error) {
2151         error_propagate(errp, error);
2152         return;
2153     }
2154     if (value > 4 * GiB) {
2155         error_setg(&error,
2156                    "Machine option 'max-ram-below-4g=%"PRIu64
2157                    "' expects size less than or equal to 4G", value);
2158         error_propagate(errp, error);
2159         return;
2160     }
2161
2162     if (value < 1 * MiB) {
2163         warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2164                     "BIOS may not work with less than 1MiB", value);
2165     }
2166
2167     pcms->max_ram_below_4g = value;
2168 }
2169
2170 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2171                                   void *opaque, Error **errp)
2172 {
2173     PCMachineState *pcms = PC_MACHINE(obj);
2174     OnOffAuto vmport = pcms->vmport;
2175
2176     visit_type_OnOffAuto(v, name, &vmport, errp);
2177 }
2178
2179 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2180                                   void *opaque, Error **errp)
2181 {
2182     PCMachineState *pcms = PC_MACHINE(obj);
2183
2184     visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2185 }
2186
2187 bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2188 {
2189     bool smm_available = false;
2190
2191     if (pcms->smm == ON_OFF_AUTO_OFF) {
2192         return false;
2193     }
2194
2195     if (tcg_enabled() || qtest_enabled()) {
2196         smm_available = true;
2197     } else if (kvm_enabled()) {
2198         smm_available = kvm_has_smm();
2199     }
2200
2201     if (smm_available) {
2202         return true;
2203     }
2204
2205     if (pcms->smm == ON_OFF_AUTO_ON) {
2206         error_report("System Management Mode not supported by this hypervisor.");
2207         exit(1);
2208     }
2209     return false;
2210 }
2211
2212 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2213                                void *opaque, Error **errp)
2214 {
2215     PCMachineState *pcms = PC_MACHINE(obj);
2216     OnOffAuto smm = pcms->smm;
2217
2218     visit_type_OnOffAuto(v, name, &smm, errp);
2219 }
2220
2221 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2222                                void *opaque, Error **errp)
2223 {
2224     PCMachineState *pcms = PC_MACHINE(obj);
2225
2226     visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2227 }
2228
2229 static bool pc_machine_get_nvdimm(Object *obj, Error **errp)
2230 {
2231     PCMachineState *pcms = PC_MACHINE(obj);
2232
2233     return pcms->acpi_nvdimm_state.is_enabled;
2234 }
2235
2236 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp)
2237 {
2238     PCMachineState *pcms = PC_MACHINE(obj);
2239
2240     pcms->acpi_nvdimm_state.is_enabled = value;
2241 }
2242
2243 static char *pc_machine_get_nvdimm_persistence(Object *obj, Error **errp)
2244 {
2245     PCMachineState *pcms = PC_MACHINE(obj);
2246
2247     return g_strdup(pcms->acpi_nvdimm_state.persistence_string);
2248 }
2249
2250 static void pc_machine_set_nvdimm_persistence(Object *obj, const char *value,
2251                                                Error **errp)
2252 {
2253     PCMachineState *pcms = PC_MACHINE(obj);
2254     AcpiNVDIMMState *nvdimm_state = &pcms->acpi_nvdimm_state;
2255
2256     if (strcmp(value, "cpu") == 0)
2257         nvdimm_state->persistence = 3;
2258     else if (strcmp(value, "mem-ctrl") == 0)
2259         nvdimm_state->persistence = 2;
2260     else {
2261         error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
2262                    value);
2263         return;
2264     }
2265
2266     g_free(nvdimm_state->persistence_string);
2267     nvdimm_state->persistence_string = g_strdup(value);
2268 }
2269
2270 static bool pc_machine_get_smbus(Object *obj, Error **errp)
2271 {
2272     PCMachineState *pcms = PC_MACHINE(obj);
2273
2274     return pcms->smbus_enabled;
2275 }
2276
2277 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2278 {
2279     PCMachineState *pcms = PC_MACHINE(obj);
2280
2281     pcms->smbus_enabled = value;
2282 }
2283
2284 static bool pc_machine_get_sata(Object *obj, Error **errp)
2285 {
2286     PCMachineState *pcms = PC_MACHINE(obj);
2287
2288     return pcms->sata_enabled;
2289 }
2290
2291 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2292 {
2293     PCMachineState *pcms = PC_MACHINE(obj);
2294
2295     pcms->sata_enabled = value;
2296 }
2297
2298 static bool pc_machine_get_pit(Object *obj, Error **errp)
2299 {
2300     PCMachineState *pcms = PC_MACHINE(obj);
2301
2302     return pcms->pit_enabled;
2303 }
2304
2305 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2306 {
2307     PCMachineState *pcms = PC_MACHINE(obj);
2308
2309     pcms->pit_enabled = value;
2310 }
2311
2312 static void pc_machine_initfn(Object *obj)
2313 {
2314     PCMachineState *pcms = PC_MACHINE(obj);
2315
2316     pcms->max_ram_below_4g = 0; /* use default */
2317     pcms->smm = ON_OFF_AUTO_AUTO;
2318     pcms->vmport = ON_OFF_AUTO_AUTO;
2319     /* nvdimm is disabled on default. */
2320     pcms->acpi_nvdimm_state.is_enabled = false;
2321     /* acpi build is enabled by default if machine supports it */
2322     pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2323     pcms->smbus_enabled = true;
2324     pcms->sata_enabled = true;
2325     pcms->pit_enabled = true;
2326 }
2327
2328 static void pc_machine_reset(void)
2329 {
2330     CPUState *cs;
2331     X86CPU *cpu;
2332
2333     qemu_devices_reset();
2334
2335     /* Reset APIC after devices have been reset to cancel
2336      * any changes that qemu_devices_reset() might have done.
2337      */
2338     CPU_FOREACH(cs) {
2339         cpu = X86_CPU(cs);
2340
2341         if (cpu->apic_state) {
2342             device_reset(cpu->apic_state);
2343         }
2344     }
2345 }
2346
2347 static CpuInstanceProperties
2348 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2349 {
2350     MachineClass *mc = MACHINE_GET_CLASS(ms);
2351     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2352
2353     assert(cpu_index < possible_cpus->len);
2354     return possible_cpus->cpus[cpu_index].props;
2355 }
2356
2357 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2358 {
2359    X86CPUTopoInfo topo;
2360
2361    assert(idx < ms->possible_cpus->len);
2362    x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2363                             smp_cores, smp_threads, &topo);
2364    return topo.pkg_id % nb_numa_nodes;
2365 }
2366
2367 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
2368 {
2369     int i;
2370
2371     if (ms->possible_cpus) {
2372         /*
2373          * make sure that max_cpus hasn't changed since the first use, i.e.
2374          * -smp hasn't been parsed after it
2375         */
2376         assert(ms->possible_cpus->len == max_cpus);
2377         return ms->possible_cpus;
2378     }
2379
2380     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2381                                   sizeof(CPUArchId) * max_cpus);
2382     ms->possible_cpus->len = max_cpus;
2383     for (i = 0; i < ms->possible_cpus->len; i++) {
2384         X86CPUTopoInfo topo;
2385
2386         ms->possible_cpus->cpus[i].type = ms->cpu_type;
2387         ms->possible_cpus->cpus[i].vcpus_count = 1;
2388         ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
2389         x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2390                                  smp_cores, smp_threads, &topo);
2391         ms->possible_cpus->cpus[i].props.has_socket_id = true;
2392         ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2393         ms->possible_cpus->cpus[i].props.has_core_id = true;
2394         ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2395         ms->possible_cpus->cpus[i].props.has_thread_id = true;
2396         ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
2397     }
2398     return ms->possible_cpus;
2399 }
2400
2401 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2402 {
2403     /* cpu index isn't used */
2404     CPUState *cs;
2405
2406     CPU_FOREACH(cs) {
2407         X86CPU *cpu = X86_CPU(cs);
2408
2409         if (!cpu->apic_state) {
2410             cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2411         } else {
2412             apic_deliver_nmi(cpu->apic_state);
2413         }
2414     }
2415 }
2416
2417 static void pc_machine_class_init(ObjectClass *oc, void *data)
2418 {
2419     MachineClass *mc = MACHINE_CLASS(oc);
2420     PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2421     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2422     NMIClass *nc = NMI_CLASS(oc);
2423
2424     pcmc->pci_enabled = true;
2425     pcmc->has_acpi_build = true;
2426     pcmc->rsdp_in_ram = true;
2427     pcmc->smbios_defaults = true;
2428     pcmc->smbios_uuid_encoded = true;
2429     pcmc->gigabyte_align = true;
2430     pcmc->has_reserved_memory = true;
2431     pcmc->kvmclock_enabled = true;
2432     pcmc->enforce_aligned_dimm = true;
2433     /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2434      * to be used at the moment, 32K should be enough for a while.  */
2435     pcmc->acpi_data_size = 0x20000 + 0x8000;
2436     pcmc->save_tsc_khz = true;
2437     pcmc->linuxboot_dma_enabled = true;
2438     assert(!mc->get_hotplug_handler);
2439     mc->get_hotplug_handler = pc_get_hotpug_handler;
2440     mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
2441     mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
2442     mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2443     mc->auto_enable_numa_with_memhp = true;
2444     mc->has_hotpluggable_cpus = true;
2445     mc->default_boot_order = "cad";
2446     mc->hot_add_cpu = pc_hot_add_cpu;
2447     mc->block_default_type = IF_IDE;
2448     mc->max_cpus = 255;
2449     mc->reset = pc_machine_reset;
2450     hc->pre_plug = pc_machine_device_pre_plug_cb;
2451     hc->plug = pc_machine_device_plug_cb;
2452     hc->unplug_request = pc_machine_device_unplug_request_cb;
2453     hc->unplug = pc_machine_device_unplug_cb;
2454     nc->nmi_monitor_handler = x86_nmi;
2455     mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2456
2457     object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2458         pc_machine_get_device_memory_region_size, NULL,
2459         NULL, NULL, &error_abort);
2460
2461     object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2462         pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2463         NULL, NULL, &error_abort);
2464
2465     object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2466         "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2467
2468     object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2469         pc_machine_get_smm, pc_machine_set_smm,
2470         NULL, NULL, &error_abort);
2471     object_class_property_set_description(oc, PC_MACHINE_SMM,
2472         "Enable SMM (pc & q35)", &error_abort);
2473
2474     object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2475         pc_machine_get_vmport, pc_machine_set_vmport,
2476         NULL, NULL, &error_abort);
2477     object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2478         "Enable vmport (pc & q35)", &error_abort);
2479
2480     object_class_property_add_bool(oc, PC_MACHINE_NVDIMM,
2481         pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort);
2482
2483     object_class_property_add_str(oc, PC_MACHINE_NVDIMM_PERSIST,
2484         pc_machine_get_nvdimm_persistence,
2485         pc_machine_set_nvdimm_persistence, &error_abort);
2486
2487     object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2488         pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2489
2490     object_class_property_add_bool(oc, PC_MACHINE_SATA,
2491         pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2492
2493     object_class_property_add_bool(oc, PC_MACHINE_PIT,
2494         pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2495 }
2496
2497 static const TypeInfo pc_machine_info = {
2498     .name = TYPE_PC_MACHINE,
2499     .parent = TYPE_MACHINE,
2500     .abstract = true,
2501     .instance_size = sizeof(PCMachineState),
2502     .instance_init = pc_machine_initfn,
2503     .class_size = sizeof(PCMachineClass),
2504     .class_init = pc_machine_class_init,
2505     .interfaces = (InterfaceInfo[]) {
2506          { TYPE_HOTPLUG_HANDLER },
2507          { TYPE_NMI },
2508          { }
2509     },
2510 };
2511
2512 static void pc_machine_register_types(void)
2513 {
2514     type_register_static(&pc_machine_info);
2515 }
2516
2517 type_init(pc_machine_register_types)