2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "sysemu/cpus.h"
34 #include "hw/block/fdc.h"
36 #include "hw/pci/pci.h"
37 #include "hw/pci/pci_bus.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/timer/hpet.h"
40 #include "hw/firmware/smbios.h"
41 #include "hw/loader.h"
43 #include "multiboot.h"
44 #include "hw/timer/mc146818rtc.h"
45 #include "hw/dma/i8257.h"
46 #include "hw/timer/i8254.h"
47 #include "hw/input/i8042.h"
48 #include "hw/audio/pcspk.h"
49 #include "hw/pci/msi.h"
50 #include "hw/sysbus.h"
51 #include "sysemu/sysemu.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/kvm.h"
54 #include "sysemu/qtest.h"
56 #include "hw/xen/xen.h"
57 #include "ui/qemu-spice.h"
58 #include "exec/memory.h"
59 #include "exec/address-spaces.h"
60 #include "sysemu/arch_init.h"
61 #include "qemu/bitmap.h"
62 #include "qemu/config-file.h"
63 #include "qemu/error-report.h"
64 #include "qemu/option.h"
65 #include "hw/acpi/acpi.h"
66 #include "hw/acpi/cpu_hotplug.h"
67 #include "hw/boards.h"
68 #include "acpi-build.h"
69 #include "hw/mem/pc-dimm.h"
70 #include "qapi/error.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "qapi/visitor.h"
75 #include "hw/i386/intel_iommu.h"
76 #include "hw/net/ne2000-isa.h"
78 /* debug PC/ISA interrupts */
82 #define DPRINTF(fmt, ...) \
83 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
85 #define DPRINTF(fmt, ...)
88 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
89 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
90 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
91 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
92 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
94 #define E820_NR_ENTRIES 16
100 } QEMU_PACKED
__attribute((__aligned__(4)));
104 struct e820_entry entry
[E820_NR_ENTRIES
];
105 } QEMU_PACKED
__attribute((__aligned__(4)));
107 static struct e820_table e820_reserve
;
108 static struct e820_entry
*e820_table
;
109 static unsigned e820_entries
;
110 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
112 GlobalProperty pc_compat_3_1
[] = {
114 .driver
= "intel-iommu",
115 .property
= "dma-drain",
119 const size_t pc_compat_3_1_len
= G_N_ELEMENTS(pc_compat_3_1
);
121 GlobalProperty pc_compat_3_0
[] = {
123 .driver
= TYPE_X86_CPU
,
124 .property
= "x-hv-synic-kvm-only",
127 .driver
= "Skylake-Server" "-" TYPE_X86_CPU
,
131 .driver
= "Skylake-Server-IBRS" "-" TYPE_X86_CPU
,
136 const size_t pc_compat_3_0_len
= G_N_ELEMENTS(pc_compat_3_0
);
138 GlobalProperty pc_compat_2_12
[] = {
140 .driver
= TYPE_X86_CPU
,
141 .property
= "legacy-cache",
144 .driver
= TYPE_X86_CPU
,
145 .property
= "topoext",
148 .driver
= "EPYC-" TYPE_X86_CPU
,
149 .property
= "xlevel",
150 .value
= stringify(0x8000000a),
152 .driver
= "EPYC-IBPB-" TYPE_X86_CPU
,
153 .property
= "xlevel",
154 .value
= stringify(0x8000000a),
157 const size_t pc_compat_2_12_len
= G_N_ELEMENTS(pc_compat_2_12
);
159 GlobalProperty pc_compat_2_11
[] = {
161 .driver
= TYPE_X86_CPU
,
162 .property
= "x-migrate-smi-count",
165 .driver
= "Skylake-Server" "-" TYPE_X86_CPU
,
166 .property
= "clflushopt",
170 const size_t pc_compat_2_11_len
= G_N_ELEMENTS(pc_compat_2_11
);
172 GlobalProperty pc_compat_2_10
[] = {
174 .driver
= TYPE_X86_CPU
,
175 .property
= "x-hv-max-vps",
178 .driver
= "i440FX-pcihost",
179 .property
= "x-pci-hole64-fix",
182 .driver
= "q35-pcihost",
183 .property
= "x-pci-hole64-fix",
187 const size_t pc_compat_2_10_len
= G_N_ELEMENTS(pc_compat_2_10
);
189 void gsi_handler(void *opaque
, int n
, int level
)
191 GSIState
*s
= opaque
;
193 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
194 if (n
< ISA_NUM_IRQS
) {
195 qemu_set_irq(s
->i8259_irq
[n
], level
);
197 qemu_set_irq(s
->ioapic_irq
[n
], level
);
200 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
205 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
207 return 0xffffffffffffffffULL
;
210 /* MSDOS compatibility mode FPU exception support */
211 static qemu_irq ferr_irq
;
213 void pc_register_ferr_irq(qemu_irq irq
)
218 /* XXX: add IGNNE support */
219 void cpu_set_ferr(CPUX86State
*s
)
221 qemu_irq_raise(ferr_irq
);
224 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
227 qemu_irq_lower(ferr_irq
);
230 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
232 return 0xffffffffffffffffULL
;
236 uint64_t cpu_get_tsc(CPUX86State
*env
)
238 return cpu_get_ticks();
242 int cpu_get_pic_interrupt(CPUX86State
*env
)
244 X86CPU
*cpu
= x86_env_get_cpu(env
);
247 if (!kvm_irqchip_in_kernel()) {
248 intno
= apic_get_interrupt(cpu
->apic_state
);
252 /* read the irq from the PIC */
253 if (!apic_accept_pic_intr(cpu
->apic_state
)) {
258 intno
= pic_read_irq(isa_pic
);
262 static void pic_irq_request(void *opaque
, int irq
, int level
)
264 CPUState
*cs
= first_cpu
;
265 X86CPU
*cpu
= X86_CPU(cs
);
267 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
268 if (cpu
->apic_state
&& !kvm_irqchip_in_kernel()) {
271 if (apic_accept_pic_intr(cpu
->apic_state
)) {
272 apic_deliver_pic_intr(cpu
->apic_state
, level
);
277 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
279 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
284 /* PC cmos mappings */
286 #define REG_EQUIPMENT_BYTE 0x14
288 int cmos_get_fd_drive_type(FloppyDriveType fd0
)
293 case FLOPPY_DRIVE_TYPE_144
:
294 /* 1.44 Mb 3"5 drive */
297 case FLOPPY_DRIVE_TYPE_288
:
298 /* 2.88 Mb 3"5 drive */
301 case FLOPPY_DRIVE_TYPE_120
:
302 /* 1.2 Mb 5"5 drive */
305 case FLOPPY_DRIVE_TYPE_NONE
:
313 static void cmos_init_hd(ISADevice
*s
, int type_ofs
, int info_ofs
,
314 int16_t cylinders
, int8_t heads
, int8_t sectors
)
316 rtc_set_memory(s
, type_ofs
, 47);
317 rtc_set_memory(s
, info_ofs
, cylinders
);
318 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
319 rtc_set_memory(s
, info_ofs
+ 2, heads
);
320 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
321 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
322 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
323 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
324 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
325 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
328 /* convert boot_device letter to something recognizable by the bios */
329 static int boot_device2nibble(char boot_device
)
331 switch(boot_device
) {
334 return 0x01; /* floppy boot */
336 return 0x02; /* hard drive boot */
338 return 0x03; /* CD-ROM boot */
340 return 0x04; /* Network boot */
345 static void set_boot_dev(ISADevice
*s
, const char *boot_device
, Error
**errp
)
347 #define PC_MAX_BOOT_DEVICES 3
348 int nbds
, bds
[3] = { 0, };
351 nbds
= strlen(boot_device
);
352 if (nbds
> PC_MAX_BOOT_DEVICES
) {
353 error_setg(errp
, "Too many boot devices for PC");
356 for (i
= 0; i
< nbds
; i
++) {
357 bds
[i
] = boot_device2nibble(boot_device
[i
]);
359 error_setg(errp
, "Invalid boot device for PC: '%c'",
364 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
365 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
368 static void pc_boot_set(void *opaque
, const char *boot_device
, Error
**errp
)
370 set_boot_dev(opaque
, boot_device
, errp
);
373 static void pc_cmos_init_floppy(ISADevice
*rtc_state
, ISADevice
*floppy
)
376 FloppyDriveType fd_type
[2] = { FLOPPY_DRIVE_TYPE_NONE
,
377 FLOPPY_DRIVE_TYPE_NONE
};
381 for (i
= 0; i
< 2; i
++) {
382 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
385 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
386 cmos_get_fd_drive_type(fd_type
[1]);
387 rtc_set_memory(rtc_state
, 0x10, val
);
389 val
= rtc_get_memory(rtc_state
, REG_EQUIPMENT_BYTE
);
391 if (fd_type
[0] != FLOPPY_DRIVE_TYPE_NONE
) {
394 if (fd_type
[1] != FLOPPY_DRIVE_TYPE_NONE
) {
401 val
|= 0x01; /* 1 drive, ready for boot */
404 val
|= 0x41; /* 2 drives, ready for boot */
407 rtc_set_memory(rtc_state
, REG_EQUIPMENT_BYTE
, val
);
410 typedef struct pc_cmos_init_late_arg
{
411 ISADevice
*rtc_state
;
413 } pc_cmos_init_late_arg
;
415 typedef struct check_fdc_state
{
420 static int check_fdc(Object
*obj
, void *opaque
)
422 CheckFdcState
*state
= opaque
;
425 Error
*local_err
= NULL
;
427 fdc
= object_dynamic_cast(obj
, TYPE_ISA_FDC
);
432 iobase
= object_property_get_uint(obj
, "iobase", &local_err
);
433 if (local_err
|| iobase
!= 0x3f0) {
434 error_free(local_err
);
439 state
->multiple
= true;
441 state
->floppy
= ISA_DEVICE(obj
);
446 static const char * const fdc_container_path
[] = {
447 "/unattached", "/peripheral", "/peripheral-anon"
451 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
454 ISADevice
*pc_find_fdc0(void)
458 CheckFdcState state
= { 0 };
460 for (i
= 0; i
< ARRAY_SIZE(fdc_container_path
); i
++) {
461 container
= container_get(qdev_get_machine(), fdc_container_path
[i
]);
462 object_child_foreach(container
, check_fdc
, &state
);
465 if (state
.multiple
) {
466 warn_report("multiple floppy disk controllers with "
467 "iobase=0x3f0 have been found");
468 error_printf("the one being picked for CMOS setup might not reflect "
475 static void pc_cmos_init_late(void *opaque
)
477 pc_cmos_init_late_arg
*arg
= opaque
;
478 ISADevice
*s
= arg
->rtc_state
;
480 int8_t heads
, sectors
;
485 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 0,
486 &cylinders
, &heads
, §ors
) >= 0) {
487 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
490 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 1,
491 &cylinders
, &heads
, §ors
) >= 0) {
492 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
495 rtc_set_memory(s
, 0x12, val
);
498 for (i
= 0; i
< 4; i
++) {
499 /* NOTE: ide_get_geometry() returns the physical
500 geometry. It is always such that: 1 <= sects <= 63, 1
501 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
502 geometry can be different if a translation is done. */
503 if (arg
->idebus
[i
/ 2] &&
504 ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
505 &cylinders
, &heads
, §ors
) >= 0) {
506 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
507 assert((trans
& ~3) == 0);
508 val
|= trans
<< (i
* 2);
511 rtc_set_memory(s
, 0x39, val
);
513 pc_cmos_init_floppy(s
, pc_find_fdc0());
515 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
518 void pc_cmos_init(PCMachineState
*pcms
,
519 BusState
*idebus0
, BusState
*idebus1
,
523 static pc_cmos_init_late_arg arg
;
525 /* various important CMOS locations needed by PC/Bochs bios */
528 /* base memory (first MiB) */
529 val
= MIN(pcms
->below_4g_mem_size
/ KiB
, 640);
530 rtc_set_memory(s
, 0x15, val
);
531 rtc_set_memory(s
, 0x16, val
>> 8);
532 /* extended memory (next 64MiB) */
533 if (pcms
->below_4g_mem_size
> 1 * MiB
) {
534 val
= (pcms
->below_4g_mem_size
- 1 * MiB
) / KiB
;
540 rtc_set_memory(s
, 0x17, val
);
541 rtc_set_memory(s
, 0x18, val
>> 8);
542 rtc_set_memory(s
, 0x30, val
);
543 rtc_set_memory(s
, 0x31, val
>> 8);
544 /* memory between 16MiB and 4GiB */
545 if (pcms
->below_4g_mem_size
> 16 * MiB
) {
546 val
= (pcms
->below_4g_mem_size
- 16 * MiB
) / (64 * KiB
);
552 rtc_set_memory(s
, 0x34, val
);
553 rtc_set_memory(s
, 0x35, val
>> 8);
554 /* memory above 4GiB */
555 val
= pcms
->above_4g_mem_size
/ 65536;
556 rtc_set_memory(s
, 0x5b, val
);
557 rtc_set_memory(s
, 0x5c, val
>> 8);
558 rtc_set_memory(s
, 0x5d, val
>> 16);
560 object_property_add_link(OBJECT(pcms
), "rtc_state",
562 (Object
**)&pcms
->rtc
,
563 object_property_allow_set_link
,
564 OBJ_PROP_LINK_STRONG
, &error_abort
);
565 object_property_set_link(OBJECT(pcms
), OBJECT(s
),
566 "rtc_state", &error_abort
);
568 set_boot_dev(s
, MACHINE(pcms
)->boot_order
, &error_fatal
);
571 val
|= 0x02; /* FPU is there */
572 val
|= 0x04; /* PS/2 mouse installed */
573 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
575 /* hard drives and FDC */
577 arg
.idebus
[0] = idebus0
;
578 arg
.idebus
[1] = idebus1
;
579 qemu_register_reset(pc_cmos_init_late
, &arg
);
582 #define TYPE_PORT92 "port92"
583 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
585 /* port 92 stuff: could be split off */
586 typedef struct Port92State
{
587 ISADevice parent_obj
;
594 static void port92_write(void *opaque
, hwaddr addr
, uint64_t val
,
597 Port92State
*s
= opaque
;
598 int oldval
= s
->outport
;
600 DPRINTF("port92: write 0x%02" PRIx64
"\n", val
);
602 qemu_set_irq(s
->a20_out
, (val
>> 1) & 1);
603 if ((val
& 1) && !(oldval
& 1)) {
604 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
608 static uint64_t port92_read(void *opaque
, hwaddr addr
,
611 Port92State
*s
= opaque
;
615 DPRINTF("port92: read 0x%02x\n", ret
);
619 static void port92_init(ISADevice
*dev
, qemu_irq a20_out
)
621 qdev_connect_gpio_out_named(DEVICE(dev
), PORT92_A20_LINE
, 0, a20_out
);
624 static const VMStateDescription vmstate_port92_isa
= {
627 .minimum_version_id
= 1,
628 .fields
= (VMStateField
[]) {
629 VMSTATE_UINT8(outport
, Port92State
),
630 VMSTATE_END_OF_LIST()
634 static void port92_reset(DeviceState
*d
)
636 Port92State
*s
= PORT92(d
);
641 static const MemoryRegionOps port92_ops
= {
643 .write
= port92_write
,
645 .min_access_size
= 1,
646 .max_access_size
= 1,
648 .endianness
= DEVICE_LITTLE_ENDIAN
,
651 static void port92_initfn(Object
*obj
)
653 Port92State
*s
= PORT92(obj
);
655 memory_region_init_io(&s
->io
, OBJECT(s
), &port92_ops
, s
, "port92", 1);
659 qdev_init_gpio_out_named(DEVICE(obj
), &s
->a20_out
, PORT92_A20_LINE
, 1);
662 static void port92_realizefn(DeviceState
*dev
, Error
**errp
)
664 ISADevice
*isadev
= ISA_DEVICE(dev
);
665 Port92State
*s
= PORT92(dev
);
667 isa_register_ioport(isadev
, &s
->io
, 0x92);
670 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
672 DeviceClass
*dc
= DEVICE_CLASS(klass
);
674 dc
->realize
= port92_realizefn
;
675 dc
->reset
= port92_reset
;
676 dc
->vmsd
= &vmstate_port92_isa
;
678 * Reason: unlike ordinary ISA devices, this one needs additional
679 * wiring: its A20 output line needs to be wired up by
682 dc
->user_creatable
= false;
685 static const TypeInfo port92_info
= {
687 .parent
= TYPE_ISA_DEVICE
,
688 .instance_size
= sizeof(Port92State
),
689 .instance_init
= port92_initfn
,
690 .class_init
= port92_class_initfn
,
693 static void port92_register_types(void)
695 type_register_static(&port92_info
);
698 type_init(port92_register_types
)
700 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
702 X86CPU
*cpu
= opaque
;
704 /* XXX: send to all CPUs ? */
705 /* XXX: add logic to handle multiple A20 line sources */
706 x86_cpu_set_a20(cpu
, level
);
709 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
711 int index
= le32_to_cpu(e820_reserve
.count
);
712 struct e820_entry
*entry
;
714 if (type
!= E820_RAM
) {
715 /* old FW_CFG_E820_TABLE entry -- reservations only */
716 if (index
>= E820_NR_ENTRIES
) {
719 entry
= &e820_reserve
.entry
[index
++];
721 entry
->address
= cpu_to_le64(address
);
722 entry
->length
= cpu_to_le64(length
);
723 entry
->type
= cpu_to_le32(type
);
725 e820_reserve
.count
= cpu_to_le32(index
);
728 /* new "etc/e820" file -- include ram too */
729 e820_table
= g_renew(struct e820_entry
, e820_table
, e820_entries
+ 1);
730 e820_table
[e820_entries
].address
= cpu_to_le64(address
);
731 e820_table
[e820_entries
].length
= cpu_to_le64(length
);
732 e820_table
[e820_entries
].type
= cpu_to_le32(type
);
738 int e820_get_num_entries(void)
743 bool e820_get_entry(int idx
, uint32_t type
, uint64_t *address
, uint64_t *length
)
745 if (idx
< e820_entries
&& e820_table
[idx
].type
== cpu_to_le32(type
)) {
746 *address
= le64_to_cpu(e820_table
[idx
].address
);
747 *length
= le64_to_cpu(e820_table
[idx
].length
);
753 /* Enables contiguous-apic-ID mode, for compatibility */
754 static bool compat_apic_id_mode
;
756 void enable_compat_apic_id_mode(void)
758 compat_apic_id_mode
= true;
761 /* Calculates initial APIC ID for a specific CPU index
763 * Currently we need to be able to calculate the APIC ID from the CPU index
764 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
765 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
766 * all CPUs up to max_cpus.
768 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index
)
773 correct_id
= x86_apicid_from_cpu_idx(smp_cores
, smp_threads
, cpu_index
);
774 if (compat_apic_id_mode
) {
775 if (cpu_index
!= correct_id
&& !warned
&& !qtest_enabled()) {
776 error_report("APIC IDs set in compatibility mode, "
777 "CPU topology won't match the configuration");
786 static void pc_build_smbios(PCMachineState
*pcms
)
788 uint8_t *smbios_tables
, *smbios_anchor
;
789 size_t smbios_tables_len
, smbios_anchor_len
;
790 struct smbios_phys_mem_area
*mem_array
;
791 unsigned i
, array_count
;
792 MachineState
*ms
= MACHINE(pcms
);
793 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
795 /* tell smbios about cpuid version and features */
796 smbios_set_cpuid(cpu
->env
.cpuid_version
, cpu
->env
.features
[FEAT_1_EDX
]);
798 smbios_tables
= smbios_get_table_legacy(&smbios_tables_len
);
800 fw_cfg_add_bytes(pcms
->fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
801 smbios_tables
, smbios_tables_len
);
804 /* build the array of physical mem area from e820 table */
805 mem_array
= g_malloc0(sizeof(*mem_array
) * e820_get_num_entries());
806 for (i
= 0, array_count
= 0; i
< e820_get_num_entries(); i
++) {
809 if (e820_get_entry(i
, E820_RAM
, &addr
, &len
)) {
810 mem_array
[array_count
].address
= addr
;
811 mem_array
[array_count
].length
= len
;
815 smbios_get_tables(mem_array
, array_count
,
816 &smbios_tables
, &smbios_tables_len
,
817 &smbios_anchor
, &smbios_anchor_len
);
821 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-tables",
822 smbios_tables
, smbios_tables_len
);
823 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-anchor",
824 smbios_anchor
, smbios_anchor_len
);
828 static FWCfgState
*bochs_bios_init(AddressSpace
*as
, PCMachineState
*pcms
)
831 uint64_t *numa_fw_cfg
;
833 const CPUArchIdList
*cpus
;
834 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
836 fw_cfg
= fw_cfg_init_io_dma(FW_CFG_IO_BASE
, FW_CFG_IO_BASE
+ 4, as
);
837 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
839 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
841 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
842 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
843 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
844 * for CPU hotplug also uses APIC ID and not "CPU index".
845 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
846 * but the "limit to the APIC ID values SeaBIOS may see".
848 * So for compatibility reasons with old BIOSes we are stuck with
849 * "etc/max-cpus" actually being apic_id_limit
851 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)pcms
->apic_id_limit
);
852 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
853 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
,
854 acpi_tables
, acpi_tables_len
);
855 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
857 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
,
858 &e820_reserve
, sizeof(e820_reserve
));
859 fw_cfg_add_file(fw_cfg
, "etc/e820", e820_table
,
860 sizeof(struct e820_entry
) * e820_entries
);
862 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, &hpet_cfg
, sizeof(hpet_cfg
));
863 /* allocate memory for the NUMA channel: one (64bit) word for the number
864 * of nodes, one word for each VCPU->node and one word for each node to
865 * hold the amount of memory.
867 numa_fw_cfg
= g_new0(uint64_t, 1 + pcms
->apic_id_limit
+ nb_numa_nodes
);
868 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
869 cpus
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
870 for (i
= 0; i
< cpus
->len
; i
++) {
871 unsigned int apic_id
= cpus
->cpus
[i
].arch_id
;
872 assert(apic_id
< pcms
->apic_id_limit
);
873 numa_fw_cfg
[apic_id
+ 1] = cpu_to_le64(cpus
->cpus
[i
].props
.node_id
);
875 for (i
= 0; i
< nb_numa_nodes
; i
++) {
876 numa_fw_cfg
[pcms
->apic_id_limit
+ 1 + i
] =
877 cpu_to_le64(numa_info
[i
].node_mem
);
879 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, numa_fw_cfg
,
880 (1 + pcms
->apic_id_limit
+ nb_numa_nodes
) *
881 sizeof(*numa_fw_cfg
));
886 static long get_file_size(FILE *f
)
890 /* XXX: on Unix systems, using fstat() probably makes more sense */
893 fseek(f
, 0, SEEK_END
);
895 fseek(f
, where
, SEEK_SET
);
900 /* setup_data types */
902 #define SETUP_E820_EXT 1
912 } __attribute__((packed
));
914 static void load_linux(PCMachineState
*pcms
,
918 int setup_size
, kernel_size
, cmdline_size
;
919 int dtb_size
, setup_data_offset
;
921 uint8_t header
[8192], *setup
, *kernel
;
922 hwaddr real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
925 MachineState
*machine
= MACHINE(pcms
);
926 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
927 struct setup_data
*setup_data
;
928 const char *kernel_filename
= machine
->kernel_filename
;
929 const char *initrd_filename
= machine
->initrd_filename
;
930 const char *dtb_filename
= machine
->dtb
;
931 const char *kernel_cmdline
= machine
->kernel_cmdline
;
933 /* Align to 16 bytes as a paranoia measure */
934 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
936 /* load the kernel header */
937 f
= fopen(kernel_filename
, "rb");
938 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
939 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
940 MIN(ARRAY_SIZE(header
), kernel_size
)) {
941 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
942 kernel_filename
, strerror(errno
));
946 /* kernel protocol version */
948 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
950 if (ldl_p(header
+0x202) == 0x53726448) {
951 protocol
= lduw_p(header
+0x206);
953 /* This looks like a multiboot kernel. If it is, let's stop
954 treating it like a Linux kernel. */
955 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
956 kernel_cmdline
, kernel_size
, header
)) {
962 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
965 cmdline_addr
= 0x9a000 - cmdline_size
;
967 } else if (protocol
< 0x202) {
968 /* High but ancient kernel */
970 cmdline_addr
= 0x9a000 - cmdline_size
;
971 prot_addr
= 0x100000;
973 /* High and recent kernel */
975 cmdline_addr
= 0x20000;
976 prot_addr
= 0x100000;
981 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
982 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
983 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
989 /* highest address for loading the initrd */
990 if (protocol
>= 0x203) {
991 initrd_max
= ldl_p(header
+0x22c);
993 initrd_max
= 0x37ffffff;
996 if (initrd_max
>= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
) {
997 initrd_max
= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
- 1;
1000 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
1001 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
1002 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
1004 if (protocol
>= 0x202) {
1005 stl_p(header
+0x228, cmdline_addr
);
1007 stw_p(header
+0x20, 0xA33F);
1008 stw_p(header
+0x22, cmdline_addr
-real_addr
);
1011 /* handle vga= parameter */
1012 vmode
= strstr(kernel_cmdline
, "vga=");
1014 unsigned int video_mode
;
1017 if (!strncmp(vmode
, "normal", 6)) {
1018 video_mode
= 0xffff;
1019 } else if (!strncmp(vmode
, "ext", 3)) {
1020 video_mode
= 0xfffe;
1021 } else if (!strncmp(vmode
, "ask", 3)) {
1022 video_mode
= 0xfffd;
1024 video_mode
= strtol(vmode
, NULL
, 0);
1026 stw_p(header
+0x1fa, video_mode
);
1030 /* High nybble = B reserved for QEMU; low nybble is revision number.
1031 If this code is substantially changed, you may want to consider
1032 incrementing the revision. */
1033 if (protocol
>= 0x200) {
1034 header
[0x210] = 0xB0;
1037 if (protocol
>= 0x201) {
1038 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
1039 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
1043 if (initrd_filename
) {
1046 GError
*gerr
= NULL
;
1048 if (protocol
< 0x200) {
1049 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
1053 if (!g_file_get_contents(initrd_filename
, &initrd_data
,
1054 &initrd_size
, &gerr
)) {
1055 fprintf(stderr
, "qemu: error reading initrd %s: %s\n",
1056 initrd_filename
, gerr
->message
);
1059 if (initrd_size
>= initrd_max
) {
1060 fprintf(stderr
, "qemu: initrd is too large, cannot support."
1061 "(max: %"PRIu32
", need %"PRId64
")\n",
1062 initrd_max
, (uint64_t)initrd_size
);
1066 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
1068 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
1069 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
1070 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
1072 stl_p(header
+0x218, initrd_addr
);
1073 stl_p(header
+0x21c, initrd_size
);
1076 /* load kernel and setup */
1077 setup_size
= header
[0x1f1];
1078 if (setup_size
== 0) {
1081 setup_size
= (setup_size
+1)*512;
1082 if (setup_size
> kernel_size
) {
1083 fprintf(stderr
, "qemu: invalid kernel header\n");
1086 kernel_size
-= setup_size
;
1088 setup
= g_malloc(setup_size
);
1089 kernel
= g_malloc(kernel_size
);
1090 fseek(f
, 0, SEEK_SET
);
1091 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
1092 fprintf(stderr
, "fread() failed\n");
1095 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
1096 fprintf(stderr
, "fread() failed\n");
1101 /* append dtb to kernel */
1103 if (protocol
< 0x209) {
1104 fprintf(stderr
, "qemu: Linux kernel too old to load a dtb\n");
1108 dtb_size
= get_image_size(dtb_filename
);
1109 if (dtb_size
<= 0) {
1110 fprintf(stderr
, "qemu: error reading dtb %s: %s\n",
1111 dtb_filename
, strerror(errno
));
1115 setup_data_offset
= QEMU_ALIGN_UP(kernel_size
, 16);
1116 kernel_size
= setup_data_offset
+ sizeof(struct setup_data
) + dtb_size
;
1117 kernel
= g_realloc(kernel
, kernel_size
);
1119 stq_p(header
+0x250, prot_addr
+ setup_data_offset
);
1121 setup_data
= (struct setup_data
*)(kernel
+ setup_data_offset
);
1122 setup_data
->next
= 0;
1123 setup_data
->type
= cpu_to_le32(SETUP_DTB
);
1124 setup_data
->len
= cpu_to_le32(dtb_size
);
1126 load_image_size(dtb_filename
, setup_data
->data
, dtb_size
);
1129 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
1131 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
1132 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1133 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
1135 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
1136 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
1137 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
1139 option_rom
[nb_option_roms
].bootindex
= 0;
1140 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
1141 if (pcmc
->linuxboot_dma_enabled
&& fw_cfg_dma_enabled(fw_cfg
)) {
1142 option_rom
[nb_option_roms
].name
= "linuxboot_dma.bin";
1147 #define NE2000_NB_MAX 6
1149 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
1151 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
1153 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
1155 static int nb_ne2k
= 0;
1157 if (nb_ne2k
== NE2000_NB_MAX
)
1159 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
1160 ne2000_irq
[nb_ne2k
], nd
);
1164 DeviceState
*cpu_get_current_apic(void)
1167 X86CPU
*cpu
= X86_CPU(current_cpu
);
1168 return cpu
->apic_state
;
1174 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
1176 X86CPU
*cpu
= opaque
;
1179 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
1183 static void pc_new_cpu(const char *typename
, int64_t apic_id
, Error
**errp
)
1186 Error
*local_err
= NULL
;
1188 cpu
= object_new(typename
);
1190 object_property_set_uint(cpu
, apic_id
, "apic-id", &local_err
);
1191 object_property_set_bool(cpu
, true, "realized", &local_err
);
1194 error_propagate(errp
, local_err
);
1197 void pc_hot_add_cpu(const int64_t id
, Error
**errp
)
1199 MachineState
*ms
= MACHINE(qdev_get_machine());
1200 int64_t apic_id
= x86_cpu_apic_id_from_index(id
);
1201 Error
*local_err
= NULL
;
1204 error_setg(errp
, "Invalid CPU id: %" PRIi64
, id
);
1208 if (apic_id
>= ACPI_CPU_HOTPLUG_ID_LIMIT
) {
1209 error_setg(errp
, "Unable to add CPU: %" PRIi64
1210 ", resulting APIC ID (%" PRIi64
") is too large",
1215 pc_new_cpu(ms
->cpu_type
, apic_id
, &local_err
);
1217 error_propagate(errp
, local_err
);
1222 void pc_cpus_init(PCMachineState
*pcms
)
1225 const CPUArchIdList
*possible_cpus
;
1226 MachineState
*ms
= MACHINE(pcms
);
1227 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
1229 /* Calculates the limit to CPU APIC ID values
1231 * Limit for the APIC ID value, so that all
1232 * CPU APIC IDs are < pcms->apic_id_limit.
1234 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1236 pcms
->apic_id_limit
= x86_cpu_apic_id_from_index(max_cpus
- 1) + 1;
1237 possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
1238 for (i
= 0; i
< smp_cpus
; i
++) {
1239 pc_new_cpu(possible_cpus
->cpus
[i
].type
, possible_cpus
->cpus
[i
].arch_id
,
1244 static void pc_build_feature_control_file(PCMachineState
*pcms
)
1246 MachineState
*ms
= MACHINE(pcms
);
1247 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
1248 CPUX86State
*env
= &cpu
->env
;
1249 uint32_t unused
, ecx
, edx
;
1250 uint64_t feature_control_bits
= 0;
1253 cpu_x86_cpuid(env
, 1, 0, &unused
, &unused
, &ecx
, &edx
);
1254 if (ecx
& CPUID_EXT_VMX
) {
1255 feature_control_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
1258 if ((edx
& (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
)) ==
1259 (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
) &&
1260 (env
->mcg_cap
& MCG_LMCE_P
)) {
1261 feature_control_bits
|= FEATURE_CONTROL_LMCE
;
1264 if (!feature_control_bits
) {
1268 val
= g_malloc(sizeof(*val
));
1269 *val
= cpu_to_le64(feature_control_bits
| FEATURE_CONTROL_LOCKED
);
1270 fw_cfg_add_file(pcms
->fw_cfg
, "etc/msr_feature_control", val
, sizeof(*val
));
1273 static void rtc_set_cpus_count(ISADevice
*rtc
, uint16_t cpus_count
)
1275 if (cpus_count
> 0xff) {
1276 /* If the number of CPUs can't be represented in 8 bits, the
1277 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1278 * to make old BIOSes fail more predictably.
1280 rtc_set_memory(rtc
, 0x5f, 0);
1282 rtc_set_memory(rtc
, 0x5f, cpus_count
- 1);
1287 void pc_machine_done(Notifier
*notifier
, void *data
)
1289 PCMachineState
*pcms
= container_of(notifier
,
1290 PCMachineState
, machine_done
);
1291 PCIBus
*bus
= pcms
->bus
;
1293 /* set the number of CPUs */
1294 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1297 int extra_hosts
= 0;
1299 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1300 /* look for expander root buses */
1301 if (pci_bus_is_root(bus
)) {
1305 if (extra_hosts
&& pcms
->fw_cfg
) {
1306 uint64_t *val
= g_malloc(sizeof(*val
));
1307 *val
= cpu_to_le64(extra_hosts
);
1308 fw_cfg_add_file(pcms
->fw_cfg
,
1309 "etc/extra-pci-roots", val
, sizeof(*val
));
1315 pc_build_smbios(pcms
);
1316 pc_build_feature_control_file(pcms
);
1317 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1318 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1321 if (pcms
->apic_id_limit
> 255 && !xen_enabled()) {
1322 IntelIOMMUState
*iommu
= INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1324 if (!iommu
|| !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu
)) ||
1325 iommu
->intr_eim
!= ON_OFF_AUTO_ON
) {
1326 error_report("current -smp configuration requires "
1327 "Extended Interrupt Mode enabled. "
1328 "You can add an IOMMU using: "
1329 "-device intel-iommu,intremap=on,eim=on");
1335 void pc_guest_info_init(PCMachineState
*pcms
)
1339 pcms
->apic_xrupt_override
= kvm_allows_irq0_override();
1340 pcms
->numa_nodes
= nb_numa_nodes
;
1341 pcms
->node_mem
= g_malloc0(pcms
->numa_nodes
*
1342 sizeof *pcms
->node_mem
);
1343 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1344 pcms
->node_mem
[i
] = numa_info
[i
].node_mem
;
1347 pcms
->machine_done
.notify
= pc_machine_done
;
1348 qemu_add_machine_init_done_notifier(&pcms
->machine_done
);
1351 /* setup pci memory address space mapping into system address space */
1352 void pc_pci_as_mapping_init(Object
*owner
, MemoryRegion
*system_memory
,
1353 MemoryRegion
*pci_address_space
)
1355 /* Set to lower priority than RAM */
1356 memory_region_add_subregion_overlap(system_memory
, 0x0,
1357 pci_address_space
, -1);
1360 void pc_acpi_init(const char *default_dsdt
)
1364 if (acpi_tables
!= NULL
) {
1365 /* manually set via -acpitable, leave it alone */
1369 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, default_dsdt
);
1370 if (filename
== NULL
) {
1371 warn_report("failed to find %s", default_dsdt
);
1373 QemuOpts
*opts
= qemu_opts_create(qemu_find_opts("acpi"), NULL
, 0,
1377 qemu_opt_set(opts
, "file", filename
, &error_abort
);
1379 acpi_table_add_builtin(opts
, &err
);
1381 warn_reportf_err(err
, "failed to load %s: ", filename
);
1387 void xen_load_linux(PCMachineState
*pcms
)
1392 assert(MACHINE(pcms
)->kernel_filename
!= NULL
);
1394 fw_cfg
= fw_cfg_init_io(FW_CFG_IO_BASE
);
1395 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1398 load_linux(pcms
, fw_cfg
);
1399 for (i
= 0; i
< nb_option_roms
; i
++) {
1400 assert(!strcmp(option_rom
[i
].name
, "linuxboot.bin") ||
1401 !strcmp(option_rom
[i
].name
, "linuxboot_dma.bin") ||
1402 !strcmp(option_rom
[i
].name
, "multiboot.bin"));
1403 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1405 pcms
->fw_cfg
= fw_cfg
;
1408 void pc_memory_init(PCMachineState
*pcms
,
1409 MemoryRegion
*system_memory
,
1410 MemoryRegion
*rom_memory
,
1411 MemoryRegion
**ram_memory
)
1414 MemoryRegion
*ram
, *option_rom_mr
;
1415 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
1417 MachineState
*machine
= MACHINE(pcms
);
1418 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1420 assert(machine
->ram_size
== pcms
->below_4g_mem_size
+
1421 pcms
->above_4g_mem_size
);
1423 linux_boot
= (machine
->kernel_filename
!= NULL
);
1425 /* Allocate RAM. We allocate it as a single memory region and use
1426 * aliases to address portions of it, mostly for backwards compatibility
1427 * with older qemus that used qemu_ram_alloc().
1429 ram
= g_malloc(sizeof(*ram
));
1430 memory_region_allocate_system_memory(ram
, NULL
, "pc.ram",
1433 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
1434 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", ram
,
1435 0, pcms
->below_4g_mem_size
);
1436 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
1437 e820_add_entry(0, pcms
->below_4g_mem_size
, E820_RAM
);
1438 if (pcms
->above_4g_mem_size
> 0) {
1439 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
1440 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g", ram
,
1441 pcms
->below_4g_mem_size
,
1442 pcms
->above_4g_mem_size
);
1443 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
1445 e820_add_entry(0x100000000ULL
, pcms
->above_4g_mem_size
, E820_RAM
);
1448 if (!pcmc
->has_reserved_memory
&&
1449 (machine
->ram_slots
||
1450 (machine
->maxram_size
> machine
->ram_size
))) {
1451 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1453 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1458 /* always allocate the device memory information */
1459 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
1461 /* initialize device memory address space */
1462 if (pcmc
->has_reserved_memory
&&
1463 (machine
->ram_size
< machine
->maxram_size
)) {
1464 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
1466 if (machine
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1467 error_report("unsupported amount of memory slots: %"PRIu64
,
1468 machine
->ram_slots
);
1472 if (QEMU_ALIGN_UP(machine
->maxram_size
,
1473 TARGET_PAGE_SIZE
) != machine
->maxram_size
) {
1474 error_report("maximum memory size must by aligned to multiple of "
1475 "%d bytes", TARGET_PAGE_SIZE
);
1479 machine
->device_memory
->base
=
1480 ROUND_UP(0x100000000ULL
+ pcms
->above_4g_mem_size
, 1 * GiB
);
1482 if (pcmc
->enforce_aligned_dimm
) {
1483 /* size device region assuming 1G page max alignment per slot */
1484 device_mem_size
+= (1 * GiB
) * machine
->ram_slots
;
1487 if ((machine
->device_memory
->base
+ device_mem_size
) <
1489 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT
,
1490 machine
->maxram_size
);
1494 memory_region_init(&machine
->device_memory
->mr
, OBJECT(pcms
),
1495 "device-memory", device_mem_size
);
1496 memory_region_add_subregion(system_memory
, machine
->device_memory
->base
,
1497 &machine
->device_memory
->mr
);
1500 /* Initialize PC system firmware */
1501 pc_system_firmware_init(rom_memory
, !pcmc
->pci_enabled
);
1503 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1504 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
,
1506 if (pcmc
->pci_enabled
) {
1507 memory_region_set_readonly(option_rom_mr
, true);
1509 memory_region_add_subregion_overlap(rom_memory
,
1514 fw_cfg
= bochs_bios_init(&address_space_memory
, pcms
);
1518 if (pcmc
->has_reserved_memory
&& machine
->device_memory
->base
) {
1519 uint64_t *val
= g_malloc(sizeof(*val
));
1520 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1521 uint64_t res_mem_end
= machine
->device_memory
->base
;
1523 if (!pcmc
->broken_reserved_end
) {
1524 res_mem_end
+= memory_region_size(&machine
->device_memory
->mr
);
1526 *val
= cpu_to_le64(ROUND_UP(res_mem_end
, 1 * GiB
));
1527 fw_cfg_add_file(fw_cfg
, "etc/reserved-memory-end", val
, sizeof(*val
));
1531 load_linux(pcms
, fw_cfg
);
1534 for (i
= 0; i
< nb_option_roms
; i
++) {
1535 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1537 pcms
->fw_cfg
= fw_cfg
;
1539 /* Init default IOAPIC address space */
1540 pcms
->ioapic_as
= &address_space_memory
;
1544 * The 64bit pci hole starts after "above 4G RAM" and
1545 * potentially the space reserved for memory hotplug.
1547 uint64_t pc_pci_hole64_start(void)
1549 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
1550 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1551 MachineState
*ms
= MACHINE(pcms
);
1552 uint64_t hole64_start
= 0;
1554 if (pcmc
->has_reserved_memory
&& ms
->device_memory
->base
) {
1555 hole64_start
= ms
->device_memory
->base
;
1556 if (!pcmc
->broken_reserved_end
) {
1557 hole64_start
+= memory_region_size(&ms
->device_memory
->mr
);
1560 hole64_start
= 0x100000000ULL
+ pcms
->above_4g_mem_size
;
1563 return ROUND_UP(hole64_start
, 1 * GiB
);
1566 qemu_irq
pc_allocate_cpu_irq(void)
1568 return qemu_allocate_irq(pic_irq_request
, NULL
, 0);
1571 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1573 DeviceState
*dev
= NULL
;
1575 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA
);
1577 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
1578 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1579 } else if (isa_bus
) {
1580 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1581 dev
= isadev
? DEVICE(isadev
) : NULL
;
1583 rom_reset_order_override();
1587 static const MemoryRegionOps ioport80_io_ops
= {
1588 .write
= ioport80_write
,
1589 .read
= ioport80_read
,
1590 .endianness
= DEVICE_NATIVE_ENDIAN
,
1592 .min_access_size
= 1,
1593 .max_access_size
= 1,
1597 static const MemoryRegionOps ioportF0_io_ops
= {
1598 .write
= ioportF0_write
,
1599 .read
= ioportF0_read
,
1600 .endianness
= DEVICE_NATIVE_ENDIAN
,
1602 .min_access_size
= 1,
1603 .max_access_size
= 1,
1607 static void pc_superio_init(ISABus
*isa_bus
, bool create_fdctrl
, bool no_vmport
)
1610 DriveInfo
*fd
[MAX_FD
];
1612 ISADevice
*i8042
, *port92
, *vmmouse
;
1614 serial_hds_isa_init(isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
1615 parallel_hds_isa_init(isa_bus
, MAX_PARALLEL_PORTS
);
1617 for (i
= 0; i
< MAX_FD
; i
++) {
1618 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1619 create_fdctrl
|= !!fd
[i
];
1621 if (create_fdctrl
) {
1622 fdctrl_init_isa(isa_bus
, fd
);
1625 i8042
= isa_create_simple(isa_bus
, "i8042");
1627 vmport_init(isa_bus
);
1628 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
1633 DeviceState
*dev
= DEVICE(vmmouse
);
1634 qdev_prop_set_ptr(dev
, "ps2_mouse", i8042
);
1635 qdev_init_nofail(dev
);
1637 port92
= isa_create_simple(isa_bus
, "port92");
1639 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1640 i8042_setup_a20_line(i8042
, a20_line
[0]);
1641 port92_init(port92
, a20_line
[1]);
1645 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
1646 ISADevice
**rtc_state
,
1653 DeviceState
*hpet
= NULL
;
1654 int pit_isa_irq
= 0;
1655 qemu_irq pit_alt_irq
= NULL
;
1656 qemu_irq rtc_irq
= NULL
;
1657 ISADevice
*pit
= NULL
;
1658 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
1659 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
1661 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
1662 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
1664 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
1665 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
1668 * Check if an HPET shall be created.
1670 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1671 * when the HPET wants to take over. Thus we have to disable the latter.
1673 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1674 /* In order to set property, here not using sysbus_try_create_simple */
1675 hpet
= qdev_try_create(NULL
, TYPE_HPET
);
1677 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1678 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1681 uint8_t compat
= object_property_get_uint(OBJECT(hpet
),
1684 qdev_prop_set_uint32(hpet
, HPET_INTCAP
, hpet_irqs
);
1686 qdev_init_nofail(hpet
);
1687 sysbus_mmio_map(SYS_BUS_DEVICE(hpet
), 0, HPET_BASE
);
1689 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
1690 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
1693 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
1694 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
1697 *rtc_state
= mc146818_rtc_init(isa_bus
, 2000, rtc_irq
);
1699 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
1701 if (!xen_enabled() && has_pit
) {
1702 if (kvm_pit_in_kernel()) {
1703 pit
= kvm_pit_init(isa_bus
, 0x40);
1705 pit
= i8254_pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
1708 /* connect PIT to output control line of the HPET */
1709 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
1711 pcspk_init(isa_bus
, pit
);
1714 i8257_dma_init(isa_bus
, 0);
1717 pc_superio_init(isa_bus
, create_fdctrl
, no_vmport
);
1720 void pc_nic_init(PCMachineClass
*pcmc
, ISABus
*isa_bus
, PCIBus
*pci_bus
)
1724 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC
);
1725 for (i
= 0; i
< nb_nics
; i
++) {
1726 NICInfo
*nd
= &nd_table
[i
];
1727 const char *model
= nd
->model
? nd
->model
: pcmc
->default_nic_model
;
1729 if (g_str_equal(model
, "ne2k_isa")) {
1730 pc_init_ne2k_isa(isa_bus
, nd
);
1732 pci_nic_init_nofail(nd
, pci_bus
, model
, NULL
);
1735 rom_reset_order_override();
1738 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
)
1744 if (kvm_ioapic_in_kernel()) {
1745 dev
= qdev_create(NULL
, "kvm-ioapic");
1747 dev
= qdev_create(NULL
, "ioapic");
1750 object_property_add_child(object_resolve_path(parent_name
, NULL
),
1751 "ioapic", OBJECT(dev
), NULL
);
1753 qdev_init_nofail(dev
);
1754 d
= SYS_BUS_DEVICE(dev
);
1755 sysbus_mmio_map(d
, 0, IO_APIC_DEFAULT_ADDRESS
);
1757 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1758 gsi_state
->ioapic_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1762 static void pc_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
1765 const PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1766 const PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1767 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
1768 const uint64_t legacy_align
= TARGET_PAGE_SIZE
;
1771 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1772 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1773 * addition to cover this case.
1775 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
1777 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1781 if (is_nvdimm
&& !pcms
->acpi_nvdimm_state
.is_enabled
) {
1782 error_setg(errp
, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1786 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
),
1787 pcmc
->enforce_aligned_dimm
? NULL
: &legacy_align
, errp
);
1790 static void pc_memory_plug(HotplugHandler
*hotplug_dev
,
1791 DeviceState
*dev
, Error
**errp
)
1793 HotplugHandlerClass
*hhc
;
1794 Error
*local_err
= NULL
;
1795 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1796 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
1798 pc_dimm_plug(PC_DIMM(dev
), MACHINE(pcms
), &local_err
);
1804 nvdimm_plug(&pcms
->acpi_nvdimm_state
);
1807 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1808 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &error_abort
);
1810 error_propagate(errp
, local_err
);
1813 static void pc_memory_unplug_request(HotplugHandler
*hotplug_dev
,
1814 DeviceState
*dev
, Error
**errp
)
1816 HotplugHandlerClass
*hhc
;
1817 Error
*local_err
= NULL
;
1818 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1821 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1822 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1823 * addition to cover this case.
1825 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
1826 error_setg(&local_err
,
1827 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1831 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
1832 error_setg(&local_err
,
1833 "nvdimm device hot unplug is not supported yet.");
1837 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1838 hhc
->unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1841 error_propagate(errp
, local_err
);
1844 static void pc_memory_unplug(HotplugHandler
*hotplug_dev
,
1845 DeviceState
*dev
, Error
**errp
)
1847 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1848 HotplugHandlerClass
*hhc
;
1849 Error
*local_err
= NULL
;
1851 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1852 hhc
->unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1858 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(pcms
));
1859 object_unparent(OBJECT(dev
));
1862 error_propagate(errp
, local_err
);
1865 static int pc_apic_cmp(const void *a
, const void *b
)
1867 CPUArchId
*apic_a
= (CPUArchId
*)a
;
1868 CPUArchId
*apic_b
= (CPUArchId
*)b
;
1870 return apic_a
->arch_id
- apic_b
->arch_id
;
1873 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1874 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1875 * entry corresponding to CPU's apic_id returns NULL.
1877 static CPUArchId
*pc_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
1879 CPUArchId apic_id
, *found_cpu
;
1881 apic_id
.arch_id
= id
;
1882 found_cpu
= bsearch(&apic_id
, ms
->possible_cpus
->cpus
,
1883 ms
->possible_cpus
->len
, sizeof(*ms
->possible_cpus
->cpus
),
1885 if (found_cpu
&& idx
) {
1886 *idx
= found_cpu
- ms
->possible_cpus
->cpus
;
1891 static void pc_cpu_plug(HotplugHandler
*hotplug_dev
,
1892 DeviceState
*dev
, Error
**errp
)
1894 CPUArchId
*found_cpu
;
1895 HotplugHandlerClass
*hhc
;
1896 Error
*local_err
= NULL
;
1897 X86CPU
*cpu
= X86_CPU(dev
);
1898 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1900 if (pcms
->acpi_dev
) {
1901 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1902 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1908 /* increment the number of CPUs */
1911 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1914 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1917 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
1918 found_cpu
->cpu
= OBJECT(dev
);
1920 error_propagate(errp
, local_err
);
1922 static void pc_cpu_unplug_request_cb(HotplugHandler
*hotplug_dev
,
1923 DeviceState
*dev
, Error
**errp
)
1926 HotplugHandlerClass
*hhc
;
1927 Error
*local_err
= NULL
;
1928 X86CPU
*cpu
= X86_CPU(dev
);
1929 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1931 if (!pcms
->acpi_dev
) {
1932 error_setg(&local_err
, "CPU hot unplug not supported without ACPI");
1936 pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
1939 error_setg(&local_err
, "Boot CPU is unpluggable");
1943 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1944 hhc
->unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1951 error_propagate(errp
, local_err
);
1955 static void pc_cpu_unplug_cb(HotplugHandler
*hotplug_dev
,
1956 DeviceState
*dev
, Error
**errp
)
1958 CPUArchId
*found_cpu
;
1959 HotplugHandlerClass
*hhc
;
1960 Error
*local_err
= NULL
;
1961 X86CPU
*cpu
= X86_CPU(dev
);
1962 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1964 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1965 hhc
->unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1971 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
1972 found_cpu
->cpu
= NULL
;
1973 object_unparent(OBJECT(dev
));
1975 /* decrement the number of CPUs */
1977 /* Update the number of CPUs in CMOS */
1978 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1979 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1981 error_propagate(errp
, local_err
);
1984 static void pc_cpu_pre_plug(HotplugHandler
*hotplug_dev
,
1985 DeviceState
*dev
, Error
**errp
)
1989 CPUArchId
*cpu_slot
;
1990 X86CPUTopoInfo topo
;
1991 X86CPU
*cpu
= X86_CPU(dev
);
1992 MachineState
*ms
= MACHINE(hotplug_dev
);
1993 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1995 if(!object_dynamic_cast(OBJECT(cpu
), ms
->cpu_type
)) {
1996 error_setg(errp
, "Invalid CPU type, expected cpu type: '%s'",
2001 /* if APIC ID is not set, set it based on socket/core/thread properties */
2002 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
2003 int max_socket
= (max_cpus
- 1) / smp_threads
/ smp_cores
;
2005 if (cpu
->socket_id
< 0) {
2006 error_setg(errp
, "CPU socket-id is not set");
2008 } else if (cpu
->socket_id
> max_socket
) {
2009 error_setg(errp
, "Invalid CPU socket-id: %u must be in range 0:%u",
2010 cpu
->socket_id
, max_socket
);
2013 if (cpu
->core_id
< 0) {
2014 error_setg(errp
, "CPU core-id is not set");
2016 } else if (cpu
->core_id
> (smp_cores
- 1)) {
2017 error_setg(errp
, "Invalid CPU core-id: %u must be in range 0:%u",
2018 cpu
->core_id
, smp_cores
- 1);
2021 if (cpu
->thread_id
< 0) {
2022 error_setg(errp
, "CPU thread-id is not set");
2024 } else if (cpu
->thread_id
> (smp_threads
- 1)) {
2025 error_setg(errp
, "Invalid CPU thread-id: %u must be in range 0:%u",
2026 cpu
->thread_id
, smp_threads
- 1);
2030 topo
.pkg_id
= cpu
->socket_id
;
2031 topo
.core_id
= cpu
->core_id
;
2032 topo
.smt_id
= cpu
->thread_id
;
2033 cpu
->apic_id
= apicid_from_topo_ids(smp_cores
, smp_threads
, &topo
);
2036 cpu_slot
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
2038 MachineState
*ms
= MACHINE(pcms
);
2040 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
2041 error_setg(errp
, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
2042 " APIC ID %" PRIu32
", valid index range 0:%d",
2043 topo
.pkg_id
, topo
.core_id
, topo
.smt_id
, cpu
->apic_id
,
2044 ms
->possible_cpus
->len
- 1);
2048 if (cpu_slot
->cpu
) {
2049 error_setg(errp
, "CPU[%d] with APIC ID %" PRIu32
" exists",
2054 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
2055 * so that machine_query_hotpluggable_cpus would show correct values
2057 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2058 * once -smp refactoring is complete and there will be CPU private
2059 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2060 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
2061 if (cpu
->socket_id
!= -1 && cpu
->socket_id
!= topo
.pkg_id
) {
2062 error_setg(errp
, "property socket-id: %u doesn't match set apic-id:"
2063 " 0x%x (socket-id: %u)", cpu
->socket_id
, cpu
->apic_id
, topo
.pkg_id
);
2066 cpu
->socket_id
= topo
.pkg_id
;
2068 if (cpu
->core_id
!= -1 && cpu
->core_id
!= topo
.core_id
) {
2069 error_setg(errp
, "property core-id: %u doesn't match set apic-id:"
2070 " 0x%x (core-id: %u)", cpu
->core_id
, cpu
->apic_id
, topo
.core_id
);
2073 cpu
->core_id
= topo
.core_id
;
2075 if (cpu
->thread_id
!= -1 && cpu
->thread_id
!= topo
.smt_id
) {
2076 error_setg(errp
, "property thread-id: %u doesn't match set apic-id:"
2077 " 0x%x (thread-id: %u)", cpu
->thread_id
, cpu
->apic_id
, topo
.smt_id
);
2080 cpu
->thread_id
= topo
.smt_id
;
2082 if (cpu
->hyperv_vpindex
&& !kvm_hv_vpindex_settable()) {
2083 error_setg(errp
, "kernel doesn't allow setting HyperV VP_INDEX");
2088 cs
->cpu_index
= idx
;
2090 numa_cpu_pre_plug(cpu_slot
, dev
, errp
);
2093 static void pc_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2094 DeviceState
*dev
, Error
**errp
)
2096 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2097 pc_memory_pre_plug(hotplug_dev
, dev
, errp
);
2098 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2099 pc_cpu_pre_plug(hotplug_dev
, dev
, errp
);
2103 static void pc_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2104 DeviceState
*dev
, Error
**errp
)
2106 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2107 pc_memory_plug(hotplug_dev
, dev
, errp
);
2108 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2109 pc_cpu_plug(hotplug_dev
, dev
, errp
);
2113 static void pc_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2114 DeviceState
*dev
, Error
**errp
)
2116 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2117 pc_memory_unplug_request(hotplug_dev
, dev
, errp
);
2118 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2119 pc_cpu_unplug_request_cb(hotplug_dev
, dev
, errp
);
2121 error_setg(errp
, "acpi: device unplug request for not supported device"
2122 " type: %s", object_get_typename(OBJECT(dev
)));
2126 static void pc_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2127 DeviceState
*dev
, Error
**errp
)
2129 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2130 pc_memory_unplug(hotplug_dev
, dev
, errp
);
2131 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2132 pc_cpu_unplug_cb(hotplug_dev
, dev
, errp
);
2134 error_setg(errp
, "acpi: device unplug for not supported device"
2135 " type: %s", object_get_typename(OBJECT(dev
)));
2139 static HotplugHandler
*pc_get_hotpug_handler(MachineState
*machine
,
2142 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2143 object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2144 return HOTPLUG_HANDLER(machine
);
2151 pc_machine_get_device_memory_region_size(Object
*obj
, Visitor
*v
,
2152 const char *name
, void *opaque
,
2155 MachineState
*ms
= MACHINE(obj
);
2156 int64_t value
= memory_region_size(&ms
->device_memory
->mr
);
2158 visit_type_int(v
, name
, &value
, errp
);
2161 static void pc_machine_get_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2162 const char *name
, void *opaque
,
2165 PCMachineState
*pcms
= PC_MACHINE(obj
);
2166 uint64_t value
= pcms
->max_ram_below_4g
;
2168 visit_type_size(v
, name
, &value
, errp
);
2171 static void pc_machine_set_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2172 const char *name
, void *opaque
,
2175 PCMachineState
*pcms
= PC_MACHINE(obj
);
2176 Error
*error
= NULL
;
2179 visit_type_size(v
, name
, &value
, &error
);
2181 error_propagate(errp
, error
);
2184 if (value
> 4 * GiB
) {
2186 "Machine option 'max-ram-below-4g=%"PRIu64
2187 "' expects size less than or equal to 4G", value
);
2188 error_propagate(errp
, error
);
2192 if (value
< 1 * MiB
) {
2193 warn_report("Only %" PRIu64
" bytes of RAM below the 4GiB boundary,"
2194 "BIOS may not work with less than 1MiB", value
);
2197 pcms
->max_ram_below_4g
= value
;
2200 static void pc_machine_get_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2201 void *opaque
, Error
**errp
)
2203 PCMachineState
*pcms
= PC_MACHINE(obj
);
2204 OnOffAuto vmport
= pcms
->vmport
;
2206 visit_type_OnOffAuto(v
, name
, &vmport
, errp
);
2209 static void pc_machine_set_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2210 void *opaque
, Error
**errp
)
2212 PCMachineState
*pcms
= PC_MACHINE(obj
);
2214 visit_type_OnOffAuto(v
, name
, &pcms
->vmport
, errp
);
2217 bool pc_machine_is_smm_enabled(PCMachineState
*pcms
)
2219 bool smm_available
= false;
2221 if (pcms
->smm
== ON_OFF_AUTO_OFF
) {
2225 if (tcg_enabled() || qtest_enabled()) {
2226 smm_available
= true;
2227 } else if (kvm_enabled()) {
2228 smm_available
= kvm_has_smm();
2231 if (smm_available
) {
2235 if (pcms
->smm
== ON_OFF_AUTO_ON
) {
2236 error_report("System Management Mode not supported by this hypervisor.");
2242 static void pc_machine_get_smm(Object
*obj
, Visitor
*v
, const char *name
,
2243 void *opaque
, Error
**errp
)
2245 PCMachineState
*pcms
= PC_MACHINE(obj
);
2246 OnOffAuto smm
= pcms
->smm
;
2248 visit_type_OnOffAuto(v
, name
, &smm
, errp
);
2251 static void pc_machine_set_smm(Object
*obj
, Visitor
*v
, const char *name
,
2252 void *opaque
, Error
**errp
)
2254 PCMachineState
*pcms
= PC_MACHINE(obj
);
2256 visit_type_OnOffAuto(v
, name
, &pcms
->smm
, errp
);
2259 static bool pc_machine_get_nvdimm(Object
*obj
, Error
**errp
)
2261 PCMachineState
*pcms
= PC_MACHINE(obj
);
2263 return pcms
->acpi_nvdimm_state
.is_enabled
;
2266 static void pc_machine_set_nvdimm(Object
*obj
, bool value
, Error
**errp
)
2268 PCMachineState
*pcms
= PC_MACHINE(obj
);
2270 pcms
->acpi_nvdimm_state
.is_enabled
= value
;
2273 static char *pc_machine_get_nvdimm_persistence(Object
*obj
, Error
**errp
)
2275 PCMachineState
*pcms
= PC_MACHINE(obj
);
2277 return g_strdup(pcms
->acpi_nvdimm_state
.persistence_string
);
2280 static void pc_machine_set_nvdimm_persistence(Object
*obj
, const char *value
,
2283 PCMachineState
*pcms
= PC_MACHINE(obj
);
2284 AcpiNVDIMMState
*nvdimm_state
= &pcms
->acpi_nvdimm_state
;
2286 if (strcmp(value
, "cpu") == 0)
2287 nvdimm_state
->persistence
= 3;
2288 else if (strcmp(value
, "mem-ctrl") == 0)
2289 nvdimm_state
->persistence
= 2;
2291 error_setg(errp
, "-machine nvdimm-persistence=%s: unsupported option",
2296 g_free(nvdimm_state
->persistence_string
);
2297 nvdimm_state
->persistence_string
= g_strdup(value
);
2300 static bool pc_machine_get_smbus(Object
*obj
, Error
**errp
)
2302 PCMachineState
*pcms
= PC_MACHINE(obj
);
2304 return pcms
->smbus_enabled
;
2307 static void pc_machine_set_smbus(Object
*obj
, bool value
, Error
**errp
)
2309 PCMachineState
*pcms
= PC_MACHINE(obj
);
2311 pcms
->smbus_enabled
= value
;
2314 static bool pc_machine_get_sata(Object
*obj
, Error
**errp
)
2316 PCMachineState
*pcms
= PC_MACHINE(obj
);
2318 return pcms
->sata_enabled
;
2321 static void pc_machine_set_sata(Object
*obj
, bool value
, Error
**errp
)
2323 PCMachineState
*pcms
= PC_MACHINE(obj
);
2325 pcms
->sata_enabled
= value
;
2328 static bool pc_machine_get_pit(Object
*obj
, Error
**errp
)
2330 PCMachineState
*pcms
= PC_MACHINE(obj
);
2332 return pcms
->pit_enabled
;
2335 static void pc_machine_set_pit(Object
*obj
, bool value
, Error
**errp
)
2337 PCMachineState
*pcms
= PC_MACHINE(obj
);
2339 pcms
->pit_enabled
= value
;
2342 static void pc_machine_initfn(Object
*obj
)
2344 PCMachineState
*pcms
= PC_MACHINE(obj
);
2346 pcms
->max_ram_below_4g
= 0; /* use default */
2347 pcms
->smm
= ON_OFF_AUTO_AUTO
;
2348 pcms
->vmport
= ON_OFF_AUTO_AUTO
;
2349 /* nvdimm is disabled on default. */
2350 pcms
->acpi_nvdimm_state
.is_enabled
= false;
2351 /* acpi build is enabled by default if machine supports it */
2352 pcms
->acpi_build_enabled
= PC_MACHINE_GET_CLASS(pcms
)->has_acpi_build
;
2353 pcms
->smbus_enabled
= true;
2354 pcms
->sata_enabled
= true;
2355 pcms
->pit_enabled
= true;
2358 static void pc_machine_reset(void)
2363 qemu_devices_reset();
2365 /* Reset APIC after devices have been reset to cancel
2366 * any changes that qemu_devices_reset() might have done.
2371 if (cpu
->apic_state
) {
2372 device_reset(cpu
->apic_state
);
2377 static CpuInstanceProperties
2378 pc_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2380 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2381 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2383 assert(cpu_index
< possible_cpus
->len
);
2384 return possible_cpus
->cpus
[cpu_index
].props
;
2387 static int64_t pc_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2389 X86CPUTopoInfo topo
;
2391 assert(idx
< ms
->possible_cpus
->len
);
2392 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[idx
].arch_id
,
2393 smp_cores
, smp_threads
, &topo
);
2394 return topo
.pkg_id
% nb_numa_nodes
;
2397 static const CPUArchIdList
*pc_possible_cpu_arch_ids(MachineState
*ms
)
2401 if (ms
->possible_cpus
) {
2403 * make sure that max_cpus hasn't changed since the first use, i.e.
2404 * -smp hasn't been parsed after it
2406 assert(ms
->possible_cpus
->len
== max_cpus
);
2407 return ms
->possible_cpus
;
2410 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2411 sizeof(CPUArchId
) * max_cpus
);
2412 ms
->possible_cpus
->len
= max_cpus
;
2413 for (i
= 0; i
< ms
->possible_cpus
->len
; i
++) {
2414 X86CPUTopoInfo topo
;
2416 ms
->possible_cpus
->cpus
[i
].type
= ms
->cpu_type
;
2417 ms
->possible_cpus
->cpus
[i
].vcpus_count
= 1;
2418 ms
->possible_cpus
->cpus
[i
].arch_id
= x86_cpu_apic_id_from_index(i
);
2419 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[i
].arch_id
,
2420 smp_cores
, smp_threads
, &topo
);
2421 ms
->possible_cpus
->cpus
[i
].props
.has_socket_id
= true;
2422 ms
->possible_cpus
->cpus
[i
].props
.socket_id
= topo
.pkg_id
;
2423 ms
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
2424 ms
->possible_cpus
->cpus
[i
].props
.core_id
= topo
.core_id
;
2425 ms
->possible_cpus
->cpus
[i
].props
.has_thread_id
= true;
2426 ms
->possible_cpus
->cpus
[i
].props
.thread_id
= topo
.smt_id
;
2428 return ms
->possible_cpus
;
2431 static void x86_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
2433 /* cpu index isn't used */
2437 X86CPU
*cpu
= X86_CPU(cs
);
2439 if (!cpu
->apic_state
) {
2440 cpu_interrupt(cs
, CPU_INTERRUPT_NMI
);
2442 apic_deliver_nmi(cpu
->apic_state
);
2447 static void pc_machine_class_init(ObjectClass
*oc
, void *data
)
2449 MachineClass
*mc
= MACHINE_CLASS(oc
);
2450 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(oc
);
2451 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2452 NMIClass
*nc
= NMI_CLASS(oc
);
2454 pcmc
->pci_enabled
= true;
2455 pcmc
->has_acpi_build
= true;
2456 pcmc
->rsdp_in_ram
= true;
2457 pcmc
->smbios_defaults
= true;
2458 pcmc
->smbios_uuid_encoded
= true;
2459 pcmc
->gigabyte_align
= true;
2460 pcmc
->has_reserved_memory
= true;
2461 pcmc
->kvmclock_enabled
= true;
2462 pcmc
->enforce_aligned_dimm
= true;
2463 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2464 * to be used at the moment, 32K should be enough for a while. */
2465 pcmc
->acpi_data_size
= 0x20000 + 0x8000;
2466 pcmc
->save_tsc_khz
= true;
2467 pcmc
->linuxboot_dma_enabled
= true;
2468 assert(!mc
->get_hotplug_handler
);
2469 mc
->get_hotplug_handler
= pc_get_hotpug_handler
;
2470 mc
->cpu_index_to_instance_props
= pc_cpu_index_to_props
;
2471 mc
->get_default_cpu_node_id
= pc_get_default_cpu_node_id
;
2472 mc
->possible_cpu_arch_ids
= pc_possible_cpu_arch_ids
;
2473 mc
->auto_enable_numa_with_memhp
= true;
2474 mc
->has_hotpluggable_cpus
= true;
2475 mc
->default_boot_order
= "cad";
2476 mc
->hot_add_cpu
= pc_hot_add_cpu
;
2477 mc
->block_default_type
= IF_IDE
;
2479 mc
->reset
= pc_machine_reset
;
2480 hc
->pre_plug
= pc_machine_device_pre_plug_cb
;
2481 hc
->plug
= pc_machine_device_plug_cb
;
2482 hc
->unplug_request
= pc_machine_device_unplug_request_cb
;
2483 hc
->unplug
= pc_machine_device_unplug_cb
;
2484 nc
->nmi_monitor_handler
= x86_nmi
;
2485 mc
->default_cpu_type
= TARGET_DEFAULT_CPU_TYPE
;
2487 object_class_property_add(oc
, PC_MACHINE_DEVMEM_REGION_SIZE
, "int",
2488 pc_machine_get_device_memory_region_size
, NULL
,
2489 NULL
, NULL
, &error_abort
);
2491 object_class_property_add(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
, "size",
2492 pc_machine_get_max_ram_below_4g
, pc_machine_set_max_ram_below_4g
,
2493 NULL
, NULL
, &error_abort
);
2495 object_class_property_set_description(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
,
2496 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort
);
2498 object_class_property_add(oc
, PC_MACHINE_SMM
, "OnOffAuto",
2499 pc_machine_get_smm
, pc_machine_set_smm
,
2500 NULL
, NULL
, &error_abort
);
2501 object_class_property_set_description(oc
, PC_MACHINE_SMM
,
2502 "Enable SMM (pc & q35)", &error_abort
);
2504 object_class_property_add(oc
, PC_MACHINE_VMPORT
, "OnOffAuto",
2505 pc_machine_get_vmport
, pc_machine_set_vmport
,
2506 NULL
, NULL
, &error_abort
);
2507 object_class_property_set_description(oc
, PC_MACHINE_VMPORT
,
2508 "Enable vmport (pc & q35)", &error_abort
);
2510 object_class_property_add_bool(oc
, PC_MACHINE_NVDIMM
,
2511 pc_machine_get_nvdimm
, pc_machine_set_nvdimm
, &error_abort
);
2513 object_class_property_add_str(oc
, PC_MACHINE_NVDIMM_PERSIST
,
2514 pc_machine_get_nvdimm_persistence
,
2515 pc_machine_set_nvdimm_persistence
, &error_abort
);
2517 object_class_property_add_bool(oc
, PC_MACHINE_SMBUS
,
2518 pc_machine_get_smbus
, pc_machine_set_smbus
, &error_abort
);
2520 object_class_property_add_bool(oc
, PC_MACHINE_SATA
,
2521 pc_machine_get_sata
, pc_machine_set_sata
, &error_abort
);
2523 object_class_property_add_bool(oc
, PC_MACHINE_PIT
,
2524 pc_machine_get_pit
, pc_machine_set_pit
, &error_abort
);
2527 static const TypeInfo pc_machine_info
= {
2528 .name
= TYPE_PC_MACHINE
,
2529 .parent
= TYPE_MACHINE
,
2531 .instance_size
= sizeof(PCMachineState
),
2532 .instance_init
= pc_machine_initfn
,
2533 .class_size
= sizeof(PCMachineClass
),
2534 .class_init
= pc_machine_class_init
,
2535 .interfaces
= (InterfaceInfo
[]) {
2536 { TYPE_HOTPLUG_HANDLER
},
2542 static void pc_machine_register_types(void)
2544 type_register_static(&pc_machine_info
);
2547 type_init(pc_machine_register_types
)