2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "sysemu/cpus.h"
34 #include "hw/block/fdc.h"
36 #include "hw/pci/pci.h"
37 #include "hw/pci/pci_bus.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/timer/hpet.h"
40 #include "hw/firmware/smbios.h"
41 #include "hw/loader.h"
43 #include "multiboot.h"
44 #include "hw/timer/mc146818rtc.h"
45 #include "hw/dma/i8257.h"
46 #include "hw/timer/i8254.h"
47 #include "hw/input/i8042.h"
48 #include "hw/audio/pcspk.h"
49 #include "hw/pci/msi.h"
50 #include "hw/sysbus.h"
51 #include "sysemu/sysemu.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/kvm.h"
54 #include "sysemu/qtest.h"
56 #include "hw/xen/xen.h"
57 #include "ui/qemu-spice.h"
58 #include "exec/memory.h"
59 #include "exec/address-spaces.h"
60 #include "sysemu/arch_init.h"
61 #include "qemu/bitmap.h"
62 #include "qemu/config-file.h"
63 #include "qemu/error-report.h"
64 #include "qemu/option.h"
65 #include "hw/acpi/acpi.h"
66 #include "hw/acpi/cpu_hotplug.h"
67 #include "hw/boards.h"
68 #include "acpi-build.h"
69 #include "hw/mem/pc-dimm.h"
70 #include "qapi/error.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "qapi/visitor.h"
76 #include "hw/i386/intel_iommu.h"
77 #include "hw/net/ne2000-isa.h"
79 /* debug PC/ISA interrupts */
83 #define DPRINTF(fmt, ...) \
84 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
86 #define DPRINTF(fmt, ...)
89 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
90 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
91 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
92 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
93 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
95 #define E820_NR_ENTRIES 16
101 } QEMU_PACKED
__attribute((__aligned__(4)));
105 struct e820_entry entry
[E820_NR_ENTRIES
];
106 } QEMU_PACKED
__attribute((__aligned__(4)));
108 static struct e820_table e820_reserve
;
109 static struct e820_entry
*e820_table
;
110 static unsigned e820_entries
;
111 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
113 GlobalProperty pc_compat_3_1
[] = {
115 .driver
= "intel-iommu",
116 .property
= "dma-drain",
120 const size_t pc_compat_3_1_len
= G_N_ELEMENTS(pc_compat_3_1
);
122 GlobalProperty pc_compat_3_0
[] = {
124 .driver
= TYPE_X86_CPU
,
125 .property
= "x-hv-synic-kvm-only",
128 .driver
= "Skylake-Server" "-" TYPE_X86_CPU
,
132 .driver
= "Skylake-Server-IBRS" "-" TYPE_X86_CPU
,
137 const size_t pc_compat_3_0_len
= G_N_ELEMENTS(pc_compat_3_0
);
139 GlobalProperty pc_compat_2_12
[] = {
141 .driver
= TYPE_X86_CPU
,
142 .property
= "legacy-cache",
145 .driver
= TYPE_X86_CPU
,
146 .property
= "topoext",
149 .driver
= "EPYC-" TYPE_X86_CPU
,
150 .property
= "xlevel",
151 .value
= stringify(0x8000000a),
153 .driver
= "EPYC-IBPB-" TYPE_X86_CPU
,
154 .property
= "xlevel",
155 .value
= stringify(0x8000000a),
158 const size_t pc_compat_2_12_len
= G_N_ELEMENTS(pc_compat_2_12
);
160 GlobalProperty pc_compat_2_11
[] = {
162 .driver
= TYPE_X86_CPU
,
163 .property
= "x-migrate-smi-count",
166 .driver
= "Skylake-Server" "-" TYPE_X86_CPU
,
167 .property
= "clflushopt",
171 const size_t pc_compat_2_11_len
= G_N_ELEMENTS(pc_compat_2_11
);
173 GlobalProperty pc_compat_2_10
[] = {
175 .driver
= TYPE_X86_CPU
,
176 .property
= "x-hv-max-vps",
179 .driver
= "i440FX-pcihost",
180 .property
= "x-pci-hole64-fix",
183 .driver
= "q35-pcihost",
184 .property
= "x-pci-hole64-fix",
188 const size_t pc_compat_2_10_len
= G_N_ELEMENTS(pc_compat_2_10
);
190 GlobalProperty pc_compat_2_9
[] = {
193 .property
= "extended-tseg-mbytes",
194 .value
= stringify(0),
197 const size_t pc_compat_2_9_len
= G_N_ELEMENTS(pc_compat_2_9
);
199 GlobalProperty pc_compat_2_8
[] = {
201 .driver
= TYPE_X86_CPU
,
202 .property
= "tcg-cpuid",
206 .driver
= "kvmclock",
207 .property
= "x-mach-use-reliable-get-clock",
211 .driver
= "ICH9-LPC",
212 .property
= "x-smi-broadcast",
216 .driver
= TYPE_X86_CPU
,
217 .property
= "vmware-cpuid-freq",
221 .driver
= "Haswell-" TYPE_X86_CPU
,
222 .property
= "stepping",
226 const size_t pc_compat_2_8_len
= G_N_ELEMENTS(pc_compat_2_8
);
228 GlobalProperty pc_compat_2_7
[] = {
230 .driver
= TYPE_X86_CPU
,
231 .property
= "l3-cache",
235 .driver
= TYPE_X86_CPU
,
236 .property
= "full-cpuid-auto-level",
240 .driver
= "Opteron_G3" "-" TYPE_X86_CPU
,
241 .property
= "family",
245 .driver
= "Opteron_G3" "-" TYPE_X86_CPU
,
250 .driver
= "Opteron_G3" "-" TYPE_X86_CPU
,
251 .property
= "stepping",
255 .driver
= "isa-pcspk",
256 .property
= "migrate",
260 const size_t pc_compat_2_7_len
= G_N_ELEMENTS(pc_compat_2_7
);
262 GlobalProperty pc_compat_2_6
[] = {
264 .driver
= TYPE_X86_CPU
,
265 .property
= "cpuid-0xb",
269 .property
= "romfile",
273 .driver
= TYPE_X86_CPU
,
274 .property
= "fill-mtrr-mask",
278 .driver
= "apic-common",
279 .property
= "legacy-instance-id",
283 const size_t pc_compat_2_6_len
= G_N_ELEMENTS(pc_compat_2_6
);
285 GlobalProperty pc_compat_2_5
[] = {};
286 const size_t pc_compat_2_5_len
= G_N_ELEMENTS(pc_compat_2_5
);
288 GlobalProperty pc_compat_2_4
[] = {
289 PC_CPU_MODEL_IDS("2.4.0")
291 .driver
= "Haswell-" TYPE_X86_CPU
,
296 .driver
= "Haswell-noTSX-" TYPE_X86_CPU
,
301 .driver
= "Broadwell-" TYPE_X86_CPU
,
306 .driver
= "Broadwell-noTSX-" TYPE_X86_CPU
,
311 .driver
= "host" "-" TYPE_X86_CPU
,
312 .property
= "host-cache-info",
316 .driver
= TYPE_X86_CPU
,
321 .driver
= "qemu64" "-" TYPE_X86_CPU
,
326 .driver
= "qemu64" "-" TYPE_X86_CPU
,
331 .driver
= "qemu64" "-" TYPE_X86_CPU
,
332 .property
= "popcnt",
336 .driver
= "qemu32" "-" TYPE_X86_CPU
,
337 .property
= "popcnt",
340 .driver
= "Opteron_G2" "-" TYPE_X86_CPU
,
341 .property
= "rdtscp",
344 .driver
= "Opteron_G3" "-" TYPE_X86_CPU
,
345 .property
= "rdtscp",
348 .driver
= "Opteron_G4" "-" TYPE_X86_CPU
,
349 .property
= "rdtscp",
352 .driver
= "Opteron_G5" "-" TYPE_X86_CPU
,
353 .property
= "rdtscp",
357 const size_t pc_compat_2_4_len
= G_N_ELEMENTS(pc_compat_2_4
);
359 GlobalProperty pc_compat_2_3
[] = {
360 PC_CPU_MODEL_IDS("2.3.0")
362 .driver
= TYPE_X86_CPU
,
366 .driver
= "qemu64" "-" TYPE_X86_CPU
,
367 .property
= "min-level",
368 .value
= stringify(4),
370 .driver
= "kvm64" "-" TYPE_X86_CPU
,
371 .property
= "min-level",
372 .value
= stringify(5),
374 .driver
= "pentium3" "-" TYPE_X86_CPU
,
375 .property
= "min-level",
376 .value
= stringify(2),
378 .driver
= "n270" "-" TYPE_X86_CPU
,
379 .property
= "min-level",
380 .value
= stringify(5),
382 .driver
= "Conroe" "-" TYPE_X86_CPU
,
383 .property
= "min-level",
384 .value
= stringify(4),
386 .driver
= "Penryn" "-" TYPE_X86_CPU
,
387 .property
= "min-level",
388 .value
= stringify(4),
390 .driver
= "Nehalem" "-" TYPE_X86_CPU
,
391 .property
= "min-level",
392 .value
= stringify(4),
394 .driver
= "n270" "-" TYPE_X86_CPU
,
395 .property
= "min-xlevel",
396 .value
= stringify(0x8000000a),
398 .driver
= "Penryn" "-" TYPE_X86_CPU
,
399 .property
= "min-xlevel",
400 .value
= stringify(0x8000000a),
402 .driver
= "Conroe" "-" TYPE_X86_CPU
,
403 .property
= "min-xlevel",
404 .value
= stringify(0x8000000a),
406 .driver
= "Nehalem" "-" TYPE_X86_CPU
,
407 .property
= "min-xlevel",
408 .value
= stringify(0x8000000a),
410 .driver
= "Westmere" "-" TYPE_X86_CPU
,
411 .property
= "min-xlevel",
412 .value
= stringify(0x8000000a),
414 .driver
= "SandyBridge" "-" TYPE_X86_CPU
,
415 .property
= "min-xlevel",
416 .value
= stringify(0x8000000a),
418 .driver
= "IvyBridge" "-" TYPE_X86_CPU
,
419 .property
= "min-xlevel",
420 .value
= stringify(0x8000000a),
422 .driver
= "Haswell" "-" TYPE_X86_CPU
,
423 .property
= "min-xlevel",
424 .value
= stringify(0x8000000a),
426 .driver
= "Haswell-noTSX" "-" TYPE_X86_CPU
,
427 .property
= "min-xlevel",
428 .value
= stringify(0x8000000a),
430 .driver
= "Broadwell" "-" TYPE_X86_CPU
,
431 .property
= "min-xlevel",
432 .value
= stringify(0x8000000a),
434 .driver
= "Broadwell-noTSX" "-" TYPE_X86_CPU
,
435 .property
= "min-xlevel",
436 .value
= stringify(0x8000000a),
438 .driver
= TYPE_X86_CPU
,
439 .property
= "kvm-no-smi-migration",
443 const size_t pc_compat_2_3_len
= G_N_ELEMENTS(pc_compat_2_3
);
445 GlobalProperty pc_compat_2_2
[] = {
446 PC_CPU_MODEL_IDS("2.2.0")
448 .driver
= "kvm64" "-" TYPE_X86_CPU
,
453 .driver
= "kvm32" "-" TYPE_X86_CPU
,
458 .driver
= "Conroe" "-" TYPE_X86_CPU
,
463 .driver
= "Penryn" "-" TYPE_X86_CPU
,
468 .driver
= "Nehalem" "-" TYPE_X86_CPU
,
473 .driver
= "Westmere" "-" TYPE_X86_CPU
,
478 .driver
= "SandyBridge" "-" TYPE_X86_CPU
,
483 .driver
= "Haswell" "-" TYPE_X86_CPU
,
488 .driver
= "Broadwell" "-" TYPE_X86_CPU
,
493 .driver
= "Opteron_G1" "-" TYPE_X86_CPU
,
498 .driver
= "Opteron_G2" "-" TYPE_X86_CPU
,
503 .driver
= "Opteron_G3" "-" TYPE_X86_CPU
,
508 .driver
= "Opteron_G4" "-" TYPE_X86_CPU
,
513 .driver
= "Opteron_G5" "-" TYPE_X86_CPU
,
518 .driver
= "Haswell" "-" TYPE_X86_CPU
,
523 .driver
= "Haswell" "-" TYPE_X86_CPU
,
524 .property
= "rdrand",
528 .driver
= "Broadwell" "-" TYPE_X86_CPU
,
533 .driver
= "Broadwell" "-" TYPE_X86_CPU
,
534 .property
= "rdrand",
538 const size_t pc_compat_2_2_len
= G_N_ELEMENTS(pc_compat_2_2
);
540 GlobalProperty pc_compat_2_1
[] = {
541 PC_CPU_MODEL_IDS("2.1.0")
543 .driver
= "coreduo" "-" TYPE_X86_CPU
,
548 .driver
= "core2duo" "-" TYPE_X86_CPU
,
553 const size_t pc_compat_2_1_len
= G_N_ELEMENTS(pc_compat_2_1
);
555 GlobalProperty pc_compat_2_0
[] = {
556 PC_CPU_MODEL_IDS("2.0.0")
558 .driver
= "virtio-scsi-pci",
559 .property
= "any_layout",
562 .driver
= "PIIX4_PM",
563 .property
= "memory-hotplug-support",
568 .property
= "version",
569 .value
= stringify(0x11),
572 .driver
= "nec-usb-xhci",
573 .property
= "superspeed-ports-first",
577 .driver
= "nec-usb-xhci",
578 .property
= "force-pcie-endcap",
582 .driver
= "pci-serial",
583 .property
= "prog_if",
584 .value
= stringify(0),
587 .driver
= "pci-serial-2x",
588 .property
= "prog_if",
589 .value
= stringify(0),
592 .driver
= "pci-serial-4x",
593 .property
= "prog_if",
594 .value
= stringify(0),
597 .driver
= "virtio-net-pci",
598 .property
= "guest_announce",
602 .driver
= "ICH9-LPC",
603 .property
= "memory-hotplug-support",
606 .driver
= "xio3130-downstream",
607 .property
= COMPAT_PROP_PCP
,
611 .property
= COMPAT_PROP_PCP
,
615 const size_t pc_compat_2_0_len
= G_N_ELEMENTS(pc_compat_2_0
);
617 GlobalProperty pc_compat_1_7
[] = {
618 PC_CPU_MODEL_IDS("1.7.0")
620 .driver
= TYPE_USB_DEVICE
,
621 .property
= "msos-desc",
625 .driver
= "PIIX4_PM",
626 .property
= "acpi-pci-hotplug-with-bridge-support",
631 .property
= HPET_INTCAP
,
632 .value
= stringify(4),
635 const size_t pc_compat_1_7_len
= G_N_ELEMENTS(pc_compat_1_7
);
637 GlobalProperty pc_compat_1_6
[] = {
638 PC_CPU_MODEL_IDS("1.6.0")
641 .property
= "mitigation",
644 .driver
= "qemu64-" TYPE_X86_CPU
,
646 .value
= stringify(2),
648 .driver
= "qemu32-" TYPE_X86_CPU
,
650 .value
= stringify(3),
652 .driver
= "i440FX-pcihost",
653 .property
= "short_root_bus",
654 .value
= stringify(1),
656 .driver
= "q35-pcihost",
657 .property
= "short_root_bus",
658 .value
= stringify(1),
661 const size_t pc_compat_1_6_len
= G_N_ELEMENTS(pc_compat_1_6
);
663 GlobalProperty pc_compat_1_5
[] = {
664 PC_CPU_MODEL_IDS("1.5.0")
666 .driver
= "Conroe-" TYPE_X86_CPU
,
668 .value
= stringify(2),
670 .driver
= "Conroe-" TYPE_X86_CPU
,
671 .property
= "min-level",
672 .value
= stringify(2),
674 .driver
= "Penryn-" TYPE_X86_CPU
,
676 .value
= stringify(2),
678 .driver
= "Penryn-" TYPE_X86_CPU
,
679 .property
= "min-level",
680 .value
= stringify(2),
682 .driver
= "Nehalem-" TYPE_X86_CPU
,
684 .value
= stringify(2),
686 .driver
= "Nehalem-" TYPE_X86_CPU
,
687 .property
= "min-level",
688 .value
= stringify(2),
690 .driver
= "virtio-net-pci",
691 .property
= "any_layout",
694 .driver
= TYPE_X86_CPU
,
698 .driver
= "i440FX-pcihost",
699 .property
= "short_root_bus",
700 .value
= stringify(0),
702 .driver
= "q35-pcihost",
703 .property
= "short_root_bus",
704 .value
= stringify(0),
707 const size_t pc_compat_1_5_len
= G_N_ELEMENTS(pc_compat_1_5
);
709 GlobalProperty pc_compat_1_4
[] = {
710 PC_CPU_MODEL_IDS("1.4.0")
713 .property
= "discard_granularity",
714 .value
= stringify(0),
717 .property
= "discard_granularity",
718 .value
= stringify(0),
720 .driver
= "scsi-disk",
721 .property
= "discard_granularity",
722 .value
= stringify(0),
725 .property
= "discard_granularity",
726 .value
= stringify(0),
729 .property
= "discard_granularity",
730 .value
= stringify(0),
732 .driver
= "ide-drive",
733 .property
= "discard_granularity",
734 .value
= stringify(0),
736 .driver
= "virtio-blk-pci",
737 .property
= "discard_granularity",
738 .value
= stringify(0),
740 .driver
= "virtio-serial-pci",
741 .property
= "vectors",
742 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */
743 .value
= stringify(0xFFFFFFFF),
745 .driver
= "virtio-net-pci",
746 .property
= "ctrl_guest_offloads",
750 .property
= "romfile",
751 .value
= "pxe-e1000.rom",
753 .driver
= "ne2k_pci",
754 .property
= "romfile",
755 .value
= "pxe-ne2k_pci.rom",
758 .property
= "romfile",
759 .value
= "pxe-pcnet.rom",
762 .property
= "romfile",
763 .value
= "pxe-rtl8139.rom",
765 .driver
= "virtio-net-pci",
766 .property
= "romfile",
767 .value
= "pxe-virtio.rom",
769 .driver
= "486-" TYPE_X86_CPU
,
771 .value
= stringify(0),
774 .driver
= "n270" "-" TYPE_X86_CPU
,
779 .driver
= "Westmere" "-" TYPE_X86_CPU
,
780 .property
= "pclmulqdq",
784 const size_t pc_compat_1_4_len
= G_N_ELEMENTS(pc_compat_1_4
);
786 void gsi_handler(void *opaque
, int n
, int level
)
788 GSIState
*s
= opaque
;
790 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
791 if (n
< ISA_NUM_IRQS
) {
792 qemu_set_irq(s
->i8259_irq
[n
], level
);
794 qemu_set_irq(s
->ioapic_irq
[n
], level
);
797 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
802 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
804 return 0xffffffffffffffffULL
;
807 /* MSDOS compatibility mode FPU exception support */
808 static qemu_irq ferr_irq
;
810 void pc_register_ferr_irq(qemu_irq irq
)
815 /* XXX: add IGNNE support */
816 void cpu_set_ferr(CPUX86State
*s
)
818 qemu_irq_raise(ferr_irq
);
821 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
824 qemu_irq_lower(ferr_irq
);
827 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
829 return 0xffffffffffffffffULL
;
833 uint64_t cpu_get_tsc(CPUX86State
*env
)
835 return cpu_get_ticks();
839 int cpu_get_pic_interrupt(CPUX86State
*env
)
841 X86CPU
*cpu
= x86_env_get_cpu(env
);
844 if (!kvm_irqchip_in_kernel()) {
845 intno
= apic_get_interrupt(cpu
->apic_state
);
849 /* read the irq from the PIC */
850 if (!apic_accept_pic_intr(cpu
->apic_state
)) {
855 intno
= pic_read_irq(isa_pic
);
859 static void pic_irq_request(void *opaque
, int irq
, int level
)
861 CPUState
*cs
= first_cpu
;
862 X86CPU
*cpu
= X86_CPU(cs
);
864 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
865 if (cpu
->apic_state
&& !kvm_irqchip_in_kernel()) {
868 if (apic_accept_pic_intr(cpu
->apic_state
)) {
869 apic_deliver_pic_intr(cpu
->apic_state
, level
);
874 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
876 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
881 /* PC cmos mappings */
883 #define REG_EQUIPMENT_BYTE 0x14
885 int cmos_get_fd_drive_type(FloppyDriveType fd0
)
890 case FLOPPY_DRIVE_TYPE_144
:
891 /* 1.44 Mb 3"5 drive */
894 case FLOPPY_DRIVE_TYPE_288
:
895 /* 2.88 Mb 3"5 drive */
898 case FLOPPY_DRIVE_TYPE_120
:
899 /* 1.2 Mb 5"5 drive */
902 case FLOPPY_DRIVE_TYPE_NONE
:
910 static void cmos_init_hd(ISADevice
*s
, int type_ofs
, int info_ofs
,
911 int16_t cylinders
, int8_t heads
, int8_t sectors
)
913 rtc_set_memory(s
, type_ofs
, 47);
914 rtc_set_memory(s
, info_ofs
, cylinders
);
915 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
916 rtc_set_memory(s
, info_ofs
+ 2, heads
);
917 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
918 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
919 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
920 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
921 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
922 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
925 /* convert boot_device letter to something recognizable by the bios */
926 static int boot_device2nibble(char boot_device
)
928 switch(boot_device
) {
931 return 0x01; /* floppy boot */
933 return 0x02; /* hard drive boot */
935 return 0x03; /* CD-ROM boot */
937 return 0x04; /* Network boot */
942 static void set_boot_dev(ISADevice
*s
, const char *boot_device
, Error
**errp
)
944 #define PC_MAX_BOOT_DEVICES 3
945 int nbds
, bds
[3] = { 0, };
948 nbds
= strlen(boot_device
);
949 if (nbds
> PC_MAX_BOOT_DEVICES
) {
950 error_setg(errp
, "Too many boot devices for PC");
953 for (i
= 0; i
< nbds
; i
++) {
954 bds
[i
] = boot_device2nibble(boot_device
[i
]);
956 error_setg(errp
, "Invalid boot device for PC: '%c'",
961 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
962 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
965 static void pc_boot_set(void *opaque
, const char *boot_device
, Error
**errp
)
967 set_boot_dev(opaque
, boot_device
, errp
);
970 static void pc_cmos_init_floppy(ISADevice
*rtc_state
, ISADevice
*floppy
)
973 FloppyDriveType fd_type
[2] = { FLOPPY_DRIVE_TYPE_NONE
,
974 FLOPPY_DRIVE_TYPE_NONE
};
978 for (i
= 0; i
< 2; i
++) {
979 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
982 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
983 cmos_get_fd_drive_type(fd_type
[1]);
984 rtc_set_memory(rtc_state
, 0x10, val
);
986 val
= rtc_get_memory(rtc_state
, REG_EQUIPMENT_BYTE
);
988 if (fd_type
[0] != FLOPPY_DRIVE_TYPE_NONE
) {
991 if (fd_type
[1] != FLOPPY_DRIVE_TYPE_NONE
) {
998 val
|= 0x01; /* 1 drive, ready for boot */
1001 val
|= 0x41; /* 2 drives, ready for boot */
1004 rtc_set_memory(rtc_state
, REG_EQUIPMENT_BYTE
, val
);
1007 typedef struct pc_cmos_init_late_arg
{
1008 ISADevice
*rtc_state
;
1009 BusState
*idebus
[2];
1010 } pc_cmos_init_late_arg
;
1012 typedef struct check_fdc_state
{
1017 static int check_fdc(Object
*obj
, void *opaque
)
1019 CheckFdcState
*state
= opaque
;
1022 Error
*local_err
= NULL
;
1024 fdc
= object_dynamic_cast(obj
, TYPE_ISA_FDC
);
1029 iobase
= object_property_get_uint(obj
, "iobase", &local_err
);
1030 if (local_err
|| iobase
!= 0x3f0) {
1031 error_free(local_err
);
1035 if (state
->floppy
) {
1036 state
->multiple
= true;
1038 state
->floppy
= ISA_DEVICE(obj
);
1043 static const char * const fdc_container_path
[] = {
1044 "/unattached", "/peripheral", "/peripheral-anon"
1048 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
1051 ISADevice
*pc_find_fdc0(void)
1055 CheckFdcState state
= { 0 };
1057 for (i
= 0; i
< ARRAY_SIZE(fdc_container_path
); i
++) {
1058 container
= container_get(qdev_get_machine(), fdc_container_path
[i
]);
1059 object_child_foreach(container
, check_fdc
, &state
);
1062 if (state
.multiple
) {
1063 warn_report("multiple floppy disk controllers with "
1064 "iobase=0x3f0 have been found");
1065 error_printf("the one being picked for CMOS setup might not reflect "
1069 return state
.floppy
;
1072 static void pc_cmos_init_late(void *opaque
)
1074 pc_cmos_init_late_arg
*arg
= opaque
;
1075 ISADevice
*s
= arg
->rtc_state
;
1077 int8_t heads
, sectors
;
1082 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 0,
1083 &cylinders
, &heads
, §ors
) >= 0) {
1084 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
1087 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 1,
1088 &cylinders
, &heads
, §ors
) >= 0) {
1089 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
1092 rtc_set_memory(s
, 0x12, val
);
1095 for (i
= 0; i
< 4; i
++) {
1096 /* NOTE: ide_get_geometry() returns the physical
1097 geometry. It is always such that: 1 <= sects <= 63, 1
1098 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
1099 geometry can be different if a translation is done. */
1100 if (arg
->idebus
[i
/ 2] &&
1101 ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
1102 &cylinders
, &heads
, §ors
) >= 0) {
1103 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
1104 assert((trans
& ~3) == 0);
1105 val
|= trans
<< (i
* 2);
1108 rtc_set_memory(s
, 0x39, val
);
1110 pc_cmos_init_floppy(s
, pc_find_fdc0());
1112 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
1115 void pc_cmos_init(PCMachineState
*pcms
,
1116 BusState
*idebus0
, BusState
*idebus1
,
1120 static pc_cmos_init_late_arg arg
;
1122 /* various important CMOS locations needed by PC/Bochs bios */
1125 /* base memory (first MiB) */
1126 val
= MIN(pcms
->below_4g_mem_size
/ KiB
, 640);
1127 rtc_set_memory(s
, 0x15, val
);
1128 rtc_set_memory(s
, 0x16, val
>> 8);
1129 /* extended memory (next 64MiB) */
1130 if (pcms
->below_4g_mem_size
> 1 * MiB
) {
1131 val
= (pcms
->below_4g_mem_size
- 1 * MiB
) / KiB
;
1137 rtc_set_memory(s
, 0x17, val
);
1138 rtc_set_memory(s
, 0x18, val
>> 8);
1139 rtc_set_memory(s
, 0x30, val
);
1140 rtc_set_memory(s
, 0x31, val
>> 8);
1141 /* memory between 16MiB and 4GiB */
1142 if (pcms
->below_4g_mem_size
> 16 * MiB
) {
1143 val
= (pcms
->below_4g_mem_size
- 16 * MiB
) / (64 * KiB
);
1149 rtc_set_memory(s
, 0x34, val
);
1150 rtc_set_memory(s
, 0x35, val
>> 8);
1151 /* memory above 4GiB */
1152 val
= pcms
->above_4g_mem_size
/ 65536;
1153 rtc_set_memory(s
, 0x5b, val
);
1154 rtc_set_memory(s
, 0x5c, val
>> 8);
1155 rtc_set_memory(s
, 0x5d, val
>> 16);
1157 object_property_add_link(OBJECT(pcms
), "rtc_state",
1159 (Object
**)&pcms
->rtc
,
1160 object_property_allow_set_link
,
1161 OBJ_PROP_LINK_STRONG
, &error_abort
);
1162 object_property_set_link(OBJECT(pcms
), OBJECT(s
),
1163 "rtc_state", &error_abort
);
1165 set_boot_dev(s
, MACHINE(pcms
)->boot_order
, &error_fatal
);
1168 val
|= 0x02; /* FPU is there */
1169 val
|= 0x04; /* PS/2 mouse installed */
1170 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
1172 /* hard drives and FDC */
1174 arg
.idebus
[0] = idebus0
;
1175 arg
.idebus
[1] = idebus1
;
1176 qemu_register_reset(pc_cmos_init_late
, &arg
);
1179 #define TYPE_PORT92 "port92"
1180 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
1182 /* port 92 stuff: could be split off */
1183 typedef struct Port92State
{
1184 ISADevice parent_obj
;
1191 static void port92_write(void *opaque
, hwaddr addr
, uint64_t val
,
1194 Port92State
*s
= opaque
;
1195 int oldval
= s
->outport
;
1197 DPRINTF("port92: write 0x%02" PRIx64
"\n", val
);
1199 qemu_set_irq(s
->a20_out
, (val
>> 1) & 1);
1200 if ((val
& 1) && !(oldval
& 1)) {
1201 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
1205 static uint64_t port92_read(void *opaque
, hwaddr addr
,
1208 Port92State
*s
= opaque
;
1212 DPRINTF("port92: read 0x%02x\n", ret
);
1216 static void port92_init(ISADevice
*dev
, qemu_irq a20_out
)
1218 qdev_connect_gpio_out_named(DEVICE(dev
), PORT92_A20_LINE
, 0, a20_out
);
1221 static const VMStateDescription vmstate_port92_isa
= {
1224 .minimum_version_id
= 1,
1225 .fields
= (VMStateField
[]) {
1226 VMSTATE_UINT8(outport
, Port92State
),
1227 VMSTATE_END_OF_LIST()
1231 static void port92_reset(DeviceState
*d
)
1233 Port92State
*s
= PORT92(d
);
1238 static const MemoryRegionOps port92_ops
= {
1239 .read
= port92_read
,
1240 .write
= port92_write
,
1242 .min_access_size
= 1,
1243 .max_access_size
= 1,
1245 .endianness
= DEVICE_LITTLE_ENDIAN
,
1248 static void port92_initfn(Object
*obj
)
1250 Port92State
*s
= PORT92(obj
);
1252 memory_region_init_io(&s
->io
, OBJECT(s
), &port92_ops
, s
, "port92", 1);
1256 qdev_init_gpio_out_named(DEVICE(obj
), &s
->a20_out
, PORT92_A20_LINE
, 1);
1259 static void port92_realizefn(DeviceState
*dev
, Error
**errp
)
1261 ISADevice
*isadev
= ISA_DEVICE(dev
);
1262 Port92State
*s
= PORT92(dev
);
1264 isa_register_ioport(isadev
, &s
->io
, 0x92);
1267 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
1269 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1271 dc
->realize
= port92_realizefn
;
1272 dc
->reset
= port92_reset
;
1273 dc
->vmsd
= &vmstate_port92_isa
;
1275 * Reason: unlike ordinary ISA devices, this one needs additional
1276 * wiring: its A20 output line needs to be wired up by
1279 dc
->user_creatable
= false;
1282 static const TypeInfo port92_info
= {
1283 .name
= TYPE_PORT92
,
1284 .parent
= TYPE_ISA_DEVICE
,
1285 .instance_size
= sizeof(Port92State
),
1286 .instance_init
= port92_initfn
,
1287 .class_init
= port92_class_initfn
,
1290 static void port92_register_types(void)
1292 type_register_static(&port92_info
);
1295 type_init(port92_register_types
)
1297 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
1299 X86CPU
*cpu
= opaque
;
1301 /* XXX: send to all CPUs ? */
1302 /* XXX: add logic to handle multiple A20 line sources */
1303 x86_cpu_set_a20(cpu
, level
);
1306 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
1308 int index
= le32_to_cpu(e820_reserve
.count
);
1309 struct e820_entry
*entry
;
1311 if (type
!= E820_RAM
) {
1312 /* old FW_CFG_E820_TABLE entry -- reservations only */
1313 if (index
>= E820_NR_ENTRIES
) {
1316 entry
= &e820_reserve
.entry
[index
++];
1318 entry
->address
= cpu_to_le64(address
);
1319 entry
->length
= cpu_to_le64(length
);
1320 entry
->type
= cpu_to_le32(type
);
1322 e820_reserve
.count
= cpu_to_le32(index
);
1325 /* new "etc/e820" file -- include ram too */
1326 e820_table
= g_renew(struct e820_entry
, e820_table
, e820_entries
+ 1);
1327 e820_table
[e820_entries
].address
= cpu_to_le64(address
);
1328 e820_table
[e820_entries
].length
= cpu_to_le64(length
);
1329 e820_table
[e820_entries
].type
= cpu_to_le32(type
);
1332 return e820_entries
;
1335 int e820_get_num_entries(void)
1337 return e820_entries
;
1340 bool e820_get_entry(int idx
, uint32_t type
, uint64_t *address
, uint64_t *length
)
1342 if (idx
< e820_entries
&& e820_table
[idx
].type
== cpu_to_le32(type
)) {
1343 *address
= le64_to_cpu(e820_table
[idx
].address
);
1344 *length
= le64_to_cpu(e820_table
[idx
].length
);
1350 /* Enables contiguous-apic-ID mode, for compatibility */
1351 static bool compat_apic_id_mode
;
1353 void enable_compat_apic_id_mode(void)
1355 compat_apic_id_mode
= true;
1358 /* Calculates initial APIC ID for a specific CPU index
1360 * Currently we need to be able to calculate the APIC ID from the CPU index
1361 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
1362 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
1363 * all CPUs up to max_cpus.
1365 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index
)
1367 uint32_t correct_id
;
1370 correct_id
= x86_apicid_from_cpu_idx(smp_cores
, smp_threads
, cpu_index
);
1371 if (compat_apic_id_mode
) {
1372 if (cpu_index
!= correct_id
&& !warned
&& !qtest_enabled()) {
1373 error_report("APIC IDs set in compatibility mode, "
1374 "CPU topology won't match the configuration");
1383 static void pc_build_smbios(PCMachineState
*pcms
)
1385 uint8_t *smbios_tables
, *smbios_anchor
;
1386 size_t smbios_tables_len
, smbios_anchor_len
;
1387 struct smbios_phys_mem_area
*mem_array
;
1388 unsigned i
, array_count
;
1389 MachineState
*ms
= MACHINE(pcms
);
1390 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
1392 /* tell smbios about cpuid version and features */
1393 smbios_set_cpuid(cpu
->env
.cpuid_version
, cpu
->env
.features
[FEAT_1_EDX
]);
1395 smbios_tables
= smbios_get_table_legacy(&smbios_tables_len
);
1396 if (smbios_tables
) {
1397 fw_cfg_add_bytes(pcms
->fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
1398 smbios_tables
, smbios_tables_len
);
1401 /* build the array of physical mem area from e820 table */
1402 mem_array
= g_malloc0(sizeof(*mem_array
) * e820_get_num_entries());
1403 for (i
= 0, array_count
= 0; i
< e820_get_num_entries(); i
++) {
1406 if (e820_get_entry(i
, E820_RAM
, &addr
, &len
)) {
1407 mem_array
[array_count
].address
= addr
;
1408 mem_array
[array_count
].length
= len
;
1412 smbios_get_tables(mem_array
, array_count
,
1413 &smbios_tables
, &smbios_tables_len
,
1414 &smbios_anchor
, &smbios_anchor_len
);
1417 if (smbios_anchor
) {
1418 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-tables",
1419 smbios_tables
, smbios_tables_len
);
1420 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-anchor",
1421 smbios_anchor
, smbios_anchor_len
);
1425 static FWCfgState
*bochs_bios_init(AddressSpace
*as
, PCMachineState
*pcms
)
1428 uint64_t *numa_fw_cfg
;
1430 const CPUArchIdList
*cpus
;
1431 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
1433 fw_cfg
= fw_cfg_init_io_dma(FW_CFG_IO_BASE
, FW_CFG_IO_BASE
+ 4, as
);
1434 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1436 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
1438 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
1439 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
1440 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
1441 * for CPU hotplug also uses APIC ID and not "CPU index".
1442 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
1443 * but the "limit to the APIC ID values SeaBIOS may see".
1445 * So for compatibility reasons with old BIOSes we are stuck with
1446 * "etc/max-cpus" actually being apic_id_limit
1448 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)pcms
->apic_id_limit
);
1449 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1450 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
,
1451 acpi_tables
, acpi_tables_len
);
1452 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
1454 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
,
1455 &e820_reserve
, sizeof(e820_reserve
));
1456 fw_cfg_add_file(fw_cfg
, "etc/e820", e820_table
,
1457 sizeof(struct e820_entry
) * e820_entries
);
1459 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, &hpet_cfg
, sizeof(hpet_cfg
));
1460 /* allocate memory for the NUMA channel: one (64bit) word for the number
1461 * of nodes, one word for each VCPU->node and one word for each node to
1462 * hold the amount of memory.
1464 numa_fw_cfg
= g_new0(uint64_t, 1 + pcms
->apic_id_limit
+ nb_numa_nodes
);
1465 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
1466 cpus
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
1467 for (i
= 0; i
< cpus
->len
; i
++) {
1468 unsigned int apic_id
= cpus
->cpus
[i
].arch_id
;
1469 assert(apic_id
< pcms
->apic_id_limit
);
1470 numa_fw_cfg
[apic_id
+ 1] = cpu_to_le64(cpus
->cpus
[i
].props
.node_id
);
1472 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1473 numa_fw_cfg
[pcms
->apic_id_limit
+ 1 + i
] =
1474 cpu_to_le64(numa_info
[i
].node_mem
);
1476 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, numa_fw_cfg
,
1477 (1 + pcms
->apic_id_limit
+ nb_numa_nodes
) *
1478 sizeof(*numa_fw_cfg
));
1483 static long get_file_size(FILE *f
)
1487 /* XXX: on Unix systems, using fstat() probably makes more sense */
1490 fseek(f
, 0, SEEK_END
);
1492 fseek(f
, where
, SEEK_SET
);
1497 /* setup_data types */
1498 #define SETUP_NONE 0
1499 #define SETUP_E820_EXT 1
1509 } __attribute__((packed
));
1511 static void load_linux(PCMachineState
*pcms
,
1515 int setup_size
, kernel_size
, cmdline_size
;
1516 int dtb_size
, setup_data_offset
;
1517 uint32_t initrd_max
;
1518 uint8_t header
[8192], *setup
, *kernel
;
1519 hwaddr real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
1522 MachineState
*machine
= MACHINE(pcms
);
1523 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1524 struct setup_data
*setup_data
;
1525 const char *kernel_filename
= machine
->kernel_filename
;
1526 const char *initrd_filename
= machine
->initrd_filename
;
1527 const char *dtb_filename
= machine
->dtb
;
1528 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1530 /* Align to 16 bytes as a paranoia measure */
1531 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
1533 /* load the kernel header */
1534 f
= fopen(kernel_filename
, "rb");
1535 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
1536 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
1537 MIN(ARRAY_SIZE(header
), kernel_size
)) {
1538 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
1539 kernel_filename
, strerror(errno
));
1543 /* kernel protocol version */
1545 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
1547 if (ldl_p(header
+0x202) == 0x53726448) {
1548 protocol
= lduw_p(header
+0x206);
1550 /* This looks like a multiboot kernel. If it is, let's stop
1551 treating it like a Linux kernel. */
1552 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
1553 kernel_cmdline
, kernel_size
, header
)) {
1559 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
1561 real_addr
= 0x90000;
1562 cmdline_addr
= 0x9a000 - cmdline_size
;
1563 prot_addr
= 0x10000;
1564 } else if (protocol
< 0x202) {
1565 /* High but ancient kernel */
1566 real_addr
= 0x90000;
1567 cmdline_addr
= 0x9a000 - cmdline_size
;
1568 prot_addr
= 0x100000;
1570 /* High and recent kernel */
1571 real_addr
= 0x10000;
1572 cmdline_addr
= 0x20000;
1573 prot_addr
= 0x100000;
1578 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
1579 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
1580 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
1586 /* highest address for loading the initrd */
1587 if (protocol
>= 0x203) {
1588 initrd_max
= ldl_p(header
+0x22c);
1590 initrd_max
= 0x37ffffff;
1593 if (initrd_max
>= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
) {
1594 initrd_max
= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
- 1;
1597 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
1598 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
1599 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
1601 if (protocol
>= 0x202) {
1602 stl_p(header
+0x228, cmdline_addr
);
1604 stw_p(header
+0x20, 0xA33F);
1605 stw_p(header
+0x22, cmdline_addr
-real_addr
);
1608 /* handle vga= parameter */
1609 vmode
= strstr(kernel_cmdline
, "vga=");
1611 unsigned int video_mode
;
1614 if (!strncmp(vmode
, "normal", 6)) {
1615 video_mode
= 0xffff;
1616 } else if (!strncmp(vmode
, "ext", 3)) {
1617 video_mode
= 0xfffe;
1618 } else if (!strncmp(vmode
, "ask", 3)) {
1619 video_mode
= 0xfffd;
1621 video_mode
= strtol(vmode
, NULL
, 0);
1623 stw_p(header
+0x1fa, video_mode
);
1627 /* High nybble = B reserved for QEMU; low nybble is revision number.
1628 If this code is substantially changed, you may want to consider
1629 incrementing the revision. */
1630 if (protocol
>= 0x200) {
1631 header
[0x210] = 0xB0;
1634 if (protocol
>= 0x201) {
1635 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
1636 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
1640 if (initrd_filename
) {
1643 GError
*gerr
= NULL
;
1645 if (protocol
< 0x200) {
1646 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
1650 if (!g_file_get_contents(initrd_filename
, &initrd_data
,
1651 &initrd_size
, &gerr
)) {
1652 fprintf(stderr
, "qemu: error reading initrd %s: %s\n",
1653 initrd_filename
, gerr
->message
);
1656 if (initrd_size
>= initrd_max
) {
1657 fprintf(stderr
, "qemu: initrd is too large, cannot support."
1658 "(max: %"PRIu32
", need %"PRId64
")\n",
1659 initrd_max
, (uint64_t)initrd_size
);
1663 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
1665 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
1666 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
1667 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
1669 stl_p(header
+0x218, initrd_addr
);
1670 stl_p(header
+0x21c, initrd_size
);
1673 /* load kernel and setup */
1674 setup_size
= header
[0x1f1];
1675 if (setup_size
== 0) {
1678 setup_size
= (setup_size
+1)*512;
1679 if (setup_size
> kernel_size
) {
1680 fprintf(stderr
, "qemu: invalid kernel header\n");
1683 kernel_size
-= setup_size
;
1685 setup
= g_malloc(setup_size
);
1686 kernel
= g_malloc(kernel_size
);
1687 fseek(f
, 0, SEEK_SET
);
1688 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
1689 fprintf(stderr
, "fread() failed\n");
1692 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
1693 fprintf(stderr
, "fread() failed\n");
1698 /* append dtb to kernel */
1700 if (protocol
< 0x209) {
1701 fprintf(stderr
, "qemu: Linux kernel too old to load a dtb\n");
1705 dtb_size
= get_image_size(dtb_filename
);
1706 if (dtb_size
<= 0) {
1707 fprintf(stderr
, "qemu: error reading dtb %s: %s\n",
1708 dtb_filename
, strerror(errno
));
1712 setup_data_offset
= QEMU_ALIGN_UP(kernel_size
, 16);
1713 kernel_size
= setup_data_offset
+ sizeof(struct setup_data
) + dtb_size
;
1714 kernel
= g_realloc(kernel
, kernel_size
);
1716 stq_p(header
+0x250, prot_addr
+ setup_data_offset
);
1718 setup_data
= (struct setup_data
*)(kernel
+ setup_data_offset
);
1719 setup_data
->next
= 0;
1720 setup_data
->type
= cpu_to_le32(SETUP_DTB
);
1721 setup_data
->len
= cpu_to_le32(dtb_size
);
1723 load_image_size(dtb_filename
, setup_data
->data
, dtb_size
);
1726 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
1728 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
1729 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1730 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
1732 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
1733 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
1734 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
1736 option_rom
[nb_option_roms
].bootindex
= 0;
1737 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
1738 if (pcmc
->linuxboot_dma_enabled
&& fw_cfg_dma_enabled(fw_cfg
)) {
1739 option_rom
[nb_option_roms
].name
= "linuxboot_dma.bin";
1744 #define NE2000_NB_MAX 6
1746 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
1748 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
1750 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
1752 static int nb_ne2k
= 0;
1754 if (nb_ne2k
== NE2000_NB_MAX
)
1756 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
1757 ne2000_irq
[nb_ne2k
], nd
);
1761 DeviceState
*cpu_get_current_apic(void)
1764 X86CPU
*cpu
= X86_CPU(current_cpu
);
1765 return cpu
->apic_state
;
1771 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
1773 X86CPU
*cpu
= opaque
;
1776 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
1780 static void pc_new_cpu(const char *typename
, int64_t apic_id
, Error
**errp
)
1783 Error
*local_err
= NULL
;
1785 cpu
= object_new(typename
);
1787 object_property_set_uint(cpu
, apic_id
, "apic-id", &local_err
);
1788 object_property_set_bool(cpu
, true, "realized", &local_err
);
1791 error_propagate(errp
, local_err
);
1794 void pc_hot_add_cpu(const int64_t id
, Error
**errp
)
1796 MachineState
*ms
= MACHINE(qdev_get_machine());
1797 int64_t apic_id
= x86_cpu_apic_id_from_index(id
);
1798 Error
*local_err
= NULL
;
1801 error_setg(errp
, "Invalid CPU id: %" PRIi64
, id
);
1805 if (apic_id
>= ACPI_CPU_HOTPLUG_ID_LIMIT
) {
1806 error_setg(errp
, "Unable to add CPU: %" PRIi64
1807 ", resulting APIC ID (%" PRIi64
") is too large",
1812 pc_new_cpu(ms
->cpu_type
, apic_id
, &local_err
);
1814 error_propagate(errp
, local_err
);
1819 void pc_cpus_init(PCMachineState
*pcms
)
1822 const CPUArchIdList
*possible_cpus
;
1823 MachineState
*ms
= MACHINE(pcms
);
1824 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
1826 /* Calculates the limit to CPU APIC ID values
1828 * Limit for the APIC ID value, so that all
1829 * CPU APIC IDs are < pcms->apic_id_limit.
1831 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1833 pcms
->apic_id_limit
= x86_cpu_apic_id_from_index(max_cpus
- 1) + 1;
1834 possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
1835 for (i
= 0; i
< smp_cpus
; i
++) {
1836 pc_new_cpu(possible_cpus
->cpus
[i
].type
, possible_cpus
->cpus
[i
].arch_id
,
1841 static void pc_build_feature_control_file(PCMachineState
*pcms
)
1843 MachineState
*ms
= MACHINE(pcms
);
1844 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
1845 CPUX86State
*env
= &cpu
->env
;
1846 uint32_t unused
, ecx
, edx
;
1847 uint64_t feature_control_bits
= 0;
1850 cpu_x86_cpuid(env
, 1, 0, &unused
, &unused
, &ecx
, &edx
);
1851 if (ecx
& CPUID_EXT_VMX
) {
1852 feature_control_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
1855 if ((edx
& (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
)) ==
1856 (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
) &&
1857 (env
->mcg_cap
& MCG_LMCE_P
)) {
1858 feature_control_bits
|= FEATURE_CONTROL_LMCE
;
1861 if (!feature_control_bits
) {
1865 val
= g_malloc(sizeof(*val
));
1866 *val
= cpu_to_le64(feature_control_bits
| FEATURE_CONTROL_LOCKED
);
1867 fw_cfg_add_file(pcms
->fw_cfg
, "etc/msr_feature_control", val
, sizeof(*val
));
1870 static void rtc_set_cpus_count(ISADevice
*rtc
, uint16_t cpus_count
)
1872 if (cpus_count
> 0xff) {
1873 /* If the number of CPUs can't be represented in 8 bits, the
1874 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1875 * to make old BIOSes fail more predictably.
1877 rtc_set_memory(rtc
, 0x5f, 0);
1879 rtc_set_memory(rtc
, 0x5f, cpus_count
- 1);
1884 void pc_machine_done(Notifier
*notifier
, void *data
)
1886 PCMachineState
*pcms
= container_of(notifier
,
1887 PCMachineState
, machine_done
);
1888 PCIBus
*bus
= pcms
->bus
;
1890 /* set the number of CPUs */
1891 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1894 int extra_hosts
= 0;
1896 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1897 /* look for expander root buses */
1898 if (pci_bus_is_root(bus
)) {
1902 if (extra_hosts
&& pcms
->fw_cfg
) {
1903 uint64_t *val
= g_malloc(sizeof(*val
));
1904 *val
= cpu_to_le64(extra_hosts
);
1905 fw_cfg_add_file(pcms
->fw_cfg
,
1906 "etc/extra-pci-roots", val
, sizeof(*val
));
1912 pc_build_smbios(pcms
);
1913 pc_build_feature_control_file(pcms
);
1914 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1915 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1918 if (pcms
->apic_id_limit
> 255 && !xen_enabled()) {
1919 IntelIOMMUState
*iommu
= INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1921 if (!iommu
|| !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu
)) ||
1922 iommu
->intr_eim
!= ON_OFF_AUTO_ON
) {
1923 error_report("current -smp configuration requires "
1924 "Extended Interrupt Mode enabled. "
1925 "You can add an IOMMU using: "
1926 "-device intel-iommu,intremap=on,eim=on");
1932 void pc_guest_info_init(PCMachineState
*pcms
)
1936 pcms
->apic_xrupt_override
= kvm_allows_irq0_override();
1937 pcms
->numa_nodes
= nb_numa_nodes
;
1938 pcms
->node_mem
= g_malloc0(pcms
->numa_nodes
*
1939 sizeof *pcms
->node_mem
);
1940 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1941 pcms
->node_mem
[i
] = numa_info
[i
].node_mem
;
1944 pcms
->machine_done
.notify
= pc_machine_done
;
1945 qemu_add_machine_init_done_notifier(&pcms
->machine_done
);
1948 /* setup pci memory address space mapping into system address space */
1949 void pc_pci_as_mapping_init(Object
*owner
, MemoryRegion
*system_memory
,
1950 MemoryRegion
*pci_address_space
)
1952 /* Set to lower priority than RAM */
1953 memory_region_add_subregion_overlap(system_memory
, 0x0,
1954 pci_address_space
, -1);
1957 void pc_acpi_init(const char *default_dsdt
)
1961 if (acpi_tables
!= NULL
) {
1962 /* manually set via -acpitable, leave it alone */
1966 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, default_dsdt
);
1967 if (filename
== NULL
) {
1968 warn_report("failed to find %s", default_dsdt
);
1970 QemuOpts
*opts
= qemu_opts_create(qemu_find_opts("acpi"), NULL
, 0,
1974 qemu_opt_set(opts
, "file", filename
, &error_abort
);
1976 acpi_table_add_builtin(opts
, &err
);
1978 warn_reportf_err(err
, "failed to load %s: ", filename
);
1984 void xen_load_linux(PCMachineState
*pcms
)
1989 assert(MACHINE(pcms
)->kernel_filename
!= NULL
);
1991 fw_cfg
= fw_cfg_init_io(FW_CFG_IO_BASE
);
1992 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1995 load_linux(pcms
, fw_cfg
);
1996 for (i
= 0; i
< nb_option_roms
; i
++) {
1997 assert(!strcmp(option_rom
[i
].name
, "linuxboot.bin") ||
1998 !strcmp(option_rom
[i
].name
, "linuxboot_dma.bin") ||
1999 !strcmp(option_rom
[i
].name
, "multiboot.bin"));
2000 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
2002 pcms
->fw_cfg
= fw_cfg
;
2005 void pc_memory_init(PCMachineState
*pcms
,
2006 MemoryRegion
*system_memory
,
2007 MemoryRegion
*rom_memory
,
2008 MemoryRegion
**ram_memory
)
2011 MemoryRegion
*ram
, *option_rom_mr
;
2012 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
2014 MachineState
*machine
= MACHINE(pcms
);
2015 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2017 assert(machine
->ram_size
== pcms
->below_4g_mem_size
+
2018 pcms
->above_4g_mem_size
);
2020 linux_boot
= (machine
->kernel_filename
!= NULL
);
2022 /* Allocate RAM. We allocate it as a single memory region and use
2023 * aliases to address portions of it, mostly for backwards compatibility
2024 * with older qemus that used qemu_ram_alloc().
2026 ram
= g_malloc(sizeof(*ram
));
2027 memory_region_allocate_system_memory(ram
, NULL
, "pc.ram",
2030 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
2031 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", ram
,
2032 0, pcms
->below_4g_mem_size
);
2033 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
2034 e820_add_entry(0, pcms
->below_4g_mem_size
, E820_RAM
);
2035 if (pcms
->above_4g_mem_size
> 0) {
2036 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
2037 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g", ram
,
2038 pcms
->below_4g_mem_size
,
2039 pcms
->above_4g_mem_size
);
2040 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
2042 e820_add_entry(0x100000000ULL
, pcms
->above_4g_mem_size
, E820_RAM
);
2045 if (!pcmc
->has_reserved_memory
&&
2046 (machine
->ram_slots
||
2047 (machine
->maxram_size
> machine
->ram_size
))) {
2048 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2050 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
2055 /* always allocate the device memory information */
2056 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2058 /* initialize device memory address space */
2059 if (pcmc
->has_reserved_memory
&&
2060 (machine
->ram_size
< machine
->maxram_size
)) {
2061 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2063 if (machine
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
2064 error_report("unsupported amount of memory slots: %"PRIu64
,
2065 machine
->ram_slots
);
2069 if (QEMU_ALIGN_UP(machine
->maxram_size
,
2070 TARGET_PAGE_SIZE
) != machine
->maxram_size
) {
2071 error_report("maximum memory size must by aligned to multiple of "
2072 "%d bytes", TARGET_PAGE_SIZE
);
2076 machine
->device_memory
->base
=
2077 ROUND_UP(0x100000000ULL
+ pcms
->above_4g_mem_size
, 1 * GiB
);
2079 if (pcmc
->enforce_aligned_dimm
) {
2080 /* size device region assuming 1G page max alignment per slot */
2081 device_mem_size
+= (1 * GiB
) * machine
->ram_slots
;
2084 if ((machine
->device_memory
->base
+ device_mem_size
) <
2086 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT
,
2087 machine
->maxram_size
);
2091 memory_region_init(&machine
->device_memory
->mr
, OBJECT(pcms
),
2092 "device-memory", device_mem_size
);
2093 memory_region_add_subregion(system_memory
, machine
->device_memory
->base
,
2094 &machine
->device_memory
->mr
);
2097 /* Initialize PC system firmware */
2098 pc_system_firmware_init(rom_memory
, !pcmc
->pci_enabled
);
2100 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
2101 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
,
2103 if (pcmc
->pci_enabled
) {
2104 memory_region_set_readonly(option_rom_mr
, true);
2106 memory_region_add_subregion_overlap(rom_memory
,
2111 fw_cfg
= bochs_bios_init(&address_space_memory
, pcms
);
2115 if (pcmc
->has_reserved_memory
&& machine
->device_memory
->base
) {
2116 uint64_t *val
= g_malloc(sizeof(*val
));
2117 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2118 uint64_t res_mem_end
= machine
->device_memory
->base
;
2120 if (!pcmc
->broken_reserved_end
) {
2121 res_mem_end
+= memory_region_size(&machine
->device_memory
->mr
);
2123 *val
= cpu_to_le64(ROUND_UP(res_mem_end
, 1 * GiB
));
2124 fw_cfg_add_file(fw_cfg
, "etc/reserved-memory-end", val
, sizeof(*val
));
2128 load_linux(pcms
, fw_cfg
);
2131 for (i
= 0; i
< nb_option_roms
; i
++) {
2132 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
2134 pcms
->fw_cfg
= fw_cfg
;
2136 /* Init default IOAPIC address space */
2137 pcms
->ioapic_as
= &address_space_memory
;
2141 * The 64bit pci hole starts after "above 4G RAM" and
2142 * potentially the space reserved for memory hotplug.
2144 uint64_t pc_pci_hole64_start(void)
2146 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
2147 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2148 MachineState
*ms
= MACHINE(pcms
);
2149 uint64_t hole64_start
= 0;
2151 if (pcmc
->has_reserved_memory
&& ms
->device_memory
->base
) {
2152 hole64_start
= ms
->device_memory
->base
;
2153 if (!pcmc
->broken_reserved_end
) {
2154 hole64_start
+= memory_region_size(&ms
->device_memory
->mr
);
2157 hole64_start
= 0x100000000ULL
+ pcms
->above_4g_mem_size
;
2160 return ROUND_UP(hole64_start
, 1 * GiB
);
2163 qemu_irq
pc_allocate_cpu_irq(void)
2165 return qemu_allocate_irq(pic_irq_request
, NULL
, 0);
2168 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
2170 DeviceState
*dev
= NULL
;
2172 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA
);
2174 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
2175 dev
= pcidev
? &pcidev
->qdev
: NULL
;
2176 } else if (isa_bus
) {
2177 ISADevice
*isadev
= isa_vga_init(isa_bus
);
2178 dev
= isadev
? DEVICE(isadev
) : NULL
;
2180 rom_reset_order_override();
2184 static const MemoryRegionOps ioport80_io_ops
= {
2185 .write
= ioport80_write
,
2186 .read
= ioport80_read
,
2187 .endianness
= DEVICE_NATIVE_ENDIAN
,
2189 .min_access_size
= 1,
2190 .max_access_size
= 1,
2194 static const MemoryRegionOps ioportF0_io_ops
= {
2195 .write
= ioportF0_write
,
2196 .read
= ioportF0_read
,
2197 .endianness
= DEVICE_NATIVE_ENDIAN
,
2199 .min_access_size
= 1,
2200 .max_access_size
= 1,
2204 static void pc_superio_init(ISABus
*isa_bus
, bool create_fdctrl
, bool no_vmport
)
2207 DriveInfo
*fd
[MAX_FD
];
2209 ISADevice
*i8042
, *port92
, *vmmouse
;
2211 serial_hds_isa_init(isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
2212 parallel_hds_isa_init(isa_bus
, MAX_PARALLEL_PORTS
);
2214 for (i
= 0; i
< MAX_FD
; i
++) {
2215 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
2216 create_fdctrl
|= !!fd
[i
];
2218 if (create_fdctrl
) {
2219 fdctrl_init_isa(isa_bus
, fd
);
2222 i8042
= isa_create_simple(isa_bus
, "i8042");
2224 vmport_init(isa_bus
);
2225 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
2230 DeviceState
*dev
= DEVICE(vmmouse
);
2231 qdev_prop_set_ptr(dev
, "ps2_mouse", i8042
);
2232 qdev_init_nofail(dev
);
2234 port92
= isa_create_simple(isa_bus
, "port92");
2236 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
2237 i8042_setup_a20_line(i8042
, a20_line
[0]);
2238 port92_init(port92
, a20_line
[1]);
2242 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
2243 ISADevice
**rtc_state
,
2250 DeviceState
*hpet
= NULL
;
2251 int pit_isa_irq
= 0;
2252 qemu_irq pit_alt_irq
= NULL
;
2253 qemu_irq rtc_irq
= NULL
;
2254 ISADevice
*pit
= NULL
;
2255 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
2256 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
2258 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
2259 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
2261 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
2262 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
2265 * Check if an HPET shall be created.
2267 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
2268 * when the HPET wants to take over. Thus we have to disable the latter.
2270 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
2271 /* In order to set property, here not using sysbus_try_create_simple */
2272 hpet
= qdev_try_create(NULL
, TYPE_HPET
);
2274 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
2275 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
2278 uint8_t compat
= object_property_get_uint(OBJECT(hpet
),
2281 qdev_prop_set_uint32(hpet
, HPET_INTCAP
, hpet_irqs
);
2283 qdev_init_nofail(hpet
);
2284 sysbus_mmio_map(SYS_BUS_DEVICE(hpet
), 0, HPET_BASE
);
2286 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
2287 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
2290 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
2291 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
2294 *rtc_state
= mc146818_rtc_init(isa_bus
, 2000, rtc_irq
);
2296 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
2298 if (!xen_enabled() && has_pit
) {
2299 if (kvm_pit_in_kernel()) {
2300 pit
= kvm_pit_init(isa_bus
, 0x40);
2302 pit
= i8254_pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
2305 /* connect PIT to output control line of the HPET */
2306 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
2308 pcspk_init(isa_bus
, pit
);
2311 i8257_dma_init(isa_bus
, 0);
2314 pc_superio_init(isa_bus
, create_fdctrl
, no_vmport
);
2317 void pc_nic_init(PCMachineClass
*pcmc
, ISABus
*isa_bus
, PCIBus
*pci_bus
)
2321 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC
);
2322 for (i
= 0; i
< nb_nics
; i
++) {
2323 NICInfo
*nd
= &nd_table
[i
];
2324 const char *model
= nd
->model
? nd
->model
: pcmc
->default_nic_model
;
2326 if (g_str_equal(model
, "ne2k_isa")) {
2327 pc_init_ne2k_isa(isa_bus
, nd
);
2329 pci_nic_init_nofail(nd
, pci_bus
, model
, NULL
);
2332 rom_reset_order_override();
2335 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
)
2341 if (kvm_ioapic_in_kernel()) {
2342 dev
= qdev_create(NULL
, TYPE_KVM_IOAPIC
);
2344 dev
= qdev_create(NULL
, TYPE_IOAPIC
);
2347 object_property_add_child(object_resolve_path(parent_name
, NULL
),
2348 "ioapic", OBJECT(dev
), NULL
);
2350 qdev_init_nofail(dev
);
2351 d
= SYS_BUS_DEVICE(dev
);
2352 sysbus_mmio_map(d
, 0, IO_APIC_DEFAULT_ADDRESS
);
2354 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
2355 gsi_state
->ioapic_irq
[i
] = qdev_get_gpio_in(dev
, i
);
2359 static void pc_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2362 const PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2363 const PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2364 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2365 const uint64_t legacy_align
= TARGET_PAGE_SIZE
;
2368 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2369 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2370 * addition to cover this case.
2372 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
2374 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2378 if (is_nvdimm
&& !pcms
->acpi_nvdimm_state
.is_enabled
) {
2379 error_setg(errp
, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
2383 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
),
2384 pcmc
->enforce_aligned_dimm
? NULL
: &legacy_align
, errp
);
2387 static void pc_memory_plug(HotplugHandler
*hotplug_dev
,
2388 DeviceState
*dev
, Error
**errp
)
2390 HotplugHandlerClass
*hhc
;
2391 Error
*local_err
= NULL
;
2392 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2393 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2395 pc_dimm_plug(PC_DIMM(dev
), MACHINE(pcms
), &local_err
);
2401 nvdimm_plug(&pcms
->acpi_nvdimm_state
);
2404 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
2405 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &error_abort
);
2407 error_propagate(errp
, local_err
);
2410 static void pc_memory_unplug_request(HotplugHandler
*hotplug_dev
,
2411 DeviceState
*dev
, Error
**errp
)
2413 HotplugHandlerClass
*hhc
;
2414 Error
*local_err
= NULL
;
2415 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2418 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2419 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2420 * addition to cover this case.
2422 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
2423 error_setg(&local_err
,
2424 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2428 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2429 error_setg(&local_err
,
2430 "nvdimm device hot unplug is not supported yet.");
2434 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
2435 hhc
->unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2438 error_propagate(errp
, local_err
);
2441 static void pc_memory_unplug(HotplugHandler
*hotplug_dev
,
2442 DeviceState
*dev
, Error
**errp
)
2444 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2445 HotplugHandlerClass
*hhc
;
2446 Error
*local_err
= NULL
;
2448 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
2449 hhc
->unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2455 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(pcms
));
2456 object_unparent(OBJECT(dev
));
2459 error_propagate(errp
, local_err
);
2462 static int pc_apic_cmp(const void *a
, const void *b
)
2464 CPUArchId
*apic_a
= (CPUArchId
*)a
;
2465 CPUArchId
*apic_b
= (CPUArchId
*)b
;
2467 return apic_a
->arch_id
- apic_b
->arch_id
;
2470 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
2471 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
2472 * entry corresponding to CPU's apic_id returns NULL.
2474 static CPUArchId
*pc_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2476 CPUArchId apic_id
, *found_cpu
;
2478 apic_id
.arch_id
= id
;
2479 found_cpu
= bsearch(&apic_id
, ms
->possible_cpus
->cpus
,
2480 ms
->possible_cpus
->len
, sizeof(*ms
->possible_cpus
->cpus
),
2482 if (found_cpu
&& idx
) {
2483 *idx
= found_cpu
- ms
->possible_cpus
->cpus
;
2488 static void pc_cpu_plug(HotplugHandler
*hotplug_dev
,
2489 DeviceState
*dev
, Error
**errp
)
2491 CPUArchId
*found_cpu
;
2492 HotplugHandlerClass
*hhc
;
2493 Error
*local_err
= NULL
;
2494 X86CPU
*cpu
= X86_CPU(dev
);
2495 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2497 if (pcms
->acpi_dev
) {
2498 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
2499 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2505 /* increment the number of CPUs */
2508 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
2511 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
2514 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
2515 found_cpu
->cpu
= OBJECT(dev
);
2517 error_propagate(errp
, local_err
);
2519 static void pc_cpu_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2520 DeviceState
*dev
, Error
**errp
)
2523 HotplugHandlerClass
*hhc
;
2524 Error
*local_err
= NULL
;
2525 X86CPU
*cpu
= X86_CPU(dev
);
2526 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2528 if (!pcms
->acpi_dev
) {
2529 error_setg(&local_err
, "CPU hot unplug not supported without ACPI");
2533 pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
2536 error_setg(&local_err
, "Boot CPU is unpluggable");
2540 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
2541 hhc
->unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2548 error_propagate(errp
, local_err
);
2552 static void pc_cpu_unplug_cb(HotplugHandler
*hotplug_dev
,
2553 DeviceState
*dev
, Error
**errp
)
2555 CPUArchId
*found_cpu
;
2556 HotplugHandlerClass
*hhc
;
2557 Error
*local_err
= NULL
;
2558 X86CPU
*cpu
= X86_CPU(dev
);
2559 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2561 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
2562 hhc
->unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2568 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
2569 found_cpu
->cpu
= NULL
;
2570 object_unparent(OBJECT(dev
));
2572 /* decrement the number of CPUs */
2574 /* Update the number of CPUs in CMOS */
2575 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
2576 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
2578 error_propagate(errp
, local_err
);
2581 static void pc_cpu_pre_plug(HotplugHandler
*hotplug_dev
,
2582 DeviceState
*dev
, Error
**errp
)
2586 CPUArchId
*cpu_slot
;
2587 X86CPUTopoInfo topo
;
2588 X86CPU
*cpu
= X86_CPU(dev
);
2589 MachineState
*ms
= MACHINE(hotplug_dev
);
2590 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2592 if(!object_dynamic_cast(OBJECT(cpu
), ms
->cpu_type
)) {
2593 error_setg(errp
, "Invalid CPU type, expected cpu type: '%s'",
2598 /* if APIC ID is not set, set it based on socket/core/thread properties */
2599 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
2600 int max_socket
= (max_cpus
- 1) / smp_threads
/ smp_cores
;
2602 if (cpu
->socket_id
< 0) {
2603 error_setg(errp
, "CPU socket-id is not set");
2605 } else if (cpu
->socket_id
> max_socket
) {
2606 error_setg(errp
, "Invalid CPU socket-id: %u must be in range 0:%u",
2607 cpu
->socket_id
, max_socket
);
2610 if (cpu
->core_id
< 0) {
2611 error_setg(errp
, "CPU core-id is not set");
2613 } else if (cpu
->core_id
> (smp_cores
- 1)) {
2614 error_setg(errp
, "Invalid CPU core-id: %u must be in range 0:%u",
2615 cpu
->core_id
, smp_cores
- 1);
2618 if (cpu
->thread_id
< 0) {
2619 error_setg(errp
, "CPU thread-id is not set");
2621 } else if (cpu
->thread_id
> (smp_threads
- 1)) {
2622 error_setg(errp
, "Invalid CPU thread-id: %u must be in range 0:%u",
2623 cpu
->thread_id
, smp_threads
- 1);
2627 topo
.pkg_id
= cpu
->socket_id
;
2628 topo
.core_id
= cpu
->core_id
;
2629 topo
.smt_id
= cpu
->thread_id
;
2630 cpu
->apic_id
= apicid_from_topo_ids(smp_cores
, smp_threads
, &topo
);
2633 cpu_slot
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
2635 MachineState
*ms
= MACHINE(pcms
);
2637 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
2638 error_setg(errp
, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
2639 " APIC ID %" PRIu32
", valid index range 0:%d",
2640 topo
.pkg_id
, topo
.core_id
, topo
.smt_id
, cpu
->apic_id
,
2641 ms
->possible_cpus
->len
- 1);
2645 if (cpu_slot
->cpu
) {
2646 error_setg(errp
, "CPU[%d] with APIC ID %" PRIu32
" exists",
2651 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
2652 * so that machine_query_hotpluggable_cpus would show correct values
2654 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2655 * once -smp refactoring is complete and there will be CPU private
2656 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2657 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
2658 if (cpu
->socket_id
!= -1 && cpu
->socket_id
!= topo
.pkg_id
) {
2659 error_setg(errp
, "property socket-id: %u doesn't match set apic-id:"
2660 " 0x%x (socket-id: %u)", cpu
->socket_id
, cpu
->apic_id
, topo
.pkg_id
);
2663 cpu
->socket_id
= topo
.pkg_id
;
2665 if (cpu
->core_id
!= -1 && cpu
->core_id
!= topo
.core_id
) {
2666 error_setg(errp
, "property core-id: %u doesn't match set apic-id:"
2667 " 0x%x (core-id: %u)", cpu
->core_id
, cpu
->apic_id
, topo
.core_id
);
2670 cpu
->core_id
= topo
.core_id
;
2672 if (cpu
->thread_id
!= -1 && cpu
->thread_id
!= topo
.smt_id
) {
2673 error_setg(errp
, "property thread-id: %u doesn't match set apic-id:"
2674 " 0x%x (thread-id: %u)", cpu
->thread_id
, cpu
->apic_id
, topo
.smt_id
);
2677 cpu
->thread_id
= topo
.smt_id
;
2679 if (cpu
->hyperv_vpindex
&& !kvm_hv_vpindex_settable()) {
2680 error_setg(errp
, "kernel doesn't allow setting HyperV VP_INDEX");
2685 cs
->cpu_index
= idx
;
2687 numa_cpu_pre_plug(cpu_slot
, dev
, errp
);
2690 static void pc_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2691 DeviceState
*dev
, Error
**errp
)
2693 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2694 pc_memory_pre_plug(hotplug_dev
, dev
, errp
);
2695 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2696 pc_cpu_pre_plug(hotplug_dev
, dev
, errp
);
2700 static void pc_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2701 DeviceState
*dev
, Error
**errp
)
2703 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2704 pc_memory_plug(hotplug_dev
, dev
, errp
);
2705 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2706 pc_cpu_plug(hotplug_dev
, dev
, errp
);
2710 static void pc_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2711 DeviceState
*dev
, Error
**errp
)
2713 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2714 pc_memory_unplug_request(hotplug_dev
, dev
, errp
);
2715 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2716 pc_cpu_unplug_request_cb(hotplug_dev
, dev
, errp
);
2718 error_setg(errp
, "acpi: device unplug request for not supported device"
2719 " type: %s", object_get_typename(OBJECT(dev
)));
2723 static void pc_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2724 DeviceState
*dev
, Error
**errp
)
2726 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2727 pc_memory_unplug(hotplug_dev
, dev
, errp
);
2728 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2729 pc_cpu_unplug_cb(hotplug_dev
, dev
, errp
);
2731 error_setg(errp
, "acpi: device unplug for not supported device"
2732 " type: %s", object_get_typename(OBJECT(dev
)));
2736 static HotplugHandler
*pc_get_hotpug_handler(MachineState
*machine
,
2739 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2740 object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2741 return HOTPLUG_HANDLER(machine
);
2748 pc_machine_get_device_memory_region_size(Object
*obj
, Visitor
*v
,
2749 const char *name
, void *opaque
,
2752 MachineState
*ms
= MACHINE(obj
);
2753 int64_t value
= memory_region_size(&ms
->device_memory
->mr
);
2755 visit_type_int(v
, name
, &value
, errp
);
2758 static void pc_machine_get_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2759 const char *name
, void *opaque
,
2762 PCMachineState
*pcms
= PC_MACHINE(obj
);
2763 uint64_t value
= pcms
->max_ram_below_4g
;
2765 visit_type_size(v
, name
, &value
, errp
);
2768 static void pc_machine_set_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2769 const char *name
, void *opaque
,
2772 PCMachineState
*pcms
= PC_MACHINE(obj
);
2773 Error
*error
= NULL
;
2776 visit_type_size(v
, name
, &value
, &error
);
2778 error_propagate(errp
, error
);
2781 if (value
> 4 * GiB
) {
2783 "Machine option 'max-ram-below-4g=%"PRIu64
2784 "' expects size less than or equal to 4G", value
);
2785 error_propagate(errp
, error
);
2789 if (value
< 1 * MiB
) {
2790 warn_report("Only %" PRIu64
" bytes of RAM below the 4GiB boundary,"
2791 "BIOS may not work with less than 1MiB", value
);
2794 pcms
->max_ram_below_4g
= value
;
2797 static void pc_machine_get_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2798 void *opaque
, Error
**errp
)
2800 PCMachineState
*pcms
= PC_MACHINE(obj
);
2801 OnOffAuto vmport
= pcms
->vmport
;
2803 visit_type_OnOffAuto(v
, name
, &vmport
, errp
);
2806 static void pc_machine_set_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2807 void *opaque
, Error
**errp
)
2809 PCMachineState
*pcms
= PC_MACHINE(obj
);
2811 visit_type_OnOffAuto(v
, name
, &pcms
->vmport
, errp
);
2814 bool pc_machine_is_smm_enabled(PCMachineState
*pcms
)
2816 bool smm_available
= false;
2818 if (pcms
->smm
== ON_OFF_AUTO_OFF
) {
2822 if (tcg_enabled() || qtest_enabled()) {
2823 smm_available
= true;
2824 } else if (kvm_enabled()) {
2825 smm_available
= kvm_has_smm();
2828 if (smm_available
) {
2832 if (pcms
->smm
== ON_OFF_AUTO_ON
) {
2833 error_report("System Management Mode not supported by this hypervisor.");
2839 static void pc_machine_get_smm(Object
*obj
, Visitor
*v
, const char *name
,
2840 void *opaque
, Error
**errp
)
2842 PCMachineState
*pcms
= PC_MACHINE(obj
);
2843 OnOffAuto smm
= pcms
->smm
;
2845 visit_type_OnOffAuto(v
, name
, &smm
, errp
);
2848 static void pc_machine_set_smm(Object
*obj
, Visitor
*v
, const char *name
,
2849 void *opaque
, Error
**errp
)
2851 PCMachineState
*pcms
= PC_MACHINE(obj
);
2853 visit_type_OnOffAuto(v
, name
, &pcms
->smm
, errp
);
2856 static bool pc_machine_get_nvdimm(Object
*obj
, Error
**errp
)
2858 PCMachineState
*pcms
= PC_MACHINE(obj
);
2860 return pcms
->acpi_nvdimm_state
.is_enabled
;
2863 static void pc_machine_set_nvdimm(Object
*obj
, bool value
, Error
**errp
)
2865 PCMachineState
*pcms
= PC_MACHINE(obj
);
2867 pcms
->acpi_nvdimm_state
.is_enabled
= value
;
2870 static char *pc_machine_get_nvdimm_persistence(Object
*obj
, Error
**errp
)
2872 PCMachineState
*pcms
= PC_MACHINE(obj
);
2874 return g_strdup(pcms
->acpi_nvdimm_state
.persistence_string
);
2877 static void pc_machine_set_nvdimm_persistence(Object
*obj
, const char *value
,
2880 PCMachineState
*pcms
= PC_MACHINE(obj
);
2881 AcpiNVDIMMState
*nvdimm_state
= &pcms
->acpi_nvdimm_state
;
2883 if (strcmp(value
, "cpu") == 0)
2884 nvdimm_state
->persistence
= 3;
2885 else if (strcmp(value
, "mem-ctrl") == 0)
2886 nvdimm_state
->persistence
= 2;
2888 error_setg(errp
, "-machine nvdimm-persistence=%s: unsupported option",
2893 g_free(nvdimm_state
->persistence_string
);
2894 nvdimm_state
->persistence_string
= g_strdup(value
);
2897 static bool pc_machine_get_smbus(Object
*obj
, Error
**errp
)
2899 PCMachineState
*pcms
= PC_MACHINE(obj
);
2901 return pcms
->smbus_enabled
;
2904 static void pc_machine_set_smbus(Object
*obj
, bool value
, Error
**errp
)
2906 PCMachineState
*pcms
= PC_MACHINE(obj
);
2908 pcms
->smbus_enabled
= value
;
2911 static bool pc_machine_get_sata(Object
*obj
, Error
**errp
)
2913 PCMachineState
*pcms
= PC_MACHINE(obj
);
2915 return pcms
->sata_enabled
;
2918 static void pc_machine_set_sata(Object
*obj
, bool value
, Error
**errp
)
2920 PCMachineState
*pcms
= PC_MACHINE(obj
);
2922 pcms
->sata_enabled
= value
;
2925 static bool pc_machine_get_pit(Object
*obj
, Error
**errp
)
2927 PCMachineState
*pcms
= PC_MACHINE(obj
);
2929 return pcms
->pit_enabled
;
2932 static void pc_machine_set_pit(Object
*obj
, bool value
, Error
**errp
)
2934 PCMachineState
*pcms
= PC_MACHINE(obj
);
2936 pcms
->pit_enabled
= value
;
2939 static void pc_machine_initfn(Object
*obj
)
2941 PCMachineState
*pcms
= PC_MACHINE(obj
);
2943 pcms
->max_ram_below_4g
= 0; /* use default */
2944 pcms
->smm
= ON_OFF_AUTO_AUTO
;
2945 pcms
->vmport
= ON_OFF_AUTO_AUTO
;
2946 /* nvdimm is disabled on default. */
2947 pcms
->acpi_nvdimm_state
.is_enabled
= false;
2948 /* acpi build is enabled by default if machine supports it */
2949 pcms
->acpi_build_enabled
= PC_MACHINE_GET_CLASS(pcms
)->has_acpi_build
;
2950 pcms
->smbus_enabled
= true;
2951 pcms
->sata_enabled
= true;
2952 pcms
->pit_enabled
= true;
2955 static void pc_machine_reset(void)
2960 qemu_devices_reset();
2962 /* Reset APIC after devices have been reset to cancel
2963 * any changes that qemu_devices_reset() might have done.
2968 if (cpu
->apic_state
) {
2969 device_reset(cpu
->apic_state
);
2974 static CpuInstanceProperties
2975 pc_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2977 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2978 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2980 assert(cpu_index
< possible_cpus
->len
);
2981 return possible_cpus
->cpus
[cpu_index
].props
;
2984 static int64_t pc_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2986 X86CPUTopoInfo topo
;
2988 assert(idx
< ms
->possible_cpus
->len
);
2989 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[idx
].arch_id
,
2990 smp_cores
, smp_threads
, &topo
);
2991 return topo
.pkg_id
% nb_numa_nodes
;
2994 static const CPUArchIdList
*pc_possible_cpu_arch_ids(MachineState
*ms
)
2998 if (ms
->possible_cpus
) {
3000 * make sure that max_cpus hasn't changed since the first use, i.e.
3001 * -smp hasn't been parsed after it
3003 assert(ms
->possible_cpus
->len
== max_cpus
);
3004 return ms
->possible_cpus
;
3007 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
3008 sizeof(CPUArchId
) * max_cpus
);
3009 ms
->possible_cpus
->len
= max_cpus
;
3010 for (i
= 0; i
< ms
->possible_cpus
->len
; i
++) {
3011 X86CPUTopoInfo topo
;
3013 ms
->possible_cpus
->cpus
[i
].type
= ms
->cpu_type
;
3014 ms
->possible_cpus
->cpus
[i
].vcpus_count
= 1;
3015 ms
->possible_cpus
->cpus
[i
].arch_id
= x86_cpu_apic_id_from_index(i
);
3016 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[i
].arch_id
,
3017 smp_cores
, smp_threads
, &topo
);
3018 ms
->possible_cpus
->cpus
[i
].props
.has_socket_id
= true;
3019 ms
->possible_cpus
->cpus
[i
].props
.socket_id
= topo
.pkg_id
;
3020 ms
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
3021 ms
->possible_cpus
->cpus
[i
].props
.core_id
= topo
.core_id
;
3022 ms
->possible_cpus
->cpus
[i
].props
.has_thread_id
= true;
3023 ms
->possible_cpus
->cpus
[i
].props
.thread_id
= topo
.smt_id
;
3025 return ms
->possible_cpus
;
3028 static void x86_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3030 /* cpu index isn't used */
3034 X86CPU
*cpu
= X86_CPU(cs
);
3036 if (!cpu
->apic_state
) {
3037 cpu_interrupt(cs
, CPU_INTERRUPT_NMI
);
3039 apic_deliver_nmi(cpu
->apic_state
);
3044 static void pc_machine_class_init(ObjectClass
*oc
, void *data
)
3046 MachineClass
*mc
= MACHINE_CLASS(oc
);
3047 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(oc
);
3048 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
3049 NMIClass
*nc
= NMI_CLASS(oc
);
3051 pcmc
->pci_enabled
= true;
3052 pcmc
->has_acpi_build
= true;
3053 pcmc
->rsdp_in_ram
= true;
3054 pcmc
->smbios_defaults
= true;
3055 pcmc
->smbios_uuid_encoded
= true;
3056 pcmc
->gigabyte_align
= true;
3057 pcmc
->has_reserved_memory
= true;
3058 pcmc
->kvmclock_enabled
= true;
3059 pcmc
->enforce_aligned_dimm
= true;
3060 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
3061 * to be used at the moment, 32K should be enough for a while. */
3062 pcmc
->acpi_data_size
= 0x20000 + 0x8000;
3063 pcmc
->save_tsc_khz
= true;
3064 pcmc
->linuxboot_dma_enabled
= true;
3065 assert(!mc
->get_hotplug_handler
);
3066 mc
->get_hotplug_handler
= pc_get_hotpug_handler
;
3067 mc
->cpu_index_to_instance_props
= pc_cpu_index_to_props
;
3068 mc
->get_default_cpu_node_id
= pc_get_default_cpu_node_id
;
3069 mc
->possible_cpu_arch_ids
= pc_possible_cpu_arch_ids
;
3070 mc
->auto_enable_numa_with_memhp
= true;
3071 mc
->has_hotpluggable_cpus
= true;
3072 mc
->default_boot_order
= "cad";
3073 mc
->hot_add_cpu
= pc_hot_add_cpu
;
3074 mc
->block_default_type
= IF_IDE
;
3076 mc
->reset
= pc_machine_reset
;
3077 hc
->pre_plug
= pc_machine_device_pre_plug_cb
;
3078 hc
->plug
= pc_machine_device_plug_cb
;
3079 hc
->unplug_request
= pc_machine_device_unplug_request_cb
;
3080 hc
->unplug
= pc_machine_device_unplug_cb
;
3081 nc
->nmi_monitor_handler
= x86_nmi
;
3082 mc
->default_cpu_type
= TARGET_DEFAULT_CPU_TYPE
;
3084 object_class_property_add(oc
, PC_MACHINE_DEVMEM_REGION_SIZE
, "int",
3085 pc_machine_get_device_memory_region_size
, NULL
,
3086 NULL
, NULL
, &error_abort
);
3088 object_class_property_add(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
, "size",
3089 pc_machine_get_max_ram_below_4g
, pc_machine_set_max_ram_below_4g
,
3090 NULL
, NULL
, &error_abort
);
3092 object_class_property_set_description(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
,
3093 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort
);
3095 object_class_property_add(oc
, PC_MACHINE_SMM
, "OnOffAuto",
3096 pc_machine_get_smm
, pc_machine_set_smm
,
3097 NULL
, NULL
, &error_abort
);
3098 object_class_property_set_description(oc
, PC_MACHINE_SMM
,
3099 "Enable SMM (pc & q35)", &error_abort
);
3101 object_class_property_add(oc
, PC_MACHINE_VMPORT
, "OnOffAuto",
3102 pc_machine_get_vmport
, pc_machine_set_vmport
,
3103 NULL
, NULL
, &error_abort
);
3104 object_class_property_set_description(oc
, PC_MACHINE_VMPORT
,
3105 "Enable vmport (pc & q35)", &error_abort
);
3107 object_class_property_add_bool(oc
, PC_MACHINE_NVDIMM
,
3108 pc_machine_get_nvdimm
, pc_machine_set_nvdimm
, &error_abort
);
3110 object_class_property_add_str(oc
, PC_MACHINE_NVDIMM_PERSIST
,
3111 pc_machine_get_nvdimm_persistence
,
3112 pc_machine_set_nvdimm_persistence
, &error_abort
);
3114 object_class_property_add_bool(oc
, PC_MACHINE_SMBUS
,
3115 pc_machine_get_smbus
, pc_machine_set_smbus
, &error_abort
);
3117 object_class_property_add_bool(oc
, PC_MACHINE_SATA
,
3118 pc_machine_get_sata
, pc_machine_set_sata
, &error_abort
);
3120 object_class_property_add_bool(oc
, PC_MACHINE_PIT
,
3121 pc_machine_get_pit
, pc_machine_set_pit
, &error_abort
);
3124 static const TypeInfo pc_machine_info
= {
3125 .name
= TYPE_PC_MACHINE
,
3126 .parent
= TYPE_MACHINE
,
3128 .instance_size
= sizeof(PCMachineState
),
3129 .instance_init
= pc_machine_initfn
,
3130 .class_size
= sizeof(PCMachineClass
),
3131 .class_init
= pc_machine_class_init
,
3132 .interfaces
= (InterfaceInfo
[]) {
3133 { TYPE_HOTPLUG_HANDLER
},
3139 static void pc_machine_register_types(void)
3141 type_register_static(&pc_machine_info
);
3144 type_init(pc_machine_register_types
)