2 * ARM GICv3 support - common bits of emulated and KVM kernel model
4 * Copyright (c) 2012 Linaro Limited
5 * Copyright (c) 2015 Huawei.
6 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
7 * Written by Peter Maydell
8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation, either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu/module.h"
27 #include "qemu/error-report.h"
28 #include "hw/core/cpu.h"
29 #include "hw/intc/arm_gicv3_common.h"
30 #include "hw/qdev-properties.h"
31 #include "migration/vmstate.h"
32 #include "gicv3_internal.h"
33 #include "hw/arm/linux-boot-if.h"
34 #include "sysemu/kvm.h"
37 static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State
*cs
)
39 if (cs
->gicd_no_migration_shift_bug
) {
43 /* Older versions of QEMU had a bug in the handling of state save/restore
44 * to the KVM GICv3: they got the offset in the bitmap arrays wrong,
45 * so that instead of the data for external interrupts 32 and up
46 * starting at bit position 32 in the bitmap, it started at bit
47 * position 64. If we're receiving data from a QEMU with that bug,
48 * we must move the data down into the right place.
50 memmove(cs
->group
, (uint8_t *)cs
->group
+ GIC_INTERNAL
/ 8,
51 sizeof(cs
->group
) - GIC_INTERNAL
/ 8);
52 memmove(cs
->grpmod
, (uint8_t *)cs
->grpmod
+ GIC_INTERNAL
/ 8,
53 sizeof(cs
->grpmod
) - GIC_INTERNAL
/ 8);
54 memmove(cs
->enabled
, (uint8_t *)cs
->enabled
+ GIC_INTERNAL
/ 8,
55 sizeof(cs
->enabled
) - GIC_INTERNAL
/ 8);
56 memmove(cs
->pending
, (uint8_t *)cs
->pending
+ GIC_INTERNAL
/ 8,
57 sizeof(cs
->pending
) - GIC_INTERNAL
/ 8);
58 memmove(cs
->active
, (uint8_t *)cs
->active
+ GIC_INTERNAL
/ 8,
59 sizeof(cs
->active
) - GIC_INTERNAL
/ 8);
60 memmove(cs
->edge_trigger
, (uint8_t *)cs
->edge_trigger
+ GIC_INTERNAL
/ 8,
61 sizeof(cs
->edge_trigger
) - GIC_INTERNAL
/ 8);
64 * While this new version QEMU doesn't have this kind of bug as we fix it,
65 * so it needs to set the flag to true to indicate that and it's necessary
66 * for next migration to work from this new version QEMU.
68 cs
->gicd_no_migration_shift_bug
= true;
71 static int gicv3_pre_save(void *opaque
)
73 GICv3State
*s
= (GICv3State
*)opaque
;
74 ARMGICv3CommonClass
*c
= ARM_GICV3_COMMON_GET_CLASS(s
);
83 static int gicv3_post_load(void *opaque
, int version_id
)
85 GICv3State
*s
= (GICv3State
*)opaque
;
86 ARMGICv3CommonClass
*c
= ARM_GICV3_COMMON_GET_CLASS(s
);
88 gicv3_gicd_no_migration_shift_bug_post_load(s
);
96 static bool virt_state_needed(void *opaque
)
98 GICv3CPUState
*cs
= opaque
;
100 return cs
->num_list_regs
!= 0;
103 static const VMStateDescription vmstate_gicv3_cpu_virt
= {
104 .name
= "arm_gicv3_cpu/virt",
106 .minimum_version_id
= 1,
107 .needed
= virt_state_needed
,
108 .fields
= (const VMStateField
[]) {
109 VMSTATE_UINT64_2DARRAY(ich_apr
, GICv3CPUState
, 3, 4),
110 VMSTATE_UINT64(ich_hcr_el2
, GICv3CPUState
),
111 VMSTATE_UINT64_ARRAY(ich_lr_el2
, GICv3CPUState
, GICV3_LR_MAX
),
112 VMSTATE_UINT64(ich_vmcr_el2
, GICv3CPUState
),
113 VMSTATE_END_OF_LIST()
117 static int vmstate_gicv3_cpu_pre_load(void *opaque
)
119 GICv3CPUState
*cs
= opaque
;
122 * If the sre_el1 subsection is not transferred this
123 * means SRE_EL1 is 0x7 (which might not be the same as
126 cs
->icc_sre_el1
= 0x7;
130 static bool icc_sre_el1_reg_needed(void *opaque
)
132 GICv3CPUState
*cs
= opaque
;
134 return cs
->icc_sre_el1
!= 7;
137 const VMStateDescription vmstate_gicv3_cpu_sre_el1
= {
138 .name
= "arm_gicv3_cpu/sre_el1",
140 .minimum_version_id
= 1,
141 .needed
= icc_sre_el1_reg_needed
,
142 .fields
= (const VMStateField
[]) {
143 VMSTATE_UINT64(icc_sre_el1
, GICv3CPUState
),
144 VMSTATE_END_OF_LIST()
148 static bool gicv4_needed(void *opaque
)
150 GICv3CPUState
*cs
= opaque
;
152 return cs
->gic
->revision
> 3;
155 const VMStateDescription vmstate_gicv3_gicv4
= {
156 .name
= "arm_gicv3_cpu/gicv4",
158 .minimum_version_id
= 1,
159 .needed
= gicv4_needed
,
160 .fields
= (const VMStateField
[]) {
161 VMSTATE_UINT64(gicr_vpropbaser
, GICv3CPUState
),
162 VMSTATE_UINT64(gicr_vpendbaser
, GICv3CPUState
),
163 VMSTATE_END_OF_LIST()
167 static const VMStateDescription vmstate_gicv3_cpu
= {
168 .name
= "arm_gicv3_cpu",
170 .minimum_version_id
= 1,
171 .pre_load
= vmstate_gicv3_cpu_pre_load
,
172 .fields
= (const VMStateField
[]) {
173 VMSTATE_UINT32(level
, GICv3CPUState
),
174 VMSTATE_UINT32(gicr_ctlr
, GICv3CPUState
),
175 VMSTATE_UINT32_ARRAY(gicr_statusr
, GICv3CPUState
, 2),
176 VMSTATE_UINT32(gicr_waker
, GICv3CPUState
),
177 VMSTATE_UINT64(gicr_propbaser
, GICv3CPUState
),
178 VMSTATE_UINT64(gicr_pendbaser
, GICv3CPUState
),
179 VMSTATE_UINT32(gicr_igroupr0
, GICv3CPUState
),
180 VMSTATE_UINT32(gicr_ienabler0
, GICv3CPUState
),
181 VMSTATE_UINT32(gicr_ipendr0
, GICv3CPUState
),
182 VMSTATE_UINT32(gicr_iactiver0
, GICv3CPUState
),
183 VMSTATE_UINT32(edge_trigger
, GICv3CPUState
),
184 VMSTATE_UINT32(gicr_igrpmodr0
, GICv3CPUState
),
185 VMSTATE_UINT32(gicr_nsacr
, GICv3CPUState
),
186 VMSTATE_UINT8_ARRAY(gicr_ipriorityr
, GICv3CPUState
, GIC_INTERNAL
),
187 VMSTATE_UINT64_ARRAY(icc_ctlr_el1
, GICv3CPUState
, 2),
188 VMSTATE_UINT64(icc_pmr_el1
, GICv3CPUState
),
189 VMSTATE_UINT64_ARRAY(icc_bpr
, GICv3CPUState
, 3),
190 VMSTATE_UINT64_2DARRAY(icc_apr
, GICv3CPUState
, 3, 4),
191 VMSTATE_UINT64_ARRAY(icc_igrpen
, GICv3CPUState
, 3),
192 VMSTATE_UINT64(icc_ctlr_el3
, GICv3CPUState
),
193 VMSTATE_END_OF_LIST()
195 .subsections
= (const VMStateDescription
* const []) {
196 &vmstate_gicv3_cpu_virt
,
197 &vmstate_gicv3_cpu_sre_el1
,
198 &vmstate_gicv3_gicv4
,
203 static int gicv3_pre_load(void *opaque
)
205 GICv3State
*cs
= opaque
;
208 * The gicd_no_migration_shift_bug flag is used for migration compatibility
209 * for old version QEMU which may have the GICD bmp shift bug under KVM mode.
210 * Strictly, what we want to know is whether the migration source is using
211 * KVM. Since we don't have any way to determine that, we look at whether the
212 * destination is using KVM; this is close enough because for the older QEMU
213 * versions with this bug KVM -> TCG migration didn't work anyway. If the
214 * source is a newer QEMU without this bug it will transmit the migration
215 * subsection which sets the flag to true; otherwise it will remain set to
216 * the value we select here.
219 cs
->gicd_no_migration_shift_bug
= false;
225 static bool needed_always(void *opaque
)
230 const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug
= {
231 .name
= "arm_gicv3/gicd_no_migration_shift_bug",
233 .minimum_version_id
= 1,
234 .needed
= needed_always
,
235 .fields
= (const VMStateField
[]) {
236 VMSTATE_BOOL(gicd_no_migration_shift_bug
, GICv3State
),
237 VMSTATE_END_OF_LIST()
241 static const VMStateDescription vmstate_gicv3
= {
244 .minimum_version_id
= 1,
245 .pre_load
= gicv3_pre_load
,
246 .pre_save
= gicv3_pre_save
,
247 .post_load
= gicv3_post_load
,
248 .priority
= MIG_PRI_GICV3
,
249 .fields
= (const VMStateField
[]) {
250 VMSTATE_UINT32(gicd_ctlr
, GICv3State
),
251 VMSTATE_UINT32_ARRAY(gicd_statusr
, GICv3State
, 2),
252 VMSTATE_UINT32_ARRAY(group
, GICv3State
, GICV3_BMP_SIZE
),
253 VMSTATE_UINT32_ARRAY(grpmod
, GICv3State
, GICV3_BMP_SIZE
),
254 VMSTATE_UINT32_ARRAY(enabled
, GICv3State
, GICV3_BMP_SIZE
),
255 VMSTATE_UINT32_ARRAY(pending
, GICv3State
, GICV3_BMP_SIZE
),
256 VMSTATE_UINT32_ARRAY(active
, GICv3State
, GICV3_BMP_SIZE
),
257 VMSTATE_UINT32_ARRAY(level
, GICv3State
, GICV3_BMP_SIZE
),
258 VMSTATE_UINT32_ARRAY(edge_trigger
, GICv3State
, GICV3_BMP_SIZE
),
259 VMSTATE_UINT8_ARRAY(gicd_ipriority
, GICv3State
, GICV3_MAXIRQ
),
260 VMSTATE_UINT64_ARRAY(gicd_irouter
, GICv3State
, GICV3_MAXIRQ
),
261 VMSTATE_UINT32_ARRAY(gicd_nsacr
, GICv3State
,
262 DIV_ROUND_UP(GICV3_MAXIRQ
, 16)),
263 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu
, GICv3State
, num_cpu
,
264 vmstate_gicv3_cpu
, GICv3CPUState
),
265 VMSTATE_END_OF_LIST()
267 .subsections
= (const VMStateDescription
* const []) {
268 &vmstate_gicv3_gicd_no_migration_shift_bug
,
273 void gicv3_init_irqs_and_mmio(GICv3State
*s
, qemu_irq_handler handler
,
274 const MemoryRegionOps
*ops
)
276 SysBusDevice
*sbd
= SYS_BUS_DEVICE(s
);
280 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
281 * GPIO array layout is thus:
283 * [N..N+31] PPIs for CPU 0
284 * [N+32..N+63] PPIs for CPU 1
287 i
= s
->num_irq
- GIC_INTERNAL
+ GIC_INTERNAL
* s
->num_cpu
;
288 qdev_init_gpio_in(DEVICE(s
), handler
, i
);
290 for (i
= 0; i
< s
->num_cpu
; i
++) {
291 sysbus_init_irq(sbd
, &s
->cpu
[i
].parent_irq
);
293 for (i
= 0; i
< s
->num_cpu
; i
++) {
294 sysbus_init_irq(sbd
, &s
->cpu
[i
].parent_fiq
);
296 for (i
= 0; i
< s
->num_cpu
; i
++) {
297 sysbus_init_irq(sbd
, &s
->cpu
[i
].parent_virq
);
299 for (i
= 0; i
< s
->num_cpu
; i
++) {
300 sysbus_init_irq(sbd
, &s
->cpu
[i
].parent_vfiq
);
303 memory_region_init_io(&s
->iomem_dist
, OBJECT(s
), ops
, s
,
304 "gicv3_dist", 0x10000);
305 sysbus_init_mmio(sbd
, &s
->iomem_dist
);
307 s
->redist_regions
= g_new0(GICv3RedistRegion
, s
->nb_redist_regions
);
309 for (i
= 0; i
< s
->nb_redist_regions
; i
++) {
310 char *name
= g_strdup_printf("gicv3_redist_region[%d]", i
);
311 GICv3RedistRegion
*region
= &s
->redist_regions
[i
];
314 region
->cpuidx
= cpuidx
;
315 cpuidx
+= s
->redist_region_count
[i
];
317 memory_region_init_io(®ion
->iomem
, OBJECT(s
),
318 ops
? &ops
[1] : NULL
, region
, name
,
319 s
->redist_region_count
[i
] * gicv3_redist_size(s
));
320 sysbus_init_mmio(sbd
, ®ion
->iomem
);
325 static void arm_gicv3_common_realize(DeviceState
*dev
, Error
**errp
)
327 GICv3State
*s
= ARM_GICV3_COMMON(dev
);
328 int i
, rdist_capacity
, cpuidx
;
331 * This GIC device supports only revisions 3 and 4. The GICv1/v2
332 * is a separate device.
333 * Note that subclasses of this device may impose further restrictions
334 * on the GIC revision: notably, the in-kernel KVM GIC doesn't
337 if (s
->revision
!= 3 && s
->revision
!= 4) {
338 error_setg(errp
, "unsupported GIC revision %d", s
->revision
);
342 if (s
->num_irq
> GICV3_MAXIRQ
) {
344 "requested %u interrupt lines exceeds GIC maximum %d",
345 s
->num_irq
, GICV3_MAXIRQ
);
348 if (s
->num_irq
< GIC_INTERNAL
) {
350 "requested %u interrupt lines is below GIC minimum %d",
351 s
->num_irq
, GIC_INTERNAL
);
354 if (s
->num_cpu
== 0) {
355 error_setg(errp
, "num-cpu must be at least 1");
359 /* ITLinesNumber is represented as (N / 32) - 1, so this is an
360 * implementation imposed restriction, not an architectural one,
361 * so we don't have to deal with bitfields where only some of the
362 * bits in a 32-bit word should be valid.
364 if (s
->num_irq
% 32) {
366 "%d interrupt lines unsupported: not divisible by 32",
371 if (s
->lpi_enable
&& !s
->dma
) {
372 error_setg(errp
, "Redist-ITS: Guest 'sysmem' reference link not set");
377 for (i
= 0; i
< s
->nb_redist_regions
; i
++) {
378 rdist_capacity
+= s
->redist_region_count
[i
];
380 if (rdist_capacity
!= s
->num_cpu
) {
381 error_setg(errp
, "Capacity of the redist regions(%d) "
382 "does not match the number of vcpus(%d)",
383 rdist_capacity
, s
->num_cpu
);
388 address_space_init(&s
->dma_as
, s
->dma
,
392 s
->cpu
= g_new0(GICv3CPUState
, s
->num_cpu
);
394 for (i
= 0; i
< s
->num_cpu
; i
++) {
395 CPUState
*cpu
= qemu_get_cpu(i
);
400 /* Store GICv3CPUState in CPUARMState gicv3state pointer */
401 gicv3_set_gicv3state(cpu
, &s
->cpu
[i
]);
403 /* Pre-construct the GICR_TYPER:
404 * For our implementation:
405 * Top 32 bits are the affinity value of the associated CPU
406 * CommonLPIAff == 01 (redistributors with same Aff3 share LPI table)
407 * Processor_Number == CPU index starting from 0
408 * DPGS == 0 (GICR_CTLR.DPG* not supported)
409 * Last == 1 if this is the last redistributor in a series of
410 * contiguous redistributor pages
411 * DirectLPI == 0 (direct injection of LPIs not supported)
412 * VLPIS == 1 if vLPIs supported (GICv4 and up)
413 * PLPIS == 1 if LPIs supported
415 cpu_affid
= object_property_get_uint(OBJECT(cpu
), "mp-affinity", NULL
);
417 /* The CPU mp-affinity property is in MPIDR register format; squash
418 * the affinity bytes into 32 bits as the GICR_TYPER has them.
420 cpu_affid
= ((cpu_affid
& 0xFF00000000ULL
) >> 8) |
421 (cpu_affid
& 0xFFFFFF);
422 s
->cpu
[i
].gicr_typer
= (cpu_affid
<< 32) |
427 s
->cpu
[i
].gicr_typer
|= GICR_TYPER_PLPIS
;
428 if (s
->revision
> 3) {
429 s
->cpu
[i
].gicr_typer
|= GICR_TYPER_VLPIS
;
435 * Now go through and set GICR_TYPER.Last for the final
436 * redistributor in each region.
439 for (i
= 0; i
< s
->nb_redist_regions
; i
++) {
440 cpuidx
+= s
->redist_region_count
[i
];
441 s
->cpu
[cpuidx
- 1].gicr_typer
|= GICR_TYPER_LAST
;
444 s
->itslist
= g_ptr_array_new();
447 static void arm_gicv3_finalize(Object
*obj
)
449 GICv3State
*s
= ARM_GICV3_COMMON(obj
);
451 g_free(s
->redist_region_count
);
454 static void arm_gicv3_common_reset_hold(Object
*obj
)
456 GICv3State
*s
= ARM_GICV3_COMMON(obj
);
459 for (i
= 0; i
< s
->num_cpu
; i
++) {
460 GICv3CPUState
*cs
= &s
->cpu
[i
];
465 /* Our implementation supports clearing GICR_CTLR.EnableLPIs */
466 cs
->gicr_ctlr
|= GICR_CTLR_CES
;
468 cs
->gicr_statusr
[GICV3_S
] = 0;
469 cs
->gicr_statusr
[GICV3_NS
] = 0;
470 cs
->gicr_waker
= GICR_WAKER_ProcessorSleep
| GICR_WAKER_ChildrenAsleep
;
471 cs
->gicr_propbaser
= 0;
472 cs
->gicr_pendbaser
= 0;
473 cs
->gicr_vpropbaser
= 0;
474 cs
->gicr_vpendbaser
= 0;
475 /* If we're resetting a TZ-aware GIC as if secure firmware
476 * had set it up ready to start a kernel in non-secure, we
477 * need to set interrupts to group 1 so the kernel can use them.
478 * Otherwise they reset to group 0 like the hardware.
480 if (s
->irq_reset_nonsecure
) {
481 cs
->gicr_igroupr0
= 0xffffffff;
483 cs
->gicr_igroupr0
= 0;
486 cs
->gicr_ienabler0
= 0;
487 cs
->gicr_ipendr0
= 0;
488 cs
->gicr_iactiver0
= 0;
489 cs
->edge_trigger
= 0xffff;
490 cs
->gicr_igrpmodr0
= 0;
492 memset(cs
->gicr_ipriorityr
, 0, sizeof(cs
->gicr_ipriorityr
));
494 cs
->hppi
.prio
= 0xff;
495 cs
->hpplpi
.prio
= 0xff;
496 cs
->hppvlpi
.prio
= 0xff;
498 /* State in the CPU interface must *not* be reset here, because it
499 * is part of the CPU's reset domain, not the GIC device's.
503 /* For our implementation affinity routing is always enabled */
504 if (s
->security_extn
) {
505 s
->gicd_ctlr
= GICD_CTLR_ARE_S
| GICD_CTLR_ARE_NS
;
507 s
->gicd_ctlr
= GICD_CTLR_DS
| GICD_CTLR_ARE
;
510 s
->gicd_statusr
[GICV3_S
] = 0;
511 s
->gicd_statusr
[GICV3_NS
] = 0;
513 memset(s
->group
, 0, sizeof(s
->group
));
514 memset(s
->grpmod
, 0, sizeof(s
->grpmod
));
515 memset(s
->enabled
, 0, sizeof(s
->enabled
));
516 memset(s
->pending
, 0, sizeof(s
->pending
));
517 memset(s
->active
, 0, sizeof(s
->active
));
518 memset(s
->level
, 0, sizeof(s
->level
));
519 memset(s
->edge_trigger
, 0, sizeof(s
->edge_trigger
));
520 memset(s
->gicd_ipriority
, 0, sizeof(s
->gicd_ipriority
));
521 memset(s
->gicd_irouter
, 0, sizeof(s
->gicd_irouter
));
522 memset(s
->gicd_nsacr
, 0, sizeof(s
->gicd_nsacr
));
523 /* GICD_IROUTER are UNKNOWN at reset so in theory the guest must
524 * write these to get sane behaviour and we need not populate the
525 * pointer cache here; however having the cache be different for
526 * "happened to be 0 from reset" and "guest wrote 0" would be
529 gicv3_cache_all_target_cpustates(s
);
531 if (s
->irq_reset_nonsecure
) {
532 /* If we're resetting a TZ-aware GIC as if secure firmware
533 * had set it up ready to start a kernel in non-secure, we
534 * need to set interrupts to group 1 so the kernel can use them.
535 * Otherwise they reset to group 0 like the hardware.
537 for (i
= GIC_INTERNAL
; i
< s
->num_irq
; i
++) {
538 gicv3_gicd_group_set(s
, i
);
541 s
->gicd_no_migration_shift_bug
= true;
544 static void arm_gic_common_linux_init(ARMLinuxBootIf
*obj
,
547 GICv3State
*s
= ARM_GICV3_COMMON(obj
);
549 if (s
->security_extn
&& !secure_boot
) {
550 /* We're directly booting a kernel into NonSecure. If this GIC
551 * implements the security extensions then we must configure it
552 * to have all the interrupts be NonSecure (this is a job that
553 * is done by the Secure boot firmware in real hardware, and in
554 * this mode QEMU is acting as a minimalist firmware-and-bootloader
557 s
->irq_reset_nonsecure
= true;
561 static Property arm_gicv3_common_properties
[] = {
562 DEFINE_PROP_UINT32("num-cpu", GICv3State
, num_cpu
, 1),
563 DEFINE_PROP_UINT32("num-irq", GICv3State
, num_irq
, 32),
564 DEFINE_PROP_UINT32("revision", GICv3State
, revision
, 3),
565 DEFINE_PROP_BOOL("has-lpi", GICv3State
, lpi_enable
, 0),
566 DEFINE_PROP_BOOL("has-security-extensions", GICv3State
, security_extn
, 0),
568 * Compatibility property: force 8 bits of physical priority, even
569 * if the CPU being emulated should have fewer.
571 DEFINE_PROP_BOOL("force-8-bit-prio", GICv3State
, force_8bit_prio
, 0),
572 DEFINE_PROP_ARRAY("redist-region-count", GICv3State
, nb_redist_regions
,
573 redist_region_count
, qdev_prop_uint32
, uint32_t),
574 DEFINE_PROP_LINK("sysmem", GICv3State
, dma
, TYPE_MEMORY_REGION
,
576 DEFINE_PROP_END_OF_LIST(),
579 static void arm_gicv3_common_class_init(ObjectClass
*klass
, void *data
)
581 DeviceClass
*dc
= DEVICE_CLASS(klass
);
582 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
583 ARMLinuxBootIfClass
*albifc
= ARM_LINUX_BOOT_IF_CLASS(klass
);
585 rc
->phases
.hold
= arm_gicv3_common_reset_hold
;
586 dc
->realize
= arm_gicv3_common_realize
;
587 device_class_set_props(dc
, arm_gicv3_common_properties
);
588 dc
->vmsd
= &vmstate_gicv3
;
589 albifc
->arm_linux_init
= arm_gic_common_linux_init
;
592 static const TypeInfo arm_gicv3_common_type
= {
593 .name
= TYPE_ARM_GICV3_COMMON
,
594 .parent
= TYPE_SYS_BUS_DEVICE
,
595 .instance_size
= sizeof(GICv3State
),
596 .class_size
= sizeof(ARMGICv3CommonClass
),
597 .class_init
= arm_gicv3_common_class_init
,
598 .instance_finalize
= arm_gicv3_finalize
,
600 .interfaces
= (InterfaceInfo
[]) {
601 { TYPE_ARM_LINUX_BOOT_IF
},
606 static void register_types(void)
608 type_register_static(&arm_gicv3_common_type
);
611 type_init(register_types
)
613 const char *gicv3_class_name(void)
615 if (kvm_irqchip_in_kernel()) {
616 return "kvm-arm-gicv3";
619 error_report("Userspace GICv3 is not supported with KVM");