hw/mips_jazz.c

   1 /*
   2  * QEMU MIPS Jazz support
   3  *
   4  * Copyright (c) 2007-2008 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "mips_cpudevs.h"
  28 #include "pc.h"
  29 #include "isa.h"
  30 #include "fdc.h"
  31 #include "sysemu.h"
  32 #include "audio/audio.h"
  33 #include "boards.h"
  34 #include "net.h"
  35 #include "esp.h"
  36 #include "mips-bios.h"
  37 #include "loader.h"
  38 #include "mc146818rtc.h"
  39 #include "blockdev.h"
  40
  41 enum jazz_model_e
  42 {
  43     JAZZ_MAGNUM,
  44     JAZZ_PICA61,
  45 };
  46
  47 static void main_cpu_reset(void *opaque)
  48 {
  49     CPUState *env = opaque;
  50     cpu_reset(env);
  51 }
  52
  53 static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
  54 {
  55     return cpu_inw(0x71);
  56 }
  57
  58 static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  59 {
  60     cpu_outw(0x71, val & 0xff);
  61 }
  62
  63 static CPUReadMemoryFunc * const rtc_read[3] = {
  64     rtc_readb,
  65     rtc_readb,
  66     rtc_readb,
  67 };
  68
  69 static CPUWriteMemoryFunc * const rtc_write[3] = {
  70     rtc_writeb,
  71     rtc_writeb,
  72     rtc_writeb,
  73 };
  74
  75 static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  76 {
  77     /* Nothing to do. That is only to ensure that
  78      * the current DMA acknowledge cycle is completed. */
  79 }
  80
  81 static CPUReadMemoryFunc * const dma_dummy_read[3] = {
  82     NULL,
  83     NULL,
  84     NULL,
  85 };
  86
  87 static CPUWriteMemoryFunc * const dma_dummy_write[3] = {
  88     dma_dummy_writeb,
  89     dma_dummy_writeb,
  90     dma_dummy_writeb,
  91 };
  92
  93 static void audio_init(qemu_irq *pic)
  94 {
  95     struct soundhw *c;
  96     int audio_enabled = 0;
  97
  98     for (c = soundhw; !audio_enabled && c->name; ++c) {
  99         audio_enabled = c->enabled;
 100     }
 101
 102     if (audio_enabled) {
 103         for (c = soundhw; c->name; ++c) {
 104             if (c->enabled) {
 105                 if (c->isa) {
 106                     c->init.init_isa(pic);
 107                 }
 108             }
 109         }
 110     }
 111 }
 112
 113 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
 114 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
 115
 116 static void cpu_request_exit(void *opaque, int irq, int level)
 117 {
 118     CPUState *env = cpu_single_env;
 119
 120     if (env && level) {
 121         cpu_exit(env);
 122     }
 123 }
 124
 125 static
 126 void mips_jazz_init (ram_addr_t ram_size,
 127                      const char *cpu_model,
 128                      enum jazz_model_e jazz_model)
 129 {
 130     char *filename;
 131     int bios_size, n;
 132     CPUState *env;
 133     qemu_irq *rc4030, *i8259;
 134     rc4030_dma *dmas;
 135     void* rc4030_opaque;
 136     int s_rtc, s_dma_dummy;
 137     NICInfo *nd;
 138     PITState *pit;
 139     DriveInfo *fds[MAX_FD];
 140     qemu_irq esp_reset, dma_enable;
 141     qemu_irq *cpu_exit_irq;
 142     ram_addr_t ram_offset;
 143     ram_addr_t bios_offset;
 144
 145     /* init CPUs */
 146     if (cpu_model == NULL) {
 147 #ifdef TARGET_MIPS64
 148         cpu_model = "R4000";
 149 #else
 150         /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
 151         cpu_model = "24Kf";
 152 #endif
 153     }
 154     env = cpu_init(cpu_model);
 155     if (!env) {
 156         fprintf(stderr, "Unable to find CPU definition\n");
 157         exit(1);
 158     }
 159     qemu_register_reset(main_cpu_reset, env);
 160
 161     /* allocate RAM */
 162     ram_offset = qemu_ram_alloc(NULL, "mips_jazz.ram", ram_size);
 163     cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
 164
 165     bios_offset = qemu_ram_alloc(NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
 166     cpu_register_physical_memory(0x1fc00000LL,
 167                                  MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
 168     cpu_register_physical_memory(0xfff00000LL,
 169                                  MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
 170
 171     /* load the BIOS image. */
 172     if (bios_name == NULL)
 173         bios_name = BIOS_FILENAME;
 174     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 175     if (filename) {
 176         bios_size = load_image_targphys(filename, 0xfff00000LL,
 177                                         MAGNUM_BIOS_SIZE);
 178         qemu_free(filename);
 179     } else {
 180         bios_size = -1;
 181     }
 182     if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
 183         fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
 184                 bios_name);
 185         exit(1);
 186     }
 187
 188     /* Init CPU internal devices */
 189     cpu_mips_irq_init_cpu(env);
 190     cpu_mips_clock_init(env);
 191
 192     /* Chipset */
 193     rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
 194     s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL,
 195                                          DEVICE_NATIVE_ENDIAN);
 196     cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
 197
 198     /* ISA devices */
 199     i8259 = i8259_init(env->irq[4]);
 200     isa_bus_new(NULL);
 201     isa_bus_irqs(i8259);
 202     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 203     DMA_init(0, cpu_exit_irq);
 204     pit = pit_init(0x40, i8259[0]);
 205     pcspk_init(pit);
 206
 207     /* ISA IO space at 0x90000000 */
 208 #ifdef TARGET_WORDS_BIGENDIAN
 209     isa_mmio_init(0x90000000, 0x01000000, 1);
 210 #else
 211     isa_mmio_init(0x90000000, 0x01000000, 0);
 212 #endif
 213
 214     isa_mem_base = 0x11000000;
 215
 216     /* Video card */
 217     switch (jazz_model) {
 218     case JAZZ_MAGNUM:
 219         g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
 220         break;
 221     case JAZZ_PICA61:
 222         isa_vga_mm_init(0x40000000, 0x60000000, 0);
 223         break;
 224     default:
 225         break;
 226     }
 227
 228     /* Network controller */
 229     for (n = 0; n < nb_nics; n++) {
 230         nd = &nd_table[n];
 231         if (!nd->model)
 232             nd->model = qemu_strdup("dp83932");
 233         if (strcmp(nd->model, "dp83932") == 0) {
 234             dp83932_init(nd, 0x80001000, 2, rc4030[4],
 235                          rc4030_opaque, rc4030_dma_memory_rw);
 236             break;
 237         } else if (strcmp(nd->model, "?") == 0) {
 238             fprintf(stderr, "qemu: Supported NICs: dp83932\n");
 239             exit(1);
 240         } else {
 241             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 242             exit(1);
 243         }
 244     }
 245
 246     /* SCSI adapter */
 247     esp_init(0x80002000, 0,
 248              rc4030_dma_read, rc4030_dma_write, dmas[0],
 249              rc4030[5], &esp_reset, &dma_enable);
 250
 251     /* Floppy */
 252     if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
 253         fprintf(stderr, "qemu: too many floppy drives\n");
 254         exit(1);
 255     }
 256     for (n = 0; n < MAX_FD; n++) {
 257         fds[n] = drive_get(IF_FLOPPY, 0, n);
 258     }
 259     fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
 260
 261     /* Real time clock */
 262     rtc_init(1980, NULL);
 263     s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL,
 264                                    DEVICE_NATIVE_ENDIAN);
 265     cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
 266
 267     /* Keyboard (i8042) */
 268     i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
 269
 270     /* Serial ports */
 271     if (serial_hds[0]) {
 272 #ifdef TARGET_WORDS_BIGENDIAN
 273         serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1);
 274 #else
 275         serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0);
 276 #endif
 277     }
 278     if (serial_hds[1]) {
 279 #ifdef TARGET_WORDS_BIGENDIAN
 280         serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1);
 281 #else
 282         serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0);
 283 #endif
 284     }
 285
 286     /* Parallel port */
 287     if (parallel_hds[0])
 288         parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
 289
 290     /* Sound card */
 291     /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
 292     audio_init(i8259);
 293
 294     /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
 295     ds1225y_init(0x80009000, "nvram");
 296
 297     /* LED indicator */
 298     jazz_led_init(0x8000f000);
 299 }
 300
 301 static
 302 void mips_magnum_init (ram_addr_t ram_size,
 303                        const char *boot_device,
 304                        const char *kernel_filename, const char *kernel_cmdline,
 305                        const char *initrd_filename, const char *cpu_model)
 306 {
 307     mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM);
 308 }
 309
 310 static
 311 void mips_pica61_init (ram_addr_t ram_size,
 312                        const char *boot_device,
 313                        const char *kernel_filename, const char *kernel_cmdline,
 314                        const char *initrd_filename, const char *cpu_model)
 315 {
 316     mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61);
 317 }
 318
 319 static QEMUMachine mips_magnum_machine = {
 320     .name = "magnum",
 321     .desc = "MIPS Magnum",
 322     .init = mips_magnum_init,
 323     .use_scsi = 1,
 324 };
 325
 326 static QEMUMachine mips_pica61_machine = {
 327     .name = "pica61",
 328     .desc = "Acer Pica 61",
 329     .init = mips_pica61_init,
 330     .use_scsi = 1,
 331 };
 332
 333 static void mips_jazz_machine_init(void)
 334 {
 335     qemu_register_machine(&mips_magnum_machine);
 336     qemu_register_machine(&mips_pica61_machine);
 337 }
 338
 339 machine_init(mips_jazz_machine_init);