hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licenced under the GNU GPL v2.
   7  */
   8
   9 #include "hw.h"
  10 #include "arm-misc.h"
  11 #include "devices.h"
  12 #include "net.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "pc.h"
  16 #include "qemu-timer.h"
  17 #include "block.h"
  18 #include "flash.h"
  19 #include "console.h"
  20 #include "audio/audio.h"
  21 #include "i2c.h"
  22
  23 #define MP_MISC_BASE            0x80002000
  24 #define MP_MISC_SIZE            0x00001000
  25
  26 #define MP_ETH_BASE             0x80008000
  27 #define MP_ETH_SIZE             0x00001000
  28
  29 #define MP_WLAN_BASE            0x8000C000
  30 #define MP_WLAN_SIZE            0x00000800
  31
  32 #define MP_UART1_BASE           0x8000C840
  33 #define MP_UART2_BASE           0x8000C940
  34
  35 #define MP_GPIO_BASE            0x8000D000
  36 #define MP_GPIO_SIZE            0x00001000
  37
  38 #define MP_FLASHCFG_BASE        0x90006000
  39 #define MP_FLASHCFG_SIZE        0x00001000
  40
  41 #define MP_AUDIO_BASE           0x90007000
  42 #define MP_AUDIO_SIZE           0x00001000
  43
  44 #define MP_PIC_BASE             0x90008000
  45 #define MP_PIC_SIZE             0x00001000
  46
  47 #define MP_PIT_BASE             0x90009000
  48 #define MP_PIT_SIZE             0x00001000
  49
  50 #define MP_LCD_BASE             0x9000c000
  51 #define MP_LCD_SIZE             0x00001000
  52
  53 #define MP_SRAM_BASE            0xC0000000
  54 #define MP_SRAM_SIZE            0x00020000
  55
  56 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  57 #define MP_FLASH_SIZE_MAX       32*1024*1024
  58
  59 #define MP_TIMER1_IRQ           4
  60 /* ... */
  61 #define MP_TIMER4_IRQ           7
  62 #define MP_EHCI_IRQ             8
  63 #define MP_ETH_IRQ              9
  64 #define MP_UART1_IRQ            11
  65 #define MP_UART2_IRQ            11
  66 #define MP_GPIO_IRQ             12
  67 #define MP_RTC_IRQ              28
  68 #define MP_AUDIO_IRQ            30
  69
  70 static uint32_t gpio_in_state = 0xffffffff;
  71 static uint32_t gpio_isr;
  72 static uint32_t gpio_out_state;
  73 static ram_addr_t sram_off;
  74
  75 typedef enum i2c_state {
  76     STOPPED = 0,
  77     INITIALIZING,
  78     SENDING_BIT7,
  79     SENDING_BIT6,
  80     SENDING_BIT5,
  81     SENDING_BIT4,
  82     SENDING_BIT3,
  83     SENDING_BIT2,
  84     SENDING_BIT1,
  85     SENDING_BIT0,
  86     WAITING_FOR_ACK,
  87     RECEIVING_BIT7,
  88     RECEIVING_BIT6,
  89     RECEIVING_BIT5,
  90     RECEIVING_BIT4,
  91     RECEIVING_BIT3,
  92     RECEIVING_BIT2,
  93     RECEIVING_BIT1,
  94     RECEIVING_BIT0,
  95     SENDING_ACK
  96 } i2c_state;
  97
  98 typedef struct i2c_interface {
  99     i2c_bus *bus;
 100     i2c_state state;
 101     int last_data;
 102     int last_clock;
 103     uint8_t buffer;
 104     int current_addr;
 105 } i2c_interface;
 106
 107 static void i2c_enter_stop(i2c_interface *i2c)
 108 {
 109     if (i2c->current_addr >= 0)
 110         i2c_end_transfer(i2c->bus);
 111     i2c->current_addr = -1;
 112     i2c->state = STOPPED;
 113 }
 114
 115 static void i2c_state_update(i2c_interface *i2c, int data, int clock)
 116 {
 117     if (!i2c)
 118         return;
 119
 120     switch (i2c->state) {
 121     case STOPPED:
 122         if (data == 0 && i2c->last_data == 1 && clock == 1)
 123             i2c->state = INITIALIZING;
 124         break;
 125
 126     case INITIALIZING:
 127         if (clock == 0 && i2c->last_clock == 1 && data == 0)
 128             i2c->state = SENDING_BIT7;
 129         else
 130             i2c_enter_stop(i2c);
 131         break;
 132
 133     case SENDING_BIT7 ... SENDING_BIT0:
 134         if (clock == 0 && i2c->last_clock == 1) {
 135             i2c->buffer = (i2c->buffer << 1) | data;
 136             i2c->state++; /* will end up in WAITING_FOR_ACK */
 137         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 138             i2c_enter_stop(i2c);
 139         break;
 140
 141     case WAITING_FOR_ACK:
 142         if (clock == 0 && i2c->last_clock == 1) {
 143             if (i2c->current_addr < 0) {
 144                 i2c->current_addr = i2c->buffer;
 145                 i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
 146                                    i2c->buffer & 1);
 147             } else
 148                 i2c_send(i2c->bus, i2c->buffer);
 149             if (i2c->current_addr & 1) {
 150                 i2c->state = RECEIVING_BIT7;
 151                 i2c->buffer = i2c_recv(i2c->bus);
 152             } else
 153                 i2c->state = SENDING_BIT7;
 154         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 155             i2c_enter_stop(i2c);
 156         break;
 157
 158     case RECEIVING_BIT7 ... RECEIVING_BIT0:
 159         if (clock == 0 && i2c->last_clock == 1) {
 160             i2c->state++; /* will end up in SENDING_ACK */
 161             i2c->buffer <<= 1;
 162         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 163             i2c_enter_stop(i2c);
 164         break;
 165
 166     case SENDING_ACK:
 167         if (clock == 0 && i2c->last_clock == 1) {
 168             i2c->state = RECEIVING_BIT7;
 169             if (data == 0)
 170                 i2c->buffer = i2c_recv(i2c->bus);
 171             else
 172                 i2c_nack(i2c->bus);
 173         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 174             i2c_enter_stop(i2c);
 175         break;
 176     }
 177
 178     i2c->last_data = data;
 179     i2c->last_clock = clock;
 180 }
 181
 182 static int i2c_get_data(i2c_interface *i2c)
 183 {
 184     if (!i2c)
 185         return 0;
 186
 187     switch (i2c->state) {
 188     case RECEIVING_BIT7 ... RECEIVING_BIT0:
 189         return (i2c->buffer >> 7);
 190
 191     case WAITING_FOR_ACK:
 192     default:
 193         return 0;
 194     }
 195 }
 196
 197 static i2c_interface *mixer_i2c;
 198
 199 #ifdef HAS_AUDIO
 200
 201 /* Audio register offsets */
 202 #define MP_AUDIO_PLAYBACK_MODE  0x00
 203 #define MP_AUDIO_CLOCK_DIV      0x18
 204 #define MP_AUDIO_IRQ_STATUS     0x20
 205 #define MP_AUDIO_IRQ_ENABLE     0x24
 206 #define MP_AUDIO_TX_START_LO    0x28
 207 #define MP_AUDIO_TX_THRESHOLD   0x2C
 208 #define MP_AUDIO_TX_STATUS      0x38
 209 #define MP_AUDIO_TX_START_HI    0x40
 210
 211 /* Status register and IRQ enable bits */
 212 #define MP_AUDIO_TX_HALF        (1 << 6)
 213 #define MP_AUDIO_TX_FULL        (1 << 7)
 214
 215 /* Playback mode bits */
 216 #define MP_AUDIO_16BIT_SAMPLE   (1 << 0)
 217 #define MP_AUDIO_PLAYBACK_EN    (1 << 7)
 218 #define MP_AUDIO_CLOCK_24MHZ    (1 << 9)
 219 #define MP_AUDIO_MONO           (1 << 14)
 220
 221 /* Wolfson 8750 I2C address */
 222 #define MP_WM_ADDR              0x34
 223
 224 static const char audio_name[] = "mv88w8618";
 225
 226 typedef struct musicpal_audio_state {
 227     qemu_irq irq;
 228     uint32_t playback_mode;
 229     uint32_t status;
 230     uint32_t irq_enable;
 231     unsigned long phys_buf;
 232     uint32_t target_buffer;
 233     unsigned int threshold;
 234     unsigned int play_pos;
 235     unsigned int last_free;
 236     uint32_t clock_div;
 237     i2c_slave *wm;
 238 } musicpal_audio_state;
 239
 240 static void audio_callback(void *opaque, int free_out, int free_in)
 241 {
 242     musicpal_audio_state *s = opaque;
 243     int16_t *codec_buffer;
 244     int8_t buf[4096];
 245     int8_t *mem_buffer;
 246     int pos, block_size;
 247
 248     if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
 249         return;
 250
 251     if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
 252         free_out <<= 1;
 253
 254     if (!(s->playback_mode & MP_AUDIO_MONO))
 255         free_out <<= 1;
 256
 257     block_size = s->threshold/2;
 258     if (free_out - s->last_free < block_size)
 259         return;
 260
 261     if (block_size > 4096)
 262         return;
 263
 264     cpu_physical_memory_read(s->target_buffer + s->play_pos, (void *)buf,
 265                              block_size);
 266     mem_buffer = buf;
 267     if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) {
 268         if (s->playback_mode & MP_AUDIO_MONO) {
 269             codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
 270             for (pos = 0; pos < block_size; pos += 2) {
 271                 *codec_buffer++ = *(int16_t *)mem_buffer;
 272                 *codec_buffer++ = *(int16_t *)mem_buffer;
 273                 mem_buffer += 2;
 274             }
 275         } else
 276             memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
 277                    (uint32_t *)mem_buffer, block_size);
 278     } else {
 279         if (s->playback_mode & MP_AUDIO_MONO) {
 280             codec_buffer = wm8750_dac_buffer(s->wm, block_size);
 281             for (pos = 0; pos < block_size; pos++) {
 282                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer);
 283                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 284             }
 285         } else {
 286             codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
 287             for (pos = 0; pos < block_size; pos += 2) {
 288                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 289                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 290             }
 291         }
 292     }
 293     wm8750_dac_commit(s->wm);
 294
 295     s->last_free = free_out - block_size;
 296
 297     if (s->play_pos == 0) {
 298         s->status |= MP_AUDIO_TX_HALF;
 299         s->play_pos = block_size;
 300     } else {
 301         s->status |= MP_AUDIO_TX_FULL;
 302         s->play_pos = 0;
 303     }
 304
 305     if (s->status & s->irq_enable)
 306         qemu_irq_raise(s->irq);
 307 }
 308
 309 static void musicpal_audio_clock_update(musicpal_audio_state *s)
 310 {
 311     int rate;
 312
 313     if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
 314         rate = 24576000 / 64; /* 24.576MHz */
 315     else
 316         rate = 11289600 / 64; /* 11.2896MHz */
 317
 318     rate /= ((s->clock_div >> 8) & 0xff) + 1;
 319
 320     wm8750_set_bclk_in(s->wm, rate);
 321 }
 322
 323 static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset)
 324 {
 325     musicpal_audio_state *s = opaque;
 326
 327     switch (offset) {
 328     case MP_AUDIO_PLAYBACK_MODE:
 329         return s->playback_mode;
 330
 331     case MP_AUDIO_CLOCK_DIV:
 332         return s->clock_div;
 333
 334     case MP_AUDIO_IRQ_STATUS:
 335         return s->status;
 336
 337     case MP_AUDIO_IRQ_ENABLE:
 338         return s->irq_enable;
 339
 340     case MP_AUDIO_TX_STATUS:
 341         return s->play_pos >> 2;
 342
 343     default:
 344         return 0;
 345     }
 346 }
 347
 348 static void musicpal_audio_write(void *opaque, target_phys_addr_t offset,
 349                                  uint32_t value)
 350 {
 351     musicpal_audio_state *s = opaque;
 352
 353     switch (offset) {
 354     case MP_AUDIO_PLAYBACK_MODE:
 355         if (value & MP_AUDIO_PLAYBACK_EN &&
 356             !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) {
 357             s->status = 0;
 358             s->last_free = 0;
 359             s->play_pos = 0;
 360         }
 361         s->playback_mode = value;
 362         musicpal_audio_clock_update(s);
 363         break;
 364
 365     case MP_AUDIO_CLOCK_DIV:
 366         s->clock_div = value;
 367         s->last_free = 0;
 368         s->play_pos = 0;
 369         musicpal_audio_clock_update(s);
 370         break;
 371
 372     case MP_AUDIO_IRQ_STATUS:
 373         s->status &= ~value;
 374         break;
 375
 376     case MP_AUDIO_IRQ_ENABLE:
 377         s->irq_enable = value;
 378         if (s->status & s->irq_enable)
 379             qemu_irq_raise(s->irq);
 380         break;
 381
 382     case MP_AUDIO_TX_START_LO:
 383         s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF);
 384         s->target_buffer = s->phys_buf;
 385         s->play_pos = 0;
 386         s->last_free = 0;
 387         break;
 388
 389     case MP_AUDIO_TX_THRESHOLD:
 390         s->threshold = (value + 1) * 4;
 391         break;
 392
 393     case MP_AUDIO_TX_START_HI:
 394         s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16);
 395         s->target_buffer = s->phys_buf;
 396         s->play_pos = 0;
 397         s->last_free = 0;
 398         break;
 399     }
 400 }
 401
 402 static void musicpal_audio_reset(void *opaque)
 403 {
 404     musicpal_audio_state *s = opaque;
 405
 406     s->playback_mode = 0;
 407     s->status = 0;
 408     s->irq_enable = 0;
 409 }
 410
 411 static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
 412     musicpal_audio_read,
 413     musicpal_audio_read,
 414     musicpal_audio_read
 415 };
 416
 417 static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
 418     musicpal_audio_write,
 419     musicpal_audio_write,
 420     musicpal_audio_write
 421 };
 422
 423 static i2c_interface *musicpal_audio_init(qemu_irq irq)
 424 {
 425     AudioState *audio;
 426     musicpal_audio_state *s;
 427     i2c_interface *i2c;
 428     int iomemtype;
 429
 430     audio = AUD_init();
 431
 432     s = qemu_mallocz(sizeof(musicpal_audio_state));
 433     s->irq = irq;
 434
 435     i2c = qemu_mallocz(sizeof(i2c_interface));
 436     i2c->bus = i2c_init_bus();
 437     i2c->current_addr = -1;
 438
 439     s->wm = wm8750_init(i2c->bus, audio);
 440     if (!s->wm)
 441         return NULL;
 442     i2c_set_slave_address(s->wm, MP_WM_ADDR);
 443     wm8750_data_req_set(s->wm, audio_callback, s);
 444
 445     iomemtype = cpu_register_io_memory(0, musicpal_audio_readfn,
 446                        musicpal_audio_writefn, s);
 447     cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype);
 448
 449     qemu_register_reset(musicpal_audio_reset, s);
 450
 451     return i2c;
 452 }
 453 #else  /* !HAS_AUDIO */
 454 static i2c_interface *musicpal_audio_init(qemu_irq irq)
 455 {
 456     return NULL;
 457 }
 458 #endif /* !HAS_AUDIO */
 459
 460 /* Ethernet register offsets */
 461 #define MP_ETH_SMIR             0x010
 462 #define MP_ETH_PCXR             0x408
 463 #define MP_ETH_SDCMR            0x448
 464 #define MP_ETH_ICR              0x450
 465 #define MP_ETH_IMR              0x458
 466 #define MP_ETH_FRDP0            0x480
 467 #define MP_ETH_FRDP1            0x484
 468 #define MP_ETH_FRDP2            0x488
 469 #define MP_ETH_FRDP3            0x48C
 470 #define MP_ETH_CRDP0            0x4A0
 471 #define MP_ETH_CRDP1            0x4A4
 472 #define MP_ETH_CRDP2            0x4A8
 473 #define MP_ETH_CRDP3            0x4AC
 474 #define MP_ETH_CTDP0            0x4E0
 475 #define MP_ETH_CTDP1            0x4E4
 476 #define MP_ETH_CTDP2            0x4E8
 477 #define MP_ETH_CTDP3            0x4EC
 478
 479 /* MII PHY access */
 480 #define MP_ETH_SMIR_DATA        0x0000FFFF
 481 #define MP_ETH_SMIR_ADDR        0x03FF0000
 482 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
 483 #define MP_ETH_SMIR_RDVALID     (1 << 27)
 484
 485 /* PHY registers */
 486 #define MP_ETH_PHY1_BMSR        0x00210000
 487 #define MP_ETH_PHY1_PHYSID1     0x00410000
 488 #define MP_ETH_PHY1_PHYSID2     0x00610000
 489
 490 #define MP_PHY_BMSR_LINK        0x0004
 491 #define MP_PHY_BMSR_AUTONEG     0x0008
 492
 493 #define MP_PHY_88E3015          0x01410E20
 494
 495 /* TX descriptor status */
 496 #define MP_ETH_TX_OWN           (1 << 31)
 497
 498 /* RX descriptor status */
 499 #define MP_ETH_RX_OWN           (1 << 31)
 500
 501 /* Interrupt cause/mask bits */
 502 #define MP_ETH_IRQ_RX_BIT       0
 503 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 504 #define MP_ETH_IRQ_TXHI_BIT     2
 505 #define MP_ETH_IRQ_TXLO_BIT     3
 506
 507 /* Port config bits */
 508 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 509
 510 /* SDMA command bits */
 511 #define MP_ETH_CMD_TXHI         (1 << 23)
 512 #define MP_ETH_CMD_TXLO         (1 << 22)
 513
 514 typedef struct mv88w8618_tx_desc {
 515     uint32_t cmdstat;
 516     uint16_t res;
 517     uint16_t bytes;
 518     uint32_t buffer;
 519     uint32_t next;
 520 } mv88w8618_tx_desc;
 521
 522 typedef struct mv88w8618_rx_desc {
 523     uint32_t cmdstat;
 524     uint16_t bytes;
 525     uint16_t buffer_size;
 526     uint32_t buffer;
 527     uint32_t next;
 528 } mv88w8618_rx_desc;
 529
 530 typedef struct mv88w8618_eth_state {
 531     qemu_irq irq;
 532     uint32_t smir;
 533     uint32_t icr;
 534     uint32_t imr;
 535     int mmio_index;
 536     int vlan_header;
 537     uint32_t tx_queue[2];
 538     uint32_t rx_queue[4];
 539     uint32_t frx_queue[4];
 540     uint32_t cur_rx[4];
 541     VLANClientState *vc;
 542 } mv88w8618_eth_state;
 543
 544 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 545 {
 546     cpu_to_le32s(&desc->cmdstat);
 547     cpu_to_le16s(&desc->bytes);
 548     cpu_to_le16s(&desc->buffer_size);
 549     cpu_to_le32s(&desc->buffer);
 550     cpu_to_le32s(&desc->next);
 551     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 552 }
 553
 554 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 555 {
 556     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 557     le32_to_cpus(&desc->cmdstat);
 558     le16_to_cpus(&desc->bytes);
 559     le16_to_cpus(&desc->buffer_size);
 560     le32_to_cpus(&desc->buffer);
 561     le32_to_cpus(&desc->next);
 562 }
 563
 564 static int eth_can_receive(void *opaque)
 565 {
 566     return 1;
 567 }
 568
 569 static void eth_receive(void *opaque, const uint8_t *buf, int size)
 570 {
 571     mv88w8618_eth_state *s = opaque;
 572     uint32_t desc_addr;
 573     mv88w8618_rx_desc desc;
 574     int i;
 575
 576     for (i = 0; i < 4; i++) {
 577         desc_addr = s->cur_rx[i];
 578         if (!desc_addr)
 579             continue;
 580         do {
 581             eth_rx_desc_get(desc_addr, &desc);
 582             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 583                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 584                                           buf, size);
 585                 desc.bytes = size + s->vlan_header;
 586                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 587                 s->cur_rx[i] = desc.next;
 588
 589                 s->icr |= MP_ETH_IRQ_RX;
 590                 if (s->icr & s->imr)
 591                     qemu_irq_raise(s->irq);
 592                 eth_rx_desc_put(desc_addr, &desc);
 593                 return;
 594             }
 595             desc_addr = desc.next;
 596         } while (desc_addr != s->rx_queue[i]);
 597     }
 598 }
 599
 600 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 601 {
 602     cpu_to_le32s(&desc->cmdstat);
 603     cpu_to_le16s(&desc->res);
 604     cpu_to_le16s(&desc->bytes);
 605     cpu_to_le32s(&desc->buffer);
 606     cpu_to_le32s(&desc->next);
 607     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 608 }
 609
 610 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 611 {
 612     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 613     le32_to_cpus(&desc->cmdstat);
 614     le16_to_cpus(&desc->res);
 615     le16_to_cpus(&desc->bytes);
 616     le32_to_cpus(&desc->buffer);
 617     le32_to_cpus(&desc->next);
 618 }
 619
 620 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 621 {
 622     uint32_t desc_addr = s->tx_queue[queue_index];
 623     mv88w8618_tx_desc desc;
 624     uint8_t buf[2048];
 625     int len;
 626
 627
 628     do {
 629         eth_tx_desc_get(desc_addr, &desc);
 630         if (desc.cmdstat & MP_ETH_TX_OWN) {
 631             len = desc.bytes;
 632             if (len < 2048) {
 633                 cpu_physical_memory_read(desc.buffer, buf, len);
 634                 qemu_send_packet(s->vc, buf, len);
 635             }
 636             desc.cmdstat &= ~MP_ETH_TX_OWN;
 637             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 638             eth_tx_desc_put(desc_addr, &desc);
 639         }
 640         desc_addr = desc.next;
 641     } while (desc_addr != s->tx_queue[queue_index]);
 642 }
 643
 644 static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
 645 {
 646     mv88w8618_eth_state *s = opaque;
 647
 648     switch (offset) {
 649     case MP_ETH_SMIR:
 650         if (s->smir & MP_ETH_SMIR_OPCODE) {
 651             switch (s->smir & MP_ETH_SMIR_ADDR) {
 652             case MP_ETH_PHY1_BMSR:
 653                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 654                        MP_ETH_SMIR_RDVALID;
 655             case MP_ETH_PHY1_PHYSID1:
 656                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 657             case MP_ETH_PHY1_PHYSID2:
 658                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 659             default:
 660                 return MP_ETH_SMIR_RDVALID;
 661             }
 662         }
 663         return 0;
 664
 665     case MP_ETH_ICR:
 666         return s->icr;
 667
 668     case MP_ETH_IMR:
 669         return s->imr;
 670
 671     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 672         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 673
 674     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 675         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 676
 677     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 678         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 679
 680     default:
 681         return 0;
 682     }
 683 }
 684
 685 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 686                                 uint32_t value)
 687 {
 688     mv88w8618_eth_state *s = opaque;
 689
 690     switch (offset) {
 691     case MP_ETH_SMIR:
 692         s->smir = value;
 693         break;
 694
 695     case MP_ETH_PCXR:
 696         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 697         break;
 698
 699     case MP_ETH_SDCMR:
 700         if (value & MP_ETH_CMD_TXHI)
 701             eth_send(s, 1);
 702         if (value & MP_ETH_CMD_TXLO)
 703             eth_send(s, 0);
 704         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
 705             qemu_irq_raise(s->irq);
 706         break;
 707
 708     case MP_ETH_ICR:
 709         s->icr &= value;
 710         break;
 711
 712     case MP_ETH_IMR:
 713         s->imr = value;
 714         if (s->icr & s->imr)
 715             qemu_irq_raise(s->irq);
 716         break;
 717
 718     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 719         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 720         break;
 721
 722     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 723         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 724             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 725         break;
 726
 727     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 728         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 729         break;
 730     }
 731 }
 732
 733 static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
 734     mv88w8618_eth_read,
 735     mv88w8618_eth_read,
 736     mv88w8618_eth_read
 737 };
 738
 739 static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
 740     mv88w8618_eth_write,
 741     mv88w8618_eth_write,
 742     mv88w8618_eth_write
 743 };
 744
 745 static void eth_cleanup(VLANClientState *vc)
 746 {
 747     mv88w8618_eth_state *s = vc->opaque;
 748
 749     cpu_unregister_io_memory(s->mmio_index);
 750
 751     qemu_free(s);
 752 }
 753
 754 static void mv88w8618_eth_init(NICInfo *nd, uint32_t base, qemu_irq irq)
 755 {
 756     mv88w8618_eth_state *s;
 757
 758     qemu_check_nic_model(nd, "mv88w8618");
 759
 760     s = qemu_mallocz(sizeof(mv88w8618_eth_state));
 761     s->irq = irq;
 762     s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
 763                                  eth_receive, eth_can_receive,
 764                                  eth_cleanup, s);
 765     s->mmio_index = cpu_register_io_memory(0, mv88w8618_eth_readfn,
 766                                            mv88w8618_eth_writefn, s);
 767     cpu_register_physical_memory(base, MP_ETH_SIZE, s->mmio_index);
 768 }
 769
 770 /* LCD register offsets */
 771 #define MP_LCD_IRQCTRL          0x180
 772 #define MP_LCD_IRQSTAT          0x184
 773 #define MP_LCD_SPICTRL          0x1ac
 774 #define MP_LCD_INST             0x1bc
 775 #define MP_LCD_DATA             0x1c0
 776
 777 /* Mode magics */
 778 #define MP_LCD_SPI_DATA         0x00100011
 779 #define MP_LCD_SPI_CMD          0x00104011
 780 #define MP_LCD_SPI_INVALID      0x00000000
 781
 782 /* Commmands */
 783 #define MP_LCD_INST_SETPAGE0    0xB0
 784 /* ... */
 785 #define MP_LCD_INST_SETPAGE7    0xB7
 786
 787 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 788
 789 typedef struct musicpal_lcd_state {
 790     uint32_t mode;
 791     uint32_t irqctrl;
 792     int page;
 793     int page_off;
 794     DisplayState *ds;
 795     uint8_t video_ram[128*64/8];
 796 } musicpal_lcd_state;
 797
 798 static uint32_t lcd_brightness;
 799
 800 static uint8_t scale_lcd_color(uint8_t col)
 801 {
 802     int tmp = col;
 803
 804     switch (lcd_brightness) {
 805     case 0x00000007: /* 0 */
 806         return 0;
 807
 808     case 0x00020000: /* 1 */
 809         return (tmp * 1) / 7;
 810
 811     case 0x00020001: /* 2 */
 812         return (tmp * 2) / 7;
 813
 814     case 0x00040000: /* 3 */
 815         return (tmp * 3) / 7;
 816
 817     case 0x00010006: /* 4 */
 818         return (tmp * 4) / 7;
 819
 820     case 0x00020005: /* 5 */
 821         return (tmp * 5) / 7;
 822
 823     case 0x00040003: /* 6 */
 824         return (tmp * 6) / 7;
 825
 826     case 0x00030004: /* 7 */
 827     default:
 828         return col;
 829     }
 830 }
 831
 832 #define SET_LCD_PIXEL(depth, type) \
 833 static inline void glue(set_lcd_pixel, depth) \
 834         (musicpal_lcd_state *s, int x, int y, type col) \
 835 { \
 836     int dx, dy; \
 837     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 838 \
 839     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 840         for (dx = 0; dx < 3; dx++, pixel++) \
 841             *pixel = col; \
 842 }
 843 SET_LCD_PIXEL(8, uint8_t)
 844 SET_LCD_PIXEL(16, uint16_t)
 845 SET_LCD_PIXEL(32, uint32_t)
 846
 847 #include "pixel_ops.h"
 848
 849 static void lcd_refresh(void *opaque)
 850 {
 851     musicpal_lcd_state *s = opaque;
 852     int x, y, col;
 853
 854     switch (ds_get_bits_per_pixel(s->ds)) {
 855     case 0:
 856         return;
 857 #define LCD_REFRESH(depth, func) \
 858     case depth: \
 859         col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 860                    scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 861                    scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
 862         for (x = 0; x < 128; x++) \
 863             for (y = 0; y < 64; y++) \
 864                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
 865                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 866                 else \
 867                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 868         break;
 869     LCD_REFRESH(8, rgb_to_pixel8)
 870     LCD_REFRESH(16, rgb_to_pixel16)
 871     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 872                      rgb_to_pixel32bgr : rgb_to_pixel32))
 873     default:
 874         hw_error("unsupported colour depth %i\n",
 875                   ds_get_bits_per_pixel(s->ds));
 876     }
 877
 878     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 879 }
 880
 881 static void lcd_invalidate(void *opaque)
 882 {
 883 }
 884
 885 static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
 886 {
 887     musicpal_lcd_state *s = opaque;
 888
 889     switch (offset) {
 890     case MP_LCD_IRQCTRL:
 891         return s->irqctrl;
 892
 893     default:
 894         return 0;
 895     }
 896 }
 897
 898 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 899                                uint32_t value)
 900 {
 901     musicpal_lcd_state *s = opaque;
 902
 903     switch (offset) {
 904     case MP_LCD_IRQCTRL:
 905         s->irqctrl = value;
 906         break;
 907
 908     case MP_LCD_SPICTRL:
 909         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
 910             s->mode = value;
 911         else
 912             s->mode = MP_LCD_SPI_INVALID;
 913         break;
 914
 915     case MP_LCD_INST:
 916         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 917             s->page = value - MP_LCD_INST_SETPAGE0;
 918             s->page_off = 0;
 919         }
 920         break;
 921
 922     case MP_LCD_DATA:
 923         if (s->mode == MP_LCD_SPI_CMD) {
 924             if (value >= MP_LCD_INST_SETPAGE0 &&
 925                 value <= MP_LCD_INST_SETPAGE7) {
 926                 s->page = value - MP_LCD_INST_SETPAGE0;
 927                 s->page_off = 0;
 928             }
 929         } else if (s->mode == MP_LCD_SPI_DATA) {
 930             s->video_ram[s->page*128 + s->page_off] = value;
 931             s->page_off = (s->page_off + 1) & 127;
 932         }
 933         break;
 934     }
 935 }
 936
 937 static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
 938     musicpal_lcd_read,
 939     musicpal_lcd_read,
 940     musicpal_lcd_read
 941 };
 942
 943 static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
 944     musicpal_lcd_write,
 945     musicpal_lcd_write,
 946     musicpal_lcd_write
 947 };
 948
 949 static void musicpal_lcd_init(void)
 950 {
 951     musicpal_lcd_state *s;
 952     int iomemtype;
 953
 954     s = qemu_mallocz(sizeof(musicpal_lcd_state));
 955     iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
 956                                        musicpal_lcd_writefn, s);
 957     cpu_register_physical_memory(MP_LCD_BASE, MP_LCD_SIZE, iomemtype);
 958
 959     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 960                                  NULL, NULL, s);
 961     qemu_console_resize(s->ds, 128*3, 64*3);
 962 }
 963
 964 /* PIC register offsets */
 965 #define MP_PIC_STATUS           0x00
 966 #define MP_PIC_ENABLE_SET       0x08
 967 #define MP_PIC_ENABLE_CLR       0x0C
 968
 969 typedef struct mv88w8618_pic_state
 970 {
 971     uint32_t level;
 972     uint32_t enabled;
 973     qemu_irq parent_irq;
 974 } mv88w8618_pic_state;
 975
 976 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 977 {
 978     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 979 }
 980
 981 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 982 {
 983     mv88w8618_pic_state *s = opaque;
 984
 985     if (level)
 986         s->level |= 1 << irq;
 987     else
 988         s->level &= ~(1 << irq);
 989     mv88w8618_pic_update(s);
 990 }
 991
 992 static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
 993 {
 994     mv88w8618_pic_state *s = opaque;
 995
 996     switch (offset) {
 997     case MP_PIC_STATUS:
 998         return s->level & s->enabled;
 999
1000     default:
1001         return 0;
1002     }
1003 }
1004
1005 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
1006                                 uint32_t value)
1007 {
1008     mv88w8618_pic_state *s = opaque;
1009
1010     switch (offset) {
1011     case MP_PIC_ENABLE_SET:
1012         s->enabled |= value;
1013         break;
1014
1015     case MP_PIC_ENABLE_CLR:
1016         s->enabled &= ~value;
1017         s->level &= ~value;
1018         break;
1019     }
1020     mv88w8618_pic_update(s);
1021 }
1022
1023 static void mv88w8618_pic_reset(void *opaque)
1024 {
1025     mv88w8618_pic_state *s = opaque;
1026
1027     s->level = 0;
1028     s->enabled = 0;
1029 }
1030
1031 static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
1032     mv88w8618_pic_read,
1033     mv88w8618_pic_read,
1034     mv88w8618_pic_read
1035 };
1036
1037 static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
1038     mv88w8618_pic_write,
1039     mv88w8618_pic_write,
1040     mv88w8618_pic_write
1041 };
1042
1043 static qemu_irq *mv88w8618_pic_init(uint32_t base, qemu_irq parent_irq)
1044 {
1045     mv88w8618_pic_state *s;
1046     int iomemtype;
1047     qemu_irq *qi;
1048
1049     s = qemu_mallocz(sizeof(mv88w8618_pic_state));
1050     qi = qemu_allocate_irqs(mv88w8618_pic_set_irq, s, 32);
1051     s->parent_irq = parent_irq;
1052     iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
1053                                        mv88w8618_pic_writefn, s);
1054     cpu_register_physical_memory(base, MP_PIC_SIZE, iomemtype);
1055
1056     qemu_register_reset(mv88w8618_pic_reset, s);
1057
1058     return qi;
1059 }
1060
1061 /* PIT register offsets */
1062 #define MP_PIT_TIMER1_LENGTH    0x00
1063 /* ... */
1064 #define MP_PIT_TIMER4_LENGTH    0x0C
1065 #define MP_PIT_CONTROL          0x10
1066 #define MP_PIT_TIMER1_VALUE     0x14
1067 /* ... */
1068 #define MP_PIT_TIMER4_VALUE     0x20
1069 #define MP_BOARD_RESET          0x34
1070
1071 /* Magic board reset value (probably some watchdog behind it) */
1072 #define MP_BOARD_RESET_MAGIC    0x10000
1073
1074 typedef struct mv88w8618_timer_state {
1075     ptimer_state *timer;
1076     uint32_t limit;
1077     int freq;
1078     qemu_irq irq;
1079 } mv88w8618_timer_state;
1080
1081 typedef struct mv88w8618_pit_state {
1082     void *timer[4];
1083     uint32_t control;
1084 } mv88w8618_pit_state;
1085
1086 static void mv88w8618_timer_tick(void *opaque)
1087 {
1088     mv88w8618_timer_state *s = opaque;
1089
1090     qemu_irq_raise(s->irq);
1091 }
1092
1093 static void *mv88w8618_timer_init(uint32_t freq, qemu_irq irq)
1094 {
1095     mv88w8618_timer_state *s;
1096     QEMUBH *bh;
1097
1098     s = qemu_mallocz(sizeof(mv88w8618_timer_state));
1099     s->irq = irq;
1100     s->freq = freq;
1101
1102     bh = qemu_bh_new(mv88w8618_timer_tick, s);
1103     s->timer = ptimer_init(bh);
1104
1105     return s;
1106 }
1107
1108 static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
1109 {
1110     mv88w8618_pit_state *s = opaque;
1111     mv88w8618_timer_state *t;
1112
1113     switch (offset) {
1114     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
1115         t = s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
1116         return ptimer_get_count(t->timer);
1117
1118     default:
1119         return 0;
1120     }
1121 }
1122
1123 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
1124                                 uint32_t value)
1125 {
1126     mv88w8618_pit_state *s = opaque;
1127     mv88w8618_timer_state *t;
1128     int i;
1129
1130     switch (offset) {
1131     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
1132         t = s->timer[offset >> 2];
1133         t->limit = value;
1134         ptimer_set_limit(t->timer, t->limit, 1);
1135         break;
1136
1137     case MP_PIT_CONTROL:
1138         for (i = 0; i < 4; i++) {
1139             if (value & 0xf) {
1140                 t = s->timer[i];
1141                 ptimer_set_limit(t->timer, t->limit, 0);
1142                 ptimer_set_freq(t->timer, t->freq);
1143                 ptimer_run(t->timer, 0);
1144             }
1145             value >>= 4;
1146         }
1147         break;
1148
1149     case MP_BOARD_RESET:
1150         if (value == MP_BOARD_RESET_MAGIC)
1151             qemu_system_reset_request();
1152         break;
1153     }
1154 }
1155
1156 static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
1157     mv88w8618_pit_read,
1158     mv88w8618_pit_read,
1159     mv88w8618_pit_read
1160 };
1161
1162 static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
1163     mv88w8618_pit_write,
1164     mv88w8618_pit_write,
1165     mv88w8618_pit_write
1166 };
1167
1168 static void mv88w8618_pit_init(uint32_t base, qemu_irq *pic, int irq)
1169 {
1170     int iomemtype;
1171     mv88w8618_pit_state *s;
1172
1173     s = qemu_mallocz(sizeof(mv88w8618_pit_state));
1174
1175     /* Letting them all run at 1 MHz is likely just a pragmatic
1176      * simplification. */
1177     s->timer[0] = mv88w8618_timer_init(1000000, pic[irq]);
1178     s->timer[1] = mv88w8618_timer_init(1000000, pic[irq + 1]);
1179     s->timer[2] = mv88w8618_timer_init(1000000, pic[irq + 2]);
1180     s->timer[3] = mv88w8618_timer_init(1000000, pic[irq + 3]);
1181
1182     iomemtype = cpu_register_io_memory(0, mv88w8618_pit_readfn,
1183                                        mv88w8618_pit_writefn, s);
1184     cpu_register_physical_memory(base, MP_PIT_SIZE, iomemtype);
1185 }
1186
1187 /* Flash config register offsets */
1188 #define MP_FLASHCFG_CFGR0    0x04
1189
1190 typedef struct mv88w8618_flashcfg_state {
1191     uint32_t cfgr0;
1192 } mv88w8618_flashcfg_state;
1193
1194 static uint32_t mv88w8618_flashcfg_read(void *opaque,
1195                                         target_phys_addr_t offset)
1196 {
1197     mv88w8618_flashcfg_state *s = opaque;
1198
1199     switch (offset) {
1200     case MP_FLASHCFG_CFGR0:
1201         return s->cfgr0;
1202
1203     default:
1204         return 0;
1205     }
1206 }
1207
1208 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
1209                                      uint32_t value)
1210 {
1211     mv88w8618_flashcfg_state *s = opaque;
1212
1213     switch (offset) {
1214     case MP_FLASHCFG_CFGR0:
1215         s->cfgr0 = value;
1216         break;
1217     }
1218 }
1219
1220 static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
1221     mv88w8618_flashcfg_read,
1222     mv88w8618_flashcfg_read,
1223     mv88w8618_flashcfg_read
1224 };
1225
1226 static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
1227     mv88w8618_flashcfg_write,
1228     mv88w8618_flashcfg_write,
1229     mv88w8618_flashcfg_write
1230 };
1231
1232 static void mv88w8618_flashcfg_init(uint32_t base)
1233 {
1234     int iomemtype;
1235     mv88w8618_flashcfg_state *s;
1236
1237     s = qemu_mallocz(sizeof(mv88w8618_flashcfg_state));
1238
1239     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1240     iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
1241                        mv88w8618_flashcfg_writefn, s);
1242     cpu_register_physical_memory(base, MP_FLASHCFG_SIZE, iomemtype);
1243 }
1244
1245 /* Misc register offsets */
1246 #define MP_MISC_BOARD_REVISION  0x18
1247
1248 #define MP_BOARD_REVISION       0x31
1249
1250 static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
1251 {
1252     switch (offset) {
1253     case MP_MISC_BOARD_REVISION:
1254         return MP_BOARD_REVISION;
1255
1256     default:
1257         return 0;
1258     }
1259 }
1260
1261 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
1262                                 uint32_t value)
1263 {
1264 }
1265
1266 static CPUReadMemoryFunc *musicpal_misc_readfn[] = {
1267     musicpal_misc_read,
1268     musicpal_misc_read,
1269     musicpal_misc_read,
1270 };
1271
1272 static CPUWriteMemoryFunc *musicpal_misc_writefn[] = {
1273     musicpal_misc_write,
1274     musicpal_misc_write,
1275     musicpal_misc_write,
1276 };
1277
1278 static void musicpal_misc_init(void)
1279 {
1280     int iomemtype;
1281
1282     iomemtype = cpu_register_io_memory(0, musicpal_misc_readfn,
1283                                        musicpal_misc_writefn, NULL);
1284     cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
1285 }
1286
1287 /* WLAN register offsets */
1288 #define MP_WLAN_MAGIC1          0x11c
1289 #define MP_WLAN_MAGIC2          0x124
1290
1291 static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
1292 {
1293     switch (offset) {
1294     /* Workaround to allow loading the binary-only wlandrv.ko crap
1295      * from the original Freecom firmware. */
1296     case MP_WLAN_MAGIC1:
1297         return ~3;
1298     case MP_WLAN_MAGIC2:
1299         return -1;
1300
1301     default:
1302         return 0;
1303     }
1304 }
1305
1306 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
1307                                  uint32_t value)
1308 {
1309 }
1310
1311 static CPUReadMemoryFunc *mv88w8618_wlan_readfn[] = {
1312     mv88w8618_wlan_read,
1313     mv88w8618_wlan_read,
1314     mv88w8618_wlan_read,
1315 };
1316
1317 static CPUWriteMemoryFunc *mv88w8618_wlan_writefn[] = {
1318     mv88w8618_wlan_write,
1319     mv88w8618_wlan_write,
1320     mv88w8618_wlan_write,
1321 };
1322
1323 static void mv88w8618_wlan_init(uint32_t base)
1324 {
1325     int iomemtype;
1326
1327     iomemtype = cpu_register_io_memory(0, mv88w8618_wlan_readfn,
1328                                        mv88w8618_wlan_writefn, NULL);
1329     cpu_register_physical_memory(base, MP_WLAN_SIZE, iomemtype);
1330 }
1331
1332 /* GPIO register offsets */
1333 #define MP_GPIO_OE_LO           0x008
1334 #define MP_GPIO_OUT_LO          0x00c
1335 #define MP_GPIO_IN_LO           0x010
1336 #define MP_GPIO_ISR_LO          0x020
1337 #define MP_GPIO_OE_HI           0x508
1338 #define MP_GPIO_OUT_HI          0x50c
1339 #define MP_GPIO_IN_HI           0x510
1340 #define MP_GPIO_ISR_HI          0x520
1341
1342 /* GPIO bits & masks */
1343 #define MP_GPIO_WHEEL_VOL       (1 << 8)
1344 #define MP_GPIO_WHEEL_VOL_INV   (1 << 9)
1345 #define MP_GPIO_WHEEL_NAV       (1 << 10)
1346 #define MP_GPIO_WHEEL_NAV_INV   (1 << 11)
1347 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1348 #define MP_GPIO_BTN_FAVORITS    (1 << 19)
1349 #define MP_GPIO_BTN_MENU        (1 << 20)
1350 #define MP_GPIO_BTN_VOLUME      (1 << 21)
1351 #define MP_GPIO_BTN_NAVIGATION  (1 << 22)
1352 #define MP_GPIO_I2C_DATA_BIT    29
1353 #define MP_GPIO_I2C_DATA        (1 << MP_GPIO_I2C_DATA_BIT)
1354 #define MP_GPIO_I2C_CLOCK_BIT   30
1355
1356 /* LCD brightness bits in GPIO_OE_HI */
1357 #define MP_OE_LCD_BRIGHTNESS    0x0007
1358
1359 static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
1360 {
1361     switch (offset) {
1362     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1363         return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1364
1365     case MP_GPIO_OUT_LO:
1366         return gpio_out_state & 0xFFFF;
1367     case MP_GPIO_OUT_HI:
1368         return gpio_out_state >> 16;
1369
1370     case MP_GPIO_IN_LO:
1371         return gpio_in_state & 0xFFFF;
1372     case MP_GPIO_IN_HI:
1373         /* Update received I2C data */
1374         gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) |
1375                         (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT);
1376         return gpio_in_state >> 16;
1377
1378     case MP_GPIO_ISR_LO:
1379         return gpio_isr & 0xFFFF;
1380     case MP_GPIO_ISR_HI:
1381         return gpio_isr >> 16;
1382
1383     default:
1384         return 0;
1385     }
1386 }
1387
1388 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1389                                 uint32_t value)
1390 {
1391     switch (offset) {
1392     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1393         lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1394                          (value & MP_OE_LCD_BRIGHTNESS);
1395         break;
1396
1397     case MP_GPIO_OUT_LO:
1398         gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF);
1399         break;
1400     case MP_GPIO_OUT_HI:
1401         gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16);
1402         lcd_brightness = (lcd_brightness & 0xFFFF) |
1403                          (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS);
1404         i2c_state_update(mixer_i2c,
1405                          (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
1406                          (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1407         break;
1408
1409     }
1410 }
1411
1412 static CPUReadMemoryFunc *musicpal_gpio_readfn[] = {
1413     musicpal_gpio_read,
1414     musicpal_gpio_read,
1415     musicpal_gpio_read,
1416 };
1417
1418 static CPUWriteMemoryFunc *musicpal_gpio_writefn[] = {
1419     musicpal_gpio_write,
1420     musicpal_gpio_write,
1421     musicpal_gpio_write,
1422 };
1423
1424 static void musicpal_gpio_init(void)
1425 {
1426     int iomemtype;
1427
1428     iomemtype = cpu_register_io_memory(0, musicpal_gpio_readfn,
1429                                        musicpal_gpio_writefn, NULL);
1430     cpu_register_physical_memory(MP_GPIO_BASE, MP_GPIO_SIZE, iomemtype);
1431 }
1432
1433 /* Keyboard codes & masks */
1434 #define KEY_RELEASED            0x80
1435 #define KEY_CODE                0x7f
1436
1437 #define KEYCODE_TAB             0x0f
1438 #define KEYCODE_ENTER           0x1c
1439 #define KEYCODE_F               0x21
1440 #define KEYCODE_M               0x32
1441
1442 #define KEYCODE_EXTENDED        0xe0
1443 #define KEYCODE_UP              0x48
1444 #define KEYCODE_DOWN            0x50
1445 #define KEYCODE_LEFT            0x4b
1446 #define KEYCODE_RIGHT           0x4d
1447
1448 static void musicpal_key_event(void *opaque, int keycode)
1449 {
1450     qemu_irq irq = opaque;
1451     uint32_t event = 0;
1452     static int kbd_extended;
1453
1454     if (keycode == KEYCODE_EXTENDED) {
1455         kbd_extended = 1;
1456         return;
1457     }
1458
1459     if (kbd_extended)
1460         switch (keycode & KEY_CODE) {
1461         case KEYCODE_UP:
1462             event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV;
1463             break;
1464
1465         case KEYCODE_DOWN:
1466             event = MP_GPIO_WHEEL_NAV;
1467             break;
1468
1469         case KEYCODE_LEFT:
1470             event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV;
1471             break;
1472
1473         case KEYCODE_RIGHT:
1474             event = MP_GPIO_WHEEL_VOL;
1475             break;
1476         }
1477     else {
1478         switch (keycode & KEY_CODE) {
1479         case KEYCODE_F:
1480             event = MP_GPIO_BTN_FAVORITS;
1481             break;
1482
1483         case KEYCODE_TAB:
1484             event = MP_GPIO_BTN_VOLUME;
1485             break;
1486
1487         case KEYCODE_ENTER:
1488             event = MP_GPIO_BTN_NAVIGATION;
1489             break;
1490
1491         case KEYCODE_M:
1492             event = MP_GPIO_BTN_MENU;
1493             break;
1494         }
1495         /* Do not repeat already pressed buttons */
1496         if (!(keycode & KEY_RELEASED) && !(gpio_in_state & event))
1497             event = 0;
1498     }
1499
1500     if (event) {
1501         if (keycode & KEY_RELEASED) {
1502             gpio_in_state |= event;
1503         } else {
1504             gpio_in_state &= ~event;
1505             gpio_isr = event;
1506             qemu_irq_raise(irq);
1507         }
1508     }
1509
1510     kbd_extended = 0;
1511 }
1512
1513 static struct arm_boot_info musicpal_binfo = {
1514     .loader_start = 0x0,
1515     .board_id = 0x20e,
1516 };
1517
1518 static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
1519                const char *boot_device,
1520                const char *kernel_filename, const char *kernel_cmdline,
1521                const char *initrd_filename, const char *cpu_model)
1522 {
1523     CPUState *env;
1524     qemu_irq *pic;
1525     int index;
1526     unsigned long flash_size;
1527
1528     if (!cpu_model)
1529         cpu_model = "arm926";
1530
1531     env = cpu_init(cpu_model);
1532     if (!env) {
1533         fprintf(stderr, "Unable to find CPU definition\n");
1534         exit(1);
1535     }
1536     pic = arm_pic_init_cpu(env);
1537
1538     /* For now we use a fixed - the original - RAM size */
1539     cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1540                                  qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1541
1542     sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1543     cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1544
1545     pic = mv88w8618_pic_init(MP_PIC_BASE, pic[ARM_PIC_CPU_IRQ]);
1546     mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ);
1547
1548     if (serial_hds[0])
1549         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1550                    serial_hds[0], 1);
1551     if (serial_hds[1])
1552         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1553                    serial_hds[1], 1);
1554
1555     /* Register flash */
1556     index = drive_get_index(IF_PFLASH, 0, 0);
1557     if (index != -1) {
1558         flash_size = bdrv_getlength(drives_table[index].bdrv);
1559         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1560             flash_size != 32*1024*1024) {
1561             fprintf(stderr, "Invalid flash image size\n");
1562             exit(1);
1563         }
1564
1565         /*
1566          * The original U-Boot accesses the flash at 0xFE000000 instead of
1567          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1568          * image is smaller than 32 MB.
1569          */
1570         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1571                               drives_table[index].bdrv, 0x10000,
1572                               (flash_size + 0xffff) >> 16,
1573                               MP_FLASH_SIZE_MAX / flash_size,
1574                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1575                               0x5555, 0x2AAA);
1576     }
1577     mv88w8618_flashcfg_init(MP_FLASHCFG_BASE);
1578
1579     musicpal_lcd_init();
1580
1581     qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);
1582
1583     mv88w8618_eth_init(&nd_table[0], MP_ETH_BASE, pic[MP_ETH_IRQ]);
1584
1585     mixer_i2c = musicpal_audio_init(pic[MP_AUDIO_IRQ]);
1586
1587     mv88w8618_wlan_init(MP_WLAN_BASE);
1588
1589     musicpal_misc_init();
1590     musicpal_gpio_init();
1591
1592     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1593     musicpal_binfo.kernel_filename = kernel_filename;
1594     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1595     musicpal_binfo.initrd_filename = initrd_filename;
1596     arm_load_kernel(env, &musicpal_binfo);
1597 }
1598
1599 QEMUMachine musicpal_machine = {
1600     .name = "musicpal",
1601     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1602     .init = musicpal_init,
1603 };