hw/nand.c

   1 /*
   2  * Flash NAND memory emulation.  Based on "16M x 8 Bit NAND Flash
   3  * Memory" datasheet for the KM29U128AT / K9F2808U0A chips from
   4  * Samsung Electronic.
   5  *
   6  * Copyright (c) 2006 Openedhand Ltd.
   7  * Written by Andrzej Zaborowski <balrog@zabor.org>
   8  *
   9  * Support for additional features based on "MT29F2G16ABCWP 2Gx16"
  10  * datasheet from Micron Technology and "NAND02G-B2C" datasheet
  11  * from ST Microelectronics.
  12  *
  13  * This code is licensed under the GNU GPL v2.
  14  */
  15
  16 #ifndef NAND_IO
  17
  18 # include "hw.h"
  19 # include "flash.h"
  20 # include "blockdev.h"
  21
  22 # define NAND_CMD_READ0         0x00
  23 # define NAND_CMD_READ1         0x01
  24 # define NAND_CMD_READ2         0x50
  25 # define NAND_CMD_LPREAD2       0x30
  26 # define NAND_CMD_NOSERIALREAD2 0x35
  27 # define NAND_CMD_RANDOMREAD1   0x05
  28 # define NAND_CMD_RANDOMREAD2   0xe0
  29 # define NAND_CMD_READID        0x90
  30 # define NAND_CMD_RESET         0xff
  31 # define NAND_CMD_PAGEPROGRAM1  0x80
  32 # define NAND_CMD_PAGEPROGRAM2  0x10
  33 # define NAND_CMD_CACHEPROGRAM2 0x15
  34 # define NAND_CMD_BLOCKERASE1   0x60
  35 # define NAND_CMD_BLOCKERASE2   0xd0
  36 # define NAND_CMD_READSTATUS    0x70
  37 # define NAND_CMD_COPYBACKPRG1  0x85
  38
  39 # define NAND_IOSTATUS_ERROR    (1 << 0)
  40 # define NAND_IOSTATUS_PLANE0   (1 << 1)
  41 # define NAND_IOSTATUS_PLANE1   (1 << 2)
  42 # define NAND_IOSTATUS_PLANE2   (1 << 3)
  43 # define NAND_IOSTATUS_PLANE3   (1 << 4)
  44 # define NAND_IOSTATUS_BUSY     (1 << 6)
  45 # define NAND_IOSTATUS_UNPROTCT (1 << 7)
  46
  47 # define MAX_PAGE               0x800
  48 # define MAX_OOB                0x40
  49
  50 struct NANDFlashState {
  51     uint8_t manf_id, chip_id;
  52     uint8_t buswidth; /* in BYTES */
  53     int size, pages;
  54     int page_shift, oob_shift, erase_shift, addr_shift;
  55     uint8_t *storage;
  56     BlockDriverState *bdrv;
  57     int mem_oob;
  58
  59     uint8_t cle, ale, ce, wp, gnd;
  60
  61     uint8_t io[MAX_PAGE + MAX_OOB + 0x400];
  62     uint8_t *ioaddr;
  63     int iolen;
  64
  65     uint32_t cmd;
  66     uint64_t addr;
  67     int addrlen;
  68     int status;
  69     int offset;
  70
  71     void (*blk_write)(NANDFlashState *s);
  72     void (*blk_erase)(NANDFlashState *s);
  73     void (*blk_load)(NANDFlashState *s, uint64_t addr, int offset);
  74
  75     uint32_t ioaddr_vmstate;
  76 };
  77
  78 static void mem_and(uint8_t *dest, const uint8_t *src, size_t n)
  79 {
  80     /* Like memcpy() but we logical-AND the data into the destination */
  81     int i;
  82     for (i = 0; i < n; i++) {
  83         dest[i] &= src[i];
  84     }
  85 }
  86
  87 # define NAND_NO_AUTOINCR       0x00000001
  88 # define NAND_BUSWIDTH_16       0x00000002
  89 # define NAND_NO_PADDING        0x00000004
  90 # define NAND_CACHEPRG          0x00000008
  91 # define NAND_COPYBACK          0x00000010
  92 # define NAND_IS_AND            0x00000020
  93 # define NAND_4PAGE_ARRAY       0x00000040
  94 # define NAND_NO_READRDY        0x00000100
  95 # define NAND_SAMSUNG_LP        (NAND_NO_PADDING | NAND_COPYBACK)
  96
  97 # define NAND_IO
  98
  99 # define PAGE(addr)             ((addr) >> ADDR_SHIFT)
 100 # define PAGE_START(page)       (PAGE(page) * (PAGE_SIZE + OOB_SIZE))
 101 # define PAGE_MASK              ((1 << ADDR_SHIFT) - 1)
 102 # define OOB_SHIFT              (PAGE_SHIFT - 5)
 103 # define OOB_SIZE               (1 << OOB_SHIFT)
 104 # define SECTOR(addr)           ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT))
 105 # define SECTOR_OFFSET(addr)    ((addr) & ((511 >> PAGE_SHIFT) << 8))
 106
 107 # define PAGE_SIZE              256
 108 # define PAGE_SHIFT             8
 109 # define PAGE_SECTORS           1
 110 # define ADDR_SHIFT             8
 111 # include "nand.c"
 112 # define PAGE_SIZE              512
 113 # define PAGE_SHIFT             9
 114 # define PAGE_SECTORS           1
 115 # define ADDR_SHIFT             8
 116 # include "nand.c"
 117 # define PAGE_SIZE              2048
 118 # define PAGE_SHIFT             11
 119 # define PAGE_SECTORS           4
 120 # define ADDR_SHIFT             16
 121 # include "nand.c"
 122
 123 /* Information based on Linux drivers/mtd/nand/nand_ids.c */
 124 static const struct {
 125     int size;
 126     int width;
 127     int page_shift;
 128     int erase_shift;
 129     uint32_t options;
 130 } nand_flash_ids[0x100] = {
 131     [0 ... 0xff] = { 0 },
 132
 133     [0x6e] = { 1,       8,      8, 4, 0 },
 134     [0x64] = { 2,       8,      8, 4, 0 },
 135     [0x6b] = { 4,       8,      9, 4, 0 },
 136     [0xe8] = { 1,       8,      8, 4, 0 },
 137     [0xec] = { 1,       8,      8, 4, 0 },
 138     [0xea] = { 2,       8,      8, 4, 0 },
 139     [0xd5] = { 4,       8,      9, 4, 0 },
 140     [0xe3] = { 4,       8,      9, 4, 0 },
 141     [0xe5] = { 4,       8,      9, 4, 0 },
 142     [0xd6] = { 8,       8,      9, 4, 0 },
 143
 144     [0x39] = { 8,       8,      9, 4, 0 },
 145     [0xe6] = { 8,       8,      9, 4, 0 },
 146     [0x49] = { 8,       16,     9, 4, NAND_BUSWIDTH_16 },
 147     [0x59] = { 8,       16,     9, 4, NAND_BUSWIDTH_16 },
 148
 149     [0x33] = { 16,      8,      9, 5, 0 },
 150     [0x73] = { 16,      8,      9, 5, 0 },
 151     [0x43] = { 16,      16,     9, 5, NAND_BUSWIDTH_16 },
 152     [0x53] = { 16,      16,     9, 5, NAND_BUSWIDTH_16 },
 153
 154     [0x35] = { 32,      8,      9, 5, 0 },
 155     [0x75] = { 32,      8,      9, 5, 0 },
 156     [0x45] = { 32,      16,     9, 5, NAND_BUSWIDTH_16 },
 157     [0x55] = { 32,      16,     9, 5, NAND_BUSWIDTH_16 },
 158
 159     [0x36] = { 64,      8,      9, 5, 0 },
 160     [0x76] = { 64,      8,      9, 5, 0 },
 161     [0x46] = { 64,      16,     9, 5, NAND_BUSWIDTH_16 },
 162     [0x56] = { 64,      16,     9, 5, NAND_BUSWIDTH_16 },
 163
 164     [0x78] = { 128,     8,      9, 5, 0 },
 165     [0x39] = { 128,     8,      9, 5, 0 },
 166     [0x79] = { 128,     8,      9, 5, 0 },
 167     [0x72] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 168     [0x49] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 169     [0x74] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 170     [0x59] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 171
 172     [0x71] = { 256,     8,      9, 5, 0 },
 173
 174     /*
 175      * These are the new chips with large page size. The pagesize and the
 176      * erasesize is determined from the extended id bytes
 177      */
 178 # define LP_OPTIONS     (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR)
 179 # define LP_OPTIONS16   (LP_OPTIONS | NAND_BUSWIDTH_16)
 180
 181     /* 512 Megabit */
 182     [0xa2] = { 64,      8,      0, 0, LP_OPTIONS },
 183     [0xf2] = { 64,      8,      0, 0, LP_OPTIONS },
 184     [0xb2] = { 64,      16,     0, 0, LP_OPTIONS16 },
 185     [0xc2] = { 64,      16,     0, 0, LP_OPTIONS16 },
 186
 187     /* 1 Gigabit */
 188     [0xa1] = { 128,     8,      0, 0, LP_OPTIONS },
 189     [0xf1] = { 128,     8,      0, 0, LP_OPTIONS },
 190     [0xb1] = { 128,     16,     0, 0, LP_OPTIONS16 },
 191     [0xc1] = { 128,     16,     0, 0, LP_OPTIONS16 },
 192
 193     /* 2 Gigabit */
 194     [0xaa] = { 256,     8,      0, 0, LP_OPTIONS },
 195     [0xda] = { 256,     8,      0, 0, LP_OPTIONS },
 196     [0xba] = { 256,     16,     0, 0, LP_OPTIONS16 },
 197     [0xca] = { 256,     16,     0, 0, LP_OPTIONS16 },
 198
 199     /* 4 Gigabit */
 200     [0xac] = { 512,     8,      0, 0, LP_OPTIONS },
 201     [0xdc] = { 512,     8,      0, 0, LP_OPTIONS },
 202     [0xbc] = { 512,     16,     0, 0, LP_OPTIONS16 },
 203     [0xcc] = { 512,     16,     0, 0, LP_OPTIONS16 },
 204
 205     /* 8 Gigabit */
 206     [0xa3] = { 1024,    8,      0, 0, LP_OPTIONS },
 207     [0xd3] = { 1024,    8,      0, 0, LP_OPTIONS },
 208     [0xb3] = { 1024,    16,     0, 0, LP_OPTIONS16 },
 209     [0xc3] = { 1024,    16,     0, 0, LP_OPTIONS16 },
 210
 211     /* 16 Gigabit */
 212     [0xa5] = { 2048,    8,      0, 0, LP_OPTIONS },
 213     [0xd5] = { 2048,    8,      0, 0, LP_OPTIONS },
 214     [0xb5] = { 2048,    16,     0, 0, LP_OPTIONS16 },
 215     [0xc5] = { 2048,    16,     0, 0, LP_OPTIONS16 },
 216 };
 217
 218 static void nand_reset(NANDFlashState *s)
 219 {
 220     s->cmd = NAND_CMD_READ0;
 221     s->addr = 0;
 222     s->addrlen = 0;
 223     s->iolen = 0;
 224     s->offset = 0;
 225     s->status &= NAND_IOSTATUS_UNPROTCT;
 226 }
 227
 228 static inline void nand_pushio_byte(NANDFlashState *s, uint8_t value)
 229 {
 230     s->ioaddr[s->iolen++] = value;
 231     for (value = s->buswidth; --value;) {
 232         s->ioaddr[s->iolen++] = 0;
 233     }
 234 }
 235
 236 static void nand_command(NANDFlashState *s)
 237 {
 238     unsigned int offset;
 239     switch (s->cmd) {
 240     case NAND_CMD_READ0:
 241         s->iolen = 0;
 242         break;
 243
 244     case NAND_CMD_READID:
 245         s->ioaddr = s->io;
 246         s->iolen = 0;
 247         nand_pushio_byte(s, s->manf_id);
 248         nand_pushio_byte(s, s->chip_id);
 249         nand_pushio_byte(s, 'Q'); /* Don't-care byte (often 0xa5) */
 250         if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
 251             /* Page Size, Block Size, Spare Size; bit 6 indicates
 252              * 8 vs 16 bit width NAND.
 253              */
 254             nand_pushio_byte(s, (s->buswidth == 2) ? 0x55 : 0x15);
 255         } else {
 256             nand_pushio_byte(s, 0xc0); /* Multi-plane */
 257         }
 258         break;
 259
 260     case NAND_CMD_RANDOMREAD2:
 261     case NAND_CMD_NOSERIALREAD2:
 262         if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP))
 263             break;
 264         offset = s->addr & ((1 << s->addr_shift) - 1);
 265         s->blk_load(s, s->addr, offset);
 266         if (s->gnd)
 267             s->iolen = (1 << s->page_shift) - offset;
 268         else
 269             s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
 270         break;
 271
 272     case NAND_CMD_RESET:
 273         nand_reset(s);
 274         break;
 275
 276     case NAND_CMD_PAGEPROGRAM1:
 277         s->ioaddr = s->io;
 278         s->iolen = 0;
 279         break;
 280
 281     case NAND_CMD_PAGEPROGRAM2:
 282         if (s->wp) {
 283             s->blk_write(s);
 284         }
 285         break;
 286
 287     case NAND_CMD_BLOCKERASE1:
 288         break;
 289
 290     case NAND_CMD_BLOCKERASE2:
 291         if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP)
 292             s->addr <<= 16;
 293         else
 294             s->addr <<= 8;
 295
 296         if (s->wp) {
 297             s->blk_erase(s);
 298         }
 299         break;
 300
 301     case NAND_CMD_READSTATUS:
 302         s->ioaddr = s->io;
 303         s->iolen = 0;
 304         nand_pushio_byte(s, s->status);
 305         break;
 306
 307     default:
 308         printf("%s: Unknown NAND command 0x%02x\n", __FUNCTION__, s->cmd);
 309     }
 310 }
 311
 312 static void nand_pre_save(void *opaque)
 313 {
 314     NANDFlashState *s = opaque;
 315
 316     s->ioaddr_vmstate = s->ioaddr - s->io;
 317 }
 318
 319 static int nand_post_load(void *opaque, int version_id)
 320 {
 321     NANDFlashState *s = opaque;
 322
 323     if (s->ioaddr_vmstate > sizeof(s->io)) {
 324         return -EINVAL;
 325     }
 326     s->ioaddr = s->io + s->ioaddr_vmstate;
 327
 328     return 0;
 329 }
 330
 331 static const VMStateDescription vmstate_nand = {
 332     .name = "nand",
 333     .version_id = 1,
 334     .minimum_version_id = 1,
 335     .minimum_version_id_old = 1,
 336     .pre_save = nand_pre_save,
 337     .post_load = nand_post_load,
 338     .fields      = (VMStateField[]) {
 339         VMSTATE_UINT8(cle, NANDFlashState),
 340         VMSTATE_UINT8(ale, NANDFlashState),
 341         VMSTATE_UINT8(ce, NANDFlashState),
 342         VMSTATE_UINT8(wp, NANDFlashState),
 343         VMSTATE_UINT8(gnd, NANDFlashState),
 344         VMSTATE_BUFFER(io, NANDFlashState),
 345         VMSTATE_UINT32(ioaddr_vmstate, NANDFlashState),
 346         VMSTATE_INT32(iolen, NANDFlashState),
 347         VMSTATE_UINT32(cmd, NANDFlashState),
 348         VMSTATE_UINT64(addr, NANDFlashState),
 349         VMSTATE_INT32(addrlen, NANDFlashState),
 350         VMSTATE_INT32(status, NANDFlashState),
 351         VMSTATE_INT32(offset, NANDFlashState),
 352         /* XXX: do we want to save s->storage too? */
 353         VMSTATE_END_OF_LIST()
 354     }
 355 };
 356
 357 /*
 358  * Chip inputs are CLE, ALE, CE, WP, GND and eight I/O pins.  Chip
 359  * outputs are R/B and eight I/O pins.
 360  *
 361  * CE, WP and R/B are active low.
 362  */
 363 void nand_setpins(NANDFlashState *s, uint8_t cle, uint8_t ale,
 364                   uint8_t ce, uint8_t wp, uint8_t gnd)
 365 {
 366     s->cle = cle;
 367     s->ale = ale;
 368     s->ce = ce;
 369     s->wp = wp;
 370     s->gnd = gnd;
 371     if (wp)
 372         s->status |= NAND_IOSTATUS_UNPROTCT;
 373     else
 374         s->status &= ~NAND_IOSTATUS_UNPROTCT;
 375 }
 376
 377 void nand_getpins(NANDFlashState *s, int *rb)
 378 {
 379     *rb = 1;
 380 }
 381
 382 void nand_setio(NANDFlashState *s, uint32_t value)
 383 {
 384     int i;
 385
 386     if (!s->ce && s->cle) {
 387         if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
 388             if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2)
 389                 return;
 390             if (value == NAND_CMD_RANDOMREAD1) {
 391                 s->addr &= ~((1 << s->addr_shift) - 1);
 392                 s->addrlen = 0;
 393                 return;
 394             }
 395         }
 396         if (value == NAND_CMD_READ0)
 397             s->offset = 0;
 398         else if (value == NAND_CMD_READ1) {
 399             s->offset = 0x100;
 400             value = NAND_CMD_READ0;
 401         }
 402         else if (value == NAND_CMD_READ2) {
 403             s->offset = 1 << s->page_shift;
 404             value = NAND_CMD_READ0;
 405         }
 406
 407         s->cmd = value;
 408
 409         if (s->cmd == NAND_CMD_READSTATUS ||
 410                 s->cmd == NAND_CMD_PAGEPROGRAM2 ||
 411                 s->cmd == NAND_CMD_BLOCKERASE1 ||
 412                 s->cmd == NAND_CMD_BLOCKERASE2 ||
 413                 s->cmd == NAND_CMD_NOSERIALREAD2 ||
 414                 s->cmd == NAND_CMD_RANDOMREAD2 ||
 415                 s->cmd == NAND_CMD_RESET)
 416             nand_command(s);
 417
 418         if (s->cmd != NAND_CMD_RANDOMREAD2) {
 419             s->addrlen = 0;
 420         }
 421     }
 422
 423     if (s->ale) {
 424         unsigned int shift = s->addrlen * 8;
 425         unsigned int mask = ~(0xff << shift);
 426         unsigned int v = value << shift;
 427
 428         s->addr = (s->addr & mask) | v;
 429         s->addrlen ++;
 430
 431         switch (s->addrlen) {
 432         case 1:
 433             if (s->cmd == NAND_CMD_READID) {
 434                 nand_command(s);
 435             }
 436             break;
 437         case 2: /* fix cache address as a byte address */
 438             s->addr <<= (s->buswidth - 1);
 439             break;
 440         case 3:
 441             if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
 442                     (s->cmd == NAND_CMD_READ0 ||
 443                      s->cmd == NAND_CMD_PAGEPROGRAM1)) {
 444                 nand_command(s);
 445             }
 446             break;
 447         case 4:
 448             if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
 449                     nand_flash_ids[s->chip_id].size < 256 && /* 1Gb or less */
 450                     (s->cmd == NAND_CMD_READ0 ||
 451                      s->cmd == NAND_CMD_PAGEPROGRAM1)) {
 452                 nand_command(s);
 453             }
 454             break;
 455         case 5:
 456             if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
 457                     nand_flash_ids[s->chip_id].size >= 256 && /* 2Gb or more */
 458                     (s->cmd == NAND_CMD_READ0 ||
 459                      s->cmd == NAND_CMD_PAGEPROGRAM1)) {
 460                 nand_command(s);
 461             }
 462             break;
 463         default:
 464             break;
 465         }
 466     }
 467
 468     if (!s->cle && !s->ale && s->cmd == NAND_CMD_PAGEPROGRAM1) {
 469         if (s->iolen < (1 << s->page_shift) + (1 << s->oob_shift)) {
 470             for (i = s->buswidth; i--; value >>= 8) {
 471                 s->io[s->iolen ++] = (uint8_t) (value & 0xff);
 472             }
 473         }
 474     } else if (!s->cle && !s->ale && s->cmd == NAND_CMD_COPYBACKPRG1) {
 475         if ((s->addr & ((1 << s->addr_shift) - 1)) <
 476                 (1 << s->page_shift) + (1 << s->oob_shift)) {
 477             for (i = s->buswidth; i--; s->addr++, value >>= 8) {
 478                 s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] =
 479                     (uint8_t) (value & 0xff);
 480             }
 481         }
 482     }
 483 }
 484
 485 uint32_t nand_getio(NANDFlashState *s)
 486 {
 487     int offset;
 488     uint32_t x = 0;
 489
 490     /* Allow sequential reading */
 491     if (!s->iolen && s->cmd == NAND_CMD_READ0) {
 492         offset = (int) (s->addr & ((1 << s->addr_shift) - 1)) + s->offset;
 493         s->offset = 0;
 494
 495         s->blk_load(s, s->addr, offset);
 496         if (s->gnd)
 497             s->iolen = (1 << s->page_shift) - offset;
 498         else
 499             s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
 500     }
 501
 502     if (s->ce || s->iolen <= 0)
 503         return 0;
 504
 505     for (offset = s->buswidth; offset--;) {
 506         x |= s->ioaddr[offset] << (offset << 3);
 507     }
 508     /* after receiving READ STATUS command all subsequent reads will
 509      * return the status register value until another command is issued
 510      */
 511     if (s->cmd != NAND_CMD_READSTATUS) {
 512         s->addr   += s->buswidth;
 513         s->ioaddr += s->buswidth;
 514         s->iolen  -= s->buswidth;
 515     }
 516     return x;
 517 }
 518
 519 uint32_t nand_getbuswidth(NANDFlashState *s)
 520 {
 521     return s->buswidth << 3;
 522 }
 523
 524 NANDFlashState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id)
 525 {
 526     int pagesize;
 527     NANDFlashState *s;
 528
 529     if (nand_flash_ids[chip_id].size == 0) {
 530         hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
 531     }
 532
 533     s = (NANDFlashState *) qemu_mallocz(sizeof(NANDFlashState));
 534     s->bdrv = bdrv;
 535     s->manf_id = manf_id;
 536     s->chip_id = chip_id;
 537     s->buswidth = nand_flash_ids[s->chip_id].width >> 3;
 538     s->size = nand_flash_ids[s->chip_id].size << 20;
 539     if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
 540         s->page_shift = 11;
 541         s->erase_shift = 6;
 542     } else {
 543         s->page_shift = nand_flash_ids[s->chip_id].page_shift;
 544         s->erase_shift = nand_flash_ids[s->chip_id].erase_shift;
 545     }
 546
 547     switch (1 << s->page_shift) {
 548     case 256:
 549         nand_init_256(s);
 550         break;
 551     case 512:
 552         nand_init_512(s);
 553         break;
 554     case 2048:
 555         nand_init_2048(s);
 556         break;
 557     default:
 558         hw_error("%s: Unsupported NAND block size.\n", __FUNCTION__);
 559     }
 560
 561     pagesize = 1 << s->oob_shift;
 562     s->mem_oob = 1;
 563     if (s->bdrv && bdrv_getlength(s->bdrv) >=
 564                     (s->pages << s->page_shift) + (s->pages << s->oob_shift)) {
 565         pagesize = 0;
 566         s->mem_oob = 0;
 567     }
 568
 569     if (!s->bdrv)
 570         pagesize += 1 << s->page_shift;
 571     if (pagesize)
 572         s->storage = (uint8_t *) memset(qemu_malloc(s->pages * pagesize),
 573                         0xff, s->pages * pagesize);
 574     /* Give s->ioaddr a sane value in case we save state before it
 575        is used.  */
 576     s->ioaddr = s->io;
 577
 578     vmstate_register(NULL, -1, &vmstate_nand, s);
 579
 580     return s;
 581 }
 582
 583 void nand_done(NANDFlashState *s)
 584 {
 585     if (s->bdrv) {
 586         bdrv_close(s->bdrv);
 587         bdrv_delete(s->bdrv);
 588     }
 589
 590     if (!s->bdrv || s->mem_oob)
 591         qemu_free(s->storage);
 592
 593     qemu_free(s);
 594 }
 595
 596 #else
 597
 598 /* Program a single page */
 599 static void glue(nand_blk_write_, PAGE_SIZE)(NANDFlashState *s)
 600 {
 601     uint64_t off, page, sector, soff;
 602     uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200];
 603     if (PAGE(s->addr) >= s->pages)
 604         return;
 605
 606     if (!s->bdrv) {
 607         mem_and(s->storage + PAGE_START(s->addr) + (s->addr & PAGE_MASK) +
 608                         s->offset, s->io, s->iolen);
 609     } else if (s->mem_oob) {
 610         sector = SECTOR(s->addr);
 611         off = (s->addr & PAGE_MASK) + s->offset;
 612         soff = SECTOR_OFFSET(s->addr);
 613         if (bdrv_read(s->bdrv, sector, iobuf, PAGE_SECTORS) == -1) {
 614             printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
 615             return;
 616         }
 617
 618         mem_and(iobuf + (soff | off), s->io, MIN(s->iolen, PAGE_SIZE - off));
 619         if (off + s->iolen > PAGE_SIZE) {
 620             page = PAGE(s->addr);
 621             mem_and(s->storage + (page << OOB_SHIFT), s->io + PAGE_SIZE - off,
 622                             MIN(OOB_SIZE, off + s->iolen - PAGE_SIZE));
 623         }
 624
 625         if (bdrv_write(s->bdrv, sector, iobuf, PAGE_SECTORS) == -1)
 626             printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
 627     } else {
 628         off = PAGE_START(s->addr) + (s->addr & PAGE_MASK) + s->offset;
 629         sector = off >> 9;
 630         soff = off & 0x1ff;
 631         if (bdrv_read(s->bdrv, sector, iobuf, PAGE_SECTORS + 2) == -1) {
 632             printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
 633             return;
 634         }
 635
 636         mem_and(iobuf + soff, s->io, s->iolen);
 637
 638         if (bdrv_write(s->bdrv, sector, iobuf, PAGE_SECTORS + 2) == -1)
 639             printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
 640     }
 641     s->offset = 0;
 642 }
 643
 644 /* Erase a single block */
 645 static void glue(nand_blk_erase_, PAGE_SIZE)(NANDFlashState *s)
 646 {
 647     uint64_t i, page, addr;
 648     uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, };
 649     addr = s->addr & ~((1 << (ADDR_SHIFT + s->erase_shift)) - 1);
 650
 651     if (PAGE(addr) >= s->pages)
 652         return;
 653
 654     if (!s->bdrv) {
 655         memset(s->storage + PAGE_START(addr),
 656                         0xff, (PAGE_SIZE + OOB_SIZE) << s->erase_shift);
 657     } else if (s->mem_oob) {
 658         memset(s->storage + (PAGE(addr) << OOB_SHIFT),
 659                         0xff, OOB_SIZE << s->erase_shift);
 660         i = SECTOR(addr);
 661         page = SECTOR(addr + (ADDR_SHIFT + s->erase_shift));
 662         for (; i < page; i ++)
 663             if (bdrv_write(s->bdrv, i, iobuf, 1) == -1)
 664                 printf("%s: write error in sector %" PRIu64 "\n", __func__, i);
 665     } else {
 666         addr = PAGE_START(addr);
 667         page = addr >> 9;
 668         if (bdrv_read(s->bdrv, page, iobuf, 1) == -1)
 669             printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
 670         memset(iobuf + (addr & 0x1ff), 0xff, (~addr & 0x1ff) + 1);
 671         if (bdrv_write(s->bdrv, page, iobuf, 1) == -1)
 672             printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
 673
 674         memset(iobuf, 0xff, 0x200);
 675         i = (addr & ~0x1ff) + 0x200;
 676         for (addr += ((PAGE_SIZE + OOB_SIZE) << s->erase_shift) - 0x200;
 677                         i < addr; i += 0x200)
 678             if (bdrv_write(s->bdrv, i >> 9, iobuf, 1) == -1)
 679                 printf("%s: write error in sector %" PRIu64 "\n",
 680                        __func__, i >> 9);
 681
 682         page = i >> 9;
 683         if (bdrv_read(s->bdrv, page, iobuf, 1) == -1)
 684             printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
 685         memset(iobuf, 0xff, ((addr - 1) & 0x1ff) + 1);
 686         if (bdrv_write(s->bdrv, page, iobuf, 1) == -1)
 687             printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
 688     }
 689 }
 690
 691 static void glue(nand_blk_load_, PAGE_SIZE)(NANDFlashState *s,
 692                 uint64_t addr, int offset)
 693 {
 694     if (PAGE(addr) >= s->pages)
 695         return;
 696
 697     if (s->bdrv) {
 698         if (s->mem_oob) {
 699             if (bdrv_read(s->bdrv, SECTOR(addr), s->io, PAGE_SECTORS) == -1)
 700                 printf("%s: read error in sector %" PRIu64 "\n",
 701                                 __func__, SECTOR(addr));
 702             memcpy(s->io + SECTOR_OFFSET(s->addr) + PAGE_SIZE,
 703                             s->storage + (PAGE(s->addr) << OOB_SHIFT),
 704                             OOB_SIZE);
 705             s->ioaddr = s->io + SECTOR_OFFSET(s->addr) + offset;
 706         } else {
 707             if (bdrv_read(s->bdrv, PAGE_START(addr) >> 9,
 708                                     s->io, (PAGE_SECTORS + 2)) == -1)
 709                 printf("%s: read error in sector %" PRIu64 "\n",
 710                                 __func__, PAGE_START(addr) >> 9);
 711             s->ioaddr = s->io + (PAGE_START(addr) & 0x1ff) + offset;
 712         }
 713     } else {
 714         memcpy(s->io, s->storage + PAGE_START(s->addr) +
 715                         offset, PAGE_SIZE + OOB_SIZE - offset);
 716         s->ioaddr = s->io;
 717     }
 718 }
 719
 720 static void glue(nand_init_, PAGE_SIZE)(NANDFlashState *s)
 721 {
 722     s->oob_shift = PAGE_SHIFT - 5;
 723     s->pages = s->size >> PAGE_SHIFT;
 724     s->addr_shift = ADDR_SHIFT;
 725
 726     s->blk_erase = glue(nand_blk_erase_, PAGE_SIZE);
 727     s->blk_write = glue(nand_blk_write_, PAGE_SIZE);
 728     s->blk_load = glue(nand_blk_load_, PAGE_SIZE);
 729 }
 730
 731 # undef PAGE_SIZE
 732 # undef PAGE_SHIFT
 733 # undef PAGE_SECTORS
 734 # undef ADDR_SHIFT
 735 #endif  /* NAND_IO */