hw/ne2000.c

   1 /*
   2  * QEMU NE2000 emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* debug NE2000 card */
  27 //#define DEBUG_NE2000
  28
  29 #define MAX_ETH_FRAME_SIZE 1514
  30
  31 #define E8390_CMD       0x00  /* The command register (for all pages) */
  32 /* Page 0 register offsets. */
  33 #define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
  34 #define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
  35 #define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
  36 #define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
  37 #define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
  38 #define EN0_TSR         0x04    /* Transmit status reg RD */
  39 #define EN0_TPSR        0x04    /* Transmit starting page WR */
  40 #define EN0_NCR         0x05    /* Number of collision reg RD */
  41 #define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
  42 #define EN0_FIFO        0x06    /* FIFO RD */
  43 #define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
  44 #define EN0_ISR         0x07    /* Interrupt status reg RD WR */
  45 #define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
  46 #define EN0_RSARLO      0x08    /* Remote start address reg 0 */
  47 #define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
  48 #define EN0_RSARHI      0x09    /* Remote start address reg 1 */
  49 #define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
  50 #define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
  51 #define EN0_RSR         0x0c    /* rx status reg RD */
  52 #define EN0_RXCR        0x0c    /* RX configuration reg WR */
  53 #define EN0_TXCR        0x0d    /* TX configuration reg WR */
  54 #define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
  55 #define EN0_DCFG        0x0e    /* Data configuration reg WR */
  56 #define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
  57 #define EN0_IMR         0x0f    /* Interrupt mask reg WR */
  58 #define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
  59
  60 #define EN1_PHYS        0x11
  61 #define EN1_CURPAG      0x17
  62 #define EN1_MULT        0x18
  63
  64 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  65 #define E8390_STOP      0x01    /* Stop and reset the chip */
  66 #define E8390_START     0x02    /* Start the chip, clear reset */
  67 #define E8390_TRANS     0x04    /* Transmit a frame */
  68 #define E8390_RREAD     0x08    /* Remote read */
  69 #define E8390_RWRITE    0x10    /* Remote write  */
  70 #define E8390_NODMA     0x20    /* Remote DMA */
  71 #define E8390_PAGE0     0x00    /* Select page chip registers */
  72 #define E8390_PAGE1     0x40    /* using the two high-order bits */
  73 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
  74
  75 /* Bits in EN0_ISR - Interrupt status register */
  76 #define ENISR_RX        0x01    /* Receiver, no error */
  77 #define ENISR_TX        0x02    /* Transmitter, no error */
  78 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
  79 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
  80 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
  81 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
  82 #define ENISR_RDC       0x40    /* remote dma complete */
  83 #define ENISR_RESET     0x80    /* Reset completed */
  84 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
  85
  86 /* Bits in received packet status byte and EN0_RSR*/
  87 #define ENRSR_RXOK      0x01    /* Received a good packet */
  88 #define ENRSR_CRC       0x02    /* CRC error */
  89 #define ENRSR_FAE       0x04    /* frame alignment error */
  90 #define ENRSR_FO        0x08    /* FIFO overrun */
  91 #define ENRSR_MPA       0x10    /* missed pkt */
  92 #define ENRSR_PHY       0x20    /* physical/multicast address */
  93 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
  94 #define ENRSR_DEF       0x80    /* deferring */
  95
  96 /* Transmitted packet status, EN0_TSR. */
  97 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
  98 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
  99 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 100 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 101 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 102 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 103 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 104 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 105
 106 #define NE2000_PMEM_SIZE    (32*1024)
 107 #define NE2000_PMEM_START   (16*1024)
 108 #define NE2000_PMEM_END     (NE2000_PMEM_SIZE+NE2000_PMEM_START)
 109 #define NE2000_MEM_SIZE     NE2000_PMEM_END
 110
 111 typedef struct NE2000State {
 112     uint8_t cmd;
 113     uint32_t start;
 114     uint32_t stop;
 115     uint8_t boundary;
 116     uint8_t tsr;
 117     uint8_t tpsr;
 118     uint16_t tcnt;
 119     uint16_t rcnt;
 120     uint32_t rsar;
 121     uint8_t rsr;
 122     uint8_t isr;
 123     uint8_t dcfg;
 124     uint8_t imr;
 125     uint8_t phys[6]; /* mac address */
 126     uint8_t curpag;
 127     uint8_t mult[8]; /* multicast mask array */
 128     int irq;
 129     PCIDevice *pci_dev;
 130     NetDriverState *nd;
 131     uint8_t mem[NE2000_MEM_SIZE];
 132 } NE2000State;
 133
 134 static void ne2000_reset(NE2000State *s)
 135 {
 136     int i;
 137
 138     s->isr = ENISR_RESET;
 139     memcpy(s->mem, s->nd->macaddr, 6);
 140     s->mem[14] = 0x57;
 141     s->mem[15] = 0x57;
 142
 143     /* duplicate prom data */
 144     for(i = 15;i >= 0; i--) {
 145         s->mem[2 * i] = s->mem[i];
 146         s->mem[2 * i + 1] = s->mem[i];
 147     }
 148 }
 149
 150 static void ne2000_update_irq(NE2000State *s)
 151 {
 152     int isr;
 153     isr = s->isr & s->imr;
 154 #if defined(DEBUG_NE2000)
 155     printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
 156            s->irq, isr ? 1 : 0, s->isr, s->imr);
 157 #endif
 158     if (s->irq == 16) {
 159         /* PCI irq */
 160         pci_set_irq(s->pci_dev, 0, (isr != 0));
 161     } else {
 162         /* ISA irq */
 163         pic_set_irq(s->irq, (isr != 0));
 164     }
 165 }
 166
 167 /* return the max buffer size if the NE2000 can receive more data */
 168 static int ne2000_can_receive(void *opaque)
 169 {
 170     NE2000State *s = opaque;
 171     int avail, index, boundary;
 172
 173     if (s->cmd & E8390_STOP)
 174         return 0;
 175     index = s->curpag << 8;
 176     boundary = s->boundary << 8;
 177     if (index < boundary)
 178         avail = boundary - index;
 179     else
 180         avail = (s->stop - s->start) - (index - boundary);
 181     if (avail < (MAX_ETH_FRAME_SIZE + 4))
 182         return 0;
 183     return MAX_ETH_FRAME_SIZE;
 184 }
 185
 186 #define MIN_BUF_SIZE 60
 187
 188 static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
 189 {
 190     NE2000State *s = opaque;
 191     uint8_t *p;
 192     int total_len, next, avail, len, index;
 193     uint8_t buf1[60];
 194
 195 #if defined(DEBUG_NE2000)
 196     printf("NE2000: received len=%d\n", size);
 197 #endif
 198
 199     /* if too small buffer, then expand it */
 200     if (size < MIN_BUF_SIZE) {
 201         memcpy(buf1, buf, size);
 202         memset(buf1 + size, 0, MIN_BUF_SIZE - size);
 203         buf = buf1;
 204         size = MIN_BUF_SIZE;
 205     }
 206
 207     index = s->curpag << 8;
 208     /* 4 bytes for header */
 209     total_len = size + 4;
 210     /* address for next packet (4 bytes for CRC) */
 211     next = index + ((total_len + 4 + 255) & ~0xff);
 212     if (next >= s->stop)
 213         next -= (s->stop - s->start);
 214     /* prepare packet header */
 215     p = s->mem + index;
 216     s->rsr = ENRSR_RXOK; /* receive status */
 217     /* XXX: check this */
 218     if (buf[0] & 0x01)
 219         s->rsr |= ENRSR_PHY;
 220     p[0] = s->rsr;
 221     p[1] = next >> 8;
 222     p[2] = total_len;
 223     p[3] = total_len >> 8;
 224     index += 4;
 225
 226     /* write packet data */
 227     while (size > 0) {
 228         avail = s->stop - index;
 229         len = size;
 230         if (len > avail)
 231             len = avail;
 232         memcpy(s->mem + index, buf, len);
 233         buf += len;
 234         index += len;
 235         if (index == s->stop)
 236             index = s->start;
 237         size -= len;
 238     }
 239     s->curpag = next >> 8;
 240
 241     /* now we can signal we have receive something */
 242     s->isr |= ENISR_RX;
 243     ne2000_update_irq(s);
 244 }
 245
 246 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 247 {
 248     NE2000State *s = opaque;
 249     int offset, page;
 250
 251     addr &= 0xf;
 252 #ifdef DEBUG_NE2000
 253     printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
 254 #endif
 255     if (addr == E8390_CMD) {
 256         /* control register */
 257         s->cmd = val;
 258         if (val & E8390_START) {
 259             s->isr &= ~ENISR_RESET;
 260             /* test specific case: zero length transfert */
 261             if ((val & (E8390_RREAD | E8390_RWRITE)) &&
 262                 s->rcnt == 0) {
 263                 s->isr |= ENISR_RDC;
 264                 ne2000_update_irq(s);
 265             }
 266             if (val & E8390_TRANS) {
 267                 qemu_send_packet(s->nd, s->mem + (s->tpsr << 8), s->tcnt);
 268                 /* signal end of transfert */
 269                 s->tsr = ENTSR_PTX;
 270                 s->isr |= ENISR_TX;
 271                 ne2000_update_irq(s);
 272             }
 273         }
 274     } else {
 275         page = s->cmd >> 6;
 276         offset = addr | (page << 4);
 277         switch(offset) {
 278         case EN0_STARTPG:
 279             s->start = val << 8;
 280             break;
 281         case EN0_STOPPG:
 282             s->stop = val << 8;
 283             break;
 284         case EN0_BOUNDARY:
 285             s->boundary = val;
 286             break;
 287         case EN0_IMR:
 288             s->imr = val;
 289             ne2000_update_irq(s);
 290             break;
 291         case EN0_TPSR:
 292             s->tpsr = val;
 293             break;
 294         case EN0_TCNTLO:
 295             s->tcnt = (s->tcnt & 0xff00) | val;
 296             break;
 297         case EN0_TCNTHI:
 298             s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
 299             break;
 300         case EN0_RSARLO:
 301             s->rsar = (s->rsar & 0xff00) | val;
 302             break;
 303         case EN0_RSARHI:
 304             s->rsar = (s->rsar & 0x00ff) | (val << 8);
 305             break;
 306         case EN0_RCNTLO:
 307             s->rcnt = (s->rcnt & 0xff00) | val;
 308             break;
 309         case EN0_RCNTHI:
 310             s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
 311             break;
 312         case EN0_DCFG:
 313             s->dcfg = val;
 314             break;
 315         case EN0_ISR:
 316             s->isr &= ~(val & 0x7f);
 317             ne2000_update_irq(s);
 318             break;
 319         case EN1_PHYS ... EN1_PHYS + 5:
 320             s->phys[offset - EN1_PHYS] = val;
 321             break;
 322         case EN1_CURPAG:
 323             s->curpag = val;
 324             break;
 325         case EN1_MULT ... EN1_MULT + 7:
 326             s->mult[offset - EN1_MULT] = val;
 327             break;
 328         }
 329     }
 330 }
 331
 332 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
 333 {
 334     NE2000State *s = opaque;
 335     int offset, page, ret;
 336
 337     addr &= 0xf;
 338     if (addr == E8390_CMD) {
 339         ret = s->cmd;
 340     } else {
 341         page = s->cmd >> 6;
 342         offset = addr | (page << 4);
 343         switch(offset) {
 344         case EN0_TSR:
 345             ret = s->tsr;
 346             break;
 347         case EN0_BOUNDARY:
 348             ret = s->boundary;
 349             break;
 350         case EN0_ISR:
 351             ret = s->isr;
 352             break;
 353         case EN0_RSARLO:
 354             ret = s->rsar & 0x00ff;
 355             break;
 356         case EN0_RSARHI:
 357             ret = s->rsar >> 8;
 358             break;
 359         case EN1_PHYS ... EN1_PHYS + 5:
 360             ret = s->phys[offset - EN1_PHYS];
 361             break;
 362         case EN1_CURPAG:
 363             ret = s->curpag;
 364             break;
 365         case EN1_MULT ... EN1_MULT + 7:
 366             ret = s->mult[offset - EN1_MULT];
 367             break;
 368         case EN0_RSR:
 369             ret = s->rsr;
 370             break;
 371         default:
 372             ret = 0x00;
 373             break;
 374         }
 375     }
 376 #ifdef DEBUG_NE2000
 377     printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
 378 #endif
 379     return ret;
 380 }
 381
 382 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
 383                                      uint32_t val)
 384 {
 385     if (addr < 32 ||
 386         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 387         s->mem[addr] = val;
 388     }
 389 }
 390
 391 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
 392                                      uint32_t val)
 393 {
 394     addr &= ~1; /* XXX: check exact behaviour if not even */
 395     if (addr < 32 ||
 396         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 397         *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
 398     }
 399 }
 400
 401 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
 402                                      uint32_t val)
 403 {
 404     addr &= ~1; /* XXX: check exact behaviour if not even */
 405     if (addr < 32 ||
 406         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 407         cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
 408     }
 409 }
 410
 411 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
 412 {
 413     if (addr < 32 ||
 414         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 415         return s->mem[addr];
 416     } else {
 417         return 0xff;
 418     }
 419 }
 420
 421 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
 422 {
 423     addr &= ~1; /* XXX: check exact behaviour if not even */
 424     if (addr < 32 ||
 425         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 426         return le16_to_cpu(*(uint16_t *)(s->mem + addr));
 427     } else {
 428         return 0xffff;
 429     }
 430 }
 431
 432 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
 433 {
 434     addr &= ~1; /* XXX: check exact behaviour if not even */
 435     if (addr < 32 ||
 436         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 437         return le32_to_cpupu((uint32_t *)(s->mem + addr));
 438     } else {
 439         return 0xffffffff;
 440     }
 441 }
 442
 443 static inline void ne2000_dma_update(NE2000State *s, int len)
 444 {
 445     s->rsar += len;
 446     /* wrap */
 447     /* XXX: check what to do if rsar > stop */
 448     if (s->rsar == s->stop)
 449         s->rsar = s->start;
 450
 451     if (s->rcnt <= len) {
 452         s->rcnt = 0;
 453         /* signal end of transfert */
 454         s->isr |= ENISR_RDC;
 455         ne2000_update_irq(s);
 456     } else {
 457         s->rcnt -= len;
 458     }
 459 }
 460
 461 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 462 {
 463     NE2000State *s = opaque;
 464
 465 #ifdef DEBUG_NE2000
 466     printf("NE2000: asic write val=0x%04x\n", val);
 467 #endif
 468     if (s->rcnt == 0)
 469         return;
 470     if (s->dcfg & 0x01) {
 471         /* 16 bit access */
 472         ne2000_mem_writew(s, s->rsar, val);
 473         ne2000_dma_update(s, 2);
 474     } else {
 475         /* 8 bit access */
 476         ne2000_mem_writeb(s, s->rsar, val);
 477         ne2000_dma_update(s, 1);
 478     }
 479 }
 480
 481 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
 482 {
 483     NE2000State *s = opaque;
 484     int ret;
 485
 486     if (s->dcfg & 0x01) {
 487         /* 16 bit access */
 488         ret = ne2000_mem_readw(s, s->rsar);
 489         ne2000_dma_update(s, 2);
 490     } else {
 491         /* 8 bit access */
 492         ret = ne2000_mem_readb(s, s->rsar);
 493         ne2000_dma_update(s, 1);
 494     }
 495 #ifdef DEBUG_NE2000
 496     printf("NE2000: asic read val=0x%04x\n", ret);
 497 #endif
 498     return ret;
 499 }
 500
 501 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 502 {
 503     NE2000State *s = opaque;
 504
 505 #ifdef DEBUG_NE2000
 506     printf("NE2000: asic writel val=0x%04x\n", val);
 507 #endif
 508     if (s->rcnt == 0)
 509         return;
 510     /* 32 bit access */
 511     ne2000_mem_writel(s, s->rsar, val);
 512     ne2000_dma_update(s, 4);
 513 }
 514
 515 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
 516 {
 517     NE2000State *s = opaque;
 518     int ret;
 519
 520     /* 32 bit access */
 521     ret = ne2000_mem_readl(s, s->rsar);
 522     ne2000_dma_update(s, 4);
 523 #ifdef DEBUG_NE2000
 524     printf("NE2000: asic readl val=0x%04x\n", ret);
 525 #endif
 526     return ret;
 527 }
 528
 529 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 530 {
 531     /* nothing to do (end of reset pulse) */
 532 }
 533
 534 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
 535 {
 536     NE2000State *s = opaque;
 537     ne2000_reset(s);
 538     return 0;
 539 }
 540
 541 void isa_ne2000_init(int base, int irq, NetDriverState *nd)
 542 {
 543     NE2000State *s;
 544
 545     s = qemu_mallocz(sizeof(NE2000State));
 546     if (!s)
 547         return;
 548
 549     register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
 550     register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
 551
 552     register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
 553     register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
 554     register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
 555     register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 556
 557     register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
 558     register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
 559     s->irq = irq;
 560     s->nd = nd;
 561
 562     ne2000_reset(s);
 563
 564     qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s);
 565 }
 566
 567 /***********************************************************/
 568 /* PCI NE2000 definitions */
 569
 570 typedef struct PCINE2000State {
 571     PCIDevice dev;
 572     NE2000State ne2000;
 573 } PCINE2000State;
 574
 575 static void ne2000_map(PCIDevice *pci_dev, int region_num,
 576                        uint32_t addr, uint32_t size, int type)
 577 {
 578     PCINE2000State *d = (PCINE2000State *)pci_dev;
 579     NE2000State *s = &d->ne2000;
 580
 581     register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
 582     register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
 583
 584     register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
 585     register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
 586     register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
 587     register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 588     register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
 589     register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
 590
 591     register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
 592     register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
 593 }
 594
 595 void pci_ne2000_init(PCIBus *bus, NetDriverState *nd)
 596 {
 597     PCINE2000State *d;
 598     NE2000State *s;
 599     uint8_t *pci_conf;
 600
 601     d = (PCINE2000State *)pci_register_device(bus,
 602                                               "NE2000", sizeof(PCINE2000State),
 603                                               -1,
 604                                               NULL, NULL);
 605     pci_conf = d->dev.config;
 606     pci_conf[0x00] = 0xec; // Realtek 8029
 607     pci_conf[0x01] = 0x10;
 608     pci_conf[0x02] = 0x29;
 609     pci_conf[0x03] = 0x80;
 610     pci_conf[0x0a] = 0x00; // ethernet network controller
 611     pci_conf[0x0b] = 0x02;
 612     pci_conf[0x0e] = 0x00; // header_type
 613     pci_conf[0x3d] = 1; // interrupt pin 0
 614
 615     pci_register_io_region((PCIDevice *)d, 0, 0x100,
 616                            PCI_ADDRESS_SPACE_IO, ne2000_map);
 617     s = &d->ne2000;
 618     s->irq = 16; // PCI interrupt
 619     s->pci_dev = (PCIDevice *)d;
 620     s->nd = nd;
 621     ne2000_reset(s);
 622     qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s);
 623 }