hw/ne2000.c

   1 /*
   2  * QEMU NE2000 emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* debug NE2000 card */
  27 //#define DEBUG_NE2000
  28
  29 #define MAX_ETH_FRAME_SIZE 1514
  30
  31 #define E8390_CMD       0x00  /* The command register (for all pages) */
  32 /* Page 0 register offsets. */
  33 #define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
  34 #define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
  35 #define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
  36 #define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
  37 #define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
  38 #define EN0_TSR         0x04    /* Transmit status reg RD */
  39 #define EN0_TPSR        0x04    /* Transmit starting page WR */
  40 #define EN0_NCR         0x05    /* Number of collision reg RD */
  41 #define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
  42 #define EN0_FIFO        0x06    /* FIFO RD */
  43 #define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
  44 #define EN0_ISR         0x07    /* Interrupt status reg RD WR */
  45 #define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
  46 #define EN0_RSARLO      0x08    /* Remote start address reg 0 */
  47 #define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
  48 #define EN0_RSARHI      0x09    /* Remote start address reg 1 */
  49 #define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
  50 #define EN0_RTL8029ID0  0x0a    /* Realtek ID byte #1 RD */
  51 #define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
  52 #define EN0_RTL8029ID1  0x0b    /* Realtek ID byte #2 RD */
  53 #define EN0_RSR         0x0c    /* rx status reg RD */
  54 #define EN0_RXCR        0x0c    /* RX configuration reg WR */
  55 #define EN0_TXCR        0x0d    /* TX configuration reg WR */
  56 #define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
  57 #define EN0_DCFG        0x0e    /* Data configuration reg WR */
  58 #define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
  59 #define EN0_IMR         0x0f    /* Interrupt mask reg WR */
  60 #define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
  61
  62 #define EN1_PHYS        0x11
  63 #define EN1_CURPAG      0x17
  64 #define EN1_MULT        0x18
  65
  66 #define EN2_STARTPG     0x21    /* Starting page of ring bfr RD */
  67 #define EN2_STOPPG      0x22    /* Ending page +1 of ring bfr RD */
  68
  69 #define EN3_CONFIG0     0x33
  70 #define EN3_CONFIG1     0x34
  71 #define EN3_CONFIG2     0x35
  72 #define EN3_CONFIG3     0x36
  73
  74 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  75 #define E8390_STOP      0x01    /* Stop and reset the chip */
  76 #define E8390_START     0x02    /* Start the chip, clear reset */
  77 #define E8390_TRANS     0x04    /* Transmit a frame */
  78 #define E8390_RREAD     0x08    /* Remote read */
  79 #define E8390_RWRITE    0x10    /* Remote write  */
  80 #define E8390_NODMA     0x20    /* Remote DMA */
  81 #define E8390_PAGE0     0x00    /* Select page chip registers */
  82 #define E8390_PAGE1     0x40    /* using the two high-order bits */
  83 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
  84
  85 /* Bits in EN0_ISR - Interrupt status register */
  86 #define ENISR_RX        0x01    /* Receiver, no error */
  87 #define ENISR_TX        0x02    /* Transmitter, no error */
  88 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
  89 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
  90 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
  91 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
  92 #define ENISR_RDC       0x40    /* remote dma complete */
  93 #define ENISR_RESET     0x80    /* Reset completed */
  94 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
  95
  96 /* Bits in received packet status byte and EN0_RSR*/
  97 #define ENRSR_RXOK      0x01    /* Received a good packet */
  98 #define ENRSR_CRC       0x02    /* CRC error */
  99 #define ENRSR_FAE       0x04    /* frame alignment error */
 100 #define ENRSR_FO        0x08    /* FIFO overrun */
 101 #define ENRSR_MPA       0x10    /* missed pkt */
 102 #define ENRSR_PHY       0x20    /* physical/multicast address */
 103 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
 104 #define ENRSR_DEF       0x80    /* deferring */
 105
 106 /* Transmitted packet status, EN0_TSR. */
 107 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
 108 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
 109 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 110 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 111 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 112 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 113 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 114 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 115
 116 #define NE2000_PMEM_SIZE    (32*1024)
 117 #define NE2000_PMEM_START   (16*1024)
 118 #define NE2000_PMEM_END     (NE2000_PMEM_SIZE+NE2000_PMEM_START)
 119 #define NE2000_MEM_SIZE     NE2000_PMEM_END
 120
 121 typedef struct NE2000State {
 122     uint8_t cmd;
 123     uint32_t start;
 124     uint32_t stop;
 125     uint8_t boundary;
 126     uint8_t tsr;
 127     uint8_t tpsr;
 128     uint16_t tcnt;
 129     uint16_t rcnt;
 130     uint32_t rsar;
 131     uint8_t rsr;
 132     uint8_t rxcr;
 133     uint8_t isr;
 134     uint8_t dcfg;
 135     uint8_t imr;
 136     uint8_t phys[6]; /* mac address */
 137     uint8_t curpag;
 138     uint8_t mult[8]; /* multicast mask array */
 139     int irq;
 140     PCIDevice *pci_dev;
 141     VLANClientState *vc;
 142     uint8_t macaddr[6];
 143     uint8_t mem[NE2000_MEM_SIZE];
 144 } NE2000State;
 145
 146 static void ne2000_reset(NE2000State *s)
 147 {
 148     int i;
 149
 150     s->isr = ENISR_RESET;
 151     memcpy(s->mem, s->macaddr, 6);
 152     s->mem[14] = 0x57;
 153     s->mem[15] = 0x57;
 154
 155     /* duplicate prom data */
 156     for(i = 15;i >= 0; i--) {
 157         s->mem[2 * i] = s->mem[i];
 158         s->mem[2 * i + 1] = s->mem[i];
 159     }
 160 }
 161
 162 static void ne2000_update_irq(NE2000State *s)
 163 {
 164     int isr;
 165     isr = (s->isr & s->imr) & 0x7f;
 166 #if defined(DEBUG_NE2000)
 167     printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
 168            s->irq, isr ? 1 : 0, s->isr, s->imr);
 169 #endif
 170     if (s->irq == 16) {
 171         /* PCI irq */
 172         pci_set_irq(s->pci_dev, 0, (isr != 0));
 173     } else {
 174         /* ISA irq */
 175         pic_set_irq(s->irq, (isr != 0));
 176     }
 177 }
 178
 179 #define POLYNOMIAL 0x04c11db6
 180
 181 /* From FreeBSD */
 182 /* XXX: optimize */
 183 static int compute_mcast_idx(const uint8_t *ep)
 184 {
 185     uint32_t crc;
 186     int carry, i, j;
 187     uint8_t b;
 188
 189     crc = 0xffffffff;
 190     for (i = 0; i < 6; i++) {
 191         b = *ep++;
 192         for (j = 0; j < 8; j++) {
 193             carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
 194             crc <<= 1;
 195             b >>= 1;
 196             if (carry)
 197                 crc = ((crc ^ POLYNOMIAL) | carry);
 198         }
 199     }
 200     return (crc >> 26);
 201 }
 202
 203 /* return the max buffer size if the NE2000 can receive more data */
 204 static int ne2000_can_receive(void *opaque)
 205 {
 206     NE2000State *s = opaque;
 207     int avail, index, boundary;
 208
 209     if (s->cmd & E8390_STOP)
 210         return 0;
 211     index = s->curpag << 8;
 212     boundary = s->boundary << 8;
 213     if (index < boundary)
 214         avail = boundary - index;
 215     else
 216         avail = (s->stop - s->start) - (index - boundary);
 217     if (avail < (MAX_ETH_FRAME_SIZE + 4))
 218         return 0;
 219     return MAX_ETH_FRAME_SIZE;
 220 }
 221
 222 #define MIN_BUF_SIZE 60
 223
 224 static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
 225 {
 226     NE2000State *s = opaque;
 227     uint8_t *p;
 228     int total_len, next, avail, len, index, mcast_idx;
 229     uint8_t buf1[60];
 230     static const uint8_t broadcast_macaddr[6] =
 231         { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 232
 233 #if defined(DEBUG_NE2000)
 234     printf("NE2000: received len=%d\n", size);
 235 #endif
 236
 237     if (!ne2000_can_receive(s))
 238         return;
 239
 240     /* XXX: check this */
 241     if (s->rxcr & 0x10) {
 242         /* promiscuous: receive all */
 243     } else {
 244         if (!memcmp(buf,  broadcast_macaddr, 6)) {
 245             /* broadcast address */
 246             if (!(s->rxcr & 0x04))
 247                 return;
 248         } else if (buf[0] & 0x01) {
 249             /* multicast */
 250             if (!(s->rxcr & 0x08))
 251                 return;
 252             mcast_idx = compute_mcast_idx(buf);
 253             if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
 254                 return;
 255         } else if (s->mem[0] == buf[0] &&
 256                    s->mem[2] == buf[1] &&
 257                    s->mem[4] == buf[2] &&
 258                    s->mem[6] == buf[3] &&
 259                    s->mem[8] == buf[4] &&
 260                    s->mem[10] == buf[5]) {
 261             /* match */
 262         } else {
 263             return;
 264         }
 265     }
 266
 267
 268     /* if too small buffer, then expand it */
 269     if (size < MIN_BUF_SIZE) {
 270         memcpy(buf1, buf, size);
 271         memset(buf1 + size, 0, MIN_BUF_SIZE - size);
 272         buf = buf1;
 273         size = MIN_BUF_SIZE;
 274     }
 275
 276     index = s->curpag << 8;
 277     /* 4 bytes for header */
 278     total_len = size + 4;
 279     /* address for next packet (4 bytes for CRC) */
 280     next = index + ((total_len + 4 + 255) & ~0xff);
 281     if (next >= s->stop)
 282         next -= (s->stop - s->start);
 283     /* prepare packet header */
 284     p = s->mem + index;
 285     s->rsr = ENRSR_RXOK; /* receive status */
 286     /* XXX: check this */
 287     if (buf[0] & 0x01)
 288         s->rsr |= ENRSR_PHY;
 289     p[0] = s->rsr;
 290     p[1] = next >> 8;
 291     p[2] = total_len;
 292     p[3] = total_len >> 8;
 293     index += 4;
 294
 295     /* write packet data */
 296     while (size > 0) {
 297         avail = s->stop - index;
 298         len = size;
 299         if (len > avail)
 300             len = avail;
 301         memcpy(s->mem + index, buf, len);
 302         buf += len;
 303         index += len;
 304         if (index == s->stop)
 305             index = s->start;
 306         size -= len;
 307     }
 308     s->curpag = next >> 8;
 309
 310     /* now we can signal we have receive something */
 311     s->isr |= ENISR_RX;
 312     ne2000_update_irq(s);
 313 }
 314
 315 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 316 {
 317     NE2000State *s = opaque;
 318     int offset, page, index;
 319
 320     addr &= 0xf;
 321 #ifdef DEBUG_NE2000
 322     printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
 323 #endif
 324     if (addr == E8390_CMD) {
 325         /* control register */
 326         s->cmd = val;
 327         if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
 328             s->isr &= ~ENISR_RESET;
 329             /* test specific case: zero length transfert */
 330             if ((val & (E8390_RREAD | E8390_RWRITE)) &&
 331                 s->rcnt == 0) {
 332                 s->isr |= ENISR_RDC;
 333                 ne2000_update_irq(s);
 334             }
 335             if (val & E8390_TRANS) {
 336                 index = (s->tpsr << 8);
 337                 /* XXX: next 2 lines are a hack to make netware 3.11 work */
 338                 if (index >= NE2000_PMEM_END)
 339                     index -= NE2000_PMEM_SIZE;
 340                 /* fail safe: check range on the transmitted length  */
 341                 if (index + s->tcnt <= NE2000_PMEM_END) {
 342                     qemu_send_packet(s->vc, s->mem + index, s->tcnt);
 343                 }
 344                 /* signal end of transfert */
 345                 s->tsr = ENTSR_PTX;
 346                 s->isr |= ENISR_TX;
 347                 s->cmd &= ~E8390_TRANS;
 348                 ne2000_update_irq(s);
 349             }
 350         }
 351     } else {
 352         page = s->cmd >> 6;
 353         offset = addr | (page << 4);
 354         switch(offset) {
 355         case EN0_STARTPG:
 356             s->start = val << 8;
 357             break;
 358         case EN0_STOPPG:
 359             s->stop = val << 8;
 360             break;
 361         case EN0_BOUNDARY:
 362             s->boundary = val;
 363             break;
 364         case EN0_IMR:
 365             s->imr = val;
 366             ne2000_update_irq(s);
 367             break;
 368         case EN0_TPSR:
 369             s->tpsr = val;
 370             break;
 371         case EN0_TCNTLO:
 372             s->tcnt = (s->tcnt & 0xff00) | val;
 373             break;
 374         case EN0_TCNTHI:
 375             s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
 376             break;
 377         case EN0_RSARLO:
 378             s->rsar = (s->rsar & 0xff00) | val;
 379             break;
 380         case EN0_RSARHI:
 381             s->rsar = (s->rsar & 0x00ff) | (val << 8);
 382             break;
 383         case EN0_RCNTLO:
 384             s->rcnt = (s->rcnt & 0xff00) | val;
 385             break;
 386         case EN0_RCNTHI:
 387             s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
 388             break;
 389         case EN0_RXCR:
 390             s->rxcr = val;
 391             break;
 392         case EN0_DCFG:
 393             s->dcfg = val;
 394             break;
 395         case EN0_ISR:
 396             s->isr &= ~(val & 0x7f);
 397             ne2000_update_irq(s);
 398             break;
 399         case EN1_PHYS ... EN1_PHYS + 5:
 400             s->phys[offset - EN1_PHYS] = val;
 401             break;
 402         case EN1_CURPAG:
 403             s->curpag = val;
 404             break;
 405         case EN1_MULT ... EN1_MULT + 7:
 406             s->mult[offset - EN1_MULT] = val;
 407             break;
 408         }
 409     }
 410 }
 411
 412 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
 413 {
 414     NE2000State *s = opaque;
 415     int offset, page, ret;
 416
 417     addr &= 0xf;
 418     if (addr == E8390_CMD) {
 419         ret = s->cmd;
 420     } else {
 421         page = s->cmd >> 6;
 422         offset = addr | (page << 4);
 423         switch(offset) {
 424         case EN0_TSR:
 425             ret = s->tsr;
 426             break;
 427         case EN0_BOUNDARY:
 428             ret = s->boundary;
 429             break;
 430         case EN0_ISR:
 431             ret = s->isr;
 432             break;
 433         case EN0_RSARLO:
 434             ret = s->rsar & 0x00ff;
 435             break;
 436         case EN0_RSARHI:
 437             ret = s->rsar >> 8;
 438             break;
 439         case EN1_PHYS ... EN1_PHYS + 5:
 440             ret = s->phys[offset - EN1_PHYS];
 441             break;
 442         case EN1_CURPAG:
 443             ret = s->curpag;
 444             break;
 445         case EN1_MULT ... EN1_MULT + 7:
 446             ret = s->mult[offset - EN1_MULT];
 447             break;
 448         case EN0_RSR:
 449             ret = s->rsr;
 450             break;
 451         case EN2_STARTPG:
 452             ret = s->start >> 8;
 453             break;
 454         case EN2_STOPPG:
 455             ret = s->stop >> 8;
 456             break;
 457         case EN0_RTL8029ID0:
 458             ret = 0x50;
 459             break;
 460         case EN0_RTL8029ID1:
 461             ret = 0x43;
 462             break;
 463         case EN3_CONFIG0:
 464             ret = 0;            /* 10baseT media */
 465             break;
 466         case EN3_CONFIG2:
 467             ret = 0x40;         /* 10baseT active */
 468             break;
 469         case EN3_CONFIG3:
 470             ret = 0x40;         /* Full duplex */
 471             break;
 472         default:
 473             ret = 0x00;
 474             break;
 475         }
 476     }
 477 #ifdef DEBUG_NE2000
 478     printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
 479 #endif
 480     return ret;
 481 }
 482
 483 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
 484                                      uint32_t val)
 485 {
 486     if (addr < 32 ||
 487         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 488         s->mem[addr] = val;
 489     }
 490 }
 491
 492 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
 493                                      uint32_t val)
 494 {
 495     addr &= ~1; /* XXX: check exact behaviour if not even */
 496     if (addr < 32 ||
 497         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 498         *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
 499     }
 500 }
 501
 502 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
 503                                      uint32_t val)
 504 {
 505     addr &= ~1; /* XXX: check exact behaviour if not even */
 506     if (addr < 32 ||
 507         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 508         cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
 509     }
 510 }
 511
 512 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
 513 {
 514     if (addr < 32 ||
 515         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 516         return s->mem[addr];
 517     } else {
 518         return 0xff;
 519     }
 520 }
 521
 522 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
 523 {
 524     addr &= ~1; /* XXX: check exact behaviour if not even */
 525     if (addr < 32 ||
 526         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 527         return le16_to_cpu(*(uint16_t *)(s->mem + addr));
 528     } else {
 529         return 0xffff;
 530     }
 531 }
 532
 533 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
 534 {
 535     addr &= ~1; /* XXX: check exact behaviour if not even */
 536     if (addr < 32 ||
 537         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 538         return le32_to_cpupu((uint32_t *)(s->mem + addr));
 539     } else {
 540         return 0xffffffff;
 541     }
 542 }
 543
 544 static inline void ne2000_dma_update(NE2000State *s, int len)
 545 {
 546     s->rsar += len;
 547     /* wrap */
 548     /* XXX: check what to do if rsar > stop */
 549     if (s->rsar == s->stop)
 550         s->rsar = s->start;
 551
 552     if (s->rcnt <= len) {
 553         s->rcnt = 0;
 554         /* signal end of transfert */
 555         s->isr |= ENISR_RDC;
 556         ne2000_update_irq(s);
 557     } else {
 558         s->rcnt -= len;
 559     }
 560 }
 561
 562 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 563 {
 564     NE2000State *s = opaque;
 565
 566 #ifdef DEBUG_NE2000
 567     printf("NE2000: asic write val=0x%04x\n", val);
 568 #endif
 569     if (s->rcnt == 0)
 570         return;
 571     if (s->dcfg & 0x01) {
 572         /* 16 bit access */
 573         ne2000_mem_writew(s, s->rsar, val);
 574         ne2000_dma_update(s, 2);
 575     } else {
 576         /* 8 bit access */
 577         ne2000_mem_writeb(s, s->rsar, val);
 578         ne2000_dma_update(s, 1);
 579     }
 580 }
 581
 582 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
 583 {
 584     NE2000State *s = opaque;
 585     int ret;
 586
 587     if (s->dcfg & 0x01) {
 588         /* 16 bit access */
 589         ret = ne2000_mem_readw(s, s->rsar);
 590         ne2000_dma_update(s, 2);
 591     } else {
 592         /* 8 bit access */
 593         ret = ne2000_mem_readb(s, s->rsar);
 594         ne2000_dma_update(s, 1);
 595     }
 596 #ifdef DEBUG_NE2000
 597     printf("NE2000: asic read val=0x%04x\n", ret);
 598 #endif
 599     return ret;
 600 }
 601
 602 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 603 {
 604     NE2000State *s = opaque;
 605
 606 #ifdef DEBUG_NE2000
 607     printf("NE2000: asic writel val=0x%04x\n", val);
 608 #endif
 609     if (s->rcnt == 0)
 610         return;
 611     /* 32 bit access */
 612     ne2000_mem_writel(s, s->rsar, val);
 613     ne2000_dma_update(s, 4);
 614 }
 615
 616 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
 617 {
 618     NE2000State *s = opaque;
 619     int ret;
 620
 621     /* 32 bit access */
 622     ret = ne2000_mem_readl(s, s->rsar);
 623     ne2000_dma_update(s, 4);
 624 #ifdef DEBUG_NE2000
 625     printf("NE2000: asic readl val=0x%04x\n", ret);
 626 #endif
 627     return ret;
 628 }
 629
 630 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 631 {
 632     /* nothing to do (end of reset pulse) */
 633 }
 634
 635 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
 636 {
 637     NE2000State *s = opaque;
 638     ne2000_reset(s);
 639     return 0;
 640 }
 641
 642 static void ne2000_save(QEMUFile* f,void* opaque)
 643 {
 644         NE2000State* s=(NE2000State*)opaque;
 645
 646         qemu_put_8s(f, &s->rxcr);
 647
 648         qemu_put_8s(f, &s->cmd);
 649         qemu_put_be32s(f, &s->start);
 650         qemu_put_be32s(f, &s->stop);
 651         qemu_put_8s(f, &s->boundary);
 652         qemu_put_8s(f, &s->tsr);
 653         qemu_put_8s(f, &s->tpsr);
 654         qemu_put_be16s(f, &s->tcnt);
 655         qemu_put_be16s(f, &s->rcnt);
 656         qemu_put_be32s(f, &s->rsar);
 657         qemu_put_8s(f, &s->rsr);
 658         qemu_put_8s(f, &s->isr);
 659         qemu_put_8s(f, &s->dcfg);
 660         qemu_put_8s(f, &s->imr);
 661         qemu_put_buffer(f, s->phys, 6);
 662         qemu_put_8s(f, &s->curpag);
 663         qemu_put_buffer(f, s->mult, 8);
 664         qemu_put_be32s(f, &s->irq);
 665         qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
 666 }
 667
 668 static int ne2000_load(QEMUFile* f,void* opaque,int version_id)
 669 {
 670         NE2000State* s=(NE2000State*)opaque;
 671
 672         if (version_id == 2) {
 673             qemu_get_8s(f, &s->rxcr);
 674         } else if (version_id == 1) {
 675             s->rxcr = 0x0c;
 676         } else {
 677             return -EINVAL;
 678         }
 679
 680         qemu_get_8s(f, &s->cmd);
 681         qemu_get_be32s(f, &s->start);
 682         qemu_get_be32s(f, &s->stop);
 683         qemu_get_8s(f, &s->boundary);
 684         qemu_get_8s(f, &s->tsr);
 685         qemu_get_8s(f, &s->tpsr);
 686         qemu_get_be16s(f, &s->tcnt);
 687         qemu_get_be16s(f, &s->rcnt);
 688         qemu_get_be32s(f, &s->rsar);
 689         qemu_get_8s(f, &s->rsr);
 690         qemu_get_8s(f, &s->isr);
 691         qemu_get_8s(f, &s->dcfg);
 692         qemu_get_8s(f, &s->imr);
 693         qemu_get_buffer(f, s->phys, 6);
 694         qemu_get_8s(f, &s->curpag);
 695         qemu_get_buffer(f, s->mult, 8);
 696         qemu_get_be32s(f, &s->irq);
 697         qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
 698
 699         return 0;
 700 }
 701
 702 void isa_ne2000_init(int base, int irq, NICInfo *nd)
 703 {
 704     NE2000State *s;
 705
 706     s = qemu_mallocz(sizeof(NE2000State));
 707     if (!s)
 708         return;
 709
 710     register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
 711     register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
 712
 713     register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
 714     register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
 715     register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
 716     register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 717
 718     register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
 719     register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
 720     s->irq = irq;
 721     memcpy(s->macaddr, nd->macaddr, 6);
 722
 723     ne2000_reset(s);
 724
 725     s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, s);
 726
 727     snprintf(s->vc->info_str, sizeof(s->vc->info_str),
 728              "ne2000 macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
 729              s->macaddr[0],
 730              s->macaddr[1],
 731              s->macaddr[2],
 732              s->macaddr[3],
 733              s->macaddr[4],
 734              s->macaddr[5]);
 735
 736     register_savevm("ne2000", 0, 2, ne2000_save, ne2000_load, s);
 737 }
 738
 739 /***********************************************************/
 740 /* PCI NE2000 definitions */
 741
 742 typedef struct PCINE2000State {
 743     PCIDevice dev;
 744     NE2000State ne2000;
 745 } PCINE2000State;
 746
 747 static void ne2000_map(PCIDevice *pci_dev, int region_num,
 748                        uint32_t addr, uint32_t size, int type)
 749 {
 750     PCINE2000State *d = (PCINE2000State *)pci_dev;
 751     NE2000State *s = &d->ne2000;
 752
 753     register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
 754     register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
 755
 756     register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
 757     register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
 758     register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
 759     register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 760     register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
 761     register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
 762
 763     register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
 764     register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
 765 }
 766
 767 void pci_ne2000_init(PCIBus *bus, NICInfo *nd)
 768 {
 769     PCINE2000State *d;
 770     NE2000State *s;
 771     uint8_t *pci_conf;
 772
 773     d = (PCINE2000State *)pci_register_device(bus,
 774                                               "NE2000", sizeof(PCINE2000State),
 775                                               -1,
 776                                               NULL, NULL);
 777     pci_conf = d->dev.config;
 778     pci_conf[0x00] = 0xec; // Realtek 8029
 779     pci_conf[0x01] = 0x10;
 780     pci_conf[0x02] = 0x29;
 781     pci_conf[0x03] = 0x80;
 782     pci_conf[0x0a] = 0x00; // ethernet network controller
 783     pci_conf[0x0b] = 0x02;
 784     pci_conf[0x0e] = 0x00; // header_type
 785     pci_conf[0x3d] = 1; // interrupt pin 0
 786
 787     pci_register_io_region(&d->dev, 0, 0x100,
 788                            PCI_ADDRESS_SPACE_IO, ne2000_map);
 789     s = &d->ne2000;
 790     s->irq = 16; // PCI interrupt
 791     s->pci_dev = (PCIDevice *)d;
 792     memcpy(s->macaddr, nd->macaddr, 6);
 793     ne2000_reset(s);
 794     s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, s);
 795
 796     snprintf(s->vc->info_str, sizeof(s->vc->info_str),
 797              "ne2000 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
 798              s->macaddr[0],
 799              s->macaddr[1],
 800              s->macaddr[2],
 801              s->macaddr[3],
 802              s->macaddr[4],
 803              s->macaddr[5]);
 804
 805     /* XXX: instance number ? */
 806     register_savevm("ne2000", 0, 2, ne2000_save, ne2000_load, s);
 807     register_savevm("ne2000_pci", 0, 1, generic_pci_save, generic_pci_load,
 808                     &d->dev);
 809 }