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hw/nvme: fix aio cancel in flush
[mirror_qemu.git] / hw / nvme / ctrl.c
1 /*
2 * QEMU NVM Express Controller
3 *
4 * Copyright (c) 2012, Intel Corporation
5 *
6 * Written by Keith Busch <keith.busch@intel.com>
7 *
8 * This code is licensed under the GNU GPL v2 or later.
9 */
10
11 /**
12 * Reference Specs: http://www.nvmexpress.org, 1.4, 1.3, 1.2, 1.1, 1.0e
13 *
14 * https://nvmexpress.org/developers/nvme-specification/
15 *
16 *
17 * Notes on coding style
18 * ---------------------
19 * While QEMU coding style prefers lowercase hexadecimals in constants, the
20 * NVMe subsystem use thes format from the NVMe specifications in the comments
21 * (i.e. 'h' suffix instead of '0x' prefix).
22 *
23 * Usage
24 * -----
25 * See docs/system/nvme.rst for extensive documentation.
26 *
27 * Add options:
28 * -drive file=<file>,if=none,id=<drive_id>
29 * -device nvme-subsys,id=<subsys_id>,nqn=<nqn_id>
30 * -device nvme,serial=<serial>,id=<bus_name>, \
31 * cmb_size_mb=<cmb_size_mb[optional]>, \
32 * [pmrdev=<mem_backend_file_id>,] \
33 * max_ioqpairs=<N[optional]>, \
34 * aerl=<N[optional]>,aer_max_queued=<N[optional]>, \
35 * mdts=<N[optional]>,vsl=<N[optional]>, \
36 * zoned.zasl=<N[optional]>, \
37 * zoned.auto_transition=<on|off[optional]>, \
38 * sriov_max_vfs=<N[optional]> \
39 * sriov_vq_flexible=<N[optional]> \
40 * sriov_vi_flexible=<N[optional]> \
41 * sriov_max_vi_per_vf=<N[optional]> \
42 * sriov_max_vq_per_vf=<N[optional]> \
43 * subsys=<subsys_id>
44 * -device nvme-ns,drive=<drive_id>,bus=<bus_name>,nsid=<nsid>,\
45 * zoned=<true|false[optional]>, \
46 * subsys=<subsys_id>,detached=<true|false[optional]>
47 *
48 * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at
49 * offset 0 in BAR2 and supports only WDS, RDS and SQS for now. By default, the
50 * device will use the "v1.4 CMB scheme" - use the `legacy-cmb` parameter to
51 * always enable the CMBLOC and CMBSZ registers (v1.3 behavior).
52 *
53 * Enabling pmr emulation can be achieved by pointing to memory-backend-file.
54 * For example:
55 * -object memory-backend-file,id=<mem_id>,share=on,mem-path=<file_path>, \
56 * size=<size> .... -device nvme,...,pmrdev=<mem_id>
57 *
58 * The PMR will use BAR 4/5 exclusively.
59 *
60 * To place controller(s) and namespace(s) to a subsystem, then provide
61 * nvme-subsys device as above.
62 *
63 * nvme subsystem device parameters
64 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
65 * - `nqn`
66 * This parameter provides the `<nqn_id>` part of the string
67 * `nqn.2019-08.org.qemu:<nqn_id>` which will be reported in the SUBNQN field
68 * of subsystem controllers. Note that `<nqn_id>` should be unique per
69 * subsystem, but this is not enforced by QEMU. If not specified, it will
70 * default to the value of the `id` parameter (`<subsys_id>`).
71 *
72 * nvme device parameters
73 * ~~~~~~~~~~~~~~~~~~~~~~
74 * - `subsys`
75 * Specifying this parameter attaches the controller to the subsystem and
76 * the SUBNQN field in the controller will report the NQN of the subsystem
77 * device. This also enables multi controller capability represented in
78 * Identify Controller data structure in CMIC (Controller Multi-path I/O and
79 * Namespace Sharing Capabilities).
80 *
81 * - `aerl`
82 * The Asynchronous Event Request Limit (AERL). Indicates the maximum number
83 * of concurrently outstanding Asynchronous Event Request commands support
84 * by the controller. This is a 0's based value.
85 *
86 * - `aer_max_queued`
87 * This is the maximum number of events that the device will enqueue for
88 * completion when there are no outstanding AERs. When the maximum number of
89 * enqueued events are reached, subsequent events will be dropped.
90 *
91 * - `mdts`
92 * Indicates the maximum data transfer size for a command that transfers data
93 * between host-accessible memory and the controller. The value is specified
94 * as a power of two (2^n) and is in units of the minimum memory page size
95 * (CAP.MPSMIN). The default value is 7 (i.e. 512 KiB).
96 *
97 * - `vsl`
98 * Indicates the maximum data size limit for the Verify command. Like `mdts`,
99 * this value is specified as a power of two (2^n) and is in units of the
100 * minimum memory page size (CAP.MPSMIN). The default value is 7 (i.e. 512
101 * KiB).
102 *
103 * - `zoned.zasl`
104 * Indicates the maximum data transfer size for the Zone Append command. Like
105 * `mdts`, the value is specified as a power of two (2^n) and is in units of
106 * the minimum memory page size (CAP.MPSMIN). The default value is 0 (i.e.
107 * defaulting to the value of `mdts`).
108 *
109 * - `zoned.auto_transition`
110 * Indicates if zones in zone state implicitly opened can be automatically
111 * transitioned to zone state closed for resource management purposes.
112 * Defaults to 'on'.
113 *
114 * - `sriov_max_vfs`
115 * Indicates the maximum number of PCIe virtual functions supported
116 * by the controller. The default value is 0. Specifying a non-zero value
117 * enables reporting of both SR-IOV and ARI capabilities by the NVMe device.
118 * Virtual function controllers will not report SR-IOV capability.
119 *
120 * NOTE: Single Root I/O Virtualization support is experimental.
121 * All the related parameters may be subject to change.
122 *
123 * - `sriov_vq_flexible`
124 * Indicates the total number of flexible queue resources assignable to all
125 * the secondary controllers. Implicitly sets the number of primary
126 * controller's private resources to `(max_ioqpairs - sriov_vq_flexible)`.
127 *
128 * - `sriov_vi_flexible`
129 * Indicates the total number of flexible interrupt resources assignable to
130 * all the secondary controllers. Implicitly sets the number of primary
131 * controller's private resources to `(msix_qsize - sriov_vi_flexible)`.
132 *
133 * - `sriov_max_vi_per_vf`
134 * Indicates the maximum number of virtual interrupt resources assignable
135 * to a secondary controller. The default 0 resolves to
136 * `(sriov_vi_flexible / sriov_max_vfs)`.
137 *
138 * - `sriov_max_vq_per_vf`
139 * Indicates the maximum number of virtual queue resources assignable to
140 * a secondary controller. The default 0 resolves to
141 * `(sriov_vq_flexible / sriov_max_vfs)`.
142 *
143 * nvme namespace device parameters
144 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
145 * - `shared`
146 * When the parent nvme device (as defined explicitly by the 'bus' parameter
147 * or implicitly by the most recently defined NvmeBus) is linked to an
148 * nvme-subsys device, the namespace will be attached to all controllers in
149 * the subsystem. If set to 'off' (the default), the namespace will remain a
150 * private namespace and may only be attached to a single controller at a
151 * time.
152 *
153 * - `detached`
154 * This parameter is only valid together with the `subsys` parameter. If left
155 * at the default value (`false/off`), the namespace will be attached to all
156 * controllers in the NVMe subsystem at boot-up. If set to `true/on`, the
157 * namespace will be available in the subsystem but not attached to any
158 * controllers.
159 *
160 * Setting `zoned` to true selects Zoned Command Set at the namespace.
161 * In this case, the following namespace properties are available to configure
162 * zoned operation:
163 * zoned.zone_size=<zone size in bytes, default: 128MiB>
164 * The number may be followed by K, M, G as in kilo-, mega- or giga-.
165 *
166 * zoned.zone_capacity=<zone capacity in bytes, default: zone size>
167 * The value 0 (default) forces zone capacity to be the same as zone
168 * size. The value of this property may not exceed zone size.
169 *
170 * zoned.descr_ext_size=<zone descriptor extension size, default 0>
171 * This value needs to be specified in 64B units. If it is zero,
172 * namespace(s) will not support zone descriptor extensions.
173 *
174 * zoned.max_active=<Maximum Active Resources (zones), default: 0>
175 * The default value means there is no limit to the number of
176 * concurrently active zones.
177 *
178 * zoned.max_open=<Maximum Open Resources (zones), default: 0>
179 * The default value means there is no limit to the number of
180 * concurrently open zones.
181 *
182 * zoned.cross_read=<enable RAZB, default: false>
183 * Setting this property to true enables Read Across Zone Boundaries.
184 */
185
186 #include "qemu/osdep.h"
187 #include "qemu/cutils.h"
188 #include "qemu/error-report.h"
189 #include "qemu/log.h"
190 #include "qemu/units.h"
191 #include "qemu/range.h"
192 #include "qapi/error.h"
193 #include "qapi/visitor.h"
194 #include "sysemu/sysemu.h"
195 #include "sysemu/block-backend.h"
196 #include "sysemu/hostmem.h"
197 #include "hw/pci/msix.h"
198 #include "hw/pci/pcie_sriov.h"
199 #include "migration/vmstate.h"
200
201 #include "nvme.h"
202 #include "dif.h"
203 #include "trace.h"
204
205 #define NVME_MAX_IOQPAIRS 0xffff
206 #define NVME_DB_SIZE 4
207 #define NVME_SPEC_VER 0x00010400
208 #define NVME_CMB_BIR 2
209 #define NVME_PMR_BIR 4
210 #define NVME_TEMPERATURE 0x143
211 #define NVME_TEMPERATURE_WARNING 0x157
212 #define NVME_TEMPERATURE_CRITICAL 0x175
213 #define NVME_NUM_FW_SLOTS 1
214 #define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB)
215 #define NVME_MAX_VFS 127
216 #define NVME_VF_RES_GRANULARITY 1
217 #define NVME_VF_OFFSET 0x1
218 #define NVME_VF_STRIDE 1
219
220 #define NVME_GUEST_ERR(trace, fmt, ...) \
221 do { \
222 (trace_##trace)(__VA_ARGS__); \
223 qemu_log_mask(LOG_GUEST_ERROR, #trace \
224 " in %s: " fmt "\n", __func__, ## __VA_ARGS__); \
225 } while (0)
226
227 static const bool nvme_feature_support[NVME_FID_MAX] = {
228 [NVME_ARBITRATION] = true,
229 [NVME_POWER_MANAGEMENT] = true,
230 [NVME_TEMPERATURE_THRESHOLD] = true,
231 [NVME_ERROR_RECOVERY] = true,
232 [NVME_VOLATILE_WRITE_CACHE] = true,
233 [NVME_NUMBER_OF_QUEUES] = true,
234 [NVME_INTERRUPT_COALESCING] = true,
235 [NVME_INTERRUPT_VECTOR_CONF] = true,
236 [NVME_WRITE_ATOMICITY] = true,
237 [NVME_ASYNCHRONOUS_EVENT_CONF] = true,
238 [NVME_TIMESTAMP] = true,
239 [NVME_HOST_BEHAVIOR_SUPPORT] = true,
240 [NVME_COMMAND_SET_PROFILE] = true,
241 };
242
243 static const uint32_t nvme_feature_cap[NVME_FID_MAX] = {
244 [NVME_TEMPERATURE_THRESHOLD] = NVME_FEAT_CAP_CHANGE,
245 [NVME_ERROR_RECOVERY] = NVME_FEAT_CAP_CHANGE | NVME_FEAT_CAP_NS,
246 [NVME_VOLATILE_WRITE_CACHE] = NVME_FEAT_CAP_CHANGE,
247 [NVME_NUMBER_OF_QUEUES] = NVME_FEAT_CAP_CHANGE,
248 [NVME_ASYNCHRONOUS_EVENT_CONF] = NVME_FEAT_CAP_CHANGE,
249 [NVME_TIMESTAMP] = NVME_FEAT_CAP_CHANGE,
250 [NVME_HOST_BEHAVIOR_SUPPORT] = NVME_FEAT_CAP_CHANGE,
251 [NVME_COMMAND_SET_PROFILE] = NVME_FEAT_CAP_CHANGE,
252 };
253
254 static const uint32_t nvme_cse_acs[256] = {
255 [NVME_ADM_CMD_DELETE_SQ] = NVME_CMD_EFF_CSUPP,
256 [NVME_ADM_CMD_CREATE_SQ] = NVME_CMD_EFF_CSUPP,
257 [NVME_ADM_CMD_GET_LOG_PAGE] = NVME_CMD_EFF_CSUPP,
258 [NVME_ADM_CMD_DELETE_CQ] = NVME_CMD_EFF_CSUPP,
259 [NVME_ADM_CMD_CREATE_CQ] = NVME_CMD_EFF_CSUPP,
260 [NVME_ADM_CMD_IDENTIFY] = NVME_CMD_EFF_CSUPP,
261 [NVME_ADM_CMD_ABORT] = NVME_CMD_EFF_CSUPP,
262 [NVME_ADM_CMD_SET_FEATURES] = NVME_CMD_EFF_CSUPP,
263 [NVME_ADM_CMD_GET_FEATURES] = NVME_CMD_EFF_CSUPP,
264 [NVME_ADM_CMD_ASYNC_EV_REQ] = NVME_CMD_EFF_CSUPP,
265 [NVME_ADM_CMD_NS_ATTACHMENT] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_NIC,
266 [NVME_ADM_CMD_VIRT_MNGMT] = NVME_CMD_EFF_CSUPP,
267 [NVME_ADM_CMD_DBBUF_CONFIG] = NVME_CMD_EFF_CSUPP,
268 [NVME_ADM_CMD_FORMAT_NVM] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
269 };
270
271 static const uint32_t nvme_cse_iocs_none[256];
272
273 static const uint32_t nvme_cse_iocs_nvm[256] = {
274 [NVME_CMD_FLUSH] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
275 [NVME_CMD_WRITE_ZEROES] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
276 [NVME_CMD_WRITE] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
277 [NVME_CMD_READ] = NVME_CMD_EFF_CSUPP,
278 [NVME_CMD_DSM] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
279 [NVME_CMD_VERIFY] = NVME_CMD_EFF_CSUPP,
280 [NVME_CMD_COPY] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
281 [NVME_CMD_COMPARE] = NVME_CMD_EFF_CSUPP,
282 };
283
284 static const uint32_t nvme_cse_iocs_zoned[256] = {
285 [NVME_CMD_FLUSH] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
286 [NVME_CMD_WRITE_ZEROES] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
287 [NVME_CMD_WRITE] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
288 [NVME_CMD_READ] = NVME_CMD_EFF_CSUPP,
289 [NVME_CMD_DSM] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
290 [NVME_CMD_VERIFY] = NVME_CMD_EFF_CSUPP,
291 [NVME_CMD_COPY] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
292 [NVME_CMD_COMPARE] = NVME_CMD_EFF_CSUPP,
293 [NVME_CMD_ZONE_APPEND] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
294 [NVME_CMD_ZONE_MGMT_SEND] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
295 [NVME_CMD_ZONE_MGMT_RECV] = NVME_CMD_EFF_CSUPP,
296 };
297
298 static void nvme_process_sq(void *opaque);
299 static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst);
300
301 static uint16_t nvme_sqid(NvmeRequest *req)
302 {
303 return le16_to_cpu(req->sq->sqid);
304 }
305
306 static void nvme_assign_zone_state(NvmeNamespace *ns, NvmeZone *zone,
307 NvmeZoneState state)
308 {
309 if (QTAILQ_IN_USE(zone, entry)) {
310 switch (nvme_get_zone_state(zone)) {
311 case NVME_ZONE_STATE_EXPLICITLY_OPEN:
312 QTAILQ_REMOVE(&ns->exp_open_zones, zone, entry);
313 break;
314 case NVME_ZONE_STATE_IMPLICITLY_OPEN:
315 QTAILQ_REMOVE(&ns->imp_open_zones, zone, entry);
316 break;
317 case NVME_ZONE_STATE_CLOSED:
318 QTAILQ_REMOVE(&ns->closed_zones, zone, entry);
319 break;
320 case NVME_ZONE_STATE_FULL:
321 QTAILQ_REMOVE(&ns->full_zones, zone, entry);
322 default:
323 ;
324 }
325 }
326
327 nvme_set_zone_state(zone, state);
328
329 switch (state) {
330 case NVME_ZONE_STATE_EXPLICITLY_OPEN:
331 QTAILQ_INSERT_TAIL(&ns->exp_open_zones, zone, entry);
332 break;
333 case NVME_ZONE_STATE_IMPLICITLY_OPEN:
334 QTAILQ_INSERT_TAIL(&ns->imp_open_zones, zone, entry);
335 break;
336 case NVME_ZONE_STATE_CLOSED:
337 QTAILQ_INSERT_TAIL(&ns->closed_zones, zone, entry);
338 break;
339 case NVME_ZONE_STATE_FULL:
340 QTAILQ_INSERT_TAIL(&ns->full_zones, zone, entry);
341 case NVME_ZONE_STATE_READ_ONLY:
342 break;
343 default:
344 zone->d.za = 0;
345 }
346 }
347
348 static uint16_t nvme_zns_check_resources(NvmeNamespace *ns, uint32_t act,
349 uint32_t opn, uint32_t zrwa)
350 {
351 if (ns->params.max_active_zones != 0 &&
352 ns->nr_active_zones + act > ns->params.max_active_zones) {
353 trace_pci_nvme_err_insuff_active_res(ns->params.max_active_zones);
354 return NVME_ZONE_TOO_MANY_ACTIVE | NVME_DNR;
355 }
356
357 if (ns->params.max_open_zones != 0 &&
358 ns->nr_open_zones + opn > ns->params.max_open_zones) {
359 trace_pci_nvme_err_insuff_open_res(ns->params.max_open_zones);
360 return NVME_ZONE_TOO_MANY_OPEN | NVME_DNR;
361 }
362
363 if (zrwa > ns->zns.numzrwa) {
364 return NVME_NOZRWA | NVME_DNR;
365 }
366
367 return NVME_SUCCESS;
368 }
369
370 /*
371 * Check if we can open a zone without exceeding open/active limits.
372 * AOR stands for "Active and Open Resources" (see TP 4053 section 2.5).
373 */
374 static uint16_t nvme_aor_check(NvmeNamespace *ns, uint32_t act, uint32_t opn)
375 {
376 return nvme_zns_check_resources(ns, act, opn, 0);
377 }
378
379 static bool nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr)
380 {
381 hwaddr hi, lo;
382
383 if (!n->cmb.cmse) {
384 return false;
385 }
386
387 lo = n->params.legacy_cmb ? n->cmb.mem.addr : n->cmb.cba;
388 hi = lo + int128_get64(n->cmb.mem.size);
389
390 return addr >= lo && addr < hi;
391 }
392
393 static inline void *nvme_addr_to_cmb(NvmeCtrl *n, hwaddr addr)
394 {
395 hwaddr base = n->params.legacy_cmb ? n->cmb.mem.addr : n->cmb.cba;
396 return &n->cmb.buf[addr - base];
397 }
398
399 static bool nvme_addr_is_pmr(NvmeCtrl *n, hwaddr addr)
400 {
401 hwaddr hi;
402
403 if (!n->pmr.cmse) {
404 return false;
405 }
406
407 hi = n->pmr.cba + int128_get64(n->pmr.dev->mr.size);
408
409 return addr >= n->pmr.cba && addr < hi;
410 }
411
412 static inline void *nvme_addr_to_pmr(NvmeCtrl *n, hwaddr addr)
413 {
414 return memory_region_get_ram_ptr(&n->pmr.dev->mr) + (addr - n->pmr.cba);
415 }
416
417 static inline bool nvme_addr_is_iomem(NvmeCtrl *n, hwaddr addr)
418 {
419 hwaddr hi, lo;
420
421 /*
422 * The purpose of this check is to guard against invalid "local" access to
423 * the iomem (i.e. controller registers). Thus, we check against the range
424 * covered by the 'bar0' MemoryRegion since that is currently composed of
425 * two subregions (the NVMe "MBAR" and the MSI-X table/pba). Note, however,
426 * that if the device model is ever changed to allow the CMB to be located
427 * in BAR0 as well, then this must be changed.
428 */
429 lo = n->bar0.addr;
430 hi = lo + int128_get64(n->bar0.size);
431
432 return addr >= lo && addr < hi;
433 }
434
435 static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
436 {
437 hwaddr hi = addr + size - 1;
438 if (hi < addr) {
439 return 1;
440 }
441
442 if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr) && nvme_addr_is_cmb(n, hi)) {
443 memcpy(buf, nvme_addr_to_cmb(n, addr), size);
444 return 0;
445 }
446
447 if (nvme_addr_is_pmr(n, addr) && nvme_addr_is_pmr(n, hi)) {
448 memcpy(buf, nvme_addr_to_pmr(n, addr), size);
449 return 0;
450 }
451
452 return pci_dma_read(&n->parent_obj, addr, buf, size);
453 }
454
455 static int nvme_addr_write(NvmeCtrl *n, hwaddr addr, const void *buf, int size)
456 {
457 hwaddr hi = addr + size - 1;
458 if (hi < addr) {
459 return 1;
460 }
461
462 if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr) && nvme_addr_is_cmb(n, hi)) {
463 memcpy(nvme_addr_to_cmb(n, addr), buf, size);
464 return 0;
465 }
466
467 if (nvme_addr_is_pmr(n, addr) && nvme_addr_is_pmr(n, hi)) {
468 memcpy(nvme_addr_to_pmr(n, addr), buf, size);
469 return 0;
470 }
471
472 return pci_dma_write(&n->parent_obj, addr, buf, size);
473 }
474
475 static bool nvme_nsid_valid(NvmeCtrl *n, uint32_t nsid)
476 {
477 return nsid &&
478 (nsid == NVME_NSID_BROADCAST || nsid <= NVME_MAX_NAMESPACES);
479 }
480
481 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
482 {
483 return sqid < n->conf_ioqpairs + 1 && n->sq[sqid] != NULL ? 0 : -1;
484 }
485
486 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
487 {
488 return cqid < n->conf_ioqpairs + 1 && n->cq[cqid] != NULL ? 0 : -1;
489 }
490
491 static void nvme_inc_cq_tail(NvmeCQueue *cq)
492 {
493 cq->tail++;
494 if (cq->tail >= cq->size) {
495 cq->tail = 0;
496 cq->phase = !cq->phase;
497 }
498 }
499
500 static void nvme_inc_sq_head(NvmeSQueue *sq)
501 {
502 sq->head = (sq->head + 1) % sq->size;
503 }
504
505 static uint8_t nvme_cq_full(NvmeCQueue *cq)
506 {
507 return (cq->tail + 1) % cq->size == cq->head;
508 }
509
510 static uint8_t nvme_sq_empty(NvmeSQueue *sq)
511 {
512 return sq->head == sq->tail;
513 }
514
515 static void nvme_irq_check(NvmeCtrl *n)
516 {
517 uint32_t intms = ldl_le_p(&n->bar.intms);
518
519 if (msix_enabled(&(n->parent_obj))) {
520 return;
521 }
522 if (~intms & n->irq_status) {
523 pci_irq_assert(&n->parent_obj);
524 } else {
525 pci_irq_deassert(&n->parent_obj);
526 }
527 }
528
529 static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq)
530 {
531 if (cq->irq_enabled) {
532 if (msix_enabled(&(n->parent_obj))) {
533 trace_pci_nvme_irq_msix(cq->vector);
534 msix_notify(&(n->parent_obj), cq->vector);
535 } else {
536 trace_pci_nvme_irq_pin();
537 assert(cq->vector < 32);
538 n->irq_status |= 1 << cq->vector;
539 nvme_irq_check(n);
540 }
541 } else {
542 trace_pci_nvme_irq_masked();
543 }
544 }
545
546 static void nvme_irq_deassert(NvmeCtrl *n, NvmeCQueue *cq)
547 {
548 if (cq->irq_enabled) {
549 if (msix_enabled(&(n->parent_obj))) {
550 return;
551 } else {
552 assert(cq->vector < 32);
553 if (!n->cq_pending) {
554 n->irq_status &= ~(1 << cq->vector);
555 }
556 nvme_irq_check(n);
557 }
558 }
559 }
560
561 static void nvme_req_clear(NvmeRequest *req)
562 {
563 req->ns = NULL;
564 req->opaque = NULL;
565 req->aiocb = NULL;
566 memset(&req->cqe, 0x0, sizeof(req->cqe));
567 req->status = NVME_SUCCESS;
568 }
569
570 static inline void nvme_sg_init(NvmeCtrl *n, NvmeSg *sg, bool dma)
571 {
572 if (dma) {
573 pci_dma_sglist_init(&sg->qsg, &n->parent_obj, 0);
574 sg->flags = NVME_SG_DMA;
575 } else {
576 qemu_iovec_init(&sg->iov, 0);
577 }
578
579 sg->flags |= NVME_SG_ALLOC;
580 }
581
582 static inline void nvme_sg_unmap(NvmeSg *sg)
583 {
584 if (!(sg->flags & NVME_SG_ALLOC)) {
585 return;
586 }
587
588 if (sg->flags & NVME_SG_DMA) {
589 qemu_sglist_destroy(&sg->qsg);
590 } else {
591 qemu_iovec_destroy(&sg->iov);
592 }
593
594 memset(sg, 0x0, sizeof(*sg));
595 }
596
597 /*
598 * When metadata is transfered as extended LBAs, the DPTR mapped into `sg`
599 * holds both data and metadata. This function splits the data and metadata
600 * into two separate QSG/IOVs.
601 */
602 static void nvme_sg_split(NvmeSg *sg, NvmeNamespace *ns, NvmeSg *data,
603 NvmeSg *mdata)
604 {
605 NvmeSg *dst = data;
606 uint32_t trans_len, count = ns->lbasz;
607 uint64_t offset = 0;
608 bool dma = sg->flags & NVME_SG_DMA;
609 size_t sge_len;
610 size_t sg_len = dma ? sg->qsg.size : sg->iov.size;
611 int sg_idx = 0;
612
613 assert(sg->flags & NVME_SG_ALLOC);
614
615 while (sg_len) {
616 sge_len = dma ? sg->qsg.sg[sg_idx].len : sg->iov.iov[sg_idx].iov_len;
617
618 trans_len = MIN(sg_len, count);
619 trans_len = MIN(trans_len, sge_len - offset);
620
621 if (dst) {
622 if (dma) {
623 qemu_sglist_add(&dst->qsg, sg->qsg.sg[sg_idx].base + offset,
624 trans_len);
625 } else {
626 qemu_iovec_add(&dst->iov,
627 sg->iov.iov[sg_idx].iov_base + offset,
628 trans_len);
629 }
630 }
631
632 sg_len -= trans_len;
633 count -= trans_len;
634 offset += trans_len;
635
636 if (count == 0) {
637 dst = (dst == data) ? mdata : data;
638 count = (dst == data) ? ns->lbasz : ns->lbaf.ms;
639 }
640
641 if (sge_len == offset) {
642 offset = 0;
643 sg_idx++;
644 }
645 }
646 }
647
648 static uint16_t nvme_map_addr_cmb(NvmeCtrl *n, QEMUIOVector *iov, hwaddr addr,
649 size_t len)
650 {
651 if (!len) {
652 return NVME_SUCCESS;
653 }
654
655 trace_pci_nvme_map_addr_cmb(addr, len);
656
657 if (!nvme_addr_is_cmb(n, addr) || !nvme_addr_is_cmb(n, addr + len - 1)) {
658 return NVME_DATA_TRAS_ERROR;
659 }
660
661 qemu_iovec_add(iov, nvme_addr_to_cmb(n, addr), len);
662
663 return NVME_SUCCESS;
664 }
665
666 static uint16_t nvme_map_addr_pmr(NvmeCtrl *n, QEMUIOVector *iov, hwaddr addr,
667 size_t len)
668 {
669 if (!len) {
670 return NVME_SUCCESS;
671 }
672
673 if (!nvme_addr_is_pmr(n, addr) || !nvme_addr_is_pmr(n, addr + len - 1)) {
674 return NVME_DATA_TRAS_ERROR;
675 }
676
677 qemu_iovec_add(iov, nvme_addr_to_pmr(n, addr), len);
678
679 return NVME_SUCCESS;
680 }
681
682 static uint16_t nvme_map_addr(NvmeCtrl *n, NvmeSg *sg, hwaddr addr, size_t len)
683 {
684 bool cmb = false, pmr = false;
685
686 if (!len) {
687 return NVME_SUCCESS;
688 }
689
690 trace_pci_nvme_map_addr(addr, len);
691
692 if (nvme_addr_is_iomem(n, addr)) {
693 return NVME_DATA_TRAS_ERROR;
694 }
695
696 if (nvme_addr_is_cmb(n, addr)) {
697 cmb = true;
698 } else if (nvme_addr_is_pmr(n, addr)) {
699 pmr = true;
700 }
701
702 if (cmb || pmr) {
703 if (sg->flags & NVME_SG_DMA) {
704 return NVME_INVALID_USE_OF_CMB | NVME_DNR;
705 }
706
707 if (sg->iov.niov + 1 > IOV_MAX) {
708 goto max_mappings_exceeded;
709 }
710
711 if (cmb) {
712 return nvme_map_addr_cmb(n, &sg->iov, addr, len);
713 } else {
714 return nvme_map_addr_pmr(n, &sg->iov, addr, len);
715 }
716 }
717
718 if (!(sg->flags & NVME_SG_DMA)) {
719 return NVME_INVALID_USE_OF_CMB | NVME_DNR;
720 }
721
722 if (sg->qsg.nsg + 1 > IOV_MAX) {
723 goto max_mappings_exceeded;
724 }
725
726 qemu_sglist_add(&sg->qsg, addr, len);
727
728 return NVME_SUCCESS;
729
730 max_mappings_exceeded:
731 NVME_GUEST_ERR(pci_nvme_ub_too_many_mappings,
732 "number of mappings exceed 1024");
733 return NVME_INTERNAL_DEV_ERROR | NVME_DNR;
734 }
735
736 static inline bool nvme_addr_is_dma(NvmeCtrl *n, hwaddr addr)
737 {
738 return !(nvme_addr_is_cmb(n, addr) || nvme_addr_is_pmr(n, addr));
739 }
740
741 static uint16_t nvme_map_prp(NvmeCtrl *n, NvmeSg *sg, uint64_t prp1,
742 uint64_t prp2, uint32_t len)
743 {
744 hwaddr trans_len = n->page_size - (prp1 % n->page_size);
745 trans_len = MIN(len, trans_len);
746 int num_prps = (len >> n->page_bits) + 1;
747 uint16_t status;
748 int ret;
749
750 trace_pci_nvme_map_prp(trans_len, len, prp1, prp2, num_prps);
751
752 nvme_sg_init(n, sg, nvme_addr_is_dma(n, prp1));
753
754 status = nvme_map_addr(n, sg, prp1, trans_len);
755 if (status) {
756 goto unmap;
757 }
758
759 len -= trans_len;
760 if (len) {
761 if (len > n->page_size) {
762 uint64_t prp_list[n->max_prp_ents];
763 uint32_t nents, prp_trans;
764 int i = 0;
765
766 /*
767 * The first PRP list entry, pointed to by PRP2 may contain offset.
768 * Hence, we need to calculate the number of entries in based on
769 * that offset.
770 */
771 nents = (n->page_size - (prp2 & (n->page_size - 1))) >> 3;
772 prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
773 ret = nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
774 if (ret) {
775 trace_pci_nvme_err_addr_read(prp2);
776 status = NVME_DATA_TRAS_ERROR;
777 goto unmap;
778 }
779 while (len != 0) {
780 uint64_t prp_ent = le64_to_cpu(prp_list[i]);
781
782 if (i == nents - 1 && len > n->page_size) {
783 if (unlikely(prp_ent & (n->page_size - 1))) {
784 trace_pci_nvme_err_invalid_prplist_ent(prp_ent);
785 status = NVME_INVALID_PRP_OFFSET | NVME_DNR;
786 goto unmap;
787 }
788
789 i = 0;
790 nents = (len + n->page_size - 1) >> n->page_bits;
791 nents = MIN(nents, n->max_prp_ents);
792 prp_trans = nents * sizeof(uint64_t);
793 ret = nvme_addr_read(n, prp_ent, (void *)prp_list,
794 prp_trans);
795 if (ret) {
796 trace_pci_nvme_err_addr_read(prp_ent);
797 status = NVME_DATA_TRAS_ERROR;
798 goto unmap;
799 }
800 prp_ent = le64_to_cpu(prp_list[i]);
801 }
802
803 if (unlikely(prp_ent & (n->page_size - 1))) {
804 trace_pci_nvme_err_invalid_prplist_ent(prp_ent);
805 status = NVME_INVALID_PRP_OFFSET | NVME_DNR;
806 goto unmap;
807 }
808
809 trans_len = MIN(len, n->page_size);
810 status = nvme_map_addr(n, sg, prp_ent, trans_len);
811 if (status) {
812 goto unmap;
813 }
814
815 len -= trans_len;
816 i++;
817 }
818 } else {
819 if (unlikely(prp2 & (n->page_size - 1))) {
820 trace_pci_nvme_err_invalid_prp2_align(prp2);
821 status = NVME_INVALID_PRP_OFFSET | NVME_DNR;
822 goto unmap;
823 }
824 status = nvme_map_addr(n, sg, prp2, len);
825 if (status) {
826 goto unmap;
827 }
828 }
829 }
830
831 return NVME_SUCCESS;
832
833 unmap:
834 nvme_sg_unmap(sg);
835 return status;
836 }
837
838 /*
839 * Map 'nsgld' data descriptors from 'segment'. The function will subtract the
840 * number of bytes mapped in len.
841 */
842 static uint16_t nvme_map_sgl_data(NvmeCtrl *n, NvmeSg *sg,
843 NvmeSglDescriptor *segment, uint64_t nsgld,
844 size_t *len, NvmeCmd *cmd)
845 {
846 dma_addr_t addr, trans_len;
847 uint32_t dlen;
848 uint16_t status;
849
850 for (int i = 0; i < nsgld; i++) {
851 uint8_t type = NVME_SGL_TYPE(segment[i].type);
852
853 switch (type) {
854 case NVME_SGL_DESCR_TYPE_DATA_BLOCK:
855 break;
856 case NVME_SGL_DESCR_TYPE_SEGMENT:
857 case NVME_SGL_DESCR_TYPE_LAST_SEGMENT:
858 return NVME_INVALID_NUM_SGL_DESCRS | NVME_DNR;
859 default:
860 return NVME_SGL_DESCR_TYPE_INVALID | NVME_DNR;
861 }
862
863 dlen = le32_to_cpu(segment[i].len);
864
865 if (!dlen) {
866 continue;
867 }
868
869 if (*len == 0) {
870 /*
871 * All data has been mapped, but the SGL contains additional
872 * segments and/or descriptors. The controller might accept
873 * ignoring the rest of the SGL.
874 */
875 uint32_t sgls = le32_to_cpu(n->id_ctrl.sgls);
876 if (sgls & NVME_CTRL_SGLS_EXCESS_LENGTH) {
877 break;
878 }
879
880 trace_pci_nvme_err_invalid_sgl_excess_length(dlen);
881 return NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
882 }
883
884 trans_len = MIN(*len, dlen);
885
886 addr = le64_to_cpu(segment[i].addr);
887
888 if (UINT64_MAX - addr < dlen) {
889 return NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
890 }
891
892 status = nvme_map_addr(n, sg, addr, trans_len);
893 if (status) {
894 return status;
895 }
896
897 *len -= trans_len;
898 }
899
900 return NVME_SUCCESS;
901 }
902
903 static uint16_t nvme_map_sgl(NvmeCtrl *n, NvmeSg *sg, NvmeSglDescriptor sgl,
904 size_t len, NvmeCmd *cmd)
905 {
906 /*
907 * Read the segment in chunks of 256 descriptors (one 4k page) to avoid
908 * dynamically allocating a potentially huge SGL. The spec allows the SGL
909 * to be larger (as in number of bytes required to describe the SGL
910 * descriptors and segment chain) than the command transfer size, so it is
911 * not bounded by MDTS.
912 */
913 const int SEG_CHUNK_SIZE = 256;
914
915 NvmeSglDescriptor segment[SEG_CHUNK_SIZE], *sgld, *last_sgld;
916 uint64_t nsgld;
917 uint32_t seg_len;
918 uint16_t status;
919 hwaddr addr;
920 int ret;
921
922 sgld = &sgl;
923 addr = le64_to_cpu(sgl.addr);
924
925 trace_pci_nvme_map_sgl(NVME_SGL_TYPE(sgl.type), len);
926
927 nvme_sg_init(n, sg, nvme_addr_is_dma(n, addr));
928
929 /*
930 * If the entire transfer can be described with a single data block it can
931 * be mapped directly.
932 */
933 if (NVME_SGL_TYPE(sgl.type) == NVME_SGL_DESCR_TYPE_DATA_BLOCK) {
934 status = nvme_map_sgl_data(n, sg, sgld, 1, &len, cmd);
935 if (status) {
936 goto unmap;
937 }
938
939 goto out;
940 }
941
942 for (;;) {
943 switch (NVME_SGL_TYPE(sgld->type)) {
944 case NVME_SGL_DESCR_TYPE_SEGMENT:
945 case NVME_SGL_DESCR_TYPE_LAST_SEGMENT:
946 break;
947 default:
948 return NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
949 }
950
951 seg_len = le32_to_cpu(sgld->len);
952
953 /* check the length of the (Last) Segment descriptor */
954 if (!seg_len || seg_len & 0xf) {
955 return NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
956 }
957
958 if (UINT64_MAX - addr < seg_len) {
959 return NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
960 }
961
962 nsgld = seg_len / sizeof(NvmeSglDescriptor);
963
964 while (nsgld > SEG_CHUNK_SIZE) {
965 if (nvme_addr_read(n, addr, segment, sizeof(segment))) {
966 trace_pci_nvme_err_addr_read(addr);
967 status = NVME_DATA_TRAS_ERROR;
968 goto unmap;
969 }
970
971 status = nvme_map_sgl_data(n, sg, segment, SEG_CHUNK_SIZE,
972 &len, cmd);
973 if (status) {
974 goto unmap;
975 }
976
977 nsgld -= SEG_CHUNK_SIZE;
978 addr += SEG_CHUNK_SIZE * sizeof(NvmeSglDescriptor);
979 }
980
981 ret = nvme_addr_read(n, addr, segment, nsgld *
982 sizeof(NvmeSglDescriptor));
983 if (ret) {
984 trace_pci_nvme_err_addr_read(addr);
985 status = NVME_DATA_TRAS_ERROR;
986 goto unmap;
987 }
988
989 last_sgld = &segment[nsgld - 1];
990
991 /*
992 * If the segment ends with a Data Block, then we are done.
993 */
994 if (NVME_SGL_TYPE(last_sgld->type) == NVME_SGL_DESCR_TYPE_DATA_BLOCK) {
995 status = nvme_map_sgl_data(n, sg, segment, nsgld, &len, cmd);
996 if (status) {
997 goto unmap;
998 }
999
1000 goto out;
1001 }
1002
1003 /*
1004 * If the last descriptor was not a Data Block, then the current
1005 * segment must not be a Last Segment.
1006 */
1007 if (NVME_SGL_TYPE(sgld->type) == NVME_SGL_DESCR_TYPE_LAST_SEGMENT) {
1008 status = NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
1009 goto unmap;
1010 }
1011
1012 sgld = last_sgld;
1013 addr = le64_to_cpu(sgld->addr);
1014
1015 /*
1016 * Do not map the last descriptor; it will be a Segment or Last Segment
1017 * descriptor and is handled by the next iteration.
1018 */
1019 status = nvme_map_sgl_data(n, sg, segment, nsgld - 1, &len, cmd);
1020 if (status) {
1021 goto unmap;
1022 }
1023 }
1024
1025 out:
1026 /* if there is any residual left in len, the SGL was too short */
1027 if (len) {
1028 status = NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
1029 goto unmap;
1030 }
1031
1032 return NVME_SUCCESS;
1033
1034 unmap:
1035 nvme_sg_unmap(sg);
1036 return status;
1037 }
1038
1039 uint16_t nvme_map_dptr(NvmeCtrl *n, NvmeSg *sg, size_t len,
1040 NvmeCmd *cmd)
1041 {
1042 uint64_t prp1, prp2;
1043
1044 switch (NVME_CMD_FLAGS_PSDT(cmd->flags)) {
1045 case NVME_PSDT_PRP:
1046 prp1 = le64_to_cpu(cmd->dptr.prp1);
1047 prp2 = le64_to_cpu(cmd->dptr.prp2);
1048
1049 return nvme_map_prp(n, sg, prp1, prp2, len);
1050 case NVME_PSDT_SGL_MPTR_CONTIGUOUS:
1051 case NVME_PSDT_SGL_MPTR_SGL:
1052 return nvme_map_sgl(n, sg, cmd->dptr.sgl, len, cmd);
1053 default:
1054 return NVME_INVALID_FIELD;
1055 }
1056 }
1057
1058 static uint16_t nvme_map_mptr(NvmeCtrl *n, NvmeSg *sg, size_t len,
1059 NvmeCmd *cmd)
1060 {
1061 int psdt = NVME_CMD_FLAGS_PSDT(cmd->flags);
1062 hwaddr mptr = le64_to_cpu(cmd->mptr);
1063 uint16_t status;
1064
1065 if (psdt == NVME_PSDT_SGL_MPTR_SGL) {
1066 NvmeSglDescriptor sgl;
1067
1068 if (nvme_addr_read(n, mptr, &sgl, sizeof(sgl))) {
1069 return NVME_DATA_TRAS_ERROR;
1070 }
1071
1072 status = nvme_map_sgl(n, sg, sgl, len, cmd);
1073 if (status && (status & 0x7ff) == NVME_DATA_SGL_LEN_INVALID) {
1074 status = NVME_MD_SGL_LEN_INVALID | NVME_DNR;
1075 }
1076
1077 return status;
1078 }
1079
1080 nvme_sg_init(n, sg, nvme_addr_is_dma(n, mptr));
1081 status = nvme_map_addr(n, sg, mptr, len);
1082 if (status) {
1083 nvme_sg_unmap(sg);
1084 }
1085
1086 return status;
1087 }
1088
1089 static uint16_t nvme_map_data(NvmeCtrl *n, uint32_t nlb, NvmeRequest *req)
1090 {
1091 NvmeNamespace *ns = req->ns;
1092 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
1093 bool pi = !!NVME_ID_NS_DPS_TYPE(ns->id_ns.dps);
1094 bool pract = !!(le16_to_cpu(rw->control) & NVME_RW_PRINFO_PRACT);
1095 size_t len = nvme_l2b(ns, nlb);
1096 uint16_t status;
1097
1098 if (nvme_ns_ext(ns) &&
1099 !(pi && pract && ns->lbaf.ms == nvme_pi_tuple_size(ns))) {
1100 NvmeSg sg;
1101
1102 len += nvme_m2b(ns, nlb);
1103
1104 status = nvme_map_dptr(n, &sg, len, &req->cmd);
1105 if (status) {
1106 return status;
1107 }
1108
1109 nvme_sg_init(n, &req->sg, sg.flags & NVME_SG_DMA);
1110 nvme_sg_split(&sg, ns, &req->sg, NULL);
1111 nvme_sg_unmap(&sg);
1112
1113 return NVME_SUCCESS;
1114 }
1115
1116 return nvme_map_dptr(n, &req->sg, len, &req->cmd);
1117 }
1118
1119 static uint16_t nvme_map_mdata(NvmeCtrl *n, uint32_t nlb, NvmeRequest *req)
1120 {
1121 NvmeNamespace *ns = req->ns;
1122 size_t len = nvme_m2b(ns, nlb);
1123 uint16_t status;
1124
1125 if (nvme_ns_ext(ns)) {
1126 NvmeSg sg;
1127
1128 len += nvme_l2b(ns, nlb);
1129
1130 status = nvme_map_dptr(n, &sg, len, &req->cmd);
1131 if (status) {
1132 return status;
1133 }
1134
1135 nvme_sg_init(n, &req->sg, sg.flags & NVME_SG_DMA);
1136 nvme_sg_split(&sg, ns, NULL, &req->sg);
1137 nvme_sg_unmap(&sg);
1138
1139 return NVME_SUCCESS;
1140 }
1141
1142 return nvme_map_mptr(n, &req->sg, len, &req->cmd);
1143 }
1144
1145 static uint16_t nvme_tx_interleaved(NvmeCtrl *n, NvmeSg *sg, uint8_t *ptr,
1146 uint32_t len, uint32_t bytes,
1147 int32_t skip_bytes, int64_t offset,
1148 NvmeTxDirection dir)
1149 {
1150 hwaddr addr;
1151 uint32_t trans_len, count = bytes;
1152 bool dma = sg->flags & NVME_SG_DMA;
1153 int64_t sge_len;
1154 int sg_idx = 0;
1155 int ret;
1156
1157 assert(sg->flags & NVME_SG_ALLOC);
1158
1159 while (len) {
1160 sge_len = dma ? sg->qsg.sg[sg_idx].len : sg->iov.iov[sg_idx].iov_len;
1161
1162 if (sge_len - offset < 0) {
1163 offset -= sge_len;
1164 sg_idx++;
1165 continue;
1166 }
1167
1168 if (sge_len == offset) {
1169 offset = 0;
1170 sg_idx++;
1171 continue;
1172 }
1173
1174 trans_len = MIN(len, count);
1175 trans_len = MIN(trans_len, sge_len - offset);
1176
1177 if (dma) {
1178 addr = sg->qsg.sg[sg_idx].base + offset;
1179 } else {
1180 addr = (hwaddr)(uintptr_t)sg->iov.iov[sg_idx].iov_base + offset;
1181 }
1182
1183 if (dir == NVME_TX_DIRECTION_TO_DEVICE) {
1184 ret = nvme_addr_read(n, addr, ptr, trans_len);
1185 } else {
1186 ret = nvme_addr_write(n, addr, ptr, trans_len);
1187 }
1188
1189 if (ret) {
1190 return NVME_DATA_TRAS_ERROR;
1191 }
1192
1193 ptr += trans_len;
1194 len -= trans_len;
1195 count -= trans_len;
1196 offset += trans_len;
1197
1198 if (count == 0) {
1199 count = bytes;
1200 offset += skip_bytes;
1201 }
1202 }
1203
1204 return NVME_SUCCESS;
1205 }
1206
1207 static uint16_t nvme_tx(NvmeCtrl *n, NvmeSg *sg, void *ptr, uint32_t len,
1208 NvmeTxDirection dir)
1209 {
1210 assert(sg->flags & NVME_SG_ALLOC);
1211
1212 if (sg->flags & NVME_SG_DMA) {
1213 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
1214 dma_addr_t residual;
1215
1216 if (dir == NVME_TX_DIRECTION_TO_DEVICE) {
1217 dma_buf_write(ptr, len, &residual, &sg->qsg, attrs);
1218 } else {
1219 dma_buf_read(ptr, len, &residual, &sg->qsg, attrs);
1220 }
1221
1222 if (unlikely(residual)) {
1223 trace_pci_nvme_err_invalid_dma();
1224 return NVME_INVALID_FIELD | NVME_DNR;
1225 }
1226 } else {
1227 size_t bytes;
1228
1229 if (dir == NVME_TX_DIRECTION_TO_DEVICE) {
1230 bytes = qemu_iovec_to_buf(&sg->iov, 0, ptr, len);
1231 } else {
1232 bytes = qemu_iovec_from_buf(&sg->iov, 0, ptr, len);
1233 }
1234
1235 if (unlikely(bytes != len)) {
1236 trace_pci_nvme_err_invalid_dma();
1237 return NVME_INVALID_FIELD | NVME_DNR;
1238 }
1239 }
1240
1241 return NVME_SUCCESS;
1242 }
1243
1244 static inline uint16_t nvme_c2h(NvmeCtrl *n, void *ptr, uint32_t len,
1245 NvmeRequest *req)
1246 {
1247 uint16_t status;
1248
1249 status = nvme_map_dptr(n, &req->sg, len, &req->cmd);
1250 if (status) {
1251 return status;
1252 }
1253
1254 return nvme_tx(n, &req->sg, ptr, len, NVME_TX_DIRECTION_FROM_DEVICE);
1255 }
1256
1257 static inline uint16_t nvme_h2c(NvmeCtrl *n, void *ptr, uint32_t len,
1258 NvmeRequest *req)
1259 {
1260 uint16_t status;
1261
1262 status = nvme_map_dptr(n, &req->sg, len, &req->cmd);
1263 if (status) {
1264 return status;
1265 }
1266
1267 return nvme_tx(n, &req->sg, ptr, len, NVME_TX_DIRECTION_TO_DEVICE);
1268 }
1269
1270 uint16_t nvme_bounce_data(NvmeCtrl *n, void *ptr, uint32_t len,
1271 NvmeTxDirection dir, NvmeRequest *req)
1272 {
1273 NvmeNamespace *ns = req->ns;
1274 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
1275 bool pi = !!NVME_ID_NS_DPS_TYPE(ns->id_ns.dps);
1276 bool pract = !!(le16_to_cpu(rw->control) & NVME_RW_PRINFO_PRACT);
1277
1278 if (nvme_ns_ext(ns) &&
1279 !(pi && pract && ns->lbaf.ms == nvme_pi_tuple_size(ns))) {
1280 return nvme_tx_interleaved(n, &req->sg, ptr, len, ns->lbasz,
1281 ns->lbaf.ms, 0, dir);
1282 }
1283
1284 return nvme_tx(n, &req->sg, ptr, len, dir);
1285 }
1286
1287 uint16_t nvme_bounce_mdata(NvmeCtrl *n, void *ptr, uint32_t len,
1288 NvmeTxDirection dir, NvmeRequest *req)
1289 {
1290 NvmeNamespace *ns = req->ns;
1291 uint16_t status;
1292
1293 if (nvme_ns_ext(ns)) {
1294 return nvme_tx_interleaved(n, &req->sg, ptr, len, ns->lbaf.ms,
1295 ns->lbasz, ns->lbasz, dir);
1296 }
1297
1298 nvme_sg_unmap(&req->sg);
1299
1300 status = nvme_map_mptr(n, &req->sg, len, &req->cmd);
1301 if (status) {
1302 return status;
1303 }
1304
1305 return nvme_tx(n, &req->sg, ptr, len, dir);
1306 }
1307
1308 static inline void nvme_blk_read(BlockBackend *blk, int64_t offset,
1309 BlockCompletionFunc *cb, NvmeRequest *req)
1310 {
1311 assert(req->sg.flags & NVME_SG_ALLOC);
1312
1313 if (req->sg.flags & NVME_SG_DMA) {
1314 req->aiocb = dma_blk_read(blk, &req->sg.qsg, offset, BDRV_SECTOR_SIZE,
1315 cb, req);
1316 } else {
1317 req->aiocb = blk_aio_preadv(blk, offset, &req->sg.iov, 0, cb, req);
1318 }
1319 }
1320
1321 static inline void nvme_blk_write(BlockBackend *blk, int64_t offset,
1322 BlockCompletionFunc *cb, NvmeRequest *req)
1323 {
1324 assert(req->sg.flags & NVME_SG_ALLOC);
1325
1326 if (req->sg.flags & NVME_SG_DMA) {
1327 req->aiocb = dma_blk_write(blk, &req->sg.qsg, offset, BDRV_SECTOR_SIZE,
1328 cb, req);
1329 } else {
1330 req->aiocb = blk_aio_pwritev(blk, offset, &req->sg.iov, 0, cb, req);
1331 }
1332 }
1333
1334 static void nvme_update_cq_head(NvmeCQueue *cq)
1335 {
1336 pci_dma_read(&cq->ctrl->parent_obj, cq->db_addr, &cq->head,
1337 sizeof(cq->head));
1338 trace_pci_nvme_shadow_doorbell_cq(cq->cqid, cq->head);
1339 }
1340
1341 static void nvme_post_cqes(void *opaque)
1342 {
1343 NvmeCQueue *cq = opaque;
1344 NvmeCtrl *n = cq->ctrl;
1345 NvmeRequest *req, *next;
1346 bool pending = cq->head != cq->tail;
1347 int ret;
1348
1349 QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
1350 NvmeSQueue *sq;
1351 hwaddr addr;
1352
1353 if (n->dbbuf_enabled) {
1354 nvme_update_cq_head(cq);
1355 }
1356
1357 if (nvme_cq_full(cq)) {
1358 break;
1359 }
1360
1361 sq = req->sq;
1362 req->cqe.status = cpu_to_le16((req->status << 1) | cq->phase);
1363 req->cqe.sq_id = cpu_to_le16(sq->sqid);
1364 req->cqe.sq_head = cpu_to_le16(sq->head);
1365 addr = cq->dma_addr + cq->tail * n->cqe_size;
1366 ret = pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe,
1367 sizeof(req->cqe));
1368 if (ret) {
1369 trace_pci_nvme_err_addr_write(addr);
1370 trace_pci_nvme_err_cfs();
1371 stl_le_p(&n->bar.csts, NVME_CSTS_FAILED);
1372 break;
1373 }
1374 QTAILQ_REMOVE(&cq->req_list, req, entry);
1375 nvme_inc_cq_tail(cq);
1376 nvme_sg_unmap(&req->sg);
1377 QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
1378 }
1379 if (cq->tail != cq->head) {
1380 if (cq->irq_enabled && !pending) {
1381 n->cq_pending++;
1382 }
1383
1384 nvme_irq_assert(n, cq);
1385 }
1386 }
1387
1388 static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
1389 {
1390 assert(cq->cqid == req->sq->cqid);
1391 trace_pci_nvme_enqueue_req_completion(nvme_cid(req), cq->cqid,
1392 le32_to_cpu(req->cqe.result),
1393 le32_to_cpu(req->cqe.dw1),
1394 req->status);
1395
1396 if (req->status) {
1397 trace_pci_nvme_err_req_status(nvme_cid(req), nvme_nsid(req->ns),
1398 req->status, req->cmd.opcode);
1399 }
1400
1401 QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
1402 QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
1403
1404 qemu_bh_schedule(cq->bh);
1405 }
1406
1407 static void nvme_process_aers(void *opaque)
1408 {
1409 NvmeCtrl *n = opaque;
1410 NvmeAsyncEvent *event, *next;
1411
1412 trace_pci_nvme_process_aers(n->aer_queued);
1413
1414 QTAILQ_FOREACH_SAFE(event, &n->aer_queue, entry, next) {
1415 NvmeRequest *req;
1416 NvmeAerResult *result;
1417
1418 /* can't post cqe if there is nothing to complete */
1419 if (!n->outstanding_aers) {
1420 trace_pci_nvme_no_outstanding_aers();
1421 break;
1422 }
1423
1424 /* ignore if masked (cqe posted, but event not cleared) */
1425 if (n->aer_mask & (1 << event->result.event_type)) {
1426 trace_pci_nvme_aer_masked(event->result.event_type, n->aer_mask);
1427 continue;
1428 }
1429
1430 QTAILQ_REMOVE(&n->aer_queue, event, entry);
1431 n->aer_queued--;
1432
1433 n->aer_mask |= 1 << event->result.event_type;
1434 n->outstanding_aers--;
1435
1436 req = n->aer_reqs[n->outstanding_aers];
1437
1438 result = (NvmeAerResult *) &req->cqe.result;
1439 result->event_type = event->result.event_type;
1440 result->event_info = event->result.event_info;
1441 result->log_page = event->result.log_page;
1442 g_free(event);
1443
1444 trace_pci_nvme_aer_post_cqe(result->event_type, result->event_info,
1445 result->log_page);
1446
1447 nvme_enqueue_req_completion(&n->admin_cq, req);
1448 }
1449 }
1450
1451 static void nvme_enqueue_event(NvmeCtrl *n, uint8_t event_type,
1452 uint8_t event_info, uint8_t log_page)
1453 {
1454 NvmeAsyncEvent *event;
1455
1456 trace_pci_nvme_enqueue_event(event_type, event_info, log_page);
1457
1458 if (n->aer_queued == n->params.aer_max_queued) {
1459 trace_pci_nvme_enqueue_event_noqueue(n->aer_queued);
1460 return;
1461 }
1462
1463 event = g_new(NvmeAsyncEvent, 1);
1464 event->result = (NvmeAerResult) {
1465 .event_type = event_type,
1466 .event_info = event_info,
1467 .log_page = log_page,
1468 };
1469
1470 QTAILQ_INSERT_TAIL(&n->aer_queue, event, entry);
1471 n->aer_queued++;
1472
1473 nvme_process_aers(n);
1474 }
1475
1476 static void nvme_smart_event(NvmeCtrl *n, uint8_t event)
1477 {
1478 uint8_t aer_info;
1479
1480 /* Ref SPEC <Asynchronous Event Information 0x2013 SMART / Health Status> */
1481 if (!(NVME_AEC_SMART(n->features.async_config) & event)) {
1482 return;
1483 }
1484
1485 switch (event) {
1486 case NVME_SMART_SPARE:
1487 aer_info = NVME_AER_INFO_SMART_SPARE_THRESH;
1488 break;
1489 case NVME_SMART_TEMPERATURE:
1490 aer_info = NVME_AER_INFO_SMART_TEMP_THRESH;
1491 break;
1492 case NVME_SMART_RELIABILITY:
1493 case NVME_SMART_MEDIA_READ_ONLY:
1494 case NVME_SMART_FAILED_VOLATILE_MEDIA:
1495 case NVME_SMART_PMR_UNRELIABLE:
1496 aer_info = NVME_AER_INFO_SMART_RELIABILITY;
1497 break;
1498 default:
1499 return;
1500 }
1501
1502 nvme_enqueue_event(n, NVME_AER_TYPE_SMART, aer_info, NVME_LOG_SMART_INFO);
1503 }
1504
1505 static void nvme_clear_events(NvmeCtrl *n, uint8_t event_type)
1506 {
1507 n->aer_mask &= ~(1 << event_type);
1508 if (!QTAILQ_EMPTY(&n->aer_queue)) {
1509 nvme_process_aers(n);
1510 }
1511 }
1512
1513 static inline uint16_t nvme_check_mdts(NvmeCtrl *n, size_t len)
1514 {
1515 uint8_t mdts = n->params.mdts;
1516
1517 if (mdts && len > n->page_size << mdts) {
1518 trace_pci_nvme_err_mdts(len);
1519 return NVME_INVALID_FIELD | NVME_DNR;
1520 }
1521
1522 return NVME_SUCCESS;
1523 }
1524
1525 static inline uint16_t nvme_check_bounds(NvmeNamespace *ns, uint64_t slba,
1526 uint32_t nlb)
1527 {
1528 uint64_t nsze = le64_to_cpu(ns->id_ns.nsze);
1529
1530 if (unlikely(UINT64_MAX - slba < nlb || slba + nlb > nsze)) {
1531 trace_pci_nvme_err_invalid_lba_range(slba, nlb, nsze);
1532 return NVME_LBA_RANGE | NVME_DNR;
1533 }
1534
1535 return NVME_SUCCESS;
1536 }
1537
1538 static int nvme_block_status_all(NvmeNamespace *ns, uint64_t slba,
1539 uint32_t nlb, int flags)
1540 {
1541 BlockDriverState *bs = blk_bs(ns->blkconf.blk);
1542
1543 int64_t pnum = 0, bytes = nvme_l2b(ns, nlb);
1544 int64_t offset = nvme_l2b(ns, slba);
1545 int ret;
1546
1547 /*
1548 * `pnum` holds the number of bytes after offset that shares the same
1549 * allocation status as the byte at offset. If `pnum` is different from
1550 * `bytes`, we should check the allocation status of the next range and
1551 * continue this until all bytes have been checked.
1552 */
1553 do {
1554 bytes -= pnum;
1555
1556 ret = bdrv_block_status(bs, offset, bytes, &pnum, NULL, NULL);
1557 if (ret < 0) {
1558 return ret;
1559 }
1560
1561
1562 trace_pci_nvme_block_status(offset, bytes, pnum, ret,
1563 !!(ret & BDRV_BLOCK_ZERO));
1564
1565 if (!(ret & flags)) {
1566 return 1;
1567 }
1568
1569 offset += pnum;
1570 } while (pnum != bytes);
1571
1572 return 0;
1573 }
1574
1575 static uint16_t nvme_check_dulbe(NvmeNamespace *ns, uint64_t slba,
1576 uint32_t nlb)
1577 {
1578 int ret;
1579 Error *err = NULL;
1580
1581 ret = nvme_block_status_all(ns, slba, nlb, BDRV_BLOCK_DATA);
1582 if (ret) {
1583 if (ret < 0) {
1584 error_setg_errno(&err, -ret, "unable to get block status");
1585 error_report_err(err);
1586
1587 return NVME_INTERNAL_DEV_ERROR;
1588 }
1589
1590 return NVME_DULB;
1591 }
1592
1593 return NVME_SUCCESS;
1594 }
1595
1596 static void nvme_aio_err(NvmeRequest *req, int ret)
1597 {
1598 uint16_t status = NVME_SUCCESS;
1599 Error *local_err = NULL;
1600
1601 switch (req->cmd.opcode) {
1602 case NVME_CMD_READ:
1603 status = NVME_UNRECOVERED_READ;
1604 break;
1605 case NVME_CMD_FLUSH:
1606 case NVME_CMD_WRITE:
1607 case NVME_CMD_WRITE_ZEROES:
1608 case NVME_CMD_ZONE_APPEND:
1609 status = NVME_WRITE_FAULT;
1610 break;
1611 default:
1612 status = NVME_INTERNAL_DEV_ERROR;
1613 break;
1614 }
1615
1616 trace_pci_nvme_err_aio(nvme_cid(req), strerror(-ret), status);
1617
1618 error_setg_errno(&local_err, -ret, "aio failed");
1619 error_report_err(local_err);
1620
1621 /*
1622 * Set the command status code to the first encountered error but allow a
1623 * subsequent Internal Device Error to trump it.
1624 */
1625 if (req->status && status != NVME_INTERNAL_DEV_ERROR) {
1626 return;
1627 }
1628
1629 req->status = status;
1630 }
1631
1632 static inline uint32_t nvme_zone_idx(NvmeNamespace *ns, uint64_t slba)
1633 {
1634 return ns->zone_size_log2 > 0 ? slba >> ns->zone_size_log2 :
1635 slba / ns->zone_size;
1636 }
1637
1638 static inline NvmeZone *nvme_get_zone_by_slba(NvmeNamespace *ns, uint64_t slba)
1639 {
1640 uint32_t zone_idx = nvme_zone_idx(ns, slba);
1641
1642 if (zone_idx >= ns->num_zones) {
1643 return NULL;
1644 }
1645
1646 return &ns->zone_array[zone_idx];
1647 }
1648
1649 static uint16_t nvme_check_zone_state_for_write(NvmeZone *zone)
1650 {
1651 uint64_t zslba = zone->d.zslba;
1652
1653 switch (nvme_get_zone_state(zone)) {
1654 case NVME_ZONE_STATE_EMPTY:
1655 case NVME_ZONE_STATE_IMPLICITLY_OPEN:
1656 case NVME_ZONE_STATE_EXPLICITLY_OPEN:
1657 case NVME_ZONE_STATE_CLOSED:
1658 return NVME_SUCCESS;
1659 case NVME_ZONE_STATE_FULL:
1660 trace_pci_nvme_err_zone_is_full(zslba);
1661 return NVME_ZONE_FULL;
1662 case NVME_ZONE_STATE_OFFLINE:
1663 trace_pci_nvme_err_zone_is_offline(zslba);
1664 return NVME_ZONE_OFFLINE;
1665 case NVME_ZONE_STATE_READ_ONLY:
1666 trace_pci_nvme_err_zone_is_read_only(zslba);
1667 return NVME_ZONE_READ_ONLY;
1668 default:
1669 assert(false);
1670 }
1671
1672 return NVME_INTERNAL_DEV_ERROR;
1673 }
1674
1675 static uint16_t nvme_check_zone_write(NvmeNamespace *ns, NvmeZone *zone,
1676 uint64_t slba, uint32_t nlb)
1677 {
1678 uint64_t zcap = nvme_zone_wr_boundary(zone);
1679 uint16_t status;
1680
1681 status = nvme_check_zone_state_for_write(zone);
1682 if (status) {
1683 return status;
1684 }
1685
1686 if (zone->d.za & NVME_ZA_ZRWA_VALID) {
1687 uint64_t ezrwa = zone->w_ptr + 2 * ns->zns.zrwas;
1688
1689 if (slba < zone->w_ptr || slba + nlb > ezrwa) {
1690 trace_pci_nvme_err_zone_invalid_write(slba, zone->w_ptr);
1691 return NVME_ZONE_INVALID_WRITE;
1692 }
1693 } else {
1694 if (unlikely(slba != zone->w_ptr)) {
1695 trace_pci_nvme_err_write_not_at_wp(slba, zone->d.zslba,
1696 zone->w_ptr);
1697 return NVME_ZONE_INVALID_WRITE;
1698 }
1699 }
1700
1701 if (unlikely((slba + nlb) > zcap)) {
1702 trace_pci_nvme_err_zone_boundary(slba, nlb, zcap);
1703 return NVME_ZONE_BOUNDARY_ERROR;
1704 }
1705
1706 return NVME_SUCCESS;
1707 }
1708
1709 static uint16_t nvme_check_zone_state_for_read(NvmeZone *zone)
1710 {
1711 switch (nvme_get_zone_state(zone)) {
1712 case NVME_ZONE_STATE_EMPTY:
1713 case NVME_ZONE_STATE_IMPLICITLY_OPEN:
1714 case NVME_ZONE_STATE_EXPLICITLY_OPEN:
1715 case NVME_ZONE_STATE_FULL:
1716 case NVME_ZONE_STATE_CLOSED:
1717 case NVME_ZONE_STATE_READ_ONLY:
1718 return NVME_SUCCESS;
1719 case NVME_ZONE_STATE_OFFLINE:
1720 trace_pci_nvme_err_zone_is_offline(zone->d.zslba);
1721 return NVME_ZONE_OFFLINE;
1722 default:
1723 assert(false);
1724 }
1725
1726 return NVME_INTERNAL_DEV_ERROR;
1727 }
1728
1729 static uint16_t nvme_check_zone_read(NvmeNamespace *ns, uint64_t slba,
1730 uint32_t nlb)
1731 {
1732 NvmeZone *zone;
1733 uint64_t bndry, end;
1734 uint16_t status;
1735
1736 zone = nvme_get_zone_by_slba(ns, slba);
1737 assert(zone);
1738
1739 bndry = nvme_zone_rd_boundary(ns, zone);
1740 end = slba + nlb;
1741
1742 status = nvme_check_zone_state_for_read(zone);
1743 if (status) {
1744 ;
1745 } else if (unlikely(end > bndry)) {
1746 if (!ns->params.cross_zone_read) {
1747 status = NVME_ZONE_BOUNDARY_ERROR;
1748 } else {
1749 /*
1750 * Read across zone boundary - check that all subsequent
1751 * zones that are being read have an appropriate state.
1752 */
1753 do {
1754 zone++;
1755 status = nvme_check_zone_state_for_read(zone);
1756 if (status) {
1757 break;
1758 }
1759 } while (end > nvme_zone_rd_boundary(ns, zone));
1760 }
1761 }
1762
1763 return status;
1764 }
1765
1766 static uint16_t nvme_zrm_finish(NvmeNamespace *ns, NvmeZone *zone)
1767 {
1768 switch (nvme_get_zone_state(zone)) {
1769 case NVME_ZONE_STATE_FULL:
1770 return NVME_SUCCESS;
1771
1772 case NVME_ZONE_STATE_IMPLICITLY_OPEN:
1773 case NVME_ZONE_STATE_EXPLICITLY_OPEN:
1774 nvme_aor_dec_open(ns);
1775 /* fallthrough */
1776 case NVME_ZONE_STATE_CLOSED:
1777 nvme_aor_dec_active(ns);
1778
1779 if (zone->d.za & NVME_ZA_ZRWA_VALID) {
1780 zone->d.za &= ~NVME_ZA_ZRWA_VALID;
1781 if (ns->params.numzrwa) {
1782 ns->zns.numzrwa++;
1783 }
1784 }
1785
1786 /* fallthrough */
1787 case NVME_ZONE_STATE_EMPTY:
1788 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_FULL);
1789 return NVME_SUCCESS;
1790
1791 default:
1792 return NVME_ZONE_INVAL_TRANSITION;
1793 }
1794 }
1795
1796 static uint16_t nvme_zrm_close(NvmeNamespace *ns, NvmeZone *zone)
1797 {
1798 switch (nvme_get_zone_state(zone)) {
1799 case NVME_ZONE_STATE_EXPLICITLY_OPEN:
1800 case NVME_ZONE_STATE_IMPLICITLY_OPEN:
1801 nvme_aor_dec_open(ns);
1802 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_CLOSED);
1803 /* fall through */
1804 case NVME_ZONE_STATE_CLOSED:
1805 return NVME_SUCCESS;
1806
1807 default:
1808 return NVME_ZONE_INVAL_TRANSITION;
1809 }
1810 }
1811
1812 static uint16_t nvme_zrm_reset(NvmeNamespace *ns, NvmeZone *zone)
1813 {
1814 switch (nvme_get_zone_state(zone)) {
1815 case NVME_ZONE_STATE_EXPLICITLY_OPEN:
1816 case NVME_ZONE_STATE_IMPLICITLY_OPEN:
1817 nvme_aor_dec_open(ns);
1818 /* fallthrough */
1819 case NVME_ZONE_STATE_CLOSED:
1820 nvme_aor_dec_active(ns);
1821
1822 if (zone->d.za & NVME_ZA_ZRWA_VALID) {
1823 if (ns->params.numzrwa) {
1824 ns->zns.numzrwa++;
1825 }
1826 }
1827
1828 /* fallthrough */
1829 case NVME_ZONE_STATE_FULL:
1830 zone->w_ptr = zone->d.zslba;
1831 zone->d.wp = zone->w_ptr;
1832 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_EMPTY);
1833 /* fallthrough */
1834 case NVME_ZONE_STATE_EMPTY:
1835 return NVME_SUCCESS;
1836
1837 default:
1838 return NVME_ZONE_INVAL_TRANSITION;
1839 }
1840 }
1841
1842 static void nvme_zrm_auto_transition_zone(NvmeNamespace *ns)
1843 {
1844 NvmeZone *zone;
1845
1846 if (ns->params.max_open_zones &&
1847 ns->nr_open_zones == ns->params.max_open_zones) {
1848 zone = QTAILQ_FIRST(&ns->imp_open_zones);
1849 if (zone) {
1850 /*
1851 * Automatically close this implicitly open zone.
1852 */
1853 QTAILQ_REMOVE(&ns->imp_open_zones, zone, entry);
1854 nvme_zrm_close(ns, zone);
1855 }
1856 }
1857 }
1858
1859 enum {
1860 NVME_ZRM_AUTO = 1 << 0,
1861 NVME_ZRM_ZRWA = 1 << 1,
1862 };
1863
1864 static uint16_t nvme_zrm_open_flags(NvmeCtrl *n, NvmeNamespace *ns,
1865 NvmeZone *zone, int flags)
1866 {
1867 int act = 0;
1868 uint16_t status;
1869
1870 switch (nvme_get_zone_state(zone)) {
1871 case NVME_ZONE_STATE_EMPTY:
1872 act = 1;
1873
1874 /* fallthrough */
1875
1876 case NVME_ZONE_STATE_CLOSED:
1877 if (n->params.auto_transition_zones) {
1878 nvme_zrm_auto_transition_zone(ns);
1879 }
1880 status = nvme_zns_check_resources(ns, act, 1,
1881 (flags & NVME_ZRM_ZRWA) ? 1 : 0);
1882 if (status) {
1883 return status;
1884 }
1885
1886 if (act) {
1887 nvme_aor_inc_active(ns);
1888 }
1889
1890 nvme_aor_inc_open(ns);
1891
1892 if (flags & NVME_ZRM_AUTO) {
1893 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_IMPLICITLY_OPEN);
1894 return NVME_SUCCESS;
1895 }
1896
1897 /* fallthrough */
1898
1899 case NVME_ZONE_STATE_IMPLICITLY_OPEN:
1900 if (flags & NVME_ZRM_AUTO) {
1901 return NVME_SUCCESS;
1902 }
1903
1904 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_EXPLICITLY_OPEN);
1905
1906 /* fallthrough */
1907
1908 case NVME_ZONE_STATE_EXPLICITLY_OPEN:
1909 if (flags & NVME_ZRM_ZRWA) {
1910 ns->zns.numzrwa--;
1911
1912 zone->d.za |= NVME_ZA_ZRWA_VALID;
1913 }
1914
1915 return NVME_SUCCESS;
1916
1917 default:
1918 return NVME_ZONE_INVAL_TRANSITION;
1919 }
1920 }
1921
1922 static inline uint16_t nvme_zrm_auto(NvmeCtrl *n, NvmeNamespace *ns,
1923 NvmeZone *zone)
1924 {
1925 return nvme_zrm_open_flags(n, ns, zone, NVME_ZRM_AUTO);
1926 }
1927
1928 static void nvme_advance_zone_wp(NvmeNamespace *ns, NvmeZone *zone,
1929 uint32_t nlb)
1930 {
1931 zone->d.wp += nlb;
1932
1933 if (zone->d.wp == nvme_zone_wr_boundary(zone)) {
1934 nvme_zrm_finish(ns, zone);
1935 }
1936 }
1937
1938 static void nvme_zoned_zrwa_implicit_flush(NvmeNamespace *ns, NvmeZone *zone,
1939 uint32_t nlbc)
1940 {
1941 uint16_t nzrwafgs = DIV_ROUND_UP(nlbc, ns->zns.zrwafg);
1942
1943 nlbc = nzrwafgs * ns->zns.zrwafg;
1944
1945 trace_pci_nvme_zoned_zrwa_implicit_flush(zone->d.zslba, nlbc);
1946
1947 zone->w_ptr += nlbc;
1948
1949 nvme_advance_zone_wp(ns, zone, nlbc);
1950 }
1951
1952 static void nvme_finalize_zoned_write(NvmeNamespace *ns, NvmeRequest *req)
1953 {
1954 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
1955 NvmeZone *zone;
1956 uint64_t slba;
1957 uint32_t nlb;
1958
1959 slba = le64_to_cpu(rw->slba);
1960 nlb = le16_to_cpu(rw->nlb) + 1;
1961 zone = nvme_get_zone_by_slba(ns, slba);
1962 assert(zone);
1963
1964 if (zone->d.za & NVME_ZA_ZRWA_VALID) {
1965 uint64_t ezrwa = zone->w_ptr + ns->zns.zrwas - 1;
1966 uint64_t elba = slba + nlb - 1;
1967
1968 if (elba > ezrwa) {
1969 nvme_zoned_zrwa_implicit_flush(ns, zone, elba - ezrwa);
1970 }
1971
1972 return;
1973 }
1974
1975 nvme_advance_zone_wp(ns, zone, nlb);
1976 }
1977
1978 static inline bool nvme_is_write(NvmeRequest *req)
1979 {
1980 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
1981
1982 return rw->opcode == NVME_CMD_WRITE ||
1983 rw->opcode == NVME_CMD_ZONE_APPEND ||
1984 rw->opcode == NVME_CMD_WRITE_ZEROES;
1985 }
1986
1987 static AioContext *nvme_get_aio_context(BlockAIOCB *acb)
1988 {
1989 return qemu_get_aio_context();
1990 }
1991
1992 static void nvme_misc_cb(void *opaque, int ret)
1993 {
1994 NvmeRequest *req = opaque;
1995
1996 trace_pci_nvme_misc_cb(nvme_cid(req));
1997
1998 if (ret) {
1999 nvme_aio_err(req, ret);
2000 }
2001
2002 nvme_enqueue_req_completion(nvme_cq(req), req);
2003 }
2004
2005 void nvme_rw_complete_cb(void *opaque, int ret)
2006 {
2007 NvmeRequest *req = opaque;
2008 NvmeNamespace *ns = req->ns;
2009 BlockBackend *blk = ns->blkconf.blk;
2010 BlockAcctCookie *acct = &req->acct;
2011 BlockAcctStats *stats = blk_get_stats(blk);
2012
2013 trace_pci_nvme_rw_complete_cb(nvme_cid(req), blk_name(blk));
2014
2015 if (ret) {
2016 block_acct_failed(stats, acct);
2017 nvme_aio_err(req, ret);
2018 } else {
2019 block_acct_done(stats, acct);
2020 }
2021
2022 if (ns->params.zoned && nvme_is_write(req)) {
2023 nvme_finalize_zoned_write(ns, req);
2024 }
2025
2026 nvme_enqueue_req_completion(nvme_cq(req), req);
2027 }
2028
2029 static void nvme_rw_cb(void *opaque, int ret)
2030 {
2031 NvmeRequest *req = opaque;
2032 NvmeNamespace *ns = req->ns;
2033
2034 BlockBackend *blk = ns->blkconf.blk;
2035
2036 trace_pci_nvme_rw_cb(nvme_cid(req), blk_name(blk));
2037
2038 if (ret) {
2039 goto out;
2040 }
2041
2042 if (ns->lbaf.ms) {
2043 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
2044 uint64_t slba = le64_to_cpu(rw->slba);
2045 uint32_t nlb = (uint32_t)le16_to_cpu(rw->nlb) + 1;
2046 uint64_t offset = nvme_moff(ns, slba);
2047
2048 if (req->cmd.opcode == NVME_CMD_WRITE_ZEROES) {
2049 size_t mlen = nvme_m2b(ns, nlb);
2050
2051 req->aiocb = blk_aio_pwrite_zeroes(blk, offset, mlen,
2052 BDRV_REQ_MAY_UNMAP,
2053 nvme_rw_complete_cb, req);
2054 return;
2055 }
2056
2057 if (nvme_ns_ext(ns) || req->cmd.mptr) {
2058 uint16_t status;
2059
2060 nvme_sg_unmap(&req->sg);
2061 status = nvme_map_mdata(nvme_ctrl(req), nlb, req);
2062 if (status) {
2063 ret = -EFAULT;
2064 goto out;
2065 }
2066
2067 if (req->cmd.opcode == NVME_CMD_READ) {
2068 return nvme_blk_read(blk, offset, nvme_rw_complete_cb, req);
2069 }
2070
2071 return nvme_blk_write(blk, offset, nvme_rw_complete_cb, req);
2072 }
2073 }
2074
2075 out:
2076 nvme_rw_complete_cb(req, ret);
2077 }
2078
2079 static void nvme_verify_cb(void *opaque, int ret)
2080 {
2081 NvmeBounceContext *ctx = opaque;
2082 NvmeRequest *req = ctx->req;
2083 NvmeNamespace *ns = req->ns;
2084 BlockBackend *blk = ns->blkconf.blk;
2085 BlockAcctCookie *acct = &req->acct;
2086 BlockAcctStats *stats = blk_get_stats(blk);
2087 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
2088 uint64_t slba = le64_to_cpu(rw->slba);
2089 uint8_t prinfo = NVME_RW_PRINFO(le16_to_cpu(rw->control));
2090 uint16_t apptag = le16_to_cpu(rw->apptag);
2091 uint16_t appmask = le16_to_cpu(rw->appmask);
2092 uint64_t reftag = le32_to_cpu(rw->reftag);
2093 uint64_t cdw3 = le32_to_cpu(rw->cdw3);
2094 uint16_t status;
2095
2096 reftag |= cdw3 << 32;
2097
2098 trace_pci_nvme_verify_cb(nvme_cid(req), prinfo, apptag, appmask, reftag);
2099
2100 if (ret) {
2101 block_acct_failed(stats, acct);
2102 nvme_aio_err(req, ret);
2103 goto out;
2104 }
2105
2106 block_acct_done(stats, acct);
2107
2108 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
2109 status = nvme_dif_mangle_mdata(ns, ctx->mdata.bounce,
2110 ctx->mdata.iov.size, slba);
2111 if (status) {
2112 req->status = status;
2113 goto out;
2114 }
2115
2116 req->status = nvme_dif_check(ns, ctx->data.bounce, ctx->data.iov.size,
2117 ctx->mdata.bounce, ctx->mdata.iov.size,
2118 prinfo, slba, apptag, appmask, &reftag);
2119 }
2120
2121 out:
2122 qemu_iovec_destroy(&ctx->data.iov);
2123 g_free(ctx->data.bounce);
2124
2125 qemu_iovec_destroy(&ctx->mdata.iov);
2126 g_free(ctx->mdata.bounce);
2127
2128 g_free(ctx);
2129
2130 nvme_enqueue_req_completion(nvme_cq(req), req);
2131 }
2132
2133
2134 static void nvme_verify_mdata_in_cb(void *opaque, int ret)
2135 {
2136 NvmeBounceContext *ctx = opaque;
2137 NvmeRequest *req = ctx->req;
2138 NvmeNamespace *ns = req->ns;
2139 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
2140 uint64_t slba = le64_to_cpu(rw->slba);
2141 uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
2142 size_t mlen = nvme_m2b(ns, nlb);
2143 uint64_t offset = nvme_moff(ns, slba);
2144 BlockBackend *blk = ns->blkconf.blk;
2145
2146 trace_pci_nvme_verify_mdata_in_cb(nvme_cid(req), blk_name(blk));
2147
2148 if (ret) {
2149 goto out;
2150 }
2151
2152 ctx->mdata.bounce = g_malloc(mlen);
2153
2154 qemu_iovec_reset(&ctx->mdata.iov);
2155 qemu_iovec_add(&ctx->mdata.iov, ctx->mdata.bounce, mlen);
2156
2157 req->aiocb = blk_aio_preadv(blk, offset, &ctx->mdata.iov, 0,
2158 nvme_verify_cb, ctx);
2159 return;
2160
2161 out:
2162 nvme_verify_cb(ctx, ret);
2163 }
2164
2165 struct nvme_compare_ctx {
2166 struct {
2167 QEMUIOVector iov;
2168 uint8_t *bounce;
2169 } data;
2170
2171 struct {
2172 QEMUIOVector iov;
2173 uint8_t *bounce;
2174 } mdata;
2175 };
2176
2177 static void nvme_compare_mdata_cb(void *opaque, int ret)
2178 {
2179 NvmeRequest *req = opaque;
2180 NvmeNamespace *ns = req->ns;
2181 NvmeCtrl *n = nvme_ctrl(req);
2182 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
2183 uint8_t prinfo = NVME_RW_PRINFO(le16_to_cpu(rw->control));
2184 uint16_t apptag = le16_to_cpu(rw->apptag);
2185 uint16_t appmask = le16_to_cpu(rw->appmask);
2186 uint64_t reftag = le32_to_cpu(rw->reftag);
2187 uint64_t cdw3 = le32_to_cpu(rw->cdw3);
2188 struct nvme_compare_ctx *ctx = req->opaque;
2189 g_autofree uint8_t *buf = NULL;
2190 BlockBackend *blk = ns->blkconf.blk;
2191 BlockAcctCookie *acct = &req->acct;
2192 BlockAcctStats *stats = blk_get_stats(blk);
2193 uint16_t status = NVME_SUCCESS;
2194
2195 reftag |= cdw3 << 32;
2196
2197 trace_pci_nvme_compare_mdata_cb(nvme_cid(req));
2198
2199 if (ret) {
2200 block_acct_failed(stats, acct);
2201 nvme_aio_err(req, ret);
2202 goto out;
2203 }
2204
2205 buf = g_malloc(ctx->mdata.iov.size);
2206
2207 status = nvme_bounce_mdata(n, buf, ctx->mdata.iov.size,
2208 NVME_TX_DIRECTION_TO_DEVICE, req);
2209 if (status) {
2210 req->status = status;
2211 goto out;
2212 }
2213
2214 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
2215 uint64_t slba = le64_to_cpu(rw->slba);
2216 uint8_t *bufp;
2217 uint8_t *mbufp = ctx->mdata.bounce;
2218 uint8_t *end = mbufp + ctx->mdata.iov.size;
2219 int16_t pil = 0;
2220
2221 status = nvme_dif_check(ns, ctx->data.bounce, ctx->data.iov.size,
2222 ctx->mdata.bounce, ctx->mdata.iov.size, prinfo,
2223 slba, apptag, appmask, &reftag);
2224 if (status) {
2225 req->status = status;
2226 goto out;
2227 }
2228
2229 /*
2230 * When formatted with protection information, do not compare the DIF
2231 * tuple.
2232 */
2233 if (!(ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT)) {
2234 pil = ns->lbaf.ms - nvme_pi_tuple_size(ns);
2235 }
2236
2237 for (bufp = buf; mbufp < end; bufp += ns->lbaf.ms, mbufp += ns->lbaf.ms) {
2238 if (memcmp(bufp + pil, mbufp + pil, ns->lbaf.ms - pil)) {
2239 req->status = NVME_CMP_FAILURE;
2240 goto out;
2241 }
2242 }
2243
2244 goto out;
2245 }
2246
2247 if (memcmp(buf, ctx->mdata.bounce, ctx->mdata.iov.size)) {
2248 req->status = NVME_CMP_FAILURE;
2249 goto out;
2250 }
2251
2252 block_acct_done(stats, acct);
2253
2254 out:
2255 qemu_iovec_destroy(&ctx->data.iov);
2256 g_free(ctx->data.bounce);
2257
2258 qemu_iovec_destroy(&ctx->mdata.iov);
2259 g_free(ctx->mdata.bounce);
2260
2261 g_free(ctx);
2262
2263 nvme_enqueue_req_completion(nvme_cq(req), req);
2264 }
2265
2266 static void nvme_compare_data_cb(void *opaque, int ret)
2267 {
2268 NvmeRequest *req = opaque;
2269 NvmeCtrl *n = nvme_ctrl(req);
2270 NvmeNamespace *ns = req->ns;
2271 BlockBackend *blk = ns->blkconf.blk;
2272 BlockAcctCookie *acct = &req->acct;
2273 BlockAcctStats *stats = blk_get_stats(blk);
2274
2275 struct nvme_compare_ctx *ctx = req->opaque;
2276 g_autofree uint8_t *buf = NULL;
2277 uint16_t status;
2278
2279 trace_pci_nvme_compare_data_cb(nvme_cid(req));
2280
2281 if (ret) {
2282 block_acct_failed(stats, acct);
2283 nvme_aio_err(req, ret);
2284 goto out;
2285 }
2286
2287 buf = g_malloc(ctx->data.iov.size);
2288
2289 status = nvme_bounce_data(n, buf, ctx->data.iov.size,
2290 NVME_TX_DIRECTION_TO_DEVICE, req);
2291 if (status) {
2292 req->status = status;
2293 goto out;
2294 }
2295
2296 if (memcmp(buf, ctx->data.bounce, ctx->data.iov.size)) {
2297 req->status = NVME_CMP_FAILURE;
2298 goto out;
2299 }
2300
2301 if (ns->lbaf.ms) {
2302 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
2303 uint64_t slba = le64_to_cpu(rw->slba);
2304 uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
2305 size_t mlen = nvme_m2b(ns, nlb);
2306 uint64_t offset = nvme_moff(ns, slba);
2307
2308 ctx->mdata.bounce = g_malloc(mlen);
2309
2310 qemu_iovec_init(&ctx->mdata.iov, 1);
2311 qemu_iovec_add(&ctx->mdata.iov, ctx->mdata.bounce, mlen);
2312
2313 req->aiocb = blk_aio_preadv(blk, offset, &ctx->mdata.iov, 0,
2314 nvme_compare_mdata_cb, req);
2315 return;
2316 }
2317
2318 block_acct_done(stats, acct);
2319
2320 out:
2321 qemu_iovec_destroy(&ctx->data.iov);
2322 g_free(ctx->data.bounce);
2323 g_free(ctx);
2324
2325 nvme_enqueue_req_completion(nvme_cq(req), req);
2326 }
2327
2328 typedef struct NvmeDSMAIOCB {
2329 BlockAIOCB common;
2330 BlockAIOCB *aiocb;
2331 NvmeRequest *req;
2332 QEMUBH *bh;
2333 int ret;
2334
2335 NvmeDsmRange *range;
2336 unsigned int nr;
2337 unsigned int idx;
2338 } NvmeDSMAIOCB;
2339
2340 static void nvme_dsm_cancel(BlockAIOCB *aiocb)
2341 {
2342 NvmeDSMAIOCB *iocb = container_of(aiocb, NvmeDSMAIOCB, common);
2343
2344 /* break nvme_dsm_cb loop */
2345 iocb->idx = iocb->nr;
2346 iocb->ret = -ECANCELED;
2347
2348 if (iocb->aiocb) {
2349 blk_aio_cancel_async(iocb->aiocb);
2350 iocb->aiocb = NULL;
2351 } else {
2352 /*
2353 * We only reach this if nvme_dsm_cancel() has already been called or
2354 * the command ran to completion and nvme_dsm_bh is scheduled to run.
2355 */
2356 assert(iocb->idx == iocb->nr);
2357 }
2358 }
2359
2360 static const AIOCBInfo nvme_dsm_aiocb_info = {
2361 .aiocb_size = sizeof(NvmeDSMAIOCB),
2362 .cancel_async = nvme_dsm_cancel,
2363 };
2364
2365 static void nvme_dsm_bh(void *opaque)
2366 {
2367 NvmeDSMAIOCB *iocb = opaque;
2368
2369 iocb->common.cb(iocb->common.opaque, iocb->ret);
2370
2371 qemu_bh_delete(iocb->bh);
2372 iocb->bh = NULL;
2373 qemu_aio_unref(iocb);
2374 }
2375
2376 static void nvme_dsm_cb(void *opaque, int ret);
2377
2378 static void nvme_dsm_md_cb(void *opaque, int ret)
2379 {
2380 NvmeDSMAIOCB *iocb = opaque;
2381 NvmeRequest *req = iocb->req;
2382 NvmeNamespace *ns = req->ns;
2383 NvmeDsmRange *range;
2384 uint64_t slba;
2385 uint32_t nlb;
2386
2387 if (ret < 0) {
2388 iocb->ret = ret;
2389 goto done;
2390 }
2391
2392 if (!ns->lbaf.ms) {
2393 nvme_dsm_cb(iocb, 0);
2394 return;
2395 }
2396
2397 range = &iocb->range[iocb->idx - 1];
2398 slba = le64_to_cpu(range->slba);
2399 nlb = le32_to_cpu(range->nlb);
2400
2401 /*
2402 * Check that all block were discarded (zeroed); otherwise we do not zero
2403 * the metadata.
2404 */
2405
2406 ret = nvme_block_status_all(ns, slba, nlb, BDRV_BLOCK_ZERO);
2407 if (ret) {
2408 if (ret < 0) {
2409 iocb->ret = ret;
2410 goto done;
2411 }
2412
2413 nvme_dsm_cb(iocb, 0);
2414 return;
2415 }
2416
2417 iocb->aiocb = blk_aio_pwrite_zeroes(ns->blkconf.blk, nvme_moff(ns, slba),
2418 nvme_m2b(ns, nlb), BDRV_REQ_MAY_UNMAP,
2419 nvme_dsm_cb, iocb);
2420 return;
2421
2422 done:
2423 iocb->aiocb = NULL;
2424 qemu_bh_schedule(iocb->bh);
2425 }
2426
2427 static void nvme_dsm_cb(void *opaque, int ret)
2428 {
2429 NvmeDSMAIOCB *iocb = opaque;
2430 NvmeRequest *req = iocb->req;
2431 NvmeCtrl *n = nvme_ctrl(req);
2432 NvmeNamespace *ns = req->ns;
2433 NvmeDsmRange *range;
2434 uint64_t slba;
2435 uint32_t nlb;
2436
2437 if (ret < 0) {
2438 iocb->ret = ret;
2439 goto done;
2440 }
2441
2442 next:
2443 if (iocb->idx == iocb->nr) {
2444 goto done;
2445 }
2446
2447 range = &iocb->range[iocb->idx++];
2448 slba = le64_to_cpu(range->slba);
2449 nlb = le32_to_cpu(range->nlb);
2450
2451 trace_pci_nvme_dsm_deallocate(slba, nlb);
2452
2453 if (nlb > n->dmrsl) {
2454 trace_pci_nvme_dsm_single_range_limit_exceeded(nlb, n->dmrsl);
2455 goto next;
2456 }
2457
2458 if (nvme_check_bounds(ns, slba, nlb)) {
2459 trace_pci_nvme_err_invalid_lba_range(slba, nlb,
2460 ns->id_ns.nsze);
2461 goto next;
2462 }
2463
2464 iocb->aiocb = blk_aio_pdiscard(ns->blkconf.blk, nvme_l2b(ns, slba),
2465 nvme_l2b(ns, nlb),
2466 nvme_dsm_md_cb, iocb);
2467 return;
2468
2469 done:
2470 iocb->aiocb = NULL;
2471 qemu_bh_schedule(iocb->bh);
2472 }
2473
2474 static uint16_t nvme_dsm(NvmeCtrl *n, NvmeRequest *req)
2475 {
2476 NvmeNamespace *ns = req->ns;
2477 NvmeDsmCmd *dsm = (NvmeDsmCmd *) &req->cmd;
2478 uint32_t attr = le32_to_cpu(dsm->attributes);
2479 uint32_t nr = (le32_to_cpu(dsm->nr) & 0xff) + 1;
2480 uint16_t status = NVME_SUCCESS;
2481
2482 trace_pci_nvme_dsm(nr, attr);
2483
2484 if (attr & NVME_DSMGMT_AD) {
2485 NvmeDSMAIOCB *iocb = blk_aio_get(&nvme_dsm_aiocb_info, ns->blkconf.blk,
2486 nvme_misc_cb, req);
2487
2488 iocb->req = req;
2489 iocb->bh = qemu_bh_new(nvme_dsm_bh, iocb);
2490 iocb->ret = 0;
2491 iocb->range = g_new(NvmeDsmRange, nr);
2492 iocb->nr = nr;
2493 iocb->idx = 0;
2494
2495 status = nvme_h2c(n, (uint8_t *)iocb->range, sizeof(NvmeDsmRange) * nr,
2496 req);
2497 if (status) {
2498 return status;
2499 }
2500
2501 req->aiocb = &iocb->common;
2502 nvme_dsm_cb(iocb, 0);
2503
2504 return NVME_NO_COMPLETE;
2505 }
2506
2507 return status;
2508 }
2509
2510 static uint16_t nvme_verify(NvmeCtrl *n, NvmeRequest *req)
2511 {
2512 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
2513 NvmeNamespace *ns = req->ns;
2514 BlockBackend *blk = ns->blkconf.blk;
2515 uint64_t slba = le64_to_cpu(rw->slba);
2516 uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
2517 size_t len = nvme_l2b(ns, nlb);
2518 int64_t offset = nvme_l2b(ns, slba);
2519 uint8_t prinfo = NVME_RW_PRINFO(le16_to_cpu(rw->control));
2520 uint32_t reftag = le32_to_cpu(rw->reftag);
2521 NvmeBounceContext *ctx = NULL;
2522 uint16_t status;
2523
2524 trace_pci_nvme_verify(nvme_cid(req), nvme_nsid(ns), slba, nlb);
2525
2526 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
2527 status = nvme_check_prinfo(ns, prinfo, slba, reftag);
2528 if (status) {
2529 return status;
2530 }
2531
2532 if (prinfo & NVME_PRINFO_PRACT) {
2533 return NVME_INVALID_PROT_INFO | NVME_DNR;
2534 }
2535 }
2536
2537 if (len > n->page_size << n->params.vsl) {
2538 return NVME_INVALID_FIELD | NVME_DNR;
2539 }
2540
2541 status = nvme_check_bounds(ns, slba, nlb);
2542 if (status) {
2543 return status;
2544 }
2545
2546 if (NVME_ERR_REC_DULBE(ns->features.err_rec)) {
2547 status = nvme_check_dulbe(ns, slba, nlb);
2548 if (status) {
2549 return status;
2550 }
2551 }
2552
2553 ctx = g_new0(NvmeBounceContext, 1);
2554 ctx->req = req;
2555
2556 ctx->data.bounce = g_malloc(len);
2557
2558 qemu_iovec_init(&ctx->data.iov, 1);
2559 qemu_iovec_add(&ctx->data.iov, ctx->data.bounce, len);
2560
2561 block_acct_start(blk_get_stats(blk), &req->acct, ctx->data.iov.size,
2562 BLOCK_ACCT_READ);
2563
2564 req->aiocb = blk_aio_preadv(ns->blkconf.blk, offset, &ctx->data.iov, 0,
2565 nvme_verify_mdata_in_cb, ctx);
2566 return NVME_NO_COMPLETE;
2567 }
2568
2569 typedef struct NvmeCopyAIOCB {
2570 BlockAIOCB common;
2571 BlockAIOCB *aiocb;
2572 NvmeRequest *req;
2573 QEMUBH *bh;
2574 int ret;
2575
2576 void *ranges;
2577 unsigned int format;
2578 int nr;
2579 int idx;
2580
2581 uint8_t *bounce;
2582 QEMUIOVector iov;
2583 struct {
2584 BlockAcctCookie read;
2585 BlockAcctCookie write;
2586 } acct;
2587
2588 uint64_t reftag;
2589 uint64_t slba;
2590
2591 NvmeZone *zone;
2592 } NvmeCopyAIOCB;
2593
2594 static void nvme_copy_cancel(BlockAIOCB *aiocb)
2595 {
2596 NvmeCopyAIOCB *iocb = container_of(aiocb, NvmeCopyAIOCB, common);
2597
2598 iocb->ret = -ECANCELED;
2599
2600 if (iocb->aiocb) {
2601 blk_aio_cancel_async(iocb->aiocb);
2602 iocb->aiocb = NULL;
2603 }
2604 }
2605
2606 static const AIOCBInfo nvme_copy_aiocb_info = {
2607 .aiocb_size = sizeof(NvmeCopyAIOCB),
2608 .cancel_async = nvme_copy_cancel,
2609 };
2610
2611 static void nvme_copy_bh(void *opaque)
2612 {
2613 NvmeCopyAIOCB *iocb = opaque;
2614 NvmeRequest *req = iocb->req;
2615 NvmeNamespace *ns = req->ns;
2616 BlockAcctStats *stats = blk_get_stats(ns->blkconf.blk);
2617
2618 if (iocb->idx != iocb->nr) {
2619 req->cqe.result = cpu_to_le32(iocb->idx);
2620 }
2621
2622 qemu_iovec_destroy(&iocb->iov);
2623 g_free(iocb->bounce);
2624
2625 qemu_bh_delete(iocb->bh);
2626 iocb->bh = NULL;
2627
2628 if (iocb->ret < 0) {
2629 block_acct_failed(stats, &iocb->acct.read);
2630 block_acct_failed(stats, &iocb->acct.write);
2631 } else {
2632 block_acct_done(stats, &iocb->acct.read);
2633 block_acct_done(stats, &iocb->acct.write);
2634 }
2635
2636 iocb->common.cb(iocb->common.opaque, iocb->ret);
2637 qemu_aio_unref(iocb);
2638 }
2639
2640 static void nvme_copy_cb(void *opaque, int ret);
2641
2642 static void nvme_copy_source_range_parse_format0(void *ranges, int idx,
2643 uint64_t *slba, uint32_t *nlb,
2644 uint16_t *apptag,
2645 uint16_t *appmask,
2646 uint64_t *reftag)
2647 {
2648 NvmeCopySourceRangeFormat0 *_ranges = ranges;
2649
2650 if (slba) {
2651 *slba = le64_to_cpu(_ranges[idx].slba);
2652 }
2653
2654 if (nlb) {
2655 *nlb = le16_to_cpu(_ranges[idx].nlb) + 1;
2656 }
2657
2658 if (apptag) {
2659 *apptag = le16_to_cpu(_ranges[idx].apptag);
2660 }
2661
2662 if (appmask) {
2663 *appmask = le16_to_cpu(_ranges[idx].appmask);
2664 }
2665
2666 if (reftag) {
2667 *reftag = le32_to_cpu(_ranges[idx].reftag);
2668 }
2669 }
2670
2671 static void nvme_copy_source_range_parse_format1(void *ranges, int idx,
2672 uint64_t *slba, uint32_t *nlb,
2673 uint16_t *apptag,
2674 uint16_t *appmask,
2675 uint64_t *reftag)
2676 {
2677 NvmeCopySourceRangeFormat1 *_ranges = ranges;
2678
2679 if (slba) {
2680 *slba = le64_to_cpu(_ranges[idx].slba);
2681 }
2682
2683 if (nlb) {
2684 *nlb = le16_to_cpu(_ranges[idx].nlb) + 1;
2685 }
2686
2687 if (apptag) {
2688 *apptag = le16_to_cpu(_ranges[idx].apptag);
2689 }
2690
2691 if (appmask) {
2692 *appmask = le16_to_cpu(_ranges[idx].appmask);
2693 }
2694
2695 if (reftag) {
2696 *reftag = 0;
2697
2698 *reftag |= (uint64_t)_ranges[idx].sr[4] << 40;
2699 *reftag |= (uint64_t)_ranges[idx].sr[5] << 32;
2700 *reftag |= (uint64_t)_ranges[idx].sr[6] << 24;
2701 *reftag |= (uint64_t)_ranges[idx].sr[7] << 16;
2702 *reftag |= (uint64_t)_ranges[idx].sr[8] << 8;
2703 *reftag |= (uint64_t)_ranges[idx].sr[9];
2704 }
2705 }
2706
2707 static void nvme_copy_source_range_parse(void *ranges, int idx, uint8_t format,
2708 uint64_t *slba, uint32_t *nlb,
2709 uint16_t *apptag, uint16_t *appmask,
2710 uint64_t *reftag)
2711 {
2712 switch (format) {
2713 case NVME_COPY_FORMAT_0:
2714 nvme_copy_source_range_parse_format0(ranges, idx, slba, nlb, apptag,
2715 appmask, reftag);
2716 break;
2717
2718 case NVME_COPY_FORMAT_1:
2719 nvme_copy_source_range_parse_format1(ranges, idx, slba, nlb, apptag,
2720 appmask, reftag);
2721 break;
2722
2723 default:
2724 abort();
2725 }
2726 }
2727
2728 static void nvme_copy_out_completed_cb(void *opaque, int ret)
2729 {
2730 NvmeCopyAIOCB *iocb = opaque;
2731 NvmeRequest *req = iocb->req;
2732 NvmeNamespace *ns = req->ns;
2733 uint32_t nlb;
2734
2735 nvme_copy_source_range_parse(iocb->ranges, iocb->idx, iocb->format, NULL,
2736 &nlb, NULL, NULL, NULL);
2737
2738 if (ret < 0) {
2739 iocb->ret = ret;
2740 goto out;
2741 } else if (iocb->ret < 0) {
2742 goto out;
2743 }
2744
2745 if (ns->params.zoned) {
2746 nvme_advance_zone_wp(ns, iocb->zone, nlb);
2747 }
2748
2749 iocb->idx++;
2750 iocb->slba += nlb;
2751 out:
2752 nvme_copy_cb(iocb, iocb->ret);
2753 }
2754
2755 static void nvme_copy_out_cb(void *opaque, int ret)
2756 {
2757 NvmeCopyAIOCB *iocb = opaque;
2758 NvmeRequest *req = iocb->req;
2759 NvmeNamespace *ns = req->ns;
2760 uint32_t nlb;
2761 size_t mlen;
2762 uint8_t *mbounce;
2763
2764 if (ret < 0) {
2765 iocb->ret = ret;
2766 goto out;
2767 } else if (iocb->ret < 0) {
2768 goto out;
2769 }
2770
2771 if (!ns->lbaf.ms) {
2772 nvme_copy_out_completed_cb(iocb, 0);
2773 return;
2774 }
2775
2776 nvme_copy_source_range_parse(iocb->ranges, iocb->idx, iocb->format, NULL,
2777 &nlb, NULL, NULL, NULL);
2778
2779 mlen = nvme_m2b(ns, nlb);
2780 mbounce = iocb->bounce + nvme_l2b(ns, nlb);
2781
2782 qemu_iovec_reset(&iocb->iov);
2783 qemu_iovec_add(&iocb->iov, mbounce, mlen);
2784
2785 iocb->aiocb = blk_aio_pwritev(ns->blkconf.blk, nvme_moff(ns, iocb->slba),
2786 &iocb->iov, 0, nvme_copy_out_completed_cb,
2787 iocb);
2788
2789 return;
2790
2791 out:
2792 nvme_copy_cb(iocb, ret);
2793 }
2794
2795 static void nvme_copy_in_completed_cb(void *opaque, int ret)
2796 {
2797 NvmeCopyAIOCB *iocb = opaque;
2798 NvmeRequest *req = iocb->req;
2799 NvmeNamespace *ns = req->ns;
2800 uint32_t nlb;
2801 uint64_t slba;
2802 uint16_t apptag, appmask;
2803 uint64_t reftag;
2804 size_t len;
2805 uint16_t status;
2806
2807 if (ret < 0) {
2808 iocb->ret = ret;
2809 goto out;
2810 } else if (iocb->ret < 0) {
2811 goto out;
2812 }
2813
2814 nvme_copy_source_range_parse(iocb->ranges, iocb->idx, iocb->format, &slba,
2815 &nlb, &apptag, &appmask, &reftag);
2816 len = nvme_l2b(ns, nlb);
2817
2818 trace_pci_nvme_copy_out(iocb->slba, nlb);
2819
2820 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
2821 NvmeCopyCmd *copy = (NvmeCopyCmd *)&req->cmd;
2822
2823 uint16_t prinfor = ((copy->control[0] >> 4) & 0xf);
2824 uint16_t prinfow = ((copy->control[2] >> 2) & 0xf);
2825
2826 size_t mlen = nvme_m2b(ns, nlb);
2827 uint8_t *mbounce = iocb->bounce + nvme_l2b(ns, nlb);
2828
2829 status = nvme_dif_mangle_mdata(ns, mbounce, mlen, slba);
2830 if (status) {
2831 goto invalid;
2832 }
2833 status = nvme_dif_check(ns, iocb->bounce, len, mbounce, mlen, prinfor,
2834 slba, apptag, appmask, &reftag);
2835 if (status) {
2836 goto invalid;
2837 }
2838
2839 apptag = le16_to_cpu(copy->apptag);
2840 appmask = le16_to_cpu(copy->appmask);
2841
2842 if (prinfow & NVME_PRINFO_PRACT) {
2843 status = nvme_check_prinfo(ns, prinfow, iocb->slba, iocb->reftag);
2844 if (status) {
2845 goto invalid;
2846 }
2847
2848 nvme_dif_pract_generate_dif(ns, iocb->bounce, len, mbounce, mlen,
2849 apptag, &iocb->reftag);
2850 } else {
2851 status = nvme_dif_check(ns, iocb->bounce, len, mbounce, mlen,
2852 prinfow, iocb->slba, apptag, appmask,
2853 &iocb->reftag);
2854 if (status) {
2855 goto invalid;
2856 }
2857 }
2858 }
2859
2860 status = nvme_check_bounds(ns, iocb->slba, nlb);
2861 if (status) {
2862 goto invalid;
2863 }
2864
2865 if (ns->params.zoned) {
2866 status = nvme_check_zone_write(ns, iocb->zone, iocb->slba, nlb);
2867 if (status) {
2868 goto invalid;
2869 }
2870
2871 if (!(iocb->zone->d.za & NVME_ZA_ZRWA_VALID)) {
2872 iocb->zone->w_ptr += nlb;
2873 }
2874 }
2875
2876 qemu_iovec_reset(&iocb->iov);
2877 qemu_iovec_add(&iocb->iov, iocb->bounce, len);
2878
2879 iocb->aiocb = blk_aio_pwritev(ns->blkconf.blk, nvme_l2b(ns, iocb->slba),
2880 &iocb->iov, 0, nvme_copy_out_cb, iocb);
2881
2882 return;
2883
2884 invalid:
2885 req->status = status;
2886 iocb->aiocb = NULL;
2887 if (iocb->bh) {
2888 qemu_bh_schedule(iocb->bh);
2889 }
2890
2891 return;
2892
2893 out:
2894 nvme_copy_cb(iocb, ret);
2895 }
2896
2897 static void nvme_copy_in_cb(void *opaque, int ret)
2898 {
2899 NvmeCopyAIOCB *iocb = opaque;
2900 NvmeRequest *req = iocb->req;
2901 NvmeNamespace *ns = req->ns;
2902 uint64_t slba;
2903 uint32_t nlb;
2904
2905 if (ret < 0) {
2906 iocb->ret = ret;
2907 goto out;
2908 } else if (iocb->ret < 0) {
2909 goto out;
2910 }
2911
2912 if (!ns->lbaf.ms) {
2913 nvme_copy_in_completed_cb(iocb, 0);
2914 return;
2915 }
2916
2917 nvme_copy_source_range_parse(iocb->ranges, iocb->idx, iocb->format, &slba,
2918 &nlb, NULL, NULL, NULL);
2919
2920 qemu_iovec_reset(&iocb->iov);
2921 qemu_iovec_add(&iocb->iov, iocb->bounce + nvme_l2b(ns, nlb),
2922 nvme_m2b(ns, nlb));
2923
2924 iocb->aiocb = blk_aio_preadv(ns->blkconf.blk, nvme_moff(ns, slba),
2925 &iocb->iov, 0, nvme_copy_in_completed_cb,
2926 iocb);
2927 return;
2928
2929 out:
2930 nvme_copy_cb(iocb, iocb->ret);
2931 }
2932
2933 static void nvme_copy_cb(void *opaque, int ret)
2934 {
2935 NvmeCopyAIOCB *iocb = opaque;
2936 NvmeRequest *req = iocb->req;
2937 NvmeNamespace *ns = req->ns;
2938 uint64_t slba;
2939 uint32_t nlb;
2940 size_t len;
2941 uint16_t status;
2942
2943 if (ret < 0) {
2944 iocb->ret = ret;
2945 goto done;
2946 } else if (iocb->ret < 0) {
2947 goto done;
2948 }
2949
2950 if (iocb->idx == iocb->nr) {
2951 goto done;
2952 }
2953
2954 nvme_copy_source_range_parse(iocb->ranges, iocb->idx, iocb->format, &slba,
2955 &nlb, NULL, NULL, NULL);
2956 len = nvme_l2b(ns, nlb);
2957
2958 trace_pci_nvme_copy_source_range(slba, nlb);
2959
2960 if (nlb > le16_to_cpu(ns->id_ns.mssrl)) {
2961 status = NVME_CMD_SIZE_LIMIT | NVME_DNR;
2962 goto invalid;
2963 }
2964
2965 status = nvme_check_bounds(ns, slba, nlb);
2966 if (status) {
2967 goto invalid;
2968 }
2969
2970 if (NVME_ERR_REC_DULBE(ns->features.err_rec)) {
2971 status = nvme_check_dulbe(ns, slba, nlb);
2972 if (status) {
2973 goto invalid;
2974 }
2975 }
2976
2977 if (ns->params.zoned) {
2978 status = nvme_check_zone_read(ns, slba, nlb);
2979 if (status) {
2980 goto invalid;
2981 }
2982 }
2983
2984 qemu_iovec_reset(&iocb->iov);
2985 qemu_iovec_add(&iocb->iov, iocb->bounce, len);
2986
2987 iocb->aiocb = blk_aio_preadv(ns->blkconf.blk, nvme_l2b(ns, slba),
2988 &iocb->iov, 0, nvme_copy_in_cb, iocb);
2989 return;
2990
2991 invalid:
2992 req->status = status;
2993 done:
2994 iocb->aiocb = NULL;
2995 if (iocb->bh) {
2996 qemu_bh_schedule(iocb->bh);
2997 }
2998 }
2999
3000
3001 static uint16_t nvme_copy(NvmeCtrl *n, NvmeRequest *req)
3002 {
3003 NvmeNamespace *ns = req->ns;
3004 NvmeCopyCmd *copy = (NvmeCopyCmd *)&req->cmd;
3005 NvmeCopyAIOCB *iocb = blk_aio_get(&nvme_copy_aiocb_info, ns->blkconf.blk,
3006 nvme_misc_cb, req);
3007 uint16_t nr = copy->nr + 1;
3008 uint8_t format = copy->control[0] & 0xf;
3009 uint16_t prinfor = ((copy->control[0] >> 4) & 0xf);
3010 uint16_t prinfow = ((copy->control[2] >> 2) & 0xf);
3011 size_t len = sizeof(NvmeCopySourceRangeFormat0);
3012
3013 uint16_t status;
3014
3015 trace_pci_nvme_copy(nvme_cid(req), nvme_nsid(ns), nr, format);
3016
3017 iocb->ranges = NULL;
3018 iocb->zone = NULL;
3019
3020 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps) &&
3021 ((prinfor & NVME_PRINFO_PRACT) != (prinfow & NVME_PRINFO_PRACT))) {
3022 status = NVME_INVALID_FIELD | NVME_DNR;
3023 goto invalid;
3024 }
3025
3026 if (!(n->id_ctrl.ocfs & (1 << format))) {
3027 trace_pci_nvme_err_copy_invalid_format(format);
3028 status = NVME_INVALID_FIELD | NVME_DNR;
3029 goto invalid;
3030 }
3031
3032 if (nr > ns->id_ns.msrc + 1) {
3033 status = NVME_CMD_SIZE_LIMIT | NVME_DNR;
3034 goto invalid;
3035 }
3036
3037 if ((ns->pif == 0x0 && format != 0x0) ||
3038 (ns->pif != 0x0 && format != 0x1)) {
3039 status = NVME_INVALID_FORMAT | NVME_DNR;
3040 goto invalid;
3041 }
3042
3043 if (ns->pif) {
3044 len = sizeof(NvmeCopySourceRangeFormat1);
3045 }
3046
3047 iocb->format = format;
3048 iocb->ranges = g_malloc_n(nr, len);
3049 status = nvme_h2c(n, (uint8_t *)iocb->ranges, len * nr, req);
3050 if (status) {
3051 goto invalid;
3052 }
3053
3054 iocb->slba = le64_to_cpu(copy->sdlba);
3055
3056 if (ns->params.zoned) {
3057 iocb->zone = nvme_get_zone_by_slba(ns, iocb->slba);
3058 if (!iocb->zone) {
3059 status = NVME_LBA_RANGE | NVME_DNR;
3060 goto invalid;
3061 }
3062
3063 status = nvme_zrm_auto(n, ns, iocb->zone);
3064 if (status) {
3065 goto invalid;
3066 }
3067 }
3068
3069 iocb->req = req;
3070 iocb->bh = qemu_bh_new(nvme_copy_bh, iocb);
3071 iocb->ret = 0;
3072 iocb->nr = nr;
3073 iocb->idx = 0;
3074 iocb->reftag = le32_to_cpu(copy->reftag);
3075 iocb->reftag |= (uint64_t)le32_to_cpu(copy->cdw3) << 32;
3076 iocb->bounce = g_malloc_n(le16_to_cpu(ns->id_ns.mssrl),
3077 ns->lbasz + ns->lbaf.ms);
3078
3079 qemu_iovec_init(&iocb->iov, 1);
3080
3081 block_acct_start(blk_get_stats(ns->blkconf.blk), &iocb->acct.read, 0,
3082 BLOCK_ACCT_READ);
3083 block_acct_start(blk_get_stats(ns->blkconf.blk), &iocb->acct.write, 0,
3084 BLOCK_ACCT_WRITE);
3085
3086 req->aiocb = &iocb->common;
3087 nvme_copy_cb(iocb, 0);
3088
3089 return NVME_NO_COMPLETE;
3090
3091 invalid:
3092 g_free(iocb->ranges);
3093 qemu_aio_unref(iocb);
3094 return status;
3095 }
3096
3097 static uint16_t nvme_compare(NvmeCtrl *n, NvmeRequest *req)
3098 {
3099 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
3100 NvmeNamespace *ns = req->ns;
3101 BlockBackend *blk = ns->blkconf.blk;
3102 uint64_t slba = le64_to_cpu(rw->slba);
3103 uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
3104 uint8_t prinfo = NVME_RW_PRINFO(le16_to_cpu(rw->control));
3105 size_t data_len = nvme_l2b(ns, nlb);
3106 size_t len = data_len;
3107 int64_t offset = nvme_l2b(ns, slba);
3108 struct nvme_compare_ctx *ctx = NULL;
3109 uint16_t status;
3110
3111 trace_pci_nvme_compare(nvme_cid(req), nvme_nsid(ns), slba, nlb);
3112
3113 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps) && (prinfo & NVME_PRINFO_PRACT)) {
3114 return NVME_INVALID_PROT_INFO | NVME_DNR;
3115 }
3116
3117 if (nvme_ns_ext(ns)) {
3118 len += nvme_m2b(ns, nlb);
3119 }
3120
3121 status = nvme_check_mdts(n, len);
3122 if (status) {
3123 return status;
3124 }
3125
3126 status = nvme_check_bounds(ns, slba, nlb);
3127 if (status) {
3128 return status;
3129 }
3130
3131 if (NVME_ERR_REC_DULBE(ns->features.err_rec)) {
3132 status = nvme_check_dulbe(ns, slba, nlb);
3133 if (status) {
3134 return status;
3135 }
3136 }
3137
3138 status = nvme_map_dptr(n, &req->sg, len, &req->cmd);
3139 if (status) {
3140 return status;
3141 }
3142
3143 ctx = g_new(struct nvme_compare_ctx, 1);
3144 ctx->data.bounce = g_malloc(data_len);
3145
3146 req->opaque = ctx;
3147
3148 qemu_iovec_init(&ctx->data.iov, 1);
3149 qemu_iovec_add(&ctx->data.iov, ctx->data.bounce, data_len);
3150
3151 block_acct_start(blk_get_stats(blk), &req->acct, data_len,
3152 BLOCK_ACCT_READ);
3153 req->aiocb = blk_aio_preadv(blk, offset, &ctx->data.iov, 0,
3154 nvme_compare_data_cb, req);
3155
3156 return NVME_NO_COMPLETE;
3157 }
3158
3159 typedef struct NvmeFlushAIOCB {
3160 BlockAIOCB common;
3161 BlockAIOCB *aiocb;
3162 NvmeRequest *req;
3163 int ret;
3164
3165 NvmeNamespace *ns;
3166 uint32_t nsid;
3167 bool broadcast;
3168 } NvmeFlushAIOCB;
3169
3170 static void nvme_flush_cancel(BlockAIOCB *acb)
3171 {
3172 NvmeFlushAIOCB *iocb = container_of(acb, NvmeFlushAIOCB, common);
3173
3174 iocb->ret = -ECANCELED;
3175
3176 if (iocb->aiocb) {
3177 blk_aio_cancel_async(iocb->aiocb);
3178 iocb->aiocb = NULL;
3179 }
3180 }
3181
3182 static const AIOCBInfo nvme_flush_aiocb_info = {
3183 .aiocb_size = sizeof(NvmeFlushAIOCB),
3184 .cancel_async = nvme_flush_cancel,
3185 .get_aio_context = nvme_get_aio_context,
3186 };
3187
3188 static void nvme_do_flush(NvmeFlushAIOCB *iocb);
3189
3190 static void nvme_flush_ns_cb(void *opaque, int ret)
3191 {
3192 NvmeFlushAIOCB *iocb = opaque;
3193 NvmeNamespace *ns = iocb->ns;
3194
3195 if (ret < 0) {
3196 iocb->ret = ret;
3197 goto out;
3198 } else if (iocb->ret < 0) {
3199 goto out;
3200 }
3201
3202 if (ns) {
3203 trace_pci_nvme_flush_ns(iocb->nsid);
3204
3205 iocb->ns = NULL;
3206 iocb->aiocb = blk_aio_flush(ns->blkconf.blk, nvme_flush_ns_cb, iocb);
3207 return;
3208 }
3209
3210 out:
3211 nvme_do_flush(iocb);
3212 }
3213
3214 static void nvme_do_flush(NvmeFlushAIOCB *iocb)
3215 {
3216 NvmeRequest *req = iocb->req;
3217 NvmeCtrl *n = nvme_ctrl(req);
3218 int i;
3219
3220 if (iocb->ret < 0) {
3221 goto done;
3222 }
3223
3224 if (iocb->broadcast) {
3225 for (i = iocb->nsid + 1; i <= NVME_MAX_NAMESPACES; i++) {
3226 iocb->ns = nvme_ns(n, i);
3227 if (iocb->ns) {
3228 iocb->nsid = i;
3229 break;
3230 }
3231 }
3232 }
3233
3234 if (!iocb->ns) {
3235 goto done;
3236 }
3237
3238 nvme_flush_ns_cb(iocb, 0);
3239 return;
3240
3241 done:
3242 iocb->common.cb(iocb->common.opaque, iocb->ret);
3243 qemu_aio_unref(iocb);
3244 }
3245
3246 static uint16_t nvme_flush(NvmeCtrl *n, NvmeRequest *req)
3247 {
3248 NvmeFlushAIOCB *iocb;
3249 uint32_t nsid = le32_to_cpu(req->cmd.nsid);
3250 uint16_t status;
3251
3252 iocb = qemu_aio_get(&nvme_flush_aiocb_info, NULL, nvme_misc_cb, req);
3253
3254 iocb->req = req;
3255 iocb->ret = 0;
3256 iocb->ns = NULL;
3257 iocb->nsid = 0;
3258 iocb->broadcast = (nsid == NVME_NSID_BROADCAST);
3259
3260 if (!iocb->broadcast) {
3261 if (!nvme_nsid_valid(n, nsid)) {
3262 status = NVME_INVALID_NSID | NVME_DNR;
3263 goto out;
3264 }
3265
3266 iocb->ns = nvme_ns(n, nsid);
3267 if (!iocb->ns) {
3268 status = NVME_INVALID_FIELD | NVME_DNR;
3269 goto out;
3270 }
3271
3272 iocb->nsid = nsid;
3273 }
3274
3275 req->aiocb = &iocb->common;
3276 nvme_do_flush(iocb);
3277
3278 return NVME_NO_COMPLETE;
3279
3280 out:
3281 qemu_aio_unref(iocb);
3282
3283 return status;
3284 }
3285
3286 static uint16_t nvme_read(NvmeCtrl *n, NvmeRequest *req)
3287 {
3288 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
3289 NvmeNamespace *ns = req->ns;
3290 uint64_t slba = le64_to_cpu(rw->slba);
3291 uint32_t nlb = (uint32_t)le16_to_cpu(rw->nlb) + 1;
3292 uint8_t prinfo = NVME_RW_PRINFO(le16_to_cpu(rw->control));
3293 uint64_t data_size = nvme_l2b(ns, nlb);
3294 uint64_t mapped_size = data_size;
3295 uint64_t data_offset;
3296 BlockBackend *blk = ns->blkconf.blk;
3297 uint16_t status;
3298
3299 if (nvme_ns_ext(ns)) {
3300 mapped_size += nvme_m2b(ns, nlb);
3301
3302 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
3303 bool pract = prinfo & NVME_PRINFO_PRACT;
3304
3305 if (pract && ns->lbaf.ms == nvme_pi_tuple_size(ns)) {
3306 mapped_size = data_size;
3307 }
3308 }
3309 }
3310
3311 trace_pci_nvme_read(nvme_cid(req), nvme_nsid(ns), nlb, mapped_size, slba);
3312
3313 status = nvme_check_mdts(n, mapped_size);
3314 if (status) {
3315 goto invalid;
3316 }
3317
3318 status = nvme_check_bounds(ns, slba, nlb);
3319 if (status) {
3320 goto invalid;
3321 }
3322
3323 if (ns->params.zoned) {
3324 status = nvme_check_zone_read(ns, slba, nlb);
3325 if (status) {
3326 trace_pci_nvme_err_zone_read_not_ok(slba, nlb, status);
3327 goto invalid;
3328 }
3329 }
3330
3331 if (NVME_ERR_REC_DULBE(ns->features.err_rec)) {
3332 status = nvme_check_dulbe(ns, slba, nlb);
3333 if (status) {
3334 goto invalid;
3335 }
3336 }
3337
3338 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
3339 return nvme_dif_rw(n, req);
3340 }
3341
3342 status = nvme_map_data(n, nlb, req);
3343 if (status) {
3344 goto invalid;
3345 }
3346
3347 data_offset = nvme_l2b(ns, slba);
3348
3349 block_acct_start(blk_get_stats(blk), &req->acct, data_size,
3350 BLOCK_ACCT_READ);
3351 nvme_blk_read(blk, data_offset, nvme_rw_cb, req);
3352 return NVME_NO_COMPLETE;
3353
3354 invalid:
3355 block_acct_invalid(blk_get_stats(blk), BLOCK_ACCT_READ);
3356 return status | NVME_DNR;
3357 }
3358
3359 static uint16_t nvme_do_write(NvmeCtrl *n, NvmeRequest *req, bool append,
3360 bool wrz)
3361 {
3362 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
3363 NvmeNamespace *ns = req->ns;
3364 uint64_t slba = le64_to_cpu(rw->slba);
3365 uint32_t nlb = (uint32_t)le16_to_cpu(rw->nlb) + 1;
3366 uint16_t ctrl = le16_to_cpu(rw->control);
3367 uint8_t prinfo = NVME_RW_PRINFO(ctrl);
3368 uint64_t data_size = nvme_l2b(ns, nlb);
3369 uint64_t mapped_size = data_size;
3370 uint64_t data_offset;
3371 NvmeZone *zone;
3372 NvmeZonedResult *res = (NvmeZonedResult *)&req->cqe;
3373 BlockBackend *blk = ns->blkconf.blk;
3374 uint16_t status;
3375
3376 if (nvme_ns_ext(ns)) {
3377 mapped_size += nvme_m2b(ns, nlb);
3378
3379 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
3380 bool pract = prinfo & NVME_PRINFO_PRACT;
3381
3382 if (pract && ns->lbaf.ms == nvme_pi_tuple_size(ns)) {
3383 mapped_size -= nvme_m2b(ns, nlb);
3384 }
3385 }
3386 }
3387
3388 trace_pci_nvme_write(nvme_cid(req), nvme_io_opc_str(rw->opcode),
3389 nvme_nsid(ns), nlb, mapped_size, slba);
3390
3391 if (!wrz) {
3392 status = nvme_check_mdts(n, mapped_size);
3393 if (status) {
3394 goto invalid;
3395 }
3396 }
3397
3398 status = nvme_check_bounds(ns, slba, nlb);
3399 if (status) {
3400 goto invalid;
3401 }
3402
3403 if (ns->params.zoned) {
3404 zone = nvme_get_zone_by_slba(ns, slba);
3405 assert(zone);
3406
3407 if (append) {
3408 bool piremap = !!(ctrl & NVME_RW_PIREMAP);
3409
3410 if (unlikely(zone->d.za & NVME_ZA_ZRWA_VALID)) {
3411 return NVME_INVALID_ZONE_OP | NVME_DNR;
3412 }
3413
3414 if (unlikely(slba != zone->d.zslba)) {
3415 trace_pci_nvme_err_append_not_at_start(slba, zone->d.zslba);
3416 status = NVME_INVALID_FIELD;
3417 goto invalid;
3418 }
3419
3420 if (n->params.zasl &&
3421 data_size > (uint64_t)n->page_size << n->params.zasl) {
3422 trace_pci_nvme_err_zasl(data_size);
3423 return NVME_INVALID_FIELD | NVME_DNR;
3424 }
3425
3426 slba = zone->w_ptr;
3427 rw->slba = cpu_to_le64(slba);
3428 res->slba = cpu_to_le64(slba);
3429
3430 switch (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
3431 case NVME_ID_NS_DPS_TYPE_1:
3432 if (!piremap) {
3433 return NVME_INVALID_PROT_INFO | NVME_DNR;
3434 }
3435
3436 /* fallthrough */
3437
3438 case NVME_ID_NS_DPS_TYPE_2:
3439 if (piremap) {
3440 uint32_t reftag = le32_to_cpu(rw->reftag);
3441 rw->reftag = cpu_to_le32(reftag + (slba - zone->d.zslba));
3442 }
3443
3444 break;
3445
3446 case NVME_ID_NS_DPS_TYPE_3:
3447 if (piremap) {
3448 return NVME_INVALID_PROT_INFO | NVME_DNR;
3449 }
3450
3451 break;
3452 }
3453 }
3454
3455 status = nvme_check_zone_write(ns, zone, slba, nlb);
3456 if (status) {
3457 goto invalid;
3458 }
3459
3460 status = nvme_zrm_auto(n, ns, zone);
3461 if (status) {
3462 goto invalid;
3463 }
3464
3465 if (!(zone->d.za & NVME_ZA_ZRWA_VALID)) {
3466 zone->w_ptr += nlb;
3467 }
3468 }
3469
3470 data_offset = nvme_l2b(ns, slba);
3471
3472 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
3473 return nvme_dif_rw(n, req);
3474 }
3475
3476 if (!wrz) {
3477 status = nvme_map_data(n, nlb, req);
3478 if (status) {
3479 goto invalid;
3480 }
3481
3482 block_acct_start(blk_get_stats(blk), &req->acct, data_size,
3483 BLOCK_ACCT_WRITE);
3484 nvme_blk_write(blk, data_offset, nvme_rw_cb, req);
3485 } else {
3486 req->aiocb = blk_aio_pwrite_zeroes(blk, data_offset, data_size,
3487 BDRV_REQ_MAY_UNMAP, nvme_rw_cb,
3488 req);
3489 }
3490
3491 return NVME_NO_COMPLETE;
3492
3493 invalid:
3494 block_acct_invalid(blk_get_stats(blk), BLOCK_ACCT_WRITE);
3495 return status | NVME_DNR;
3496 }
3497
3498 static inline uint16_t nvme_write(NvmeCtrl *n, NvmeRequest *req)
3499 {
3500 return nvme_do_write(n, req, false, false);
3501 }
3502
3503 static inline uint16_t nvme_write_zeroes(NvmeCtrl *n, NvmeRequest *req)
3504 {
3505 return nvme_do_write(n, req, false, true);
3506 }
3507
3508 static inline uint16_t nvme_zone_append(NvmeCtrl *n, NvmeRequest *req)
3509 {
3510 return nvme_do_write(n, req, true, false);
3511 }
3512
3513 static uint16_t nvme_get_mgmt_zone_slba_idx(NvmeNamespace *ns, NvmeCmd *c,
3514 uint64_t *slba, uint32_t *zone_idx)
3515 {
3516 uint32_t dw10 = le32_to_cpu(c->cdw10);
3517 uint32_t dw11 = le32_to_cpu(c->cdw11);
3518
3519 if (!ns->params.zoned) {
3520 trace_pci_nvme_err_invalid_opc(c->opcode);
3521 return NVME_INVALID_OPCODE | NVME_DNR;
3522 }
3523
3524 *slba = ((uint64_t)dw11) << 32 | dw10;
3525 if (unlikely(*slba >= ns->id_ns.nsze)) {
3526 trace_pci_nvme_err_invalid_lba_range(*slba, 0, ns->id_ns.nsze);
3527 *slba = 0;
3528 return NVME_LBA_RANGE | NVME_DNR;
3529 }
3530
3531 *zone_idx = nvme_zone_idx(ns, *slba);
3532 assert(*zone_idx < ns->num_zones);
3533
3534 return NVME_SUCCESS;
3535 }
3536
3537 typedef uint16_t (*op_handler_t)(NvmeNamespace *, NvmeZone *, NvmeZoneState,
3538 NvmeRequest *);
3539
3540 enum NvmeZoneProcessingMask {
3541 NVME_PROC_CURRENT_ZONE = 0,
3542 NVME_PROC_OPENED_ZONES = 1 << 0,
3543 NVME_PROC_CLOSED_ZONES = 1 << 1,
3544 NVME_PROC_READ_ONLY_ZONES = 1 << 2,
3545 NVME_PROC_FULL_ZONES = 1 << 3,
3546 };
3547
3548 static uint16_t nvme_open_zone(NvmeNamespace *ns, NvmeZone *zone,
3549 NvmeZoneState state, NvmeRequest *req)
3550 {
3551 NvmeZoneSendCmd *cmd = (NvmeZoneSendCmd *)&req->cmd;
3552 int flags = 0;
3553
3554 if (cmd->zsflags & NVME_ZSFLAG_ZRWA_ALLOC) {
3555 uint16_t ozcs = le16_to_cpu(ns->id_ns_zoned->ozcs);
3556
3557 if (!(ozcs & NVME_ID_NS_ZONED_OZCS_ZRWASUP)) {
3558 return NVME_INVALID_ZONE_OP | NVME_DNR;
3559 }
3560
3561 if (zone->w_ptr % ns->zns.zrwafg) {
3562 return NVME_NOZRWA | NVME_DNR;
3563 }
3564
3565 flags = NVME_ZRM_ZRWA;
3566 }
3567
3568 return nvme_zrm_open_flags(nvme_ctrl(req), ns, zone, flags);
3569 }
3570
3571 static uint16_t nvme_close_zone(NvmeNamespace *ns, NvmeZone *zone,
3572 NvmeZoneState state, NvmeRequest *req)
3573 {
3574 return nvme_zrm_close(ns, zone);
3575 }
3576
3577 static uint16_t nvme_finish_zone(NvmeNamespace *ns, NvmeZone *zone,
3578 NvmeZoneState state, NvmeRequest *req)
3579 {
3580 return nvme_zrm_finish(ns, zone);
3581 }
3582
3583 static uint16_t nvme_offline_zone(NvmeNamespace *ns, NvmeZone *zone,
3584 NvmeZoneState state, NvmeRequest *req)
3585 {
3586 switch (state) {
3587 case NVME_ZONE_STATE_READ_ONLY:
3588 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_OFFLINE);
3589 /* fall through */
3590 case NVME_ZONE_STATE_OFFLINE:
3591 return NVME_SUCCESS;
3592 default:
3593 return NVME_ZONE_INVAL_TRANSITION;
3594 }
3595 }
3596
3597 static uint16_t nvme_set_zd_ext(NvmeNamespace *ns, NvmeZone *zone)
3598 {
3599 uint16_t status;
3600 uint8_t state = nvme_get_zone_state(zone);
3601
3602 if (state == NVME_ZONE_STATE_EMPTY) {
3603 status = nvme_aor_check(ns, 1, 0);
3604 if (status) {
3605 return status;
3606 }
3607 nvme_aor_inc_active(ns);
3608 zone->d.za |= NVME_ZA_ZD_EXT_VALID;
3609 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_CLOSED);
3610 return NVME_SUCCESS;
3611 }
3612
3613 return NVME_ZONE_INVAL_TRANSITION;
3614 }
3615
3616 static uint16_t nvme_bulk_proc_zone(NvmeNamespace *ns, NvmeZone *zone,
3617 enum NvmeZoneProcessingMask proc_mask,
3618 op_handler_t op_hndlr, NvmeRequest *req)
3619 {
3620 uint16_t status = NVME_SUCCESS;
3621 NvmeZoneState zs = nvme_get_zone_state(zone);
3622 bool proc_zone;
3623
3624 switch (zs) {
3625 case NVME_ZONE_STATE_IMPLICITLY_OPEN:
3626 case NVME_ZONE_STATE_EXPLICITLY_OPEN:
3627 proc_zone = proc_mask & NVME_PROC_OPENED_ZONES;
3628 break;
3629 case NVME_ZONE_STATE_CLOSED:
3630 proc_zone = proc_mask & NVME_PROC_CLOSED_ZONES;
3631 break;
3632 case NVME_ZONE_STATE_READ_ONLY:
3633 proc_zone = proc_mask & NVME_PROC_READ_ONLY_ZONES;
3634 break;
3635 case NVME_ZONE_STATE_FULL:
3636 proc_zone = proc_mask & NVME_PROC_FULL_ZONES;
3637 break;
3638 default:
3639 proc_zone = false;
3640 }
3641
3642 if (proc_zone) {
3643 status = op_hndlr(ns, zone, zs, req);
3644 }
3645
3646 return status;
3647 }
3648
3649 static uint16_t nvme_do_zone_op(NvmeNamespace *ns, NvmeZone *zone,
3650 enum NvmeZoneProcessingMask proc_mask,
3651 op_handler_t op_hndlr, NvmeRequest *req)
3652 {
3653 NvmeZone *next;
3654 uint16_t status = NVME_SUCCESS;
3655 int i;
3656
3657 if (!proc_mask) {
3658 status = op_hndlr(ns, zone, nvme_get_zone_state(zone), req);
3659 } else {
3660 if (proc_mask & NVME_PROC_CLOSED_ZONES) {
3661 QTAILQ_FOREACH_SAFE(zone, &ns->closed_zones, entry, next) {
3662 status = nvme_bulk_proc_zone(ns, zone, proc_mask, op_hndlr,
3663 req);
3664 if (status && status != NVME_NO_COMPLETE) {
3665 goto out;
3666 }
3667 }
3668 }
3669 if (proc_mask & NVME_PROC_OPENED_ZONES) {
3670 QTAILQ_FOREACH_SAFE(zone, &ns->imp_open_zones, entry, next) {
3671 status = nvme_bulk_proc_zone(ns, zone, proc_mask, op_hndlr,
3672 req);
3673 if (status && status != NVME_NO_COMPLETE) {
3674 goto out;
3675 }
3676 }
3677
3678 QTAILQ_FOREACH_SAFE(zone, &ns->exp_open_zones, entry, next) {
3679 status = nvme_bulk_proc_zone(ns, zone, proc_mask, op_hndlr,
3680 req);
3681 if (status && status != NVME_NO_COMPLETE) {
3682 goto out;
3683 }
3684 }
3685 }
3686 if (proc_mask & NVME_PROC_FULL_ZONES) {
3687 QTAILQ_FOREACH_SAFE(zone, &ns->full_zones, entry, next) {
3688 status = nvme_bulk_proc_zone(ns, zone, proc_mask, op_hndlr,
3689 req);
3690 if (status && status != NVME_NO_COMPLETE) {
3691 goto out;
3692 }
3693 }
3694 }
3695
3696 if (proc_mask & NVME_PROC_READ_ONLY_ZONES) {
3697 for (i = 0; i < ns->num_zones; i++, zone++) {
3698 status = nvme_bulk_proc_zone(ns, zone, proc_mask, op_hndlr,
3699 req);
3700 if (status && status != NVME_NO_COMPLETE) {
3701 goto out;
3702 }
3703 }
3704 }
3705 }
3706
3707 out:
3708 return status;
3709 }
3710
3711 typedef struct NvmeZoneResetAIOCB {
3712 BlockAIOCB common;
3713 BlockAIOCB *aiocb;
3714 NvmeRequest *req;
3715 QEMUBH *bh;
3716 int ret;
3717
3718 bool all;
3719 int idx;
3720 NvmeZone *zone;
3721 } NvmeZoneResetAIOCB;
3722
3723 static void nvme_zone_reset_cancel(BlockAIOCB *aiocb)
3724 {
3725 NvmeZoneResetAIOCB *iocb = container_of(aiocb, NvmeZoneResetAIOCB, common);
3726 NvmeRequest *req = iocb->req;
3727 NvmeNamespace *ns = req->ns;
3728
3729 iocb->idx = ns->num_zones;
3730
3731 iocb->ret = -ECANCELED;
3732
3733 if (iocb->aiocb) {
3734 blk_aio_cancel_async(iocb->aiocb);
3735 iocb->aiocb = NULL;
3736 }
3737 }
3738
3739 static const AIOCBInfo nvme_zone_reset_aiocb_info = {
3740 .aiocb_size = sizeof(NvmeZoneResetAIOCB),
3741 .cancel_async = nvme_zone_reset_cancel,
3742 };
3743
3744 static void nvme_zone_reset_bh(void *opaque)
3745 {
3746 NvmeZoneResetAIOCB *iocb = opaque;
3747
3748 iocb->common.cb(iocb->common.opaque, iocb->ret);
3749
3750 qemu_bh_delete(iocb->bh);
3751 iocb->bh = NULL;
3752 qemu_aio_unref(iocb);
3753 }
3754
3755 static void nvme_zone_reset_cb(void *opaque, int ret);
3756
3757 static void nvme_zone_reset_epilogue_cb(void *opaque, int ret)
3758 {
3759 NvmeZoneResetAIOCB *iocb = opaque;
3760 NvmeRequest *req = iocb->req;
3761 NvmeNamespace *ns = req->ns;
3762 int64_t moff;
3763 int count;
3764
3765 if (ret < 0) {
3766 nvme_zone_reset_cb(iocb, ret);
3767 return;
3768 }
3769
3770 if (!ns->lbaf.ms) {
3771 nvme_zone_reset_cb(iocb, 0);
3772 return;
3773 }
3774
3775 moff = nvme_moff(ns, iocb->zone->d.zslba);
3776 count = nvme_m2b(ns, ns->zone_size);
3777
3778 iocb->aiocb = blk_aio_pwrite_zeroes(ns->blkconf.blk, moff, count,
3779 BDRV_REQ_MAY_UNMAP,
3780 nvme_zone_reset_cb, iocb);
3781 return;
3782 }
3783
3784 static void nvme_zone_reset_cb(void *opaque, int ret)
3785 {
3786 NvmeZoneResetAIOCB *iocb = opaque;
3787 NvmeRequest *req = iocb->req;
3788 NvmeNamespace *ns = req->ns;
3789
3790 if (ret < 0) {
3791 iocb->ret = ret;
3792 goto done;
3793 }
3794
3795 if (iocb->zone) {
3796 nvme_zrm_reset(ns, iocb->zone);
3797
3798 if (!iocb->all) {
3799 goto done;
3800 }
3801 }
3802
3803 while (iocb->idx < ns->num_zones) {
3804 NvmeZone *zone = &ns->zone_array[iocb->idx++];
3805
3806 switch (nvme_get_zone_state(zone)) {
3807 case NVME_ZONE_STATE_EMPTY:
3808 if (!iocb->all) {
3809 goto done;
3810 }
3811
3812 continue;
3813
3814 case NVME_ZONE_STATE_EXPLICITLY_OPEN:
3815 case NVME_ZONE_STATE_IMPLICITLY_OPEN:
3816 case NVME_ZONE_STATE_CLOSED:
3817 case NVME_ZONE_STATE_FULL:
3818 iocb->zone = zone;
3819 break;
3820
3821 default:
3822 continue;
3823 }
3824
3825 trace_pci_nvme_zns_zone_reset(zone->d.zslba);
3826
3827 iocb->aiocb = blk_aio_pwrite_zeroes(ns->blkconf.blk,
3828 nvme_l2b(ns, zone->d.zslba),
3829 nvme_l2b(ns, ns->zone_size),
3830 BDRV_REQ_MAY_UNMAP,
3831 nvme_zone_reset_epilogue_cb,
3832 iocb);
3833 return;
3834 }
3835
3836 done:
3837 iocb->aiocb = NULL;
3838 if (iocb->bh) {
3839 qemu_bh_schedule(iocb->bh);
3840 }
3841 }
3842
3843 static uint16_t nvme_zone_mgmt_send_zrwa_flush(NvmeCtrl *n, NvmeZone *zone,
3844 uint64_t elba, NvmeRequest *req)
3845 {
3846 NvmeNamespace *ns = req->ns;
3847 uint16_t ozcs = le16_to_cpu(ns->id_ns_zoned->ozcs);
3848 uint64_t wp = zone->d.wp;
3849 uint32_t nlb = elba - wp + 1;
3850 uint16_t status;
3851
3852
3853 if (!(ozcs & NVME_ID_NS_ZONED_OZCS_ZRWASUP)) {
3854 return NVME_INVALID_ZONE_OP | NVME_DNR;
3855 }
3856
3857 if (!(zone->d.za & NVME_ZA_ZRWA_VALID)) {
3858 return NVME_INVALID_FIELD | NVME_DNR;
3859 }
3860
3861 if (elba < wp || elba > wp + ns->zns.zrwas) {
3862 return NVME_ZONE_BOUNDARY_ERROR | NVME_DNR;
3863 }
3864
3865 if (nlb % ns->zns.zrwafg) {
3866 return NVME_INVALID_FIELD | NVME_DNR;
3867 }
3868
3869 status = nvme_zrm_auto(n, ns, zone);
3870 if (status) {
3871 return status;
3872 }
3873
3874 zone->w_ptr += nlb;
3875
3876 nvme_advance_zone_wp(ns, zone, nlb);
3877
3878 return NVME_SUCCESS;
3879 }
3880
3881 static uint16_t nvme_zone_mgmt_send(NvmeCtrl *n, NvmeRequest *req)
3882 {
3883 NvmeZoneSendCmd *cmd = (NvmeZoneSendCmd *)&req->cmd;
3884 NvmeNamespace *ns = req->ns;
3885 NvmeZone *zone;
3886 NvmeZoneResetAIOCB *iocb;
3887 uint8_t *zd_ext;
3888 uint64_t slba = 0;
3889 uint32_t zone_idx = 0;
3890 uint16_t status;
3891 uint8_t action = cmd->zsa;
3892 bool all;
3893 enum NvmeZoneProcessingMask proc_mask = NVME_PROC_CURRENT_ZONE;
3894
3895 all = cmd->zsflags & NVME_ZSFLAG_SELECT_ALL;
3896
3897 req->status = NVME_SUCCESS;
3898
3899 if (!all) {
3900 status = nvme_get_mgmt_zone_slba_idx(ns, &req->cmd, &slba, &zone_idx);
3901 if (status) {
3902 return status;
3903 }
3904 }
3905
3906 zone = &ns->zone_array[zone_idx];
3907 if (slba != zone->d.zslba && action != NVME_ZONE_ACTION_ZRWA_FLUSH) {
3908 trace_pci_nvme_err_unaligned_zone_cmd(action, slba, zone->d.zslba);
3909 return NVME_INVALID_FIELD | NVME_DNR;
3910 }
3911
3912 switch (action) {
3913
3914 case NVME_ZONE_ACTION_OPEN:
3915 if (all) {
3916 proc_mask = NVME_PROC_CLOSED_ZONES;
3917 }
3918 trace_pci_nvme_open_zone(slba, zone_idx, all);
3919 status = nvme_do_zone_op(ns, zone, proc_mask, nvme_open_zone, req);
3920 break;
3921
3922 case NVME_ZONE_ACTION_CLOSE:
3923 if (all) {
3924 proc_mask = NVME_PROC_OPENED_ZONES;
3925 }
3926 trace_pci_nvme_close_zone(slba, zone_idx, all);
3927 status = nvme_do_zone_op(ns, zone, proc_mask, nvme_close_zone, req);
3928 break;
3929
3930 case NVME_ZONE_ACTION_FINISH:
3931 if (all) {
3932 proc_mask = NVME_PROC_OPENED_ZONES | NVME_PROC_CLOSED_ZONES;
3933 }
3934 trace_pci_nvme_finish_zone(slba, zone_idx, all);
3935 status = nvme_do_zone_op(ns, zone, proc_mask, nvme_finish_zone, req);
3936 break;
3937
3938 case NVME_ZONE_ACTION_RESET:
3939 trace_pci_nvme_reset_zone(slba, zone_idx, all);
3940
3941 iocb = blk_aio_get(&nvme_zone_reset_aiocb_info, ns->blkconf.blk,
3942 nvme_misc_cb, req);
3943
3944 iocb->req = req;
3945 iocb->bh = qemu_bh_new(nvme_zone_reset_bh, iocb);
3946 iocb->ret = 0;
3947 iocb->all = all;
3948 iocb->idx = zone_idx;
3949 iocb->zone = NULL;
3950
3951 req->aiocb = &iocb->common;
3952 nvme_zone_reset_cb(iocb, 0);
3953
3954 return NVME_NO_COMPLETE;
3955
3956 case NVME_ZONE_ACTION_OFFLINE:
3957 if (all) {
3958 proc_mask = NVME_PROC_READ_ONLY_ZONES;
3959 }
3960 trace_pci_nvme_offline_zone(slba, zone_idx, all);
3961 status = nvme_do_zone_op(ns, zone, proc_mask, nvme_offline_zone, req);
3962 break;
3963
3964 case NVME_ZONE_ACTION_SET_ZD_EXT:
3965 trace_pci_nvme_set_descriptor_extension(slba, zone_idx);
3966 if (all || !ns->params.zd_extension_size) {
3967 return NVME_INVALID_FIELD | NVME_DNR;
3968 }
3969 zd_ext = nvme_get_zd_extension(ns, zone_idx);
3970 status = nvme_h2c(n, zd_ext, ns->params.zd_extension_size, req);
3971 if (status) {
3972 trace_pci_nvme_err_zd_extension_map_error(zone_idx);
3973 return status;
3974 }
3975
3976 status = nvme_set_zd_ext(ns, zone);
3977 if (status == NVME_SUCCESS) {
3978 trace_pci_nvme_zd_extension_set(zone_idx);
3979 return status;
3980 }
3981 break;
3982
3983 case NVME_ZONE_ACTION_ZRWA_FLUSH:
3984 if (all) {
3985 return NVME_INVALID_FIELD | NVME_DNR;
3986 }
3987
3988 return nvme_zone_mgmt_send_zrwa_flush(n, zone, slba, req);
3989
3990 default:
3991 trace_pci_nvme_err_invalid_mgmt_action(action);
3992 status = NVME_INVALID_FIELD;
3993 }
3994
3995 if (status == NVME_ZONE_INVAL_TRANSITION) {
3996 trace_pci_nvme_err_invalid_zone_state_transition(action, slba,
3997 zone->d.za);
3998 }
3999 if (status) {
4000 status |= NVME_DNR;
4001 }
4002
4003 return status;
4004 }
4005
4006 static bool nvme_zone_matches_filter(uint32_t zafs, NvmeZone *zl)
4007 {
4008 NvmeZoneState zs = nvme_get_zone_state(zl);
4009
4010 switch (zafs) {
4011 case NVME_ZONE_REPORT_ALL:
4012 return true;
4013 case NVME_ZONE_REPORT_EMPTY:
4014 return zs == NVME_ZONE_STATE_EMPTY;
4015 case NVME_ZONE_REPORT_IMPLICITLY_OPEN:
4016 return zs == NVME_ZONE_STATE_IMPLICITLY_OPEN;
4017 case NVME_ZONE_REPORT_EXPLICITLY_OPEN:
4018 return zs == NVME_ZONE_STATE_EXPLICITLY_OPEN;
4019 case NVME_ZONE_REPORT_CLOSED:
4020 return zs == NVME_ZONE_STATE_CLOSED;
4021 case NVME_ZONE_REPORT_FULL:
4022 return zs == NVME_ZONE_STATE_FULL;
4023 case NVME_ZONE_REPORT_READ_ONLY:
4024 return zs == NVME_ZONE_STATE_READ_ONLY;
4025 case NVME_ZONE_REPORT_OFFLINE:
4026 return zs == NVME_ZONE_STATE_OFFLINE;
4027 default:
4028 return false;
4029 }
4030 }
4031
4032 static uint16_t nvme_zone_mgmt_recv(NvmeCtrl *n, NvmeRequest *req)
4033 {
4034 NvmeCmd *cmd = (NvmeCmd *)&req->cmd;
4035 NvmeNamespace *ns = req->ns;
4036 /* cdw12 is zero-based number of dwords to return. Convert to bytes */
4037 uint32_t data_size = (le32_to_cpu(cmd->cdw12) + 1) << 2;
4038 uint32_t dw13 = le32_to_cpu(cmd->cdw13);
4039 uint32_t zone_idx, zra, zrasf, partial;
4040 uint64_t max_zones, nr_zones = 0;
4041 uint16_t status;
4042 uint64_t slba;
4043 NvmeZoneDescr *z;
4044 NvmeZone *zone;
4045 NvmeZoneReportHeader *header;
4046 void *buf, *buf_p;
4047 size_t zone_entry_sz;
4048 int i;
4049
4050 req->status = NVME_SUCCESS;
4051
4052 status = nvme_get_mgmt_zone_slba_idx(ns, cmd, &slba, &zone_idx);
4053 if (status) {
4054 return status;
4055 }
4056
4057 zra = dw13 & 0xff;
4058 if (zra != NVME_ZONE_REPORT && zra != NVME_ZONE_REPORT_EXTENDED) {
4059 return NVME_INVALID_FIELD | NVME_DNR;
4060 }
4061 if (zra == NVME_ZONE_REPORT_EXTENDED && !ns->params.zd_extension_size) {
4062 return NVME_INVALID_FIELD | NVME_DNR;
4063 }
4064
4065 zrasf = (dw13 >> 8) & 0xff;
4066 if (zrasf > NVME_ZONE_REPORT_OFFLINE) {
4067 return NVME_INVALID_FIELD | NVME_DNR;
4068 }
4069
4070 if (data_size < sizeof(NvmeZoneReportHeader)) {
4071 return NVME_INVALID_FIELD | NVME_DNR;
4072 }
4073
4074 status = nvme_check_mdts(n, data_size);
4075 if (status) {
4076 return status;
4077 }
4078
4079 partial = (dw13 >> 16) & 0x01;
4080
4081 zone_entry_sz = sizeof(NvmeZoneDescr);
4082 if (zra == NVME_ZONE_REPORT_EXTENDED) {
4083 zone_entry_sz += ns->params.zd_extension_size;
4084 }
4085
4086 max_zones = (data_size - sizeof(NvmeZoneReportHeader)) / zone_entry_sz;
4087 buf = g_malloc0(data_size);
4088
4089 zone = &ns->zone_array[zone_idx];
4090 for (i = zone_idx; i < ns->num_zones; i++) {
4091 if (partial && nr_zones >= max_zones) {
4092 break;
4093 }
4094 if (nvme_zone_matches_filter(zrasf, zone++)) {
4095 nr_zones++;
4096 }
4097 }
4098 header = (NvmeZoneReportHeader *)buf;
4099 header->nr_zones = cpu_to_le64(nr_zones);
4100
4101 buf_p = buf + sizeof(NvmeZoneReportHeader);
4102 for (; zone_idx < ns->num_zones && max_zones > 0; zone_idx++) {
4103 zone = &ns->zone_array[zone_idx];
4104 if (nvme_zone_matches_filter(zrasf, zone)) {
4105 z = (NvmeZoneDescr *)buf_p;
4106 buf_p += sizeof(NvmeZoneDescr);
4107
4108 z->zt = zone->d.zt;
4109 z->zs = zone->d.zs;
4110 z->zcap = cpu_to_le64(zone->d.zcap);
4111 z->zslba = cpu_to_le64(zone->d.zslba);
4112 z->za = zone->d.za;
4113
4114 if (nvme_wp_is_valid(zone)) {
4115 z->wp = cpu_to_le64(zone->d.wp);
4116 } else {
4117 z->wp = cpu_to_le64(~0ULL);
4118 }
4119
4120 if (zra == NVME_ZONE_REPORT_EXTENDED) {
4121 if (zone->d.za & NVME_ZA_ZD_EXT_VALID) {
4122 memcpy(buf_p, nvme_get_zd_extension(ns, zone_idx),
4123 ns->params.zd_extension_size);
4124 }
4125 buf_p += ns->params.zd_extension_size;
4126 }
4127
4128 max_zones--;
4129 }
4130 }
4131
4132 status = nvme_c2h(n, (uint8_t *)buf, data_size, req);
4133
4134 g_free(buf);
4135
4136 return status;
4137 }
4138
4139 static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
4140 {
4141 NvmeNamespace *ns;
4142 uint32_t nsid = le32_to_cpu(req->cmd.nsid);
4143
4144 trace_pci_nvme_io_cmd(nvme_cid(req), nsid, nvme_sqid(req),
4145 req->cmd.opcode, nvme_io_opc_str(req->cmd.opcode));
4146
4147 if (!nvme_nsid_valid(n, nsid)) {
4148 return NVME_INVALID_NSID | NVME_DNR;
4149 }
4150
4151 /*
4152 * In the base NVM command set, Flush may apply to all namespaces
4153 * (indicated by NSID being set to FFFFFFFFh). But if that feature is used
4154 * along with TP 4056 (Namespace Types), it may be pretty screwed up.
4155 *
4156 * If NSID is indeed set to FFFFFFFFh, we simply cannot associate the
4157 * opcode with a specific command since we cannot determine a unique I/O
4158 * command set. Opcode 0h could have any other meaning than something
4159 * equivalent to flushing and say it DOES have completely different
4160 * semantics in some other command set - does an NSID of FFFFFFFFh then
4161 * mean "for all namespaces, apply whatever command set specific command
4162 * that uses the 0h opcode?" Or does it mean "for all namespaces, apply
4163 * whatever command that uses the 0h opcode if, and only if, it allows NSID
4164 * to be FFFFFFFFh"?
4165 *
4166 * Anyway (and luckily), for now, we do not care about this since the
4167 * device only supports namespace types that includes the NVM Flush command
4168 * (NVM and Zoned), so always do an NVM Flush.
4169 */
4170 if (req->cmd.opcode == NVME_CMD_FLUSH) {
4171 return nvme_flush(n, req);
4172 }
4173
4174 ns = nvme_ns(n, nsid);
4175 if (unlikely(!ns)) {
4176 return NVME_INVALID_FIELD | NVME_DNR;
4177 }
4178
4179 if (!(ns->iocs[req->cmd.opcode] & NVME_CMD_EFF_CSUPP)) {
4180 trace_pci_nvme_err_invalid_opc(req->cmd.opcode);
4181 return NVME_INVALID_OPCODE | NVME_DNR;
4182 }
4183
4184 if (ns->status) {
4185 return ns->status;
4186 }
4187
4188 if (NVME_CMD_FLAGS_FUSE(req->cmd.flags)) {
4189 return NVME_INVALID_FIELD;
4190 }
4191
4192 req->ns = ns;
4193
4194 switch (req->cmd.opcode) {
4195 case NVME_CMD_WRITE_ZEROES:
4196 return nvme_write_zeroes(n, req);
4197 case NVME_CMD_ZONE_APPEND:
4198 return nvme_zone_append(n, req);
4199 case NVME_CMD_WRITE:
4200 return nvme_write(n, req);
4201 case NVME_CMD_READ:
4202 return nvme_read(n, req);
4203 case NVME_CMD_COMPARE:
4204 return nvme_compare(n, req);
4205 case NVME_CMD_DSM:
4206 return nvme_dsm(n, req);
4207 case NVME_CMD_VERIFY:
4208 return nvme_verify(n, req);
4209 case NVME_CMD_COPY:
4210 return nvme_copy(n, req);
4211 case NVME_CMD_ZONE_MGMT_SEND:
4212 return nvme_zone_mgmt_send(n, req);
4213 case NVME_CMD_ZONE_MGMT_RECV:
4214 return nvme_zone_mgmt_recv(n, req);
4215 default:
4216 assert(false);
4217 }
4218
4219 return NVME_INVALID_OPCODE | NVME_DNR;
4220 }
4221
4222 static void nvme_cq_notifier(EventNotifier *e)
4223 {
4224 NvmeCQueue *cq = container_of(e, NvmeCQueue, notifier);
4225 NvmeCtrl *n = cq->ctrl;
4226
4227 if (!event_notifier_test_and_clear(e)) {
4228 return;
4229 }
4230
4231 nvme_update_cq_head(cq);
4232
4233 if (cq->tail == cq->head) {
4234 if (cq->irq_enabled) {
4235 n->cq_pending--;
4236 }
4237
4238 nvme_irq_deassert(n, cq);
4239 }
4240
4241 qemu_bh_schedule(cq->bh);
4242 }
4243
4244 static int nvme_init_cq_ioeventfd(NvmeCQueue *cq)
4245 {
4246 NvmeCtrl *n = cq->ctrl;
4247 uint16_t offset = (cq->cqid << 3) + (1 << 2);
4248 int ret;
4249
4250 ret = event_notifier_init(&cq->notifier, 0);
4251 if (ret < 0) {
4252 return ret;
4253 }
4254
4255 event_notifier_set_handler(&cq->notifier, nvme_cq_notifier);
4256 memory_region_add_eventfd(&n->iomem,
4257 0x1000 + offset, 4, false, 0, &cq->notifier);
4258
4259 return 0;
4260 }
4261
4262 static void nvme_sq_notifier(EventNotifier *e)
4263 {
4264 NvmeSQueue *sq = container_of(e, NvmeSQueue, notifier);
4265
4266 if (!event_notifier_test_and_clear(e)) {
4267 return;
4268 }
4269
4270 nvme_process_sq(sq);
4271 }
4272
4273 static int nvme_init_sq_ioeventfd(NvmeSQueue *sq)
4274 {
4275 NvmeCtrl *n = sq->ctrl;
4276 uint16_t offset = sq->sqid << 3;
4277 int ret;
4278
4279 ret = event_notifier_init(&sq->notifier, 0);
4280 if (ret < 0) {
4281 return ret;
4282 }
4283
4284 event_notifier_set_handler(&sq->notifier, nvme_sq_notifier);
4285 memory_region_add_eventfd(&n->iomem,
4286 0x1000 + offset, 4, false, 0, &sq->notifier);
4287
4288 return 0;
4289 }
4290
4291 static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
4292 {
4293 uint16_t offset = sq->sqid << 3;
4294
4295 n->sq[sq->sqid] = NULL;
4296 qemu_bh_delete(sq->bh);
4297 if (sq->ioeventfd_enabled) {
4298 memory_region_del_eventfd(&n->iomem,
4299 0x1000 + offset, 4, false, 0, &sq->notifier);
4300 event_notifier_set_handler(&sq->notifier, NULL);
4301 event_notifier_cleanup(&sq->notifier);
4302 }
4303 g_free(sq->io_req);
4304 if (sq->sqid) {
4305 g_free(sq);
4306 }
4307 }
4308
4309 static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeRequest *req)
4310 {
4311 NvmeDeleteQ *c = (NvmeDeleteQ *)&req->cmd;
4312 NvmeRequest *r, *next;
4313 NvmeSQueue *sq;
4314 NvmeCQueue *cq;
4315 uint16_t qid = le16_to_cpu(c->qid);
4316
4317 if (unlikely(!qid || nvme_check_sqid(n, qid))) {
4318 trace_pci_nvme_err_invalid_del_sq(qid);
4319 return NVME_INVALID_QID | NVME_DNR;
4320 }
4321
4322 trace_pci_nvme_del_sq(qid);
4323
4324 sq = n->sq[qid];
4325 while (!QTAILQ_EMPTY(&sq->out_req_list)) {
4326 r = QTAILQ_FIRST(&sq->out_req_list);
4327 assert(r->aiocb);
4328 blk_aio_cancel(r->aiocb);
4329 }
4330
4331 assert(QTAILQ_EMPTY(&sq->out_req_list));
4332
4333 if (!nvme_check_cqid(n, sq->cqid)) {
4334 cq = n->cq[sq->cqid];
4335 QTAILQ_REMOVE(&cq->sq_list, sq, entry);
4336
4337 nvme_post_cqes(cq);
4338 QTAILQ_FOREACH_SAFE(r, &cq->req_list, entry, next) {
4339 if (r->sq == sq) {
4340 QTAILQ_REMOVE(&cq->req_list, r, entry);
4341 QTAILQ_INSERT_TAIL(&sq->req_list, r, entry);
4342 }
4343 }
4344 }
4345
4346 nvme_free_sq(sq, n);
4347 return NVME_SUCCESS;
4348 }
4349
4350 static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
4351 uint16_t sqid, uint16_t cqid, uint16_t size)
4352 {
4353 int i;
4354 NvmeCQueue *cq;
4355
4356 sq->ctrl = n;
4357 sq->dma_addr = dma_addr;
4358 sq->sqid = sqid;
4359 sq->size = size;
4360 sq->cqid = cqid;
4361 sq->head = sq->tail = 0;
4362 sq->io_req = g_new0(NvmeRequest, sq->size);
4363
4364 QTAILQ_INIT(&sq->req_list);
4365 QTAILQ_INIT(&sq->out_req_list);
4366 for (i = 0; i < sq->size; i++) {
4367 sq->io_req[i].sq = sq;
4368 QTAILQ_INSERT_TAIL(&(sq->req_list), &sq->io_req[i], entry);
4369 }
4370
4371 sq->bh = qemu_bh_new(nvme_process_sq, sq);
4372
4373 if (n->dbbuf_enabled) {
4374 sq->db_addr = n->dbbuf_dbs + (sqid << 3);
4375 sq->ei_addr = n->dbbuf_eis + (sqid << 3);
4376
4377 if (n->params.ioeventfd && sq->sqid != 0) {
4378 if (!nvme_init_sq_ioeventfd(sq)) {
4379 sq->ioeventfd_enabled = true;
4380 }
4381 }
4382 }
4383
4384 assert(n->cq[cqid]);
4385 cq = n->cq[cqid];
4386 QTAILQ_INSERT_TAIL(&(cq->sq_list), sq, entry);
4387 n->sq[sqid] = sq;
4388 }
4389
4390 static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeRequest *req)
4391 {
4392 NvmeSQueue *sq;
4393 NvmeCreateSq *c = (NvmeCreateSq *)&req->cmd;
4394
4395 uint16_t cqid = le16_to_cpu(c->cqid);
4396 uint16_t sqid = le16_to_cpu(c->sqid);
4397 uint16_t qsize = le16_to_cpu(c->qsize);
4398 uint16_t qflags = le16_to_cpu(c->sq_flags);
4399 uint64_t prp1 = le64_to_cpu(c->prp1);
4400
4401 trace_pci_nvme_create_sq(prp1, sqid, cqid, qsize, qflags);
4402
4403 if (unlikely(!cqid || nvme_check_cqid(n, cqid))) {
4404 trace_pci_nvme_err_invalid_create_sq_cqid(cqid);
4405 return NVME_INVALID_CQID | NVME_DNR;
4406 }
4407 if (unlikely(!sqid || sqid > n->conf_ioqpairs || n->sq[sqid] != NULL)) {
4408 trace_pci_nvme_err_invalid_create_sq_sqid(sqid);
4409 return NVME_INVALID_QID | NVME_DNR;
4410 }
4411 if (unlikely(!qsize || qsize > NVME_CAP_MQES(ldq_le_p(&n->bar.cap)))) {
4412 trace_pci_nvme_err_invalid_create_sq_size(qsize);
4413 return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
4414 }
4415 if (unlikely(prp1 & (n->page_size - 1))) {
4416 trace_pci_nvme_err_invalid_create_sq_addr(prp1);
4417 return NVME_INVALID_PRP_OFFSET | NVME_DNR;
4418 }
4419 if (unlikely(!(NVME_SQ_FLAGS_PC(qflags)))) {
4420 trace_pci_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflags));
4421 return NVME_INVALID_FIELD | NVME_DNR;
4422 }
4423 sq = g_malloc0(sizeof(*sq));
4424 nvme_init_sq(sq, n, prp1, sqid, cqid, qsize + 1);
4425 return NVME_SUCCESS;
4426 }
4427
4428 struct nvme_stats {
4429 uint64_t units_read;
4430 uint64_t units_written;
4431 uint64_t read_commands;
4432 uint64_t write_commands;
4433 };
4434
4435 static void nvme_set_blk_stats(NvmeNamespace *ns, struct nvme_stats *stats)
4436 {
4437 BlockAcctStats *s = blk_get_stats(ns->blkconf.blk);
4438
4439 stats->units_read += s->nr_bytes[BLOCK_ACCT_READ] >> BDRV_SECTOR_BITS;
4440 stats->units_written += s->nr_bytes[BLOCK_ACCT_WRITE] >> BDRV_SECTOR_BITS;
4441 stats->read_commands += s->nr_ops[BLOCK_ACCT_READ];
4442 stats->write_commands += s->nr_ops[BLOCK_ACCT_WRITE];
4443 }
4444
4445 static uint16_t nvme_smart_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
4446 uint64_t off, NvmeRequest *req)
4447 {
4448 uint32_t nsid = le32_to_cpu(req->cmd.nsid);
4449 struct nvme_stats stats = { 0 };
4450 NvmeSmartLog smart = { 0 };
4451 uint32_t trans_len;
4452 NvmeNamespace *ns;
4453 time_t current_ms;
4454
4455 if (off >= sizeof(smart)) {
4456 return NVME_INVALID_FIELD | NVME_DNR;
4457 }
4458
4459 if (nsid != 0xffffffff) {
4460 ns = nvme_ns(n, nsid);
4461 if (!ns) {
4462 return NVME_INVALID_NSID | NVME_DNR;
4463 }
4464 nvme_set_blk_stats(ns, &stats);
4465 } else {
4466 int i;
4467
4468 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
4469 ns = nvme_ns(n, i);
4470 if (!ns) {
4471 continue;
4472 }
4473 nvme_set_blk_stats(ns, &stats);
4474 }
4475 }
4476
4477 trans_len = MIN(sizeof(smart) - off, buf_len);
4478 smart.critical_warning = n->smart_critical_warning;
4479
4480 smart.data_units_read[0] = cpu_to_le64(DIV_ROUND_UP(stats.units_read,
4481 1000));
4482 smart.data_units_written[0] = cpu_to_le64(DIV_ROUND_UP(stats.units_written,
4483 1000));
4484 smart.host_read_commands[0] = cpu_to_le64(stats.read_commands);
4485 smart.host_write_commands[0] = cpu_to_le64(stats.write_commands);
4486
4487 smart.temperature = cpu_to_le16(n->temperature);
4488
4489 if ((n->temperature >= n->features.temp_thresh_hi) ||
4490 (n->temperature <= n->features.temp_thresh_low)) {
4491 smart.critical_warning |= NVME_SMART_TEMPERATURE;
4492 }
4493
4494 current_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
4495 smart.power_on_hours[0] =
4496 cpu_to_le64((((current_ms - n->starttime_ms) / 1000) / 60) / 60);
4497
4498 if (!rae) {
4499 nvme_clear_events(n, NVME_AER_TYPE_SMART);
4500 }
4501
4502 return nvme_c2h(n, (uint8_t *) &smart + off, trans_len, req);
4503 }
4504
4505 static uint16_t nvme_fw_log_info(NvmeCtrl *n, uint32_t buf_len, uint64_t off,
4506 NvmeRequest *req)
4507 {
4508 uint32_t trans_len;
4509 NvmeFwSlotInfoLog fw_log = {
4510 .afi = 0x1,
4511 };
4512
4513 if (off >= sizeof(fw_log)) {
4514 return NVME_INVALID_FIELD | NVME_DNR;
4515 }
4516
4517 strpadcpy((char *)&fw_log.frs1, sizeof(fw_log.frs1), "1.0", ' ');
4518 trans_len = MIN(sizeof(fw_log) - off, buf_len);
4519
4520 return nvme_c2h(n, (uint8_t *) &fw_log + off, trans_len, req);
4521 }
4522
4523 static uint16_t nvme_error_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
4524 uint64_t off, NvmeRequest *req)
4525 {
4526 uint32_t trans_len;
4527 NvmeErrorLog errlog;
4528
4529 if (off >= sizeof(errlog)) {
4530 return NVME_INVALID_FIELD | NVME_DNR;
4531 }
4532
4533 if (!rae) {
4534 nvme_clear_events(n, NVME_AER_TYPE_ERROR);
4535 }
4536
4537 memset(&errlog, 0x0, sizeof(errlog));
4538 trans_len = MIN(sizeof(errlog) - off, buf_len);
4539
4540 return nvme_c2h(n, (uint8_t *)&errlog, trans_len, req);
4541 }
4542
4543 static uint16_t nvme_changed_nslist(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
4544 uint64_t off, NvmeRequest *req)
4545 {
4546 uint32_t nslist[1024];
4547 uint32_t trans_len;
4548 int i = 0;
4549 uint32_t nsid;
4550
4551 if (off >= sizeof(nslist)) {
4552 trace_pci_nvme_err_invalid_log_page_offset(off, sizeof(nslist));
4553 return NVME_INVALID_FIELD | NVME_DNR;
4554 }
4555
4556 memset(nslist, 0x0, sizeof(nslist));
4557 trans_len = MIN(sizeof(nslist) - off, buf_len);
4558
4559 while ((nsid = find_first_bit(n->changed_nsids, NVME_CHANGED_NSID_SIZE)) !=
4560 NVME_CHANGED_NSID_SIZE) {
4561 /*
4562 * If more than 1024 namespaces, the first entry in the log page should
4563 * be set to FFFFFFFFh and the others to 0 as spec.
4564 */
4565 if (i == ARRAY_SIZE(nslist)) {
4566 memset(nslist, 0x0, sizeof(nslist));
4567 nslist[0] = 0xffffffff;
4568 break;
4569 }
4570
4571 nslist[i++] = nsid;
4572 clear_bit(nsid, n->changed_nsids);
4573 }
4574
4575 /*
4576 * Remove all the remaining list entries in case returns directly due to
4577 * more than 1024 namespaces.
4578 */
4579 if (nslist[0] == 0xffffffff) {
4580 bitmap_zero(n->changed_nsids, NVME_CHANGED_NSID_SIZE);
4581 }
4582
4583 if (!rae) {
4584 nvme_clear_events(n, NVME_AER_TYPE_NOTICE);
4585 }
4586
4587 return nvme_c2h(n, ((uint8_t *)nslist) + off, trans_len, req);
4588 }
4589
4590 static uint16_t nvme_cmd_effects(NvmeCtrl *n, uint8_t csi, uint32_t buf_len,
4591 uint64_t off, NvmeRequest *req)
4592 {
4593 NvmeEffectsLog log = {};
4594 const uint32_t *src_iocs = NULL;
4595 uint32_t trans_len;
4596
4597 if (off >= sizeof(log)) {
4598 trace_pci_nvme_err_invalid_log_page_offset(off, sizeof(log));
4599 return NVME_INVALID_FIELD | NVME_DNR;
4600 }
4601
4602 switch (NVME_CC_CSS(ldl_le_p(&n->bar.cc))) {
4603 case NVME_CC_CSS_NVM:
4604 src_iocs = nvme_cse_iocs_nvm;
4605 /* fall through */
4606 case NVME_CC_CSS_ADMIN_ONLY:
4607 break;
4608 case NVME_CC_CSS_CSI:
4609 switch (csi) {
4610 case NVME_CSI_NVM:
4611 src_iocs = nvme_cse_iocs_nvm;
4612 break;
4613 case NVME_CSI_ZONED:
4614 src_iocs = nvme_cse_iocs_zoned;
4615 break;
4616 }
4617 }
4618
4619 memcpy(log.acs, nvme_cse_acs, sizeof(nvme_cse_acs));
4620
4621 if (src_iocs) {
4622 memcpy(log.iocs, src_iocs, sizeof(log.iocs));
4623 }
4624
4625 trans_len = MIN(sizeof(log) - off, buf_len);
4626
4627 return nvme_c2h(n, ((uint8_t *)&log) + off, trans_len, req);
4628 }
4629
4630 static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req)
4631 {
4632 NvmeCmd *cmd = &req->cmd;
4633
4634 uint32_t dw10 = le32_to_cpu(cmd->cdw10);
4635 uint32_t dw11 = le32_to_cpu(cmd->cdw11);
4636 uint32_t dw12 = le32_to_cpu(cmd->cdw12);
4637 uint32_t dw13 = le32_to_cpu(cmd->cdw13);
4638 uint8_t lid = dw10 & 0xff;
4639 uint8_t lsp = (dw10 >> 8) & 0xf;
4640 uint8_t rae = (dw10 >> 15) & 0x1;
4641 uint8_t csi = le32_to_cpu(cmd->cdw14) >> 24;
4642 uint32_t numdl, numdu;
4643 uint64_t off, lpol, lpou;
4644 size_t len;
4645 uint16_t status;
4646
4647 numdl = (dw10 >> 16);
4648 numdu = (dw11 & 0xffff);
4649 lpol = dw12;
4650 lpou = dw13;
4651
4652 len = (((numdu << 16) | numdl) + 1) << 2;
4653 off = (lpou << 32ULL) | lpol;
4654
4655 if (off & 0x3) {
4656 return NVME_INVALID_FIELD | NVME_DNR;
4657 }
4658
4659 trace_pci_nvme_get_log(nvme_cid(req), lid, lsp, rae, len, off);
4660
4661 status = nvme_check_mdts(n, len);
4662 if (status) {
4663 return status;
4664 }
4665
4666 switch (lid) {
4667 case NVME_LOG_ERROR_INFO:
4668 return nvme_error_info(n, rae, len, off, req);
4669 case NVME_LOG_SMART_INFO:
4670 return nvme_smart_info(n, rae, len, off, req);
4671 case NVME_LOG_FW_SLOT_INFO:
4672 return nvme_fw_log_info(n, len, off, req);
4673 case NVME_LOG_CHANGED_NSLIST:
4674 return nvme_changed_nslist(n, rae, len, off, req);
4675 case NVME_LOG_CMD_EFFECTS:
4676 return nvme_cmd_effects(n, csi, len, off, req);
4677 default:
4678 trace_pci_nvme_err_invalid_log_page(nvme_cid(req), lid);
4679 return NVME_INVALID_FIELD | NVME_DNR;
4680 }
4681 }
4682
4683 static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
4684 {
4685 uint16_t offset = (cq->cqid << 3) + (1 << 2);
4686
4687 n->cq[cq->cqid] = NULL;
4688 qemu_bh_delete(cq->bh);
4689 if (cq->ioeventfd_enabled) {
4690 memory_region_del_eventfd(&n->iomem,
4691 0x1000 + offset, 4, false, 0, &cq->notifier);
4692 event_notifier_set_handler(&cq->notifier, NULL);
4693 event_notifier_cleanup(&cq->notifier);
4694 }
4695 if (msix_enabled(&n->parent_obj)) {
4696 msix_vector_unuse(&n->parent_obj, cq->vector);
4697 }
4698 if (cq->cqid) {
4699 g_free(cq);
4700 }
4701 }
4702
4703 static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeRequest *req)
4704 {
4705 NvmeDeleteQ *c = (NvmeDeleteQ *)&req->cmd;
4706 NvmeCQueue *cq;
4707 uint16_t qid = le16_to_cpu(c->qid);
4708
4709 if (unlikely(!qid || nvme_check_cqid(n, qid))) {
4710 trace_pci_nvme_err_invalid_del_cq_cqid(qid);
4711 return NVME_INVALID_CQID | NVME_DNR;
4712 }
4713
4714 cq = n->cq[qid];
4715 if (unlikely(!QTAILQ_EMPTY(&cq->sq_list))) {
4716 trace_pci_nvme_err_invalid_del_cq_notempty(qid);
4717 return NVME_INVALID_QUEUE_DEL;
4718 }
4719
4720 if (cq->irq_enabled && cq->tail != cq->head) {
4721 n->cq_pending--;
4722 }
4723
4724 nvme_irq_deassert(n, cq);
4725 trace_pci_nvme_del_cq(qid);
4726 nvme_free_cq(cq, n);
4727 return NVME_SUCCESS;
4728 }
4729
4730 static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,
4731 uint16_t cqid, uint16_t vector, uint16_t size,
4732 uint16_t irq_enabled)
4733 {
4734 if (msix_enabled(&n->parent_obj)) {
4735 msix_vector_use(&n->parent_obj, vector);
4736 }
4737 cq->ctrl = n;
4738 cq->cqid = cqid;
4739 cq->size = size;
4740 cq->dma_addr = dma_addr;
4741 cq->phase = 1;
4742 cq->irq_enabled = irq_enabled;
4743 cq->vector = vector;
4744 cq->head = cq->tail = 0;
4745 QTAILQ_INIT(&cq->req_list);
4746 QTAILQ_INIT(&cq->sq_list);
4747 if (n->dbbuf_enabled) {
4748 cq->db_addr = n->dbbuf_dbs + (cqid << 3) + (1 << 2);
4749 cq->ei_addr = n->dbbuf_eis + (cqid << 3) + (1 << 2);
4750
4751 if (n->params.ioeventfd && cqid != 0) {
4752 if (!nvme_init_cq_ioeventfd(cq)) {
4753 cq->ioeventfd_enabled = true;
4754 }
4755 }
4756 }
4757 n->cq[cqid] = cq;
4758 cq->bh = qemu_bh_new(nvme_post_cqes, cq);
4759 }
4760
4761 static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeRequest *req)
4762 {
4763 NvmeCQueue *cq;
4764 NvmeCreateCq *c = (NvmeCreateCq *)&req->cmd;
4765 uint16_t cqid = le16_to_cpu(c->cqid);
4766 uint16_t vector = le16_to_cpu(c->irq_vector);
4767 uint16_t qsize = le16_to_cpu(c->qsize);
4768 uint16_t qflags = le16_to_cpu(c->cq_flags);
4769 uint64_t prp1 = le64_to_cpu(c->prp1);
4770
4771 trace_pci_nvme_create_cq(prp1, cqid, vector, qsize, qflags,
4772 NVME_CQ_FLAGS_IEN(qflags) != 0);
4773
4774 if (unlikely(!cqid || cqid > n->conf_ioqpairs || n->cq[cqid] != NULL)) {
4775 trace_pci_nvme_err_invalid_create_cq_cqid(cqid);
4776 return NVME_INVALID_QID | NVME_DNR;
4777 }
4778 if (unlikely(!qsize || qsize > NVME_CAP_MQES(ldq_le_p(&n->bar.cap)))) {
4779 trace_pci_nvme_err_invalid_create_cq_size(qsize);
4780 return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
4781 }
4782 if (unlikely(prp1 & (n->page_size - 1))) {
4783 trace_pci_nvme_err_invalid_create_cq_addr(prp1);
4784 return NVME_INVALID_PRP_OFFSET | NVME_DNR;
4785 }
4786 if (unlikely(!msix_enabled(&n->parent_obj) && vector)) {
4787 trace_pci_nvme_err_invalid_create_cq_vector(vector);
4788 return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
4789 }
4790 if (unlikely(vector >= n->conf_msix_qsize)) {
4791 trace_pci_nvme_err_invalid_create_cq_vector(vector);
4792 return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
4793 }
4794 if (unlikely(!(NVME_CQ_FLAGS_PC(qflags)))) {
4795 trace_pci_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflags));
4796 return NVME_INVALID_FIELD | NVME_DNR;
4797 }
4798
4799 cq = g_malloc0(sizeof(*cq));
4800 nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1,
4801 NVME_CQ_FLAGS_IEN(qflags));
4802
4803 /*
4804 * It is only required to set qs_created when creating a completion queue;
4805 * creating a submission queue without a matching completion queue will
4806 * fail.
4807 */
4808 n->qs_created = true;
4809 return NVME_SUCCESS;
4810 }
4811
4812 static uint16_t nvme_rpt_empty_id_struct(NvmeCtrl *n, NvmeRequest *req)
4813 {
4814 uint8_t id[NVME_IDENTIFY_DATA_SIZE] = {};
4815
4816 return nvme_c2h(n, id, sizeof(id), req);
4817 }
4818
4819 static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeRequest *req)
4820 {
4821 trace_pci_nvme_identify_ctrl();
4822
4823 return nvme_c2h(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl), req);
4824 }
4825
4826 static uint16_t nvme_identify_ctrl_csi(NvmeCtrl *n, NvmeRequest *req)
4827 {
4828 NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
4829 uint8_t id[NVME_IDENTIFY_DATA_SIZE] = {};
4830 NvmeIdCtrlNvm *id_nvm = (NvmeIdCtrlNvm *)&id;
4831
4832 trace_pci_nvme_identify_ctrl_csi(c->csi);
4833
4834 switch (c->csi) {
4835 case NVME_CSI_NVM:
4836 id_nvm->vsl = n->params.vsl;
4837 id_nvm->dmrsl = cpu_to_le32(n->dmrsl);
4838 break;
4839
4840 case NVME_CSI_ZONED:
4841 ((NvmeIdCtrlZoned *)&id)->zasl = n->params.zasl;
4842 break;
4843
4844 default:
4845 return NVME_INVALID_FIELD | NVME_DNR;
4846 }
4847
4848 return nvme_c2h(n, id, sizeof(id), req);
4849 }
4850
4851 static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req, bool active)
4852 {
4853 NvmeNamespace *ns;
4854 NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
4855 uint32_t nsid = le32_to_cpu(c->nsid);
4856
4857 trace_pci_nvme_identify_ns(nsid);
4858
4859 if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) {
4860 return NVME_INVALID_NSID | NVME_DNR;
4861 }
4862
4863 ns = nvme_ns(n, nsid);
4864 if (unlikely(!ns)) {
4865 if (!active) {
4866 ns = nvme_subsys_ns(n->subsys, nsid);
4867 if (!ns) {
4868 return nvme_rpt_empty_id_struct(n, req);
4869 }
4870 } else {
4871 return nvme_rpt_empty_id_struct(n, req);
4872 }
4873 }
4874
4875 if (active || ns->csi == NVME_CSI_NVM) {
4876 return nvme_c2h(n, (uint8_t *)&ns->id_ns, sizeof(NvmeIdNs), req);
4877 }
4878
4879 return NVME_INVALID_CMD_SET | NVME_DNR;
4880 }
4881
4882 static uint16_t nvme_identify_ctrl_list(NvmeCtrl *n, NvmeRequest *req,
4883 bool attached)
4884 {
4885 NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
4886 uint32_t nsid = le32_to_cpu(c->nsid);
4887 uint16_t min_id = le16_to_cpu(c->ctrlid);
4888 uint16_t list[NVME_CONTROLLER_LIST_SIZE] = {};
4889 uint16_t *ids = &list[1];
4890 NvmeNamespace *ns;
4891 NvmeCtrl *ctrl;
4892 int cntlid, nr_ids = 0;
4893
4894 trace_pci_nvme_identify_ctrl_list(c->cns, min_id);
4895
4896 if (!n->subsys) {
4897 return NVME_INVALID_FIELD | NVME_DNR;
4898 }
4899
4900 if (attached) {
4901 if (nsid == NVME_NSID_BROADCAST) {
4902 return NVME_INVALID_FIELD | NVME_DNR;
4903 }
4904
4905 ns = nvme_subsys_ns(n->subsys, nsid);
4906 if (!ns) {
4907 return NVME_INVALID_FIELD | NVME_DNR;
4908 }
4909 }
4910
4911 for (cntlid = min_id; cntlid < ARRAY_SIZE(n->subsys->ctrls); cntlid++) {
4912 ctrl = nvme_subsys_ctrl(n->subsys, cntlid);
4913 if (!ctrl) {
4914 continue;
4915 }
4916
4917 if (attached && !nvme_ns(ctrl, nsid)) {
4918 continue;
4919 }
4920
4921 ids[nr_ids++] = cntlid;
4922 }
4923
4924 list[0] = nr_ids;
4925
4926 return nvme_c2h(n, (uint8_t *)list, sizeof(list), req);
4927 }
4928
4929 static uint16_t nvme_identify_pri_ctrl_cap(NvmeCtrl *n, NvmeRequest *req)
4930 {
4931 trace_pci_nvme_identify_pri_ctrl_cap(le16_to_cpu(n->pri_ctrl_cap.cntlid));
4932
4933 return nvme_c2h(n, (uint8_t *)&n->pri_ctrl_cap,
4934 sizeof(NvmePriCtrlCap), req);
4935 }
4936
4937 static uint16_t nvme_identify_sec_ctrl_list(NvmeCtrl *n, NvmeRequest *req)
4938 {
4939 NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
4940 uint16_t pri_ctrl_id = le16_to_cpu(n->pri_ctrl_cap.cntlid);
4941 uint16_t min_id = le16_to_cpu(c->ctrlid);
4942 uint8_t num_sec_ctrl = n->sec_ctrl_list.numcntl;
4943 NvmeSecCtrlList list = {0};
4944 uint8_t i;
4945
4946 for (i = 0; i < num_sec_ctrl; i++) {
4947 if (n->sec_ctrl_list.sec[i].scid >= min_id) {
4948 list.numcntl = num_sec_ctrl - i;
4949 memcpy(&list.sec, n->sec_ctrl_list.sec + i,
4950 list.numcntl * sizeof(NvmeSecCtrlEntry));
4951 break;
4952 }
4953 }
4954
4955 trace_pci_nvme_identify_sec_ctrl_list(pri_ctrl_id, list.numcntl);
4956
4957 return nvme_c2h(n, (uint8_t *)&list, sizeof(list), req);
4958 }
4959
4960 static uint16_t nvme_identify_ns_csi(NvmeCtrl *n, NvmeRequest *req,
4961 bool active)
4962 {
4963 NvmeNamespace *ns;
4964 NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
4965 uint32_t nsid = le32_to_cpu(c->nsid);
4966
4967 trace_pci_nvme_identify_ns_csi(nsid, c->csi);
4968
4969 if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) {
4970 return NVME_INVALID_NSID | NVME_DNR;
4971 }
4972
4973 ns = nvme_ns(n, nsid);
4974 if (unlikely(!ns)) {
4975 if (!active) {
4976 ns = nvme_subsys_ns(n->subsys, nsid);
4977 if (!ns) {
4978 return nvme_rpt_empty_id_struct(n, req);
4979 }
4980 } else {
4981 return nvme_rpt_empty_id_struct(n, req);
4982 }
4983 }
4984
4985 if (c->csi == NVME_CSI_NVM) {
4986 return nvme_c2h(n, (uint8_t *)&ns->id_ns_nvm, sizeof(NvmeIdNsNvm),
4987 req);
4988 } else if (c->csi == NVME_CSI_ZONED && ns->csi == NVME_CSI_ZONED) {
4989 return nvme_c2h(n, (uint8_t *)ns->id_ns_zoned, sizeof(NvmeIdNsZoned),
4990 req);
4991 }
4992
4993 return NVME_INVALID_FIELD | NVME_DNR;
4994 }
4995
4996 static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req,
4997 bool active)
4998 {
4999 NvmeNamespace *ns;
5000 NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
5001 uint32_t min_nsid = le32_to_cpu(c->nsid);
5002 uint8_t list[NVME_IDENTIFY_DATA_SIZE] = {};
5003 static const int data_len = sizeof(list);
5004 uint32_t *list_ptr = (uint32_t *)list;
5005 int i, j = 0;
5006
5007 trace_pci_nvme_identify_nslist(min_nsid);
5008
5009 /*
5010 * Both FFFFFFFFh (NVME_NSID_BROADCAST) and FFFFFFFFEh are invalid values
5011 * since the Active Namespace ID List should return namespaces with ids
5012 * *higher* than the NSID specified in the command. This is also specified
5013 * in the spec (NVM Express v1.3d, Section 5.15.4).
5014 */
5015 if (min_nsid >= NVME_NSID_BROADCAST - 1) {
5016 return NVME_INVALID_NSID | NVME_DNR;
5017 }
5018
5019 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
5020 ns = nvme_ns(n, i);
5021 if (!ns) {
5022 if (!active) {
5023 ns = nvme_subsys_ns(n->subsys, i);
5024 if (!ns) {
5025 continue;
5026 }
5027 } else {
5028 continue;
5029 }
5030 }
5031 if (ns->params.nsid <= min_nsid) {
5032 continue;
5033 }
5034 list_ptr[j++] = cpu_to_le32(ns->params.nsid);
5035 if (j == data_len / sizeof(uint32_t)) {
5036 break;
5037 }
5038 }
5039
5040 return nvme_c2h(n, list, data_len, req);
5041 }
5042
5043 static uint16_t nvme_identify_nslist_csi(NvmeCtrl *n, NvmeRequest *req,
5044 bool active)
5045 {
5046 NvmeNamespace *ns;
5047 NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
5048 uint32_t min_nsid = le32_to_cpu(c->nsid);
5049 uint8_t list[NVME_IDENTIFY_DATA_SIZE] = {};
5050 static const int data_len = sizeof(list);
5051 uint32_t *list_ptr = (uint32_t *)list;
5052 int i, j = 0;
5053
5054 trace_pci_nvme_identify_nslist_csi(min_nsid, c->csi);
5055
5056 /*
5057 * Same as in nvme_identify_nslist(), FFFFFFFFh/FFFFFFFFEh are invalid.
5058 */
5059 if (min_nsid >= NVME_NSID_BROADCAST - 1) {
5060 return NVME_INVALID_NSID | NVME_DNR;
5061 }
5062
5063 if (c->csi != NVME_CSI_NVM && c->csi != NVME_CSI_ZONED) {
5064 return NVME_INVALID_FIELD | NVME_DNR;
5065 }
5066
5067 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
5068 ns = nvme_ns(n, i);
5069 if (!ns) {
5070 if (!active) {
5071 ns = nvme_subsys_ns(n->subsys, i);
5072 if (!ns) {
5073 continue;
5074 }
5075 } else {
5076 continue;
5077 }
5078 }
5079 if (ns->params.nsid <= min_nsid || c->csi != ns->csi) {
5080 continue;
5081 }
5082 list_ptr[j++] = cpu_to_le32(ns->params.nsid);
5083 if (j == data_len / sizeof(uint32_t)) {
5084 break;
5085 }
5086 }
5087
5088 return nvme_c2h(n, list, data_len, req);
5089 }
5090
5091 static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req)
5092 {
5093 NvmeNamespace *ns;
5094 NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
5095 uint32_t nsid = le32_to_cpu(c->nsid);
5096 uint8_t list[NVME_IDENTIFY_DATA_SIZE] = {};
5097 uint8_t *pos = list;
5098 struct {
5099 NvmeIdNsDescr hdr;
5100 uint8_t v[NVME_NIDL_UUID];
5101 } QEMU_PACKED uuid = {};
5102 struct {
5103 NvmeIdNsDescr hdr;
5104 uint64_t v;
5105 } QEMU_PACKED eui64 = {};
5106 struct {
5107 NvmeIdNsDescr hdr;
5108 uint8_t v;
5109 } QEMU_PACKED csi = {};
5110
5111 trace_pci_nvme_identify_ns_descr_list(nsid);
5112
5113 if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) {
5114 return NVME_INVALID_NSID | NVME_DNR;
5115 }
5116
5117 ns = nvme_ns(n, nsid);
5118 if (unlikely(!ns)) {
5119 return NVME_INVALID_FIELD | NVME_DNR;
5120 }
5121
5122 if (!qemu_uuid_is_null(&ns->params.uuid)) {
5123 uuid.hdr.nidt = NVME_NIDT_UUID;
5124 uuid.hdr.nidl = NVME_NIDL_UUID;
5125 memcpy(uuid.v, ns->params.uuid.data, NVME_NIDL_UUID);
5126 memcpy(pos, &uuid, sizeof(uuid));
5127 pos += sizeof(uuid);
5128 }
5129
5130 if (ns->params.eui64) {
5131 eui64.hdr.nidt = NVME_NIDT_EUI64;
5132 eui64.hdr.nidl = NVME_NIDL_EUI64;
5133 eui64.v = cpu_to_be64(ns->params.eui64);
5134 memcpy(pos, &eui64, sizeof(eui64));
5135 pos += sizeof(eui64);
5136 }
5137
5138 csi.hdr.nidt = NVME_NIDT_CSI;
5139 csi.hdr.nidl = NVME_NIDL_CSI;
5140 csi.v = ns->csi;
5141 memcpy(pos, &csi, sizeof(csi));
5142 pos += sizeof(csi);
5143
5144 return nvme_c2h(n, list, sizeof(list), req);
5145 }
5146
5147 static uint16_t nvme_identify_cmd_set(NvmeCtrl *n, NvmeRequest *req)
5148 {
5149 uint8_t list[NVME_IDENTIFY_DATA_SIZE] = {};
5150 static const int data_len = sizeof(list);
5151
5152 trace_pci_nvme_identify_cmd_set();
5153
5154 NVME_SET_CSI(*list, NVME_CSI_NVM);
5155 NVME_SET_CSI(*list, NVME_CSI_ZONED);
5156
5157 return nvme_c2h(n, list, data_len, req);
5158 }
5159
5160 static uint16_t nvme_identify(NvmeCtrl *n, NvmeRequest *req)
5161 {
5162 NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
5163
5164 trace_pci_nvme_identify(nvme_cid(req), c->cns, le16_to_cpu(c->ctrlid),
5165 c->csi);
5166
5167 switch (c->cns) {
5168 case NVME_ID_CNS_NS:
5169 return nvme_identify_ns(n, req, true);
5170 case NVME_ID_CNS_NS_PRESENT:
5171 return nvme_identify_ns(n, req, false);
5172 case NVME_ID_CNS_NS_ATTACHED_CTRL_LIST:
5173 return nvme_identify_ctrl_list(n, req, true);
5174 case NVME_ID_CNS_CTRL_LIST:
5175 return nvme_identify_ctrl_list(n, req, false);
5176 case NVME_ID_CNS_PRIMARY_CTRL_CAP:
5177 return nvme_identify_pri_ctrl_cap(n, req);
5178 case NVME_ID_CNS_SECONDARY_CTRL_LIST:
5179 return nvme_identify_sec_ctrl_list(n, req);
5180 case NVME_ID_CNS_CS_NS:
5181 return nvme_identify_ns_csi(n, req, true);
5182 case NVME_ID_CNS_CS_NS_PRESENT:
5183 return nvme_identify_ns_csi(n, req, false);
5184 case NVME_ID_CNS_CTRL:
5185 return nvme_identify_ctrl(n, req);
5186 case NVME_ID_CNS_CS_CTRL:
5187 return nvme_identify_ctrl_csi(n, req);
5188 case NVME_ID_CNS_NS_ACTIVE_LIST:
5189 return nvme_identify_nslist(n, req, true);
5190 case NVME_ID_CNS_NS_PRESENT_LIST:
5191 return nvme_identify_nslist(n, req, false);
5192 case NVME_ID_CNS_CS_NS_ACTIVE_LIST:
5193 return nvme_identify_nslist_csi(n, req, true);
5194 case NVME_ID_CNS_CS_NS_PRESENT_LIST:
5195 return nvme_identify_nslist_csi(n, req, false);
5196 case NVME_ID_CNS_NS_DESCR_LIST:
5197 return nvme_identify_ns_descr_list(n, req);
5198 case NVME_ID_CNS_IO_COMMAND_SET:
5199 return nvme_identify_cmd_set(n, req);
5200 default:
5201 trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns));
5202 return NVME_INVALID_FIELD | NVME_DNR;
5203 }
5204 }
5205
5206 static uint16_t nvme_abort(NvmeCtrl *n, NvmeRequest *req)
5207 {
5208 uint16_t sqid = le32_to_cpu(req->cmd.cdw10) & 0xffff;
5209
5210 req->cqe.result = 1;
5211 if (nvme_check_sqid(n, sqid)) {
5212 return NVME_INVALID_FIELD | NVME_DNR;
5213 }
5214
5215 return NVME_SUCCESS;
5216 }
5217
5218 static inline void nvme_set_timestamp(NvmeCtrl *n, uint64_t ts)
5219 {
5220 trace_pci_nvme_setfeat_timestamp(ts);
5221
5222 n->host_timestamp = le64_to_cpu(ts);
5223 n->timestamp_set_qemu_clock_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
5224 }
5225
5226 static inline uint64_t nvme_get_timestamp(const NvmeCtrl *n)
5227 {
5228 uint64_t current_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
5229 uint64_t elapsed_time = current_time - n->timestamp_set_qemu_clock_ms;
5230
5231 union nvme_timestamp {
5232 struct {
5233 uint64_t timestamp:48;
5234 uint64_t sync:1;
5235 uint64_t origin:3;
5236 uint64_t rsvd1:12;
5237 };
5238 uint64_t all;
5239 };
5240
5241 union nvme_timestamp ts;
5242 ts.all = 0;
5243 ts.timestamp = n->host_timestamp + elapsed_time;
5244
5245 /* If the host timestamp is non-zero, set the timestamp origin */
5246 ts.origin = n->host_timestamp ? 0x01 : 0x00;
5247
5248 trace_pci_nvme_getfeat_timestamp(ts.all);
5249
5250 return cpu_to_le64(ts.all);
5251 }
5252
5253 static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n, NvmeRequest *req)
5254 {
5255 uint64_t timestamp = nvme_get_timestamp(n);
5256
5257 return nvme_c2h(n, (uint8_t *)&timestamp, sizeof(timestamp), req);
5258 }
5259
5260 static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRequest *req)
5261 {
5262 NvmeCmd *cmd = &req->cmd;
5263 uint32_t dw10 = le32_to_cpu(cmd->cdw10);
5264 uint32_t dw11 = le32_to_cpu(cmd->cdw11);
5265 uint32_t nsid = le32_to_cpu(cmd->nsid);
5266 uint32_t result;
5267 uint8_t fid = NVME_GETSETFEAT_FID(dw10);
5268 NvmeGetFeatureSelect sel = NVME_GETFEAT_SELECT(dw10);
5269 uint16_t iv;
5270 NvmeNamespace *ns;
5271 int i;
5272
5273 static const uint32_t nvme_feature_default[NVME_FID_MAX] = {
5274 [NVME_ARBITRATION] = NVME_ARB_AB_NOLIMIT,
5275 };
5276
5277 trace_pci_nvme_getfeat(nvme_cid(req), nsid, fid, sel, dw11);
5278
5279 if (!nvme_feature_support[fid]) {
5280 return NVME_INVALID_FIELD | NVME_DNR;
5281 }
5282
5283 if (nvme_feature_cap[fid] & NVME_FEAT_CAP_NS) {
5284 if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) {
5285 /*
5286 * The Reservation Notification Mask and Reservation Persistence
5287 * features require a status code of Invalid Field in Command when
5288 * NSID is FFFFFFFFh. Since the device does not support those
5289 * features we can always return Invalid Namespace or Format as we
5290 * should do for all other features.
5291 */
5292 return NVME_INVALID_NSID | NVME_DNR;
5293 }
5294
5295 if (!nvme_ns(n, nsid)) {
5296 return NVME_INVALID_FIELD | NVME_DNR;
5297 }
5298 }
5299
5300 switch (sel) {
5301 case NVME_GETFEAT_SELECT_CURRENT:
5302 break;
5303 case NVME_GETFEAT_SELECT_SAVED:
5304 /* no features are saveable by the controller; fallthrough */
5305 case NVME_GETFEAT_SELECT_DEFAULT:
5306 goto defaults;
5307 case NVME_GETFEAT_SELECT_CAP:
5308 result = nvme_feature_cap[fid];
5309 goto out;
5310 }
5311
5312 switch (fid) {
5313 case NVME_TEMPERATURE_THRESHOLD:
5314 result = 0;
5315
5316 /*
5317 * The controller only implements the Composite Temperature sensor, so
5318 * return 0 for all other sensors.
5319 */
5320 if (NVME_TEMP_TMPSEL(dw11) != NVME_TEMP_TMPSEL_COMPOSITE) {
5321 goto out;
5322 }
5323
5324 switch (NVME_TEMP_THSEL(dw11)) {
5325 case NVME_TEMP_THSEL_OVER:
5326 result = n->features.temp_thresh_hi;
5327 goto out;
5328 case NVME_TEMP_THSEL_UNDER:
5329 result = n->features.temp_thresh_low;
5330 goto out;
5331 }
5332
5333 return NVME_INVALID_FIELD | NVME_DNR;
5334 case NVME_ERROR_RECOVERY:
5335 if (!nvme_nsid_valid(n, nsid)) {
5336 return NVME_INVALID_NSID | NVME_DNR;
5337 }
5338
5339 ns = nvme_ns(n, nsid);
5340 if (unlikely(!ns)) {
5341 return NVME_INVALID_FIELD | NVME_DNR;
5342 }
5343
5344 result = ns->features.err_rec;
5345 goto out;
5346 case NVME_VOLATILE_WRITE_CACHE:
5347 result = 0;
5348 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
5349 ns = nvme_ns(n, i);
5350 if (!ns) {
5351 continue;
5352 }
5353
5354 result = blk_enable_write_cache(ns->blkconf.blk);
5355 if (result) {
5356 break;
5357 }
5358 }
5359 trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled");
5360 goto out;
5361 case NVME_ASYNCHRONOUS_EVENT_CONF:
5362 result = n->features.async_config;
5363 goto out;
5364 case NVME_TIMESTAMP:
5365 return nvme_get_feature_timestamp(n, req);
5366 case NVME_HOST_BEHAVIOR_SUPPORT:
5367 return nvme_c2h(n, (uint8_t *)&n->features.hbs,
5368 sizeof(n->features.hbs), req);
5369 default:
5370 break;
5371 }
5372
5373 defaults:
5374 switch (fid) {
5375 case NVME_TEMPERATURE_THRESHOLD:
5376 result = 0;
5377
5378 if (NVME_TEMP_TMPSEL(dw11) != NVME_TEMP_TMPSEL_COMPOSITE) {
5379 break;
5380 }
5381
5382 if (NVME_TEMP_THSEL(dw11) == NVME_TEMP_THSEL_OVER) {
5383 result = NVME_TEMPERATURE_WARNING;
5384 }
5385
5386 break;
5387 case NVME_NUMBER_OF_QUEUES:
5388 result = (n->conf_ioqpairs - 1) | ((n->conf_ioqpairs - 1) << 16);
5389 trace_pci_nvme_getfeat_numq(result);
5390 break;
5391 case NVME_INTERRUPT_VECTOR_CONF:
5392 iv = dw11 & 0xffff;
5393 if (iv >= n->conf_ioqpairs + 1) {
5394 return NVME_INVALID_FIELD | NVME_DNR;
5395 }
5396
5397 result = iv;
5398 if (iv == n->admin_cq.vector) {
5399 result |= NVME_INTVC_NOCOALESCING;
5400 }
5401 break;
5402 default:
5403 result = nvme_feature_default[fid];
5404 break;
5405 }
5406
5407 out:
5408 req->cqe.result = cpu_to_le32(result);
5409 return NVME_SUCCESS;
5410 }
5411
5412 static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n, NvmeRequest *req)
5413 {
5414 uint16_t ret;
5415 uint64_t timestamp;
5416
5417 ret = nvme_h2c(n, (uint8_t *)&timestamp, sizeof(timestamp), req);
5418 if (ret) {
5419 return ret;
5420 }
5421
5422 nvme_set_timestamp(n, timestamp);
5423
5424 return NVME_SUCCESS;
5425 }
5426
5427 static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req)
5428 {
5429 NvmeNamespace *ns = NULL;
5430
5431 NvmeCmd *cmd = &req->cmd;
5432 uint32_t dw10 = le32_to_cpu(cmd->cdw10);
5433 uint32_t dw11 = le32_to_cpu(cmd->cdw11);
5434 uint32_t nsid = le32_to_cpu(cmd->nsid);
5435 uint8_t fid = NVME_GETSETFEAT_FID(dw10);
5436 uint8_t save = NVME_SETFEAT_SAVE(dw10);
5437 uint16_t status;
5438 int i;
5439
5440 trace_pci_nvme_setfeat(nvme_cid(req), nsid, fid, save, dw11);
5441
5442 if (save && !(nvme_feature_cap[fid] & NVME_FEAT_CAP_SAVE)) {
5443 return NVME_FID_NOT_SAVEABLE | NVME_DNR;
5444 }
5445
5446 if (!nvme_feature_support[fid]) {
5447 return NVME_INVALID_FIELD | NVME_DNR;
5448 }
5449
5450 if (nvme_feature_cap[fid] & NVME_FEAT_CAP_NS) {
5451 if (nsid != NVME_NSID_BROADCAST) {
5452 if (!nvme_nsid_valid(n, nsid)) {
5453 return NVME_INVALID_NSID | NVME_DNR;
5454 }
5455
5456 ns = nvme_ns(n, nsid);
5457 if (unlikely(!ns)) {
5458 return NVME_INVALID_FIELD | NVME_DNR;
5459 }
5460 }
5461 } else if (nsid && nsid != NVME_NSID_BROADCAST) {
5462 if (!nvme_nsid_valid(n, nsid)) {
5463 return NVME_INVALID_NSID | NVME_DNR;
5464 }
5465
5466 return NVME_FEAT_NOT_NS_SPEC | NVME_DNR;
5467 }
5468
5469 if (!(nvme_feature_cap[fid] & NVME_FEAT_CAP_CHANGE)) {
5470 return NVME_FEAT_NOT_CHANGEABLE | NVME_DNR;
5471 }
5472
5473 switch (fid) {
5474 case NVME_TEMPERATURE_THRESHOLD:
5475 if (NVME_TEMP_TMPSEL(dw11) != NVME_TEMP_TMPSEL_COMPOSITE) {
5476 break;
5477 }
5478
5479 switch (NVME_TEMP_THSEL(dw11)) {
5480 case NVME_TEMP_THSEL_OVER:
5481 n->features.temp_thresh_hi = NVME_TEMP_TMPTH(dw11);
5482 break;
5483 case NVME_TEMP_THSEL_UNDER:
5484 n->features.temp_thresh_low = NVME_TEMP_TMPTH(dw11);
5485 break;
5486 default:
5487 return NVME_INVALID_FIELD | NVME_DNR;
5488 }
5489
5490 if ((n->temperature >= n->features.temp_thresh_hi) ||
5491 (n->temperature <= n->features.temp_thresh_low)) {
5492 nvme_smart_event(n, NVME_SMART_TEMPERATURE);
5493 }
5494
5495 break;
5496 case NVME_ERROR_RECOVERY:
5497 if (nsid == NVME_NSID_BROADCAST) {
5498 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
5499 ns = nvme_ns(n, i);
5500
5501 if (!ns) {
5502 continue;
5503 }
5504
5505 if (NVME_ID_NS_NSFEAT_DULBE(ns->id_ns.nsfeat)) {
5506 ns->features.err_rec = dw11;
5507 }
5508 }
5509
5510 break;
5511 }
5512
5513 assert(ns);
5514 if (NVME_ID_NS_NSFEAT_DULBE(ns->id_ns.nsfeat)) {
5515 ns->features.err_rec = dw11;
5516 }
5517 break;
5518 case NVME_VOLATILE_WRITE_CACHE:
5519 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
5520 ns = nvme_ns(n, i);
5521 if (!ns) {
5522 continue;
5523 }
5524
5525 if (!(dw11 & 0x1) && blk_enable_write_cache(ns->blkconf.blk)) {
5526 blk_flush(ns->blkconf.blk);
5527 }
5528
5529 blk_set_enable_write_cache(ns->blkconf.blk, dw11 & 1);
5530 }
5531
5532 break;
5533
5534 case NVME_NUMBER_OF_QUEUES:
5535 if (n->qs_created) {
5536 return NVME_CMD_SEQ_ERROR | NVME_DNR;
5537 }
5538
5539 /*
5540 * NVMe v1.3, Section 5.21.1.7: FFFFh is not an allowed value for NCQR
5541 * and NSQR.
5542 */
5543 if ((dw11 & 0xffff) == 0xffff || ((dw11 >> 16) & 0xffff) == 0xffff) {
5544 return NVME_INVALID_FIELD | NVME_DNR;
5545 }
5546
5547 trace_pci_nvme_setfeat_numq((dw11 & 0xffff) + 1,
5548 ((dw11 >> 16) & 0xffff) + 1,
5549 n->conf_ioqpairs,
5550 n->conf_ioqpairs);
5551 req->cqe.result = cpu_to_le32((n->conf_ioqpairs - 1) |
5552 ((n->conf_ioqpairs - 1) << 16));
5553 break;
5554 case NVME_ASYNCHRONOUS_EVENT_CONF:
5555 n->features.async_config = dw11;
5556 break;
5557 case NVME_TIMESTAMP:
5558 return nvme_set_feature_timestamp(n, req);
5559 case NVME_HOST_BEHAVIOR_SUPPORT:
5560 status = nvme_h2c(n, (uint8_t *)&n->features.hbs,
5561 sizeof(n->features.hbs), req);
5562 if (status) {
5563 return status;
5564 }
5565
5566 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
5567 ns = nvme_ns(n, i);
5568
5569 if (!ns) {
5570 continue;
5571 }
5572
5573 ns->id_ns.nlbaf = ns->nlbaf - 1;
5574 if (!n->features.hbs.lbafee) {
5575 ns->id_ns.nlbaf = MIN(ns->id_ns.nlbaf, 15);
5576 }
5577 }
5578
5579 return status;
5580 case NVME_COMMAND_SET_PROFILE:
5581 if (dw11 & 0x1ff) {
5582 trace_pci_nvme_err_invalid_iocsci(dw11 & 0x1ff);
5583 return NVME_CMD_SET_CMB_REJECTED | NVME_DNR;
5584 }
5585 break;
5586 default:
5587 return NVME_FEAT_NOT_CHANGEABLE | NVME_DNR;
5588 }
5589 return NVME_SUCCESS;
5590 }
5591
5592 static uint16_t nvme_aer(NvmeCtrl *n, NvmeRequest *req)
5593 {
5594 trace_pci_nvme_aer(nvme_cid(req));
5595
5596 if (n->outstanding_aers > n->params.aerl) {
5597 trace_pci_nvme_aer_aerl_exceeded();
5598 return NVME_AER_LIMIT_EXCEEDED;
5599 }
5600
5601 n->aer_reqs[n->outstanding_aers] = req;
5602 n->outstanding_aers++;
5603
5604 if (!QTAILQ_EMPTY(&n->aer_queue)) {
5605 nvme_process_aers(n);
5606 }
5607
5608 return NVME_NO_COMPLETE;
5609 }
5610
5611 static void nvme_update_dmrsl(NvmeCtrl *n)
5612 {
5613 int nsid;
5614
5615 for (nsid = 1; nsid <= NVME_MAX_NAMESPACES; nsid++) {
5616 NvmeNamespace *ns = nvme_ns(n, nsid);
5617 if (!ns) {
5618 continue;
5619 }
5620
5621 n->dmrsl = MIN_NON_ZERO(n->dmrsl,
5622 BDRV_REQUEST_MAX_BYTES / nvme_l2b(ns, 1));
5623 }
5624 }
5625
5626 static void nvme_select_iocs_ns(NvmeCtrl *n, NvmeNamespace *ns)
5627 {
5628 uint32_t cc = ldl_le_p(&n->bar.cc);
5629
5630 ns->iocs = nvme_cse_iocs_none;
5631 switch (ns->csi) {
5632 case NVME_CSI_NVM:
5633 if (NVME_CC_CSS(cc) != NVME_CC_CSS_ADMIN_ONLY) {
5634 ns->iocs = nvme_cse_iocs_nvm;
5635 }
5636 break;
5637 case NVME_CSI_ZONED:
5638 if (NVME_CC_CSS(cc) == NVME_CC_CSS_CSI) {
5639 ns->iocs = nvme_cse_iocs_zoned;
5640 } else if (NVME_CC_CSS(cc) == NVME_CC_CSS_NVM) {
5641 ns->iocs = nvme_cse_iocs_nvm;
5642 }
5643 break;
5644 }
5645 }
5646
5647 static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeRequest *req)
5648 {
5649 NvmeNamespace *ns;
5650 NvmeCtrl *ctrl;
5651 uint16_t list[NVME_CONTROLLER_LIST_SIZE] = {};
5652 uint32_t nsid = le32_to_cpu(req->cmd.nsid);
5653 uint32_t dw10 = le32_to_cpu(req->cmd.cdw10);
5654 uint8_t sel = dw10 & 0xf;
5655 uint16_t *nr_ids = &list[0];
5656 uint16_t *ids = &list[1];
5657 uint16_t ret;
5658 int i;
5659
5660 trace_pci_nvme_ns_attachment(nvme_cid(req), dw10 & 0xf);
5661
5662 if (!nvme_nsid_valid(n, nsid)) {
5663 return NVME_INVALID_NSID | NVME_DNR;
5664 }
5665
5666 ns = nvme_subsys_ns(n->subsys, nsid);
5667 if (!ns) {
5668 return NVME_INVALID_FIELD | NVME_DNR;
5669 }
5670
5671 ret = nvme_h2c(n, (uint8_t *)list, 4096, req);
5672 if (ret) {
5673 return ret;
5674 }
5675
5676 if (!*nr_ids) {
5677 return NVME_NS_CTRL_LIST_INVALID | NVME_DNR;
5678 }
5679
5680 *nr_ids = MIN(*nr_ids, NVME_CONTROLLER_LIST_SIZE - 1);
5681 for (i = 0; i < *nr_ids; i++) {
5682 ctrl = nvme_subsys_ctrl(n->subsys, ids[i]);
5683 if (!ctrl) {
5684 return NVME_NS_CTRL_LIST_INVALID | NVME_DNR;
5685 }
5686
5687 switch (sel) {
5688 case NVME_NS_ATTACHMENT_ATTACH:
5689 if (nvme_ns(ctrl, nsid)) {
5690 return NVME_NS_ALREADY_ATTACHED | NVME_DNR;
5691 }
5692
5693 if (ns->attached && !ns->params.shared) {
5694 return NVME_NS_PRIVATE | NVME_DNR;
5695 }
5696
5697 nvme_attach_ns(ctrl, ns);
5698 nvme_select_iocs_ns(ctrl, ns);
5699
5700 break;
5701
5702 case NVME_NS_ATTACHMENT_DETACH:
5703 if (!nvme_ns(ctrl, nsid)) {
5704 return NVME_NS_NOT_ATTACHED | NVME_DNR;
5705 }
5706
5707 ctrl->namespaces[nsid] = NULL;
5708 ns->attached--;
5709
5710 nvme_update_dmrsl(ctrl);
5711
5712 break;
5713
5714 default:
5715 return NVME_INVALID_FIELD | NVME_DNR;
5716 }
5717
5718 /*
5719 * Add namespace id to the changed namespace id list for event clearing
5720 * via Get Log Page command.
5721 */
5722 if (!test_and_set_bit(nsid, ctrl->changed_nsids)) {
5723 nvme_enqueue_event(ctrl, NVME_AER_TYPE_NOTICE,
5724 NVME_AER_INFO_NOTICE_NS_ATTR_CHANGED,
5725 NVME_LOG_CHANGED_NSLIST);
5726 }
5727 }
5728
5729 return NVME_SUCCESS;
5730 }
5731
5732 typedef struct NvmeFormatAIOCB {
5733 BlockAIOCB common;
5734 BlockAIOCB *aiocb;
5735 NvmeRequest *req;
5736 int ret;
5737
5738 NvmeNamespace *ns;
5739 uint32_t nsid;
5740 bool broadcast;
5741 int64_t offset;
5742
5743 uint8_t lbaf;
5744 uint8_t mset;
5745 uint8_t pi;
5746 uint8_t pil;
5747 } NvmeFormatAIOCB;
5748
5749 static void nvme_format_cancel(BlockAIOCB *aiocb)
5750 {
5751 NvmeFormatAIOCB *iocb = container_of(aiocb, NvmeFormatAIOCB, common);
5752
5753 iocb->ret = -ECANCELED;
5754
5755 if (iocb->aiocb) {
5756 blk_aio_cancel_async(iocb->aiocb);
5757 iocb->aiocb = NULL;
5758 }
5759 }
5760
5761 static const AIOCBInfo nvme_format_aiocb_info = {
5762 .aiocb_size = sizeof(NvmeFormatAIOCB),
5763 .cancel_async = nvme_format_cancel,
5764 .get_aio_context = nvme_get_aio_context,
5765 };
5766
5767 static void nvme_format_set(NvmeNamespace *ns, uint8_t lbaf, uint8_t mset,
5768 uint8_t pi, uint8_t pil)
5769 {
5770 uint8_t lbafl = lbaf & 0xf;
5771 uint8_t lbafu = lbaf >> 4;
5772
5773 trace_pci_nvme_format_set(ns->params.nsid, lbaf, mset, pi, pil);
5774
5775 ns->id_ns.dps = (pil << 3) | pi;
5776 ns->id_ns.flbas = (lbafu << 5) | (mset << 4) | lbafl;
5777
5778 nvme_ns_init_format(ns);
5779 }
5780
5781 static void nvme_do_format(NvmeFormatAIOCB *iocb);
5782
5783 static void nvme_format_ns_cb(void *opaque, int ret)
5784 {
5785 NvmeFormatAIOCB *iocb = opaque;
5786 NvmeNamespace *ns = iocb->ns;
5787 int bytes;
5788
5789 if (iocb->ret < 0) {
5790 goto done;
5791 } else if (ret < 0) {
5792 iocb->ret = ret;
5793 goto done;
5794 }
5795
5796 assert(ns);
5797
5798 if (iocb->offset < ns->size) {
5799 bytes = MIN(BDRV_REQUEST_MAX_BYTES, ns->size - iocb->offset);
5800
5801 iocb->aiocb = blk_aio_pwrite_zeroes(ns->blkconf.blk, iocb->offset,
5802 bytes, BDRV_REQ_MAY_UNMAP,
5803 nvme_format_ns_cb, iocb);
5804
5805 iocb->offset += bytes;
5806 return;
5807 }
5808
5809 nvme_format_set(ns, iocb->lbaf, iocb->mset, iocb->pi, iocb->pil);
5810 ns->status = 0x0;
5811 iocb->ns = NULL;
5812 iocb->offset = 0;
5813
5814 done:
5815 nvme_do_format(iocb);
5816 }
5817
5818 static uint16_t nvme_format_check(NvmeNamespace *ns, uint8_t lbaf, uint8_t pi)
5819 {
5820 if (ns->params.zoned) {
5821 return NVME_INVALID_FORMAT | NVME_DNR;
5822 }
5823
5824 if (lbaf > ns->id_ns.nlbaf) {
5825 return NVME_INVALID_FORMAT | NVME_DNR;
5826 }
5827
5828 if (pi && (ns->id_ns.lbaf[lbaf].ms < nvme_pi_tuple_size(ns))) {
5829 return NVME_INVALID_FORMAT | NVME_DNR;
5830 }
5831
5832 if (pi && pi > NVME_ID_NS_DPS_TYPE_3) {
5833 return NVME_INVALID_FIELD | NVME_DNR;
5834 }
5835
5836 return NVME_SUCCESS;
5837 }
5838
5839 static void nvme_do_format(NvmeFormatAIOCB *iocb)
5840 {
5841 NvmeRequest *req = iocb->req;
5842 NvmeCtrl *n = nvme_ctrl(req);
5843 uint32_t dw10 = le32_to_cpu(req->cmd.cdw10);
5844 uint8_t lbaf = dw10 & 0xf;
5845 uint8_t pi = (dw10 >> 5) & 0x7;
5846 uint16_t status;
5847 int i;
5848
5849 if (iocb->ret < 0) {
5850 goto done;
5851 }
5852
5853 if (iocb->broadcast) {
5854 for (i = iocb->nsid + 1; i <= NVME_MAX_NAMESPACES; i++) {
5855 iocb->ns = nvme_ns(n, i);
5856 if (iocb->ns) {
5857 iocb->nsid = i;
5858 break;
5859 }
5860 }
5861 }
5862
5863 if (!iocb->ns) {
5864 goto done;
5865 }
5866
5867 status = nvme_format_check(iocb->ns, lbaf, pi);
5868 if (status) {
5869 req->status = status;
5870 goto done;
5871 }
5872
5873 iocb->ns->status = NVME_FORMAT_IN_PROGRESS;
5874 nvme_format_ns_cb(iocb, 0);
5875 return;
5876
5877 done:
5878 iocb->common.cb(iocb->common.opaque, iocb->ret);
5879 qemu_aio_unref(iocb);
5880 }
5881
5882 static uint16_t nvme_format(NvmeCtrl *n, NvmeRequest *req)
5883 {
5884 NvmeFormatAIOCB *iocb;
5885 uint32_t nsid = le32_to_cpu(req->cmd.nsid);
5886 uint32_t dw10 = le32_to_cpu(req->cmd.cdw10);
5887 uint8_t lbaf = dw10 & 0xf;
5888 uint8_t mset = (dw10 >> 4) & 0x1;
5889 uint8_t pi = (dw10 >> 5) & 0x7;
5890 uint8_t pil = (dw10 >> 8) & 0x1;
5891 uint8_t lbafu = (dw10 >> 12) & 0x3;
5892 uint16_t status;
5893
5894 iocb = qemu_aio_get(&nvme_format_aiocb_info, NULL, nvme_misc_cb, req);
5895
5896 iocb->req = req;
5897 iocb->ret = 0;
5898 iocb->ns = NULL;
5899 iocb->nsid = 0;
5900 iocb->lbaf = lbaf;
5901 iocb->mset = mset;
5902 iocb->pi = pi;
5903 iocb->pil = pil;
5904 iocb->broadcast = (nsid == NVME_NSID_BROADCAST);
5905 iocb->offset = 0;
5906
5907 if (n->features.hbs.lbafee) {
5908 iocb->lbaf |= lbafu << 4;
5909 }
5910
5911 if (!iocb->broadcast) {
5912 if (!nvme_nsid_valid(n, nsid)) {
5913 status = NVME_INVALID_NSID | NVME_DNR;
5914 goto out;
5915 }
5916
5917 iocb->ns = nvme_ns(n, nsid);
5918 if (!iocb->ns) {
5919 status = NVME_INVALID_FIELD | NVME_DNR;
5920 goto out;
5921 }
5922 }
5923
5924 req->aiocb = &iocb->common;
5925 nvme_do_format(iocb);
5926
5927 return NVME_NO_COMPLETE;
5928
5929 out:
5930 qemu_aio_unref(iocb);
5931
5932 return status;
5933 }
5934
5935 static void nvme_get_virt_res_num(NvmeCtrl *n, uint8_t rt, int *num_total,
5936 int *num_prim, int *num_sec)
5937 {
5938 *num_total = le32_to_cpu(rt ?
5939 n->pri_ctrl_cap.vifrt : n->pri_ctrl_cap.vqfrt);
5940 *num_prim = le16_to_cpu(rt ?
5941 n->pri_ctrl_cap.virfap : n->pri_ctrl_cap.vqrfap);
5942 *num_sec = le16_to_cpu(rt ? n->pri_ctrl_cap.virfa : n->pri_ctrl_cap.vqrfa);
5943 }
5944
5945 static uint16_t nvme_assign_virt_res_to_prim(NvmeCtrl *n, NvmeRequest *req,
5946 uint16_t cntlid, uint8_t rt,
5947 int nr)
5948 {
5949 int num_total, num_prim, num_sec;
5950
5951 if (cntlid != n->cntlid) {
5952 return NVME_INVALID_CTRL_ID | NVME_DNR;
5953 }
5954
5955 nvme_get_virt_res_num(n, rt, &num_total, &num_prim, &num_sec);
5956
5957 if (nr > num_total) {
5958 return NVME_INVALID_NUM_RESOURCES | NVME_DNR;
5959 }
5960
5961 if (nr > num_total - num_sec) {
5962 return NVME_INVALID_RESOURCE_ID | NVME_DNR;
5963 }
5964
5965 if (rt) {
5966 n->next_pri_ctrl_cap.virfap = cpu_to_le16(nr);
5967 } else {
5968 n->next_pri_ctrl_cap.vqrfap = cpu_to_le16(nr);
5969 }
5970
5971 req->cqe.result = cpu_to_le32(nr);
5972 return req->status;
5973 }
5974
5975 static void nvme_update_virt_res(NvmeCtrl *n, NvmeSecCtrlEntry *sctrl,
5976 uint8_t rt, int nr)
5977 {
5978 int prev_nr, prev_total;
5979
5980 if (rt) {
5981 prev_nr = le16_to_cpu(sctrl->nvi);
5982 prev_total = le32_to_cpu(n->pri_ctrl_cap.virfa);
5983 sctrl->nvi = cpu_to_le16(nr);
5984 n->pri_ctrl_cap.virfa = cpu_to_le32(prev_total + nr - prev_nr);
5985 } else {
5986 prev_nr = le16_to_cpu(sctrl->nvq);
5987 prev_total = le32_to_cpu(n->pri_ctrl_cap.vqrfa);
5988 sctrl->nvq = cpu_to_le16(nr);
5989 n->pri_ctrl_cap.vqrfa = cpu_to_le32(prev_total + nr - prev_nr);
5990 }
5991 }
5992
5993 static uint16_t nvme_assign_virt_res_to_sec(NvmeCtrl *n, NvmeRequest *req,
5994 uint16_t cntlid, uint8_t rt, int nr)
5995 {
5996 int num_total, num_prim, num_sec, num_free, diff, limit;
5997 NvmeSecCtrlEntry *sctrl;
5998
5999 sctrl = nvme_sctrl_for_cntlid(n, cntlid);
6000 if (!sctrl) {
6001 return NVME_INVALID_CTRL_ID | NVME_DNR;
6002 }
6003
6004 if (sctrl->scs) {
6005 return NVME_INVALID_SEC_CTRL_STATE | NVME_DNR;
6006 }
6007
6008 limit = le16_to_cpu(rt ? n->pri_ctrl_cap.vifrsm : n->pri_ctrl_cap.vqfrsm);
6009 if (nr > limit) {
6010 return NVME_INVALID_NUM_RESOURCES | NVME_DNR;
6011 }
6012
6013 nvme_get_virt_res_num(n, rt, &num_total, &num_prim, &num_sec);
6014 num_free = num_total - num_prim - num_sec;
6015 diff = nr - le16_to_cpu(rt ? sctrl->nvi : sctrl->nvq);
6016
6017 if (diff > num_free) {
6018 return NVME_INVALID_RESOURCE_ID | NVME_DNR;
6019 }
6020
6021 nvme_update_virt_res(n, sctrl, rt, nr);
6022 req->cqe.result = cpu_to_le32(nr);
6023
6024 return req->status;
6025 }
6026
6027 static uint16_t nvme_virt_set_state(NvmeCtrl *n, uint16_t cntlid, bool online)
6028 {
6029 NvmeCtrl *sn = NULL;
6030 NvmeSecCtrlEntry *sctrl;
6031 int vf_index;
6032
6033 sctrl = nvme_sctrl_for_cntlid(n, cntlid);
6034 if (!sctrl) {
6035 return NVME_INVALID_CTRL_ID | NVME_DNR;
6036 }
6037
6038 if (!pci_is_vf(&n->parent_obj)) {
6039 vf_index = le16_to_cpu(sctrl->vfn) - 1;
6040 sn = NVME(pcie_sriov_get_vf_at_index(&n->parent_obj, vf_index));
6041 }
6042
6043 if (online) {
6044 if (!sctrl->nvi || (le16_to_cpu(sctrl->nvq) < 2) || !sn) {
6045 return NVME_INVALID_SEC_CTRL_STATE | NVME_DNR;
6046 }
6047
6048 if (!sctrl->scs) {
6049 sctrl->scs = 0x1;
6050 nvme_ctrl_reset(sn, NVME_RESET_FUNCTION);
6051 }
6052 } else {
6053 nvme_update_virt_res(n, sctrl, NVME_VIRT_RES_INTERRUPT, 0);
6054 nvme_update_virt_res(n, sctrl, NVME_VIRT_RES_QUEUE, 0);
6055
6056 if (sctrl->scs) {
6057 sctrl->scs = 0x0;
6058 if (sn) {
6059 nvme_ctrl_reset(sn, NVME_RESET_FUNCTION);
6060 }
6061 }
6062 }
6063
6064 return NVME_SUCCESS;
6065 }
6066
6067 static uint16_t nvme_virt_mngmt(NvmeCtrl *n, NvmeRequest *req)
6068 {
6069 uint32_t dw10 = le32_to_cpu(req->cmd.cdw10);
6070 uint32_t dw11 = le32_to_cpu(req->cmd.cdw11);
6071 uint8_t act = dw10 & 0xf;
6072 uint8_t rt = (dw10 >> 8) & 0x7;
6073 uint16_t cntlid = (dw10 >> 16) & 0xffff;
6074 int nr = dw11 & 0xffff;
6075
6076 trace_pci_nvme_virt_mngmt(nvme_cid(req), act, cntlid, rt ? "VI" : "VQ", nr);
6077
6078 if (rt != NVME_VIRT_RES_QUEUE && rt != NVME_VIRT_RES_INTERRUPT) {
6079 return NVME_INVALID_RESOURCE_ID | NVME_DNR;
6080 }
6081
6082 switch (act) {
6083 case NVME_VIRT_MNGMT_ACTION_SEC_ASSIGN:
6084 return nvme_assign_virt_res_to_sec(n, req, cntlid, rt, nr);
6085 case NVME_VIRT_MNGMT_ACTION_PRM_ALLOC:
6086 return nvme_assign_virt_res_to_prim(n, req, cntlid, rt, nr);
6087 case NVME_VIRT_MNGMT_ACTION_SEC_ONLINE:
6088 return nvme_virt_set_state(n, cntlid, true);
6089 case NVME_VIRT_MNGMT_ACTION_SEC_OFFLINE:
6090 return nvme_virt_set_state(n, cntlid, false);
6091 default:
6092 return NVME_INVALID_FIELD | NVME_DNR;
6093 }
6094 }
6095
6096 static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req)
6097 {
6098 uint64_t dbs_addr = le64_to_cpu(req->cmd.dptr.prp1);
6099 uint64_t eis_addr = le64_to_cpu(req->cmd.dptr.prp2);
6100 int i;
6101
6102 /* Address should be page aligned */
6103 if (dbs_addr & (n->page_size - 1) || eis_addr & (n->page_size - 1)) {
6104 return NVME_INVALID_FIELD | NVME_DNR;
6105 }
6106
6107 /* Save shadow buffer base addr for use during queue creation */
6108 n->dbbuf_dbs = dbs_addr;
6109 n->dbbuf_eis = eis_addr;
6110 n->dbbuf_enabled = true;
6111
6112 for (i = 0; i < n->params.max_ioqpairs + 1; i++) {
6113 NvmeSQueue *sq = n->sq[i];
6114 NvmeCQueue *cq = n->cq[i];
6115
6116 if (sq) {
6117 /*
6118 * CAP.DSTRD is 0, so offset of ith sq db_addr is (i<<3)
6119 * nvme_process_db() uses this hard-coded way to calculate
6120 * doorbell offsets. Be consistent with that here.
6121 */
6122 sq->db_addr = dbs_addr + (i << 3);
6123 sq->ei_addr = eis_addr + (i << 3);
6124 pci_dma_write(&n->parent_obj, sq->db_addr, &sq->tail,
6125 sizeof(sq->tail));
6126
6127 if (n->params.ioeventfd && sq->sqid != 0) {
6128 if (!nvme_init_sq_ioeventfd(sq)) {
6129 sq->ioeventfd_enabled = true;
6130 }
6131 }
6132 }
6133
6134 if (cq) {
6135 /* CAP.DSTRD is 0, so offset of ith cq db_addr is (i<<3)+(1<<2) */
6136 cq->db_addr = dbs_addr + (i << 3) + (1 << 2);
6137 cq->ei_addr = eis_addr + (i << 3) + (1 << 2);
6138 pci_dma_write(&n->parent_obj, cq->db_addr, &cq->head,
6139 sizeof(cq->head));
6140
6141 if (n->params.ioeventfd && cq->cqid != 0) {
6142 if (!nvme_init_cq_ioeventfd(cq)) {
6143 cq->ioeventfd_enabled = true;
6144 }
6145 }
6146 }
6147 }
6148
6149 trace_pci_nvme_dbbuf_config(dbs_addr, eis_addr);
6150
6151 return NVME_SUCCESS;
6152 }
6153
6154 static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req)
6155 {
6156 trace_pci_nvme_admin_cmd(nvme_cid(req), nvme_sqid(req), req->cmd.opcode,
6157 nvme_adm_opc_str(req->cmd.opcode));
6158
6159 if (!(nvme_cse_acs[req->cmd.opcode] & NVME_CMD_EFF_CSUPP)) {
6160 trace_pci_nvme_err_invalid_admin_opc(req->cmd.opcode);
6161 return NVME_INVALID_OPCODE | NVME_DNR;
6162 }
6163
6164 /* SGLs shall not be used for Admin commands in NVMe over PCIe */
6165 if (NVME_CMD_FLAGS_PSDT(req->cmd.flags) != NVME_PSDT_PRP) {
6166 return NVME_INVALID_FIELD | NVME_DNR;
6167 }
6168
6169 if (NVME_CMD_FLAGS_FUSE(req->cmd.flags)) {
6170 return NVME_INVALID_FIELD;
6171 }
6172
6173 switch (req->cmd.opcode) {
6174 case NVME_ADM_CMD_DELETE_SQ:
6175 return nvme_del_sq(n, req);
6176 case NVME_ADM_CMD_CREATE_SQ:
6177 return nvme_create_sq(n, req);
6178 case NVME_ADM_CMD_GET_LOG_PAGE:
6179 return nvme_get_log(n, req);
6180 case NVME_ADM_CMD_DELETE_CQ:
6181 return nvme_del_cq(n, req);
6182 case NVME_ADM_CMD_CREATE_CQ:
6183 return nvme_create_cq(n, req);
6184 case NVME_ADM_CMD_IDENTIFY:
6185 return nvme_identify(n, req);
6186 case NVME_ADM_CMD_ABORT:
6187 return nvme_abort(n, req);
6188 case NVME_ADM_CMD_SET_FEATURES:
6189 return nvme_set_feature(n, req);
6190 case NVME_ADM_CMD_GET_FEATURES:
6191 return nvme_get_feature(n, req);
6192 case NVME_ADM_CMD_ASYNC_EV_REQ:
6193 return nvme_aer(n, req);
6194 case NVME_ADM_CMD_NS_ATTACHMENT:
6195 return nvme_ns_attachment(n, req);
6196 case NVME_ADM_CMD_VIRT_MNGMT:
6197 return nvme_virt_mngmt(n, req);
6198 case NVME_ADM_CMD_DBBUF_CONFIG:
6199 return nvme_dbbuf_config(n, req);
6200 case NVME_ADM_CMD_FORMAT_NVM:
6201 return nvme_format(n, req);
6202 default:
6203 assert(false);
6204 }
6205
6206 return NVME_INVALID_OPCODE | NVME_DNR;
6207 }
6208
6209 static void nvme_update_sq_eventidx(const NvmeSQueue *sq)
6210 {
6211 pci_dma_write(&sq->ctrl->parent_obj, sq->ei_addr, &sq->tail,
6212 sizeof(sq->tail));
6213 trace_pci_nvme_eventidx_sq(sq->sqid, sq->tail);
6214 }
6215
6216 static void nvme_update_sq_tail(NvmeSQueue *sq)
6217 {
6218 pci_dma_read(&sq->ctrl->parent_obj, sq->db_addr, &sq->tail,
6219 sizeof(sq->tail));
6220 trace_pci_nvme_shadow_doorbell_sq(sq->sqid, sq->tail);
6221 }
6222
6223 static void nvme_process_sq(void *opaque)
6224 {
6225 NvmeSQueue *sq = opaque;
6226 NvmeCtrl *n = sq->ctrl;
6227 NvmeCQueue *cq = n->cq[sq->cqid];
6228
6229 uint16_t status;
6230 hwaddr addr;
6231 NvmeCmd cmd;
6232 NvmeRequest *req;
6233
6234 if (n->dbbuf_enabled) {
6235 nvme_update_sq_tail(sq);
6236 }
6237
6238 while (!(nvme_sq_empty(sq) || QTAILQ_EMPTY(&sq->req_list))) {
6239 addr = sq->dma_addr + sq->head * n->sqe_size;
6240 if (nvme_addr_read(n, addr, (void *)&cmd, sizeof(cmd))) {
6241 trace_pci_nvme_err_addr_read(addr);
6242 trace_pci_nvme_err_cfs();
6243 stl_le_p(&n->bar.csts, NVME_CSTS_FAILED);
6244 break;
6245 }
6246 nvme_inc_sq_head(sq);
6247
6248 req = QTAILQ_FIRST(&sq->req_list);
6249 QTAILQ_REMOVE(&sq->req_list, req, entry);
6250 QTAILQ_INSERT_TAIL(&sq->out_req_list, req, entry);
6251 nvme_req_clear(req);
6252 req->cqe.cid = cmd.cid;
6253 memcpy(&req->cmd, &cmd, sizeof(NvmeCmd));
6254
6255 status = sq->sqid ? nvme_io_cmd(n, req) :
6256 nvme_admin_cmd(n, req);
6257 if (status != NVME_NO_COMPLETE) {
6258 req->status = status;
6259 nvme_enqueue_req_completion(cq, req);
6260 }
6261
6262 if (n->dbbuf_enabled) {
6263 nvme_update_sq_eventidx(sq);
6264 nvme_update_sq_tail(sq);
6265 }
6266 }
6267 }
6268
6269 static void nvme_update_msixcap_ts(PCIDevice *pci_dev, uint32_t table_size)
6270 {
6271 uint8_t *config;
6272
6273 if (!msix_present(pci_dev)) {
6274 return;
6275 }
6276
6277 assert(table_size > 0 && table_size <= pci_dev->msix_entries_nr);
6278
6279 config = pci_dev->config + pci_dev->msix_cap;
6280 pci_set_word_by_mask(config + PCI_MSIX_FLAGS, PCI_MSIX_FLAGS_QSIZE,
6281 table_size - 1);
6282 }
6283
6284 static void nvme_activate_virt_res(NvmeCtrl *n)
6285 {
6286 PCIDevice *pci_dev = &n->parent_obj;
6287 NvmePriCtrlCap *cap = &n->pri_ctrl_cap;
6288 NvmeSecCtrlEntry *sctrl;
6289
6290 /* -1 to account for the admin queue */
6291 if (pci_is_vf(pci_dev)) {
6292 sctrl = nvme_sctrl(n);
6293 cap->vqprt = sctrl->nvq;
6294 cap->viprt = sctrl->nvi;
6295 n->conf_ioqpairs = sctrl->nvq ? le16_to_cpu(sctrl->nvq) - 1 : 0;
6296 n->conf_msix_qsize = sctrl->nvi ? le16_to_cpu(sctrl->nvi) : 1;
6297 } else {
6298 cap->vqrfap = n->next_pri_ctrl_cap.vqrfap;
6299 cap->virfap = n->next_pri_ctrl_cap.virfap;
6300 n->conf_ioqpairs = le16_to_cpu(cap->vqprt) +
6301 le16_to_cpu(cap->vqrfap) - 1;
6302 n->conf_msix_qsize = le16_to_cpu(cap->viprt) +
6303 le16_to_cpu(cap->virfap);
6304 }
6305 }
6306
6307 static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst)
6308 {
6309 PCIDevice *pci_dev = &n->parent_obj;
6310 NvmeSecCtrlEntry *sctrl;
6311 NvmeNamespace *ns;
6312 int i;
6313
6314 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
6315 ns = nvme_ns(n, i);
6316 if (!ns) {
6317 continue;
6318 }
6319
6320 nvme_ns_drain(ns);
6321 }
6322
6323 for (i = 0; i < n->params.max_ioqpairs + 1; i++) {
6324 if (n->sq[i] != NULL) {
6325 nvme_free_sq(n->sq[i], n);
6326 }
6327 }
6328 for (i = 0; i < n->params.max_ioqpairs + 1; i++) {
6329 if (n->cq[i] != NULL) {
6330 nvme_free_cq(n->cq[i], n);
6331 }
6332 }
6333
6334 while (!QTAILQ_EMPTY(&n->aer_queue)) {
6335 NvmeAsyncEvent *event = QTAILQ_FIRST(&n->aer_queue);
6336 QTAILQ_REMOVE(&n->aer_queue, event, entry);
6337 g_free(event);
6338 }
6339
6340 if (n->params.sriov_max_vfs) {
6341 if (!pci_is_vf(pci_dev)) {
6342 for (i = 0; i < n->sec_ctrl_list.numcntl; i++) {
6343 sctrl = &n->sec_ctrl_list.sec[i];
6344 nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false);
6345 }
6346
6347 if (rst != NVME_RESET_CONTROLLER) {
6348 pcie_sriov_pf_disable_vfs(pci_dev);
6349 }
6350 }
6351
6352 if (rst != NVME_RESET_CONTROLLER) {
6353 nvme_activate_virt_res(n);
6354 }
6355 }
6356
6357 n->aer_queued = 0;
6358 n->aer_mask = 0;
6359 n->outstanding_aers = 0;
6360 n->qs_created = false;
6361
6362 nvme_update_msixcap_ts(pci_dev, n->conf_msix_qsize);
6363
6364 if (pci_is_vf(pci_dev)) {
6365 sctrl = nvme_sctrl(n);
6366
6367 stl_le_p(&n->bar.csts, sctrl->scs ? 0 : NVME_CSTS_FAILED);
6368 } else {
6369 stl_le_p(&n->bar.csts, 0);
6370 }
6371
6372 stl_le_p(&n->bar.intms, 0);
6373 stl_le_p(&n->bar.intmc, 0);
6374 stl_le_p(&n->bar.cc, 0);
6375
6376 n->dbbuf_dbs = 0;
6377 n->dbbuf_eis = 0;
6378 n->dbbuf_enabled = false;
6379 }
6380
6381 static void nvme_ctrl_shutdown(NvmeCtrl *n)
6382 {
6383 NvmeNamespace *ns;
6384 int i;
6385
6386 if (n->pmr.dev) {
6387 memory_region_msync(&n->pmr.dev->mr, 0, n->pmr.dev->size);
6388 }
6389
6390 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
6391 ns = nvme_ns(n, i);
6392 if (!ns) {
6393 continue;
6394 }
6395
6396 nvme_ns_shutdown(ns);
6397 }
6398 }
6399
6400 static void nvme_select_iocs(NvmeCtrl *n)
6401 {
6402 NvmeNamespace *ns;
6403 int i;
6404
6405 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
6406 ns = nvme_ns(n, i);
6407 if (!ns) {
6408 continue;
6409 }
6410
6411 nvme_select_iocs_ns(n, ns);
6412 }
6413 }
6414
6415 static int nvme_start_ctrl(NvmeCtrl *n)
6416 {
6417 uint64_t cap = ldq_le_p(&n->bar.cap);
6418 uint32_t cc = ldl_le_p(&n->bar.cc);
6419 uint32_t aqa = ldl_le_p(&n->bar.aqa);
6420 uint64_t asq = ldq_le_p(&n->bar.asq);
6421 uint64_t acq = ldq_le_p(&n->bar.acq);
6422 uint32_t page_bits = NVME_CC_MPS(cc) + 12;
6423 uint32_t page_size = 1 << page_bits;
6424 NvmeSecCtrlEntry *sctrl = nvme_sctrl(n);
6425
6426 if (pci_is_vf(&n->parent_obj) && !sctrl->scs) {
6427 trace_pci_nvme_err_startfail_virt_state(le16_to_cpu(sctrl->nvi),
6428 le16_to_cpu(sctrl->nvq),
6429 sctrl->scs ? "ONLINE" :
6430 "OFFLINE");
6431 return -1;
6432 }
6433 if (unlikely(n->cq[0])) {
6434 trace_pci_nvme_err_startfail_cq();
6435 return -1;
6436 }
6437 if (unlikely(n->sq[0])) {
6438 trace_pci_nvme_err_startfail_sq();
6439 return -1;
6440 }
6441 if (unlikely(asq & (page_size - 1))) {
6442 trace_pci_nvme_err_startfail_asq_misaligned(asq);
6443 return -1;
6444 }
6445 if (unlikely(acq & (page_size - 1))) {
6446 trace_pci_nvme_err_startfail_acq_misaligned(acq);
6447 return -1;
6448 }
6449 if (unlikely(!(NVME_CAP_CSS(cap) & (1 << NVME_CC_CSS(cc))))) {
6450 trace_pci_nvme_err_startfail_css(NVME_CC_CSS(cc));
6451 return -1;
6452 }
6453 if (unlikely(NVME_CC_MPS(cc) < NVME_CAP_MPSMIN(cap))) {
6454 trace_pci_nvme_err_startfail_page_too_small(
6455 NVME_CC_MPS(cc),
6456 NVME_CAP_MPSMIN(cap));
6457 return -1;
6458 }
6459 if (unlikely(NVME_CC_MPS(cc) >
6460 NVME_CAP_MPSMAX(cap))) {
6461 trace_pci_nvme_err_startfail_page_too_large(
6462 NVME_CC_MPS(cc),
6463 NVME_CAP_MPSMAX(cap));
6464 return -1;
6465 }
6466 if (unlikely(NVME_CC_IOCQES(cc) <
6467 NVME_CTRL_CQES_MIN(n->id_ctrl.cqes))) {
6468 trace_pci_nvme_err_startfail_cqent_too_small(
6469 NVME_CC_IOCQES(cc),
6470 NVME_CTRL_CQES_MIN(cap));
6471 return -1;
6472 }
6473 if (unlikely(NVME_CC_IOCQES(cc) >
6474 NVME_CTRL_CQES_MAX(n->id_ctrl.cqes))) {
6475 trace_pci_nvme_err_startfail_cqent_too_large(
6476 NVME_CC_IOCQES(cc),
6477 NVME_CTRL_CQES_MAX(cap));
6478 return -1;
6479 }
6480 if (unlikely(NVME_CC_IOSQES(cc) <
6481 NVME_CTRL_SQES_MIN(n->id_ctrl.sqes))) {
6482 trace_pci_nvme_err_startfail_sqent_too_small(
6483 NVME_CC_IOSQES(cc),
6484 NVME_CTRL_SQES_MIN(cap));
6485 return -1;
6486 }
6487 if (unlikely(NVME_CC_IOSQES(cc) >
6488 NVME_CTRL_SQES_MAX(n->id_ctrl.sqes))) {
6489 trace_pci_nvme_err_startfail_sqent_too_large(
6490 NVME_CC_IOSQES(cc),
6491 NVME_CTRL_SQES_MAX(cap));
6492 return -1;
6493 }
6494 if (unlikely(!NVME_AQA_ASQS(aqa))) {
6495 trace_pci_nvme_err_startfail_asqent_sz_zero();
6496 return -1;
6497 }
6498 if (unlikely(!NVME_AQA_ACQS(aqa))) {
6499 trace_pci_nvme_err_startfail_acqent_sz_zero();
6500 return -1;
6501 }
6502
6503 n->page_bits = page_bits;
6504 n->page_size = page_size;
6505 n->max_prp_ents = n->page_size / sizeof(uint64_t);
6506 n->cqe_size = 1 << NVME_CC_IOCQES(cc);
6507 n->sqe_size = 1 << NVME_CC_IOSQES(cc);
6508 nvme_init_cq(&n->admin_cq, n, acq, 0, 0, NVME_AQA_ACQS(aqa) + 1, 1);
6509 nvme_init_sq(&n->admin_sq, n, asq, 0, 0, NVME_AQA_ASQS(aqa) + 1);
6510
6511 nvme_set_timestamp(n, 0ULL);
6512
6513 nvme_select_iocs(n);
6514
6515 return 0;
6516 }
6517
6518 static void nvme_cmb_enable_regs(NvmeCtrl *n)
6519 {
6520 uint32_t cmbloc = ldl_le_p(&n->bar.cmbloc);
6521 uint32_t cmbsz = ldl_le_p(&n->bar.cmbsz);
6522
6523 NVME_CMBLOC_SET_CDPCILS(cmbloc, 1);
6524 NVME_CMBLOC_SET_CDPMLS(cmbloc, 1);
6525 NVME_CMBLOC_SET_BIR(cmbloc, NVME_CMB_BIR);
6526 stl_le_p(&n->bar.cmbloc, cmbloc);
6527
6528 NVME_CMBSZ_SET_SQS(cmbsz, 1);
6529 NVME_CMBSZ_SET_CQS(cmbsz, 0);
6530 NVME_CMBSZ_SET_LISTS(cmbsz, 1);
6531 NVME_CMBSZ_SET_RDS(cmbsz, 1);
6532 NVME_CMBSZ_SET_WDS(cmbsz, 1);
6533 NVME_CMBSZ_SET_SZU(cmbsz, 2); /* MBs */
6534 NVME_CMBSZ_SET_SZ(cmbsz, n->params.cmb_size_mb);
6535 stl_le_p(&n->bar.cmbsz, cmbsz);
6536 }
6537
6538 static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
6539 unsigned size)
6540 {
6541 uint64_t cap = ldq_le_p(&n->bar.cap);
6542 uint32_t cc = ldl_le_p(&n->bar.cc);
6543 uint32_t intms = ldl_le_p(&n->bar.intms);
6544 uint32_t csts = ldl_le_p(&n->bar.csts);
6545 uint32_t pmrsts = ldl_le_p(&n->bar.pmrsts);
6546
6547 if (unlikely(offset & (sizeof(uint32_t) - 1))) {
6548 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_misaligned32,
6549 "MMIO write not 32-bit aligned,"
6550 " offset=0x%"PRIx64"", offset);
6551 /* should be ignored, fall through for now */
6552 }
6553
6554 if (unlikely(size < sizeof(uint32_t))) {
6555 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_toosmall,
6556 "MMIO write smaller than 32-bits,"
6557 " offset=0x%"PRIx64", size=%u",
6558 offset, size);
6559 /* should be ignored, fall through for now */
6560 }
6561
6562 switch (offset) {
6563 case NVME_REG_INTMS:
6564 if (unlikely(msix_enabled(&(n->parent_obj)))) {
6565 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix,
6566 "undefined access to interrupt mask set"
6567 " when MSI-X is enabled");
6568 /* should be ignored, fall through for now */
6569 }
6570 intms |= data;
6571 stl_le_p(&n->bar.intms, intms);
6572 n->bar.intmc = n->bar.intms;
6573 trace_pci_nvme_mmio_intm_set(data & 0xffffffff, intms);
6574 nvme_irq_check(n);
6575 break;
6576 case NVME_REG_INTMC:
6577 if (unlikely(msix_enabled(&(n->parent_obj)))) {
6578 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix,
6579 "undefined access to interrupt mask clr"
6580 " when MSI-X is enabled");
6581 /* should be ignored, fall through for now */
6582 }
6583 intms &= ~data;
6584 stl_le_p(&n->bar.intms, intms);
6585 n->bar.intmc = n->bar.intms;
6586 trace_pci_nvme_mmio_intm_clr(data & 0xffffffff, intms);
6587 nvme_irq_check(n);
6588 break;
6589 case NVME_REG_CC:
6590 stl_le_p(&n->bar.cc, data);
6591
6592 trace_pci_nvme_mmio_cfg(data & 0xffffffff);
6593
6594 if (NVME_CC_SHN(data) && !(NVME_CC_SHN(cc))) {
6595 trace_pci_nvme_mmio_shutdown_set();
6596 nvme_ctrl_shutdown(n);
6597 csts &= ~(CSTS_SHST_MASK << CSTS_SHST_SHIFT);
6598 csts |= NVME_CSTS_SHST_COMPLETE;
6599 } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(cc)) {
6600 trace_pci_nvme_mmio_shutdown_cleared();
6601 csts &= ~(CSTS_SHST_MASK << CSTS_SHST_SHIFT);
6602 }
6603
6604 if (NVME_CC_EN(data) && !NVME_CC_EN(cc)) {
6605 if (unlikely(nvme_start_ctrl(n))) {
6606 trace_pci_nvme_err_startfail();
6607 csts = NVME_CSTS_FAILED;
6608 } else {
6609 trace_pci_nvme_mmio_start_success();
6610 csts = NVME_CSTS_READY;
6611 }
6612 } else if (!NVME_CC_EN(data) && NVME_CC_EN(cc)) {
6613 trace_pci_nvme_mmio_stopped();
6614 nvme_ctrl_reset(n, NVME_RESET_CONTROLLER);
6615
6616 break;
6617 }
6618
6619 stl_le_p(&n->bar.csts, csts);
6620
6621 break;
6622 case NVME_REG_CSTS:
6623 if (data & (1 << 4)) {
6624 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported,
6625 "attempted to W1C CSTS.NSSRO"
6626 " but CAP.NSSRS is zero (not supported)");
6627 } else if (data != 0) {
6628 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ro_csts,
6629 "attempted to set a read only bit"
6630 " of controller status");
6631 }
6632 break;
6633 case NVME_REG_NSSR:
6634 if (data == 0x4e564d65) {
6635 trace_pci_nvme_ub_mmiowr_ssreset_unsupported();
6636 } else {
6637 /* The spec says that writes of other values have no effect */
6638 return;
6639 }
6640 break;
6641 case NVME_REG_AQA:
6642 stl_le_p(&n->bar.aqa, data);
6643 trace_pci_nvme_mmio_aqattr(data & 0xffffffff);
6644 break;
6645 case NVME_REG_ASQ:
6646 stn_le_p(&n->bar.asq, size, data);
6647 trace_pci_nvme_mmio_asqaddr(data);
6648 break;
6649 case NVME_REG_ASQ + 4:
6650 stl_le_p((uint8_t *)&n->bar.asq + 4, data);
6651 trace_pci_nvme_mmio_asqaddr_hi(data, ldq_le_p(&n->bar.asq));
6652 break;
6653 case NVME_REG_ACQ:
6654 trace_pci_nvme_mmio_acqaddr(data);
6655 stn_le_p(&n->bar.acq, size, data);
6656 break;
6657 case NVME_REG_ACQ + 4:
6658 stl_le_p((uint8_t *)&n->bar.acq + 4, data);
6659 trace_pci_nvme_mmio_acqaddr_hi(data, ldq_le_p(&n->bar.acq));
6660 break;
6661 case NVME_REG_CMBLOC:
6662 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbloc_reserved,
6663 "invalid write to reserved CMBLOC"
6664 " when CMBSZ is zero, ignored");
6665 return;
6666 case NVME_REG_CMBSZ:
6667 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly,
6668 "invalid write to read only CMBSZ, ignored");
6669 return;
6670 case NVME_REG_CMBMSC:
6671 if (!NVME_CAP_CMBS(cap)) {
6672 return;
6673 }
6674
6675 stn_le_p(&n->bar.cmbmsc, size, data);
6676 n->cmb.cmse = false;
6677
6678 if (NVME_CMBMSC_CRE(data)) {
6679 nvme_cmb_enable_regs(n);
6680
6681 if (NVME_CMBMSC_CMSE(data)) {
6682 uint64_t cmbmsc = ldq_le_p(&n->bar.cmbmsc);
6683 hwaddr cba = NVME_CMBMSC_CBA(cmbmsc) << CMBMSC_CBA_SHIFT;
6684 if (cba + int128_get64(n->cmb.mem.size) < cba) {
6685 uint32_t cmbsts = ldl_le_p(&n->bar.cmbsts);
6686 NVME_CMBSTS_SET_CBAI(cmbsts, 1);
6687 stl_le_p(&n->bar.cmbsts, cmbsts);
6688 return;
6689 }
6690
6691 n->cmb.cba = cba;
6692 n->cmb.cmse = true;
6693 }
6694 } else {
6695 n->bar.cmbsz = 0;
6696 n->bar.cmbloc = 0;
6697 }
6698
6699 return;
6700 case NVME_REG_CMBMSC + 4:
6701 stl_le_p((uint8_t *)&n->bar.cmbmsc + 4, data);
6702 return;
6703
6704 case NVME_REG_PMRCAP:
6705 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly,
6706 "invalid write to PMRCAP register, ignored");
6707 return;
6708 case NVME_REG_PMRCTL:
6709 if (!NVME_CAP_PMRS(cap)) {
6710 return;
6711 }
6712
6713 stl_le_p(&n->bar.pmrctl, data);
6714 if (NVME_PMRCTL_EN(data)) {
6715 memory_region_set_enabled(&n->pmr.dev->mr, true);
6716 pmrsts = 0;
6717 } else {
6718 memory_region_set_enabled(&n->pmr.dev->mr, false);
6719 NVME_PMRSTS_SET_NRDY(pmrsts, 1);
6720 n->pmr.cmse = false;
6721 }
6722 stl_le_p(&n->bar.pmrsts, pmrsts);
6723 return;
6724 case NVME_REG_PMRSTS:
6725 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrsts_readonly,
6726 "invalid write to PMRSTS register, ignored");
6727 return;
6728 case NVME_REG_PMREBS:
6729 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrebs_readonly,
6730 "invalid write to PMREBS register, ignored");
6731 return;
6732 case NVME_REG_PMRSWTP:
6733 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly,
6734 "invalid write to PMRSWTP register, ignored");
6735 return;
6736 case NVME_REG_PMRMSCL:
6737 if (!NVME_CAP_PMRS(cap)) {
6738 return;
6739 }
6740
6741 stl_le_p(&n->bar.pmrmscl, data);
6742 n->pmr.cmse = false;
6743
6744 if (NVME_PMRMSCL_CMSE(data)) {
6745 uint64_t pmrmscu = ldl_le_p(&n->bar.pmrmscu);
6746 hwaddr cba = pmrmscu << 32 |
6747 (NVME_PMRMSCL_CBA(data) << PMRMSCL_CBA_SHIFT);
6748 if (cba + int128_get64(n->pmr.dev->mr.size) < cba) {
6749 NVME_PMRSTS_SET_CBAI(pmrsts, 1);
6750 stl_le_p(&n->bar.pmrsts, pmrsts);
6751 return;
6752 }
6753
6754 n->pmr.cmse = true;
6755 n->pmr.cba = cba;
6756 }
6757
6758 return;
6759 case NVME_REG_PMRMSCU:
6760 if (!NVME_CAP_PMRS(cap)) {
6761 return;
6762 }
6763
6764 stl_le_p(&n->bar.pmrmscu, data);
6765 return;
6766 default:
6767 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid,
6768 "invalid MMIO write,"
6769 " offset=0x%"PRIx64", data=%"PRIx64"",
6770 offset, data);
6771 break;
6772 }
6773 }
6774
6775 static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
6776 {
6777 NvmeCtrl *n = (NvmeCtrl *)opaque;
6778 uint8_t *ptr = (uint8_t *)&n->bar;
6779
6780 trace_pci_nvme_mmio_read(addr, size);
6781
6782 if (unlikely(addr & (sizeof(uint32_t) - 1))) {
6783 NVME_GUEST_ERR(pci_nvme_ub_mmiord_misaligned32,
6784 "MMIO read not 32-bit aligned,"
6785 " offset=0x%"PRIx64"", addr);
6786 /* should RAZ, fall through for now */
6787 } else if (unlikely(size < sizeof(uint32_t))) {
6788 NVME_GUEST_ERR(pci_nvme_ub_mmiord_toosmall,
6789 "MMIO read smaller than 32-bits,"
6790 " offset=0x%"PRIx64"", addr);
6791 /* should RAZ, fall through for now */
6792 }
6793
6794 if (addr > sizeof(n->bar) - size) {
6795 NVME_GUEST_ERR(pci_nvme_ub_mmiord_invalid_ofs,
6796 "MMIO read beyond last register,"
6797 " offset=0x%"PRIx64", returning 0", addr);
6798
6799 return 0;
6800 }
6801
6802 if (pci_is_vf(&n->parent_obj) && !nvme_sctrl(n)->scs &&
6803 addr != NVME_REG_CSTS) {
6804 trace_pci_nvme_err_ignored_mmio_vf_offline(addr, size);
6805 return 0;
6806 }
6807
6808 /*
6809 * When PMRWBM bit 1 is set then read from
6810 * from PMRSTS should ensure prior writes
6811 * made it to persistent media
6812 */
6813 if (addr == NVME_REG_PMRSTS &&
6814 (NVME_PMRCAP_PMRWBM(ldl_le_p(&n->bar.pmrcap)) & 0x02)) {
6815 memory_region_msync(&n->pmr.dev->mr, 0, n->pmr.dev->size);
6816 }
6817
6818 return ldn_le_p(ptr + addr, size);
6819 }
6820
6821 static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
6822 {
6823 uint32_t qid;
6824
6825 if (unlikely(addr & ((1 << 2) - 1))) {
6826 NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned,
6827 "doorbell write not 32-bit aligned,"
6828 " offset=0x%"PRIx64", ignoring", addr);
6829 return;
6830 }
6831
6832 if (((addr - 0x1000) >> 2) & 1) {
6833 /* Completion queue doorbell write */
6834
6835 uint16_t new_head = val & 0xffff;
6836 int start_sqs;
6837 NvmeCQueue *cq;
6838
6839 qid = (addr - (0x1000 + (1 << 2))) >> 3;
6840 if (unlikely(nvme_check_cqid(n, qid))) {
6841 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cq,
6842 "completion queue doorbell write"
6843 " for nonexistent queue,"
6844 " sqid=%"PRIu32", ignoring", qid);
6845
6846 /*
6847 * NVM Express v1.3d, Section 4.1 state: "If host software writes
6848 * an invalid value to the Submission Queue Tail Doorbell or
6849 * Completion Queue Head Doorbell regiter and an Asynchronous Event
6850 * Request command is outstanding, then an asynchronous event is
6851 * posted to the Admin Completion Queue with a status code of
6852 * Invalid Doorbell Write Value."
6853 *
6854 * Also note that the spec includes the "Invalid Doorbell Register"
6855 * status code, but nowhere does it specify when to use it.
6856 * However, it seems reasonable to use it here in a similar
6857 * fashion.
6858 */
6859 if (n->outstanding_aers) {
6860 nvme_enqueue_event(n, NVME_AER_TYPE_ERROR,
6861 NVME_AER_INFO_ERR_INVALID_DB_REGISTER,
6862 NVME_LOG_ERROR_INFO);
6863 }
6864
6865 return;
6866 }
6867
6868 cq = n->cq[qid];
6869 if (unlikely(new_head >= cq->size)) {
6870 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cqhead,
6871 "completion queue doorbell write value"
6872 " beyond queue size, sqid=%"PRIu32","
6873 " new_head=%"PRIu16", ignoring",
6874 qid, new_head);
6875
6876 if (n->outstanding_aers) {
6877 nvme_enqueue_event(n, NVME_AER_TYPE_ERROR,
6878 NVME_AER_INFO_ERR_INVALID_DB_VALUE,
6879 NVME_LOG_ERROR_INFO);
6880 }
6881
6882 return;
6883 }
6884
6885 trace_pci_nvme_mmio_doorbell_cq(cq->cqid, new_head);
6886
6887 start_sqs = nvme_cq_full(cq) ? 1 : 0;
6888 cq->head = new_head;
6889 if (!qid && n->dbbuf_enabled) {
6890 pci_dma_write(&n->parent_obj, cq->db_addr, &cq->head,
6891 sizeof(cq->head));
6892 }
6893 if (start_sqs) {
6894 NvmeSQueue *sq;
6895 QTAILQ_FOREACH(sq, &cq->sq_list, entry) {
6896 qemu_bh_schedule(sq->bh);
6897 }
6898 qemu_bh_schedule(cq->bh);
6899 }
6900
6901 if (cq->tail == cq->head) {
6902 if (cq->irq_enabled) {
6903 n->cq_pending--;
6904 }
6905
6906 nvme_irq_deassert(n, cq);
6907 }
6908 } else {
6909 /* Submission queue doorbell write */
6910
6911 uint16_t new_tail = val & 0xffff;
6912 NvmeSQueue *sq;
6913
6914 qid = (addr - 0x1000) >> 3;
6915 if (unlikely(nvme_check_sqid(n, qid))) {
6916 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sq,
6917 "submission queue doorbell write"
6918 " for nonexistent queue,"
6919 " sqid=%"PRIu32", ignoring", qid);
6920
6921 if (n->outstanding_aers) {
6922 nvme_enqueue_event(n, NVME_AER_TYPE_ERROR,
6923 NVME_AER_INFO_ERR_INVALID_DB_REGISTER,
6924 NVME_LOG_ERROR_INFO);
6925 }
6926
6927 return;
6928 }
6929
6930 sq = n->sq[qid];
6931 if (unlikely(new_tail >= sq->size)) {
6932 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sqtail,
6933 "submission queue doorbell write value"
6934 " beyond queue size, sqid=%"PRIu32","
6935 " new_tail=%"PRIu16", ignoring",
6936 qid, new_tail);
6937
6938 if (n->outstanding_aers) {
6939 nvme_enqueue_event(n, NVME_AER_TYPE_ERROR,
6940 NVME_AER_INFO_ERR_INVALID_DB_VALUE,
6941 NVME_LOG_ERROR_INFO);
6942 }
6943
6944 return;
6945 }
6946
6947 trace_pci_nvme_mmio_doorbell_sq(sq->sqid, new_tail);
6948
6949 sq->tail = new_tail;
6950 if (!qid && n->dbbuf_enabled) {
6951 /*
6952 * The spec states "the host shall also update the controller's
6953 * corresponding doorbell property to match the value of that entry
6954 * in the Shadow Doorbell buffer."
6955 *
6956 * Since this context is currently a VM trap, we can safely enforce
6957 * the requirement from the device side in case the host is
6958 * misbehaving.
6959 *
6960 * Note, we shouldn't have to do this, but various drivers
6961 * including ones that run on Linux, are not updating Admin Queues,
6962 * so we can't trust reading it for an appropriate sq tail.
6963 */
6964 pci_dma_write(&n->parent_obj, sq->db_addr, &sq->tail,
6965 sizeof(sq->tail));
6966 }
6967
6968 qemu_bh_schedule(sq->bh);
6969 }
6970 }
6971
6972 static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data,
6973 unsigned size)
6974 {
6975 NvmeCtrl *n = (NvmeCtrl *)opaque;
6976
6977 trace_pci_nvme_mmio_write(addr, data, size);
6978
6979 if (pci_is_vf(&n->parent_obj) && !nvme_sctrl(n)->scs &&
6980 addr != NVME_REG_CSTS) {
6981 trace_pci_nvme_err_ignored_mmio_vf_offline(addr, size);
6982 return;
6983 }
6984
6985 if (addr < sizeof(n->bar)) {
6986 nvme_write_bar(n, addr, data, size);
6987 } else {
6988 nvme_process_db(n, addr, data);
6989 }
6990 }
6991
6992 static const MemoryRegionOps nvme_mmio_ops = {
6993 .read = nvme_mmio_read,
6994 .write = nvme_mmio_write,
6995 .endianness = DEVICE_LITTLE_ENDIAN,
6996 .impl = {
6997 .min_access_size = 2,
6998 .max_access_size = 8,
6999 },
7000 };
7001
7002 static void nvme_cmb_write(void *opaque, hwaddr addr, uint64_t data,
7003 unsigned size)
7004 {
7005 NvmeCtrl *n = (NvmeCtrl *)opaque;
7006 stn_le_p(&n->cmb.buf[addr], size, data);
7007 }
7008
7009 static uint64_t nvme_cmb_read(void *opaque, hwaddr addr, unsigned size)
7010 {
7011 NvmeCtrl *n = (NvmeCtrl *)opaque;
7012 return ldn_le_p(&n->cmb.buf[addr], size);
7013 }
7014
7015 static const MemoryRegionOps nvme_cmb_ops = {
7016 .read = nvme_cmb_read,
7017 .write = nvme_cmb_write,
7018 .endianness = DEVICE_LITTLE_ENDIAN,
7019 .impl = {
7020 .min_access_size = 1,
7021 .max_access_size = 8,
7022 },
7023 };
7024
7025 static void nvme_check_constraints(NvmeCtrl *n, Error **errp)
7026 {
7027 NvmeParams *params = &n->params;
7028
7029 if (params->num_queues) {
7030 warn_report("num_queues is deprecated; please use max_ioqpairs "
7031 "instead");
7032
7033 params->max_ioqpairs = params->num_queues - 1;
7034 }
7035
7036 if (n->namespace.blkconf.blk && n->subsys) {
7037 error_setg(errp, "subsystem support is unavailable with legacy "
7038 "namespace ('drive' property)");
7039 return;
7040 }
7041
7042 if (params->max_ioqpairs < 1 ||
7043 params->max_ioqpairs > NVME_MAX_IOQPAIRS) {
7044 error_setg(errp, "max_ioqpairs must be between 1 and %d",
7045 NVME_MAX_IOQPAIRS);
7046 return;
7047 }
7048
7049 if (params->msix_qsize < 1 ||
7050 params->msix_qsize > PCI_MSIX_FLAGS_QSIZE + 1) {
7051 error_setg(errp, "msix_qsize must be between 1 and %d",
7052 PCI_MSIX_FLAGS_QSIZE + 1);
7053 return;
7054 }
7055
7056 if (!params->serial) {
7057 error_setg(errp, "serial property not set");
7058 return;
7059 }
7060
7061 if (n->pmr.dev) {
7062 if (host_memory_backend_is_mapped(n->pmr.dev)) {
7063 error_setg(errp, "can't use already busy memdev: %s",
7064 object_get_canonical_path_component(OBJECT(n->pmr.dev)));
7065 return;
7066 }
7067
7068 if (!is_power_of_2(n->pmr.dev->size)) {
7069 error_setg(errp, "pmr backend size needs to be power of 2 in size");
7070 return;
7071 }
7072
7073 host_memory_backend_set_mapped(n->pmr.dev, true);
7074 }
7075
7076 if (n->params.zasl > n->params.mdts) {
7077 error_setg(errp, "zoned.zasl (Zone Append Size Limit) must be less "
7078 "than or equal to mdts (Maximum Data Transfer Size)");
7079 return;
7080 }
7081
7082 if (!n->params.vsl) {
7083 error_setg(errp, "vsl must be non-zero");
7084 return;
7085 }
7086
7087 if (params->sriov_max_vfs) {
7088 if (!n->subsys) {
7089 error_setg(errp, "subsystem is required for the use of SR-IOV");
7090 return;
7091 }
7092
7093 if (params->sriov_max_vfs > NVME_MAX_VFS) {
7094 error_setg(errp, "sriov_max_vfs must be between 0 and %d",
7095 NVME_MAX_VFS);
7096 return;
7097 }
7098
7099 if (params->cmb_size_mb) {
7100 error_setg(errp, "CMB is not supported with SR-IOV");
7101 return;
7102 }
7103
7104 if (n->pmr.dev) {
7105 error_setg(errp, "PMR is not supported with SR-IOV");
7106 return;
7107 }
7108
7109 if (!params->sriov_vq_flexible || !params->sriov_vi_flexible) {
7110 error_setg(errp, "both sriov_vq_flexible and sriov_vi_flexible"
7111 " must be set for the use of SR-IOV");
7112 return;
7113 }
7114
7115 if (params->sriov_vq_flexible < params->sriov_max_vfs * 2) {
7116 error_setg(errp, "sriov_vq_flexible must be greater than or equal"
7117 " to %d (sriov_max_vfs * 2)", params->sriov_max_vfs * 2);
7118 return;
7119 }
7120
7121 if (params->max_ioqpairs < params->sriov_vq_flexible + 2) {
7122 error_setg(errp, "(max_ioqpairs - sriov_vq_flexible) must be"
7123 " greater than or equal to 2");
7124 return;
7125 }
7126
7127 if (params->sriov_vi_flexible < params->sriov_max_vfs) {
7128 error_setg(errp, "sriov_vi_flexible must be greater than or equal"
7129 " to %d (sriov_max_vfs)", params->sriov_max_vfs);
7130 return;
7131 }
7132
7133 if (params->msix_qsize < params->sriov_vi_flexible + 1) {
7134 error_setg(errp, "(msix_qsize - sriov_vi_flexible) must be"
7135 " greater than or equal to 1");
7136 return;
7137 }
7138
7139 if (params->sriov_max_vi_per_vf &&
7140 (params->sriov_max_vi_per_vf - 1) % NVME_VF_RES_GRANULARITY) {
7141 error_setg(errp, "sriov_max_vi_per_vf must meet:"
7142 " (sriov_max_vi_per_vf - 1) %% %d == 0 and"
7143 " sriov_max_vi_per_vf >= 1", NVME_VF_RES_GRANULARITY);
7144 return;
7145 }
7146
7147 if (params->sriov_max_vq_per_vf &&
7148 (params->sriov_max_vq_per_vf < 2 ||
7149 (params->sriov_max_vq_per_vf - 1) % NVME_VF_RES_GRANULARITY)) {
7150 error_setg(errp, "sriov_max_vq_per_vf must meet:"
7151 " (sriov_max_vq_per_vf - 1) %% %d == 0 and"
7152 " sriov_max_vq_per_vf >= 2", NVME_VF_RES_GRANULARITY);
7153 return;
7154 }
7155 }
7156 }
7157
7158 static void nvme_init_state(NvmeCtrl *n)
7159 {
7160 NvmePriCtrlCap *cap = &n->pri_ctrl_cap;
7161 NvmeSecCtrlList *list = &n->sec_ctrl_list;
7162 NvmeSecCtrlEntry *sctrl;
7163 uint8_t max_vfs;
7164 int i;
7165
7166 if (pci_is_vf(&n->parent_obj)) {
7167 sctrl = nvme_sctrl(n);
7168 max_vfs = 0;
7169 n->conf_ioqpairs = sctrl->nvq ? le16_to_cpu(sctrl->nvq) - 1 : 0;
7170 n->conf_msix_qsize = sctrl->nvi ? le16_to_cpu(sctrl->nvi) : 1;
7171 } else {
7172 max_vfs = n->params.sriov_max_vfs;
7173 n->conf_ioqpairs = n->params.max_ioqpairs;
7174 n->conf_msix_qsize = n->params.msix_qsize;
7175 }
7176
7177 n->sq = g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1);
7178 n->cq = g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1);
7179 n->temperature = NVME_TEMPERATURE;
7180 n->features.temp_thresh_hi = NVME_TEMPERATURE_WARNING;
7181 n->starttime_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
7182 n->aer_reqs = g_new0(NvmeRequest *, n->params.aerl + 1);
7183 QTAILQ_INIT(&n->aer_queue);
7184
7185 list->numcntl = cpu_to_le16(max_vfs);
7186 for (i = 0; i < max_vfs; i++) {
7187 sctrl = &list->sec[i];
7188 sctrl->pcid = cpu_to_le16(n->cntlid);
7189 sctrl->vfn = cpu_to_le16(i + 1);
7190 }
7191
7192 cap->cntlid = cpu_to_le16(n->cntlid);
7193 cap->crt = NVME_CRT_VQ | NVME_CRT_VI;
7194
7195 if (pci_is_vf(&n->parent_obj)) {
7196 cap->vqprt = cpu_to_le16(1 + n->conf_ioqpairs);
7197 } else {
7198 cap->vqprt = cpu_to_le16(1 + n->params.max_ioqpairs -
7199 n->params.sriov_vq_flexible);
7200 cap->vqfrt = cpu_to_le32(n->params.sriov_vq_flexible);
7201 cap->vqrfap = cap->vqfrt;
7202 cap->vqgran = cpu_to_le16(NVME_VF_RES_GRANULARITY);
7203 cap->vqfrsm = n->params.sriov_max_vq_per_vf ?
7204 cpu_to_le16(n->params.sriov_max_vq_per_vf) :
7205 cap->vqfrt / MAX(max_vfs, 1);
7206 }
7207
7208 if (pci_is_vf(&n->parent_obj)) {
7209 cap->viprt = cpu_to_le16(n->conf_msix_qsize);
7210 } else {
7211 cap->viprt = cpu_to_le16(n->params.msix_qsize -
7212 n->params.sriov_vi_flexible);
7213 cap->vifrt = cpu_to_le32(n->params.sriov_vi_flexible);
7214 cap->virfap = cap->vifrt;
7215 cap->vigran = cpu_to_le16(NVME_VF_RES_GRANULARITY);
7216 cap->vifrsm = n->params.sriov_max_vi_per_vf ?
7217 cpu_to_le16(n->params.sriov_max_vi_per_vf) :
7218 cap->vifrt / MAX(max_vfs, 1);
7219 }
7220 }
7221
7222 static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
7223 {
7224 uint64_t cmb_size = n->params.cmb_size_mb * MiB;
7225 uint64_t cap = ldq_le_p(&n->bar.cap);
7226
7227 n->cmb.buf = g_malloc0(cmb_size);
7228 memory_region_init_io(&n->cmb.mem, OBJECT(n), &nvme_cmb_ops, n,
7229 "nvme-cmb", cmb_size);
7230 pci_register_bar(pci_dev, NVME_CMB_BIR,
7231 PCI_BASE_ADDRESS_SPACE_MEMORY |
7232 PCI_BASE_ADDRESS_MEM_TYPE_64 |
7233 PCI_BASE_ADDRESS_MEM_PREFETCH, &n->cmb.mem);
7234
7235 NVME_CAP_SET_CMBS(cap, 1);
7236 stq_le_p(&n->bar.cap, cap);
7237
7238 if (n->params.legacy_cmb) {
7239 nvme_cmb_enable_regs(n);
7240 n->cmb.cmse = true;
7241 }
7242 }
7243
7244 static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
7245 {
7246 uint32_t pmrcap = ldl_le_p(&n->bar.pmrcap);
7247
7248 NVME_PMRCAP_SET_RDS(pmrcap, 1);
7249 NVME_PMRCAP_SET_WDS(pmrcap, 1);
7250 NVME_PMRCAP_SET_BIR(pmrcap, NVME_PMR_BIR);
7251 /* Turn on bit 1 support */
7252 NVME_PMRCAP_SET_PMRWBM(pmrcap, 0x02);
7253 NVME_PMRCAP_SET_CMSS(pmrcap, 1);
7254 stl_le_p(&n->bar.pmrcap, pmrcap);
7255
7256 pci_register_bar(pci_dev, NVME_PMR_BIR,
7257 PCI_BASE_ADDRESS_SPACE_MEMORY |
7258 PCI_BASE_ADDRESS_MEM_TYPE_64 |
7259 PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmr.dev->mr);
7260
7261 memory_region_set_enabled(&n->pmr.dev->mr, false);
7262 }
7263
7264 static uint64_t nvme_bar_size(unsigned total_queues, unsigned total_irqs,
7265 unsigned *msix_table_offset,
7266 unsigned *msix_pba_offset)
7267 {
7268 uint64_t bar_size, msix_table_size, msix_pba_size;
7269
7270 bar_size = sizeof(NvmeBar) + 2 * total_queues * NVME_DB_SIZE;
7271 bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
7272
7273 if (msix_table_offset) {
7274 *msix_table_offset = bar_size;
7275 }
7276
7277 msix_table_size = PCI_MSIX_ENTRY_SIZE * total_irqs;
7278 bar_size += msix_table_size;
7279 bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
7280
7281 if (msix_pba_offset) {
7282 *msix_pba_offset = bar_size;
7283 }
7284
7285 msix_pba_size = QEMU_ALIGN_UP(total_irqs, 64) / 8;
7286 bar_size += msix_pba_size;
7287
7288 bar_size = pow2ceil(bar_size);
7289 return bar_size;
7290 }
7291
7292 static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset)
7293 {
7294 uint16_t vf_dev_id = n->params.use_intel_id ?
7295 PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME;
7296 NvmePriCtrlCap *cap = &n->pri_ctrl_cap;
7297 uint64_t bar_size = nvme_bar_size(le16_to_cpu(cap->vqfrsm),
7298 le16_to_cpu(cap->vifrsm),
7299 NULL, NULL);
7300
7301 pcie_sriov_pf_init(pci_dev, offset, "nvme", vf_dev_id,
7302 n->params.sriov_max_vfs, n->params.sriov_max_vfs,
7303 NVME_VF_OFFSET, NVME_VF_STRIDE);
7304
7305 pcie_sriov_pf_init_vf_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
7306 PCI_BASE_ADDRESS_MEM_TYPE_64, bar_size);
7307 }
7308
7309 static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset)
7310 {
7311 Error *err = NULL;
7312 int ret;
7313
7314 ret = pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset,
7315 PCI_PM_SIZEOF, &err);
7316 if (err) {
7317 error_report_err(err);
7318 return ret;
7319 }
7320
7321 pci_set_word(pci_dev->config + offset + PCI_PM_PMC,
7322 PCI_PM_CAP_VER_1_2);
7323 pci_set_word(pci_dev->config + offset + PCI_PM_CTRL,
7324 PCI_PM_CTRL_NO_SOFT_RESET);
7325 pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL,
7326 PCI_PM_CTRL_STATE_MASK);
7327
7328 return 0;
7329 }
7330
7331 static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
7332 {
7333 uint8_t *pci_conf = pci_dev->config;
7334 uint64_t bar_size;
7335 unsigned msix_table_offset, msix_pba_offset;
7336 int ret;
7337
7338 Error *err = NULL;
7339
7340 pci_conf[PCI_INTERRUPT_PIN] = 1;
7341 pci_config_set_prog_interface(pci_conf, 0x2);
7342
7343 if (n->params.use_intel_id) {
7344 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
7345 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_NVME);
7346 } else {
7347 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REDHAT);
7348 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REDHAT_NVME);
7349 }
7350
7351 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS);
7352 nvme_add_pm_capability(pci_dev, 0x60);
7353 pcie_endpoint_cap_init(pci_dev, 0x80);
7354 pcie_cap_flr_init(pci_dev);
7355 if (n->params.sriov_max_vfs) {
7356 pcie_ari_init(pci_dev, 0x100, 1);
7357 }
7358
7359 /* add one to max_ioqpairs to account for the admin queue pair */
7360 bar_size = nvme_bar_size(n->params.max_ioqpairs + 1, n->params.msix_qsize,
7361 &msix_table_offset, &msix_pba_offset);
7362
7363 memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size);
7364 memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme",
7365 msix_table_offset);
7366 memory_region_add_subregion(&n->bar0, 0, &n->iomem);
7367
7368 if (pci_is_vf(pci_dev)) {
7369 pcie_sriov_vf_register_bar(pci_dev, 0, &n->bar0);
7370 } else {
7371 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
7372 PCI_BASE_ADDRESS_MEM_TYPE_64, &n->bar0);
7373 }
7374 ret = msix_init(pci_dev, n->params.msix_qsize,
7375 &n->bar0, 0, msix_table_offset,
7376 &n->bar0, 0, msix_pba_offset, 0, &err);
7377 if (ret < 0) {
7378 if (ret == -ENOTSUP) {
7379 warn_report_err(err);
7380 } else {
7381 error_propagate(errp, err);
7382 return ret;
7383 }
7384 }
7385
7386 nvme_update_msixcap_ts(pci_dev, n->conf_msix_qsize);
7387
7388 if (n->params.cmb_size_mb) {
7389 nvme_init_cmb(n, pci_dev);
7390 }
7391
7392 if (n->pmr.dev) {
7393 nvme_init_pmr(n, pci_dev);
7394 }
7395
7396 if (!pci_is_vf(pci_dev) && n->params.sriov_max_vfs) {
7397 nvme_init_sriov(n, pci_dev, 0x120);
7398 }
7399
7400 return 0;
7401 }
7402
7403 static void nvme_init_subnqn(NvmeCtrl *n)
7404 {
7405 NvmeSubsystem *subsys = n->subsys;
7406 NvmeIdCtrl *id = &n->id_ctrl;
7407
7408 if (!subsys) {
7409 snprintf((char *)id->subnqn, sizeof(id->subnqn),
7410 "nqn.2019-08.org.qemu:%s", n->params.serial);
7411 } else {
7412 pstrcpy((char *)id->subnqn, sizeof(id->subnqn), (char*)subsys->subnqn);
7413 }
7414 }
7415
7416 static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
7417 {
7418 NvmeIdCtrl *id = &n->id_ctrl;
7419 uint8_t *pci_conf = pci_dev->config;
7420 uint64_t cap = ldq_le_p(&n->bar.cap);
7421 NvmeSecCtrlEntry *sctrl = nvme_sctrl(n);
7422
7423 id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
7424 id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
7425 strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
7426 strpadcpy((char *)id->fr, sizeof(id->fr), QEMU_VERSION, ' ');
7427 strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' ');
7428
7429 id->cntlid = cpu_to_le16(n->cntlid);
7430
7431 id->oaes = cpu_to_le32(NVME_OAES_NS_ATTR);
7432 id->ctratt |= cpu_to_le32(NVME_CTRATT_ELBAS);
7433
7434 id->rab = 6;
7435
7436 if (n->params.use_intel_id) {
7437 id->ieee[0] = 0xb3;
7438 id->ieee[1] = 0x02;
7439 id->ieee[2] = 0x00;
7440 } else {
7441 id->ieee[0] = 0x00;
7442 id->ieee[1] = 0x54;
7443 id->ieee[2] = 0x52;
7444 }
7445
7446 id->mdts = n->params.mdts;
7447 id->ver = cpu_to_le32(NVME_SPEC_VER);
7448 id->oacs =
7449 cpu_to_le16(NVME_OACS_NS_MGMT | NVME_OACS_FORMAT | NVME_OACS_DBBUF);
7450 id->cntrltype = 0x1;
7451
7452 /*
7453 * Because the controller always completes the Abort command immediately,
7454 * there can never be more than one concurrently executing Abort command,
7455 * so this value is never used for anything. Note that there can easily be
7456 * many Abort commands in the queues, but they are not considered
7457 * "executing" until processed by nvme_abort.
7458 *
7459 * The specification recommends a value of 3 for Abort Command Limit (four
7460 * concurrently outstanding Abort commands), so lets use that though it is
7461 * inconsequential.
7462 */
7463 id->acl = 3;
7464 id->aerl = n->params.aerl;
7465 id->frmw = (NVME_NUM_FW_SLOTS << 1) | NVME_FRMW_SLOT1_RO;
7466 id->lpa = NVME_LPA_NS_SMART | NVME_LPA_CSE | NVME_LPA_EXTENDED;
7467
7468 /* recommended default value (~70 C) */
7469 id->wctemp = cpu_to_le16(NVME_TEMPERATURE_WARNING);
7470 id->cctemp = cpu_to_le16(NVME_TEMPERATURE_CRITICAL);
7471
7472 id->sqes = (0x6 << 4) | 0x6;
7473 id->cqes = (0x4 << 4) | 0x4;
7474 id->nn = cpu_to_le32(NVME_MAX_NAMESPACES);
7475 id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP |
7476 NVME_ONCS_FEATURES | NVME_ONCS_DSM |
7477 NVME_ONCS_COMPARE | NVME_ONCS_COPY);
7478
7479 /*
7480 * NOTE: If this device ever supports a command set that does NOT use 0x0
7481 * as a Flush-equivalent operation, support for the broadcast NSID in Flush
7482 * should probably be removed.
7483 *
7484 * See comment in nvme_io_cmd.
7485 */
7486 id->vwc = NVME_VWC_NSID_BROADCAST_SUPPORT | NVME_VWC_PRESENT;
7487
7488 id->ocfs = cpu_to_le16(NVME_OCFS_COPY_FORMAT_0 | NVME_OCFS_COPY_FORMAT_1);
7489 id->sgls = cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN);
7490
7491 nvme_init_subnqn(n);
7492
7493 id->psd[0].mp = cpu_to_le16(0x9c4);
7494 id->psd[0].enlat = cpu_to_le32(0x10);
7495 id->psd[0].exlat = cpu_to_le32(0x4);
7496
7497 if (n->subsys) {
7498 id->cmic |= NVME_CMIC_MULTI_CTRL;
7499 }
7500
7501 NVME_CAP_SET_MQES(cap, 0x7ff);
7502 NVME_CAP_SET_CQR(cap, 1);
7503 NVME_CAP_SET_TO(cap, 0xf);
7504 NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_NVM);
7505 NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_CSI_SUPP);
7506 NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_ADMIN_ONLY);
7507 NVME_CAP_SET_MPSMAX(cap, 4);
7508 NVME_CAP_SET_CMBS(cap, n->params.cmb_size_mb ? 1 : 0);
7509 NVME_CAP_SET_PMRS(cap, n->pmr.dev ? 1 : 0);
7510 stq_le_p(&n->bar.cap, cap);
7511
7512 stl_le_p(&n->bar.vs, NVME_SPEC_VER);
7513 n->bar.intmc = n->bar.intms = 0;
7514
7515 if (pci_is_vf(&n->parent_obj) && !sctrl->scs) {
7516 stl_le_p(&n->bar.csts, NVME_CSTS_FAILED);
7517 }
7518 }
7519
7520 static int nvme_init_subsys(NvmeCtrl *n, Error **errp)
7521 {
7522 int cntlid;
7523
7524 if (!n->subsys) {
7525 return 0;
7526 }
7527
7528 cntlid = nvme_subsys_register_ctrl(n, errp);
7529 if (cntlid < 0) {
7530 return -1;
7531 }
7532
7533 n->cntlid = cntlid;
7534
7535 return 0;
7536 }
7537
7538 void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns)
7539 {
7540 uint32_t nsid = ns->params.nsid;
7541 assert(nsid && nsid <= NVME_MAX_NAMESPACES);
7542
7543 n->namespaces[nsid] = ns;
7544 ns->attached++;
7545
7546 n->dmrsl = MIN_NON_ZERO(n->dmrsl,
7547 BDRV_REQUEST_MAX_BYTES / nvme_l2b(ns, 1));
7548 }
7549
7550 static void nvme_realize(PCIDevice *pci_dev, Error **errp)
7551 {
7552 NvmeCtrl *n = NVME(pci_dev);
7553 NvmeNamespace *ns;
7554 Error *local_err = NULL;
7555 NvmeCtrl *pn = NVME(pcie_sriov_get_pf(pci_dev));
7556
7557 if (pci_is_vf(pci_dev)) {
7558 /*
7559 * VFs derive settings from the parent. PF's lifespan exceeds
7560 * that of VF's, so it's safe to share params.serial.
7561 */
7562 memcpy(&n->params, &pn->params, sizeof(NvmeParams));
7563 n->subsys = pn->subsys;
7564 }
7565
7566 nvme_check_constraints(n, &local_err);
7567 if (local_err) {
7568 error_propagate(errp, local_err);
7569 return;
7570 }
7571
7572 qbus_init(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS,
7573 &pci_dev->qdev, n->parent_obj.qdev.id);
7574
7575 if (nvme_init_subsys(n, errp)) {
7576 error_propagate(errp, local_err);
7577 return;
7578 }
7579 nvme_init_state(n);
7580 if (nvme_init_pci(n, pci_dev, errp)) {
7581 return;
7582 }
7583 nvme_init_ctrl(n, pci_dev);
7584
7585 /* setup a namespace if the controller drive property was given */
7586 if (n->namespace.blkconf.blk) {
7587 ns = &n->namespace;
7588 ns->params.nsid = 1;
7589
7590 if (nvme_ns_setup(ns, errp)) {
7591 return;
7592 }
7593
7594 nvme_attach_ns(n, ns);
7595 }
7596 }
7597
7598 static void nvme_exit(PCIDevice *pci_dev)
7599 {
7600 NvmeCtrl *n = NVME(pci_dev);
7601 NvmeNamespace *ns;
7602 int i;
7603
7604 nvme_ctrl_reset(n, NVME_RESET_FUNCTION);
7605
7606 if (n->subsys) {
7607 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
7608 ns = nvme_ns(n, i);
7609 if (ns) {
7610 ns->attached--;
7611 }
7612 }
7613
7614 nvme_subsys_unregister_ctrl(n->subsys, n);
7615 }
7616
7617 g_free(n->cq);
7618 g_free(n->sq);
7619 g_free(n->aer_reqs);
7620
7621 if (n->params.cmb_size_mb) {
7622 g_free(n->cmb.buf);
7623 }
7624
7625 if (n->pmr.dev) {
7626 host_memory_backend_set_mapped(n->pmr.dev, false);
7627 }
7628
7629 if (!pci_is_vf(pci_dev) && n->params.sriov_max_vfs) {
7630 pcie_sriov_pf_exit(pci_dev);
7631 }
7632
7633 msix_uninit(pci_dev, &n->bar0, &n->bar0);
7634 memory_region_del_subregion(&n->bar0, &n->iomem);
7635 }
7636
7637 static Property nvme_props[] = {
7638 DEFINE_BLOCK_PROPERTIES(NvmeCtrl, namespace.blkconf),
7639 DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmr.dev, TYPE_MEMORY_BACKEND,
7640 HostMemoryBackend *),
7641 DEFINE_PROP_LINK("subsys", NvmeCtrl, subsys, TYPE_NVME_SUBSYS,
7642 NvmeSubsystem *),
7643 DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial),
7644 DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, params.cmb_size_mb, 0),
7645 DEFINE_PROP_UINT32("num_queues", NvmeCtrl, params.num_queues, 0),
7646 DEFINE_PROP_UINT32("max_ioqpairs", NvmeCtrl, params.max_ioqpairs, 64),
7647 DEFINE_PROP_UINT16("msix_qsize", NvmeCtrl, params.msix_qsize, 65),
7648 DEFINE_PROP_UINT8("aerl", NvmeCtrl, params.aerl, 3),
7649 DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, 64),
7650 DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7),
7651 DEFINE_PROP_UINT8("vsl", NvmeCtrl, params.vsl, 7),
7652 DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl, params.use_intel_id, false),
7653 DEFINE_PROP_BOOL("legacy-cmb", NvmeCtrl, params.legacy_cmb, false),
7654 DEFINE_PROP_BOOL("ioeventfd", NvmeCtrl, params.ioeventfd, false),
7655 DEFINE_PROP_UINT8("zoned.zasl", NvmeCtrl, params.zasl, 0),
7656 DEFINE_PROP_BOOL("zoned.auto_transition", NvmeCtrl,
7657 params.auto_transition_zones, true),
7658 DEFINE_PROP_UINT8("sriov_max_vfs", NvmeCtrl, params.sriov_max_vfs, 0),
7659 DEFINE_PROP_UINT16("sriov_vq_flexible", NvmeCtrl,
7660 params.sriov_vq_flexible, 0),
7661 DEFINE_PROP_UINT16("sriov_vi_flexible", NvmeCtrl,
7662 params.sriov_vi_flexible, 0),
7663 DEFINE_PROP_UINT8("sriov_max_vi_per_vf", NvmeCtrl,
7664 params.sriov_max_vi_per_vf, 0),
7665 DEFINE_PROP_UINT8("sriov_max_vq_per_vf", NvmeCtrl,
7666 params.sriov_max_vq_per_vf, 0),
7667 DEFINE_PROP_END_OF_LIST(),
7668 };
7669
7670 static void nvme_get_smart_warning(Object *obj, Visitor *v, const char *name,
7671 void *opaque, Error **errp)
7672 {
7673 NvmeCtrl *n = NVME(obj);
7674 uint8_t value = n->smart_critical_warning;
7675
7676 visit_type_uint8(v, name, &value, errp);
7677 }
7678
7679 static void nvme_set_smart_warning(Object *obj, Visitor *v, const char *name,
7680 void *opaque, Error **errp)
7681 {
7682 NvmeCtrl *n = NVME(obj);
7683 uint8_t value, old_value, cap = 0, index, event;
7684
7685 if (!visit_type_uint8(v, name, &value, errp)) {
7686 return;
7687 }
7688
7689 cap = NVME_SMART_SPARE | NVME_SMART_TEMPERATURE | NVME_SMART_RELIABILITY
7690 | NVME_SMART_MEDIA_READ_ONLY | NVME_SMART_FAILED_VOLATILE_MEDIA;
7691 if (NVME_CAP_PMRS(ldq_le_p(&n->bar.cap))) {
7692 cap |= NVME_SMART_PMR_UNRELIABLE;
7693 }
7694
7695 if ((value & cap) != value) {
7696 error_setg(errp, "unsupported smart critical warning bits: 0x%x",
7697 value & ~cap);
7698 return;
7699 }
7700
7701 old_value = n->smart_critical_warning;
7702 n->smart_critical_warning = value;
7703
7704 /* only inject new bits of smart critical warning */
7705 for (index = 0; index < NVME_SMART_WARN_MAX; index++) {
7706 event = 1 << index;
7707 if (value & ~old_value & event)
7708 nvme_smart_event(n, event);
7709 }
7710 }
7711
7712 static void nvme_pci_reset(DeviceState *qdev)
7713 {
7714 PCIDevice *pci_dev = PCI_DEVICE(qdev);
7715 NvmeCtrl *n = NVME(pci_dev);
7716
7717 trace_pci_nvme_pci_reset();
7718 nvme_ctrl_reset(n, NVME_RESET_FUNCTION);
7719 }
7720
7721 static void nvme_sriov_pre_write_ctrl(PCIDevice *dev, uint32_t address,
7722 uint32_t val, int len)
7723 {
7724 NvmeCtrl *n = NVME(dev);
7725 NvmeSecCtrlEntry *sctrl;
7726 uint16_t sriov_cap = dev->exp.sriov_cap;
7727 uint32_t off = address - sriov_cap;
7728 int i, num_vfs;
7729
7730 if (!sriov_cap) {
7731 return;
7732 }
7733
7734 if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) {
7735 if (!(val & PCI_SRIOV_CTRL_VFE)) {
7736 num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF);
7737 for (i = 0; i < num_vfs; i++) {
7738 sctrl = &n->sec_ctrl_list.sec[i];
7739 nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false);
7740 }
7741 }
7742 }
7743 }
7744
7745 static void nvme_pci_write_config(PCIDevice *dev, uint32_t address,
7746 uint32_t val, int len)
7747 {
7748 nvme_sriov_pre_write_ctrl(dev, address, val, len);
7749 pci_default_write_config(dev, address, val, len);
7750 pcie_cap_flr_write_config(dev, address, val, len);
7751 }
7752
7753 static const VMStateDescription nvme_vmstate = {
7754 .name = "nvme",
7755 .unmigratable = 1,
7756 };
7757
7758 static void nvme_class_init(ObjectClass *oc, void *data)
7759 {
7760 DeviceClass *dc = DEVICE_CLASS(oc);
7761 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
7762
7763 pc->realize = nvme_realize;
7764 pc->config_write = nvme_pci_write_config;
7765 pc->exit = nvme_exit;
7766 pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
7767 pc->revision = 2;
7768
7769 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
7770 dc->desc = "Non-Volatile Memory Express";
7771 device_class_set_props(dc, nvme_props);
7772 dc->vmsd = &nvme_vmstate;
7773 dc->reset = nvme_pci_reset;
7774 }
7775
7776 static void nvme_instance_init(Object *obj)
7777 {
7778 NvmeCtrl *n = NVME(obj);
7779
7780 device_add_bootindex_property(obj, &n->namespace.blkconf.bootindex,
7781 "bootindex", "/namespace@1,0",
7782 DEVICE(obj));
7783
7784 object_property_add(obj, "smart_critical_warning", "uint8",
7785 nvme_get_smart_warning,
7786 nvme_set_smart_warning, NULL, NULL);
7787 }
7788
7789 static const TypeInfo nvme_info = {
7790 .name = TYPE_NVME,
7791 .parent = TYPE_PCI_DEVICE,
7792 .instance_size = sizeof(NvmeCtrl),
7793 .instance_init = nvme_instance_init,
7794 .class_init = nvme_class_init,
7795 .interfaces = (InterfaceInfo[]) {
7796 { INTERFACE_PCIE_DEVICE },
7797 { }
7798 },
7799 };
7800
7801 static const TypeInfo nvme_bus_info = {
7802 .name = TYPE_NVME_BUS,
7803 .parent = TYPE_BUS,
7804 .instance_size = sizeof(NvmeBus),
7805 };
7806
7807 static void nvme_register_types(void)
7808 {
7809 type_register_static(&nvme_info);
7810 type_register_static(&nvme_bus_info);
7811 }
7812
7813 type_init(nvme_register_types)
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