4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu-common.h"
24 #include "hw/pci/pci_bridge.h"
25 #include "hw/pci/pcie.h"
26 #include "hw/pci/msix.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/pci_bus.h"
29 #include "hw/pci/pcie_regs.h"
30 #include "qemu/range.h"
34 # define PCIE_DPRINTF(fmt, ...) \
35 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
37 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
39 #define PCIE_DEV_PRINTF(dev, fmt, ...) \
40 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
43 /***************************************************************************
44 * pci express capability helper functions
48 pcie_cap_v1_fill(PCIDevice
*dev
, uint8_t port
, uint8_t type
, uint8_t version
)
50 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
51 uint8_t *cmask
= dev
->cmask
+ dev
->exp
.exp_cap
;
53 /* capability register
54 interrupt message number defaults to 0 */
55 pci_set_word(exp_cap
+ PCI_EXP_FLAGS
,
56 ((type
<< PCI_EXP_FLAGS_TYPE_SHIFT
) & PCI_EXP_FLAGS_TYPE
) |
59 /* device capability register
61 * roll based error reporting bit must be set by all
62 * Functions conforming to the ECN, PCI Express Base
63 * Specification, Revision 1.1., or subsequent PCI Express Base
64 * Specification revisions.
66 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP
, PCI_EXP_DEVCAP_RBER
);
68 pci_set_long(exp_cap
+ PCI_EXP_LNKCAP
,
69 (port
<< PCI_EXP_LNKCAP_PN_SHIFT
) |
70 PCI_EXP_LNKCAP_ASPMS_0S
|
71 QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1
) |
72 QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT
));
74 pci_set_word(exp_cap
+ PCI_EXP_LNKSTA
,
75 QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1
) |
76 QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT
));
78 if (dev
->cap_present
& QEMU_PCIE_LNKSTA_DLLLA
) {
79 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKSTA
,
80 PCI_EXP_LNKSTA_DLLLA
);
83 /* We changed link status bits over time, and changing them across
84 * migrations is generally fine as hardware changes them too.
85 * Let's not bother checking.
87 pci_set_word(cmask
+ PCI_EXP_LNKSTA
, 0);
90 int pcie_cap_init(PCIDevice
*dev
, uint8_t offset
,
91 uint8_t type
, uint8_t port
,
94 /* PCIe cap v2 init */
98 assert(pci_is_express(dev
));
100 pos
= pci_add_capability(dev
, PCI_CAP_ID_EXP
, offset
,
101 PCI_EXP_VER2_SIZEOF
, errp
);
105 dev
->exp
.exp_cap
= pos
;
106 exp_cap
= dev
->config
+ pos
;
108 /* Filling values common with v1 */
109 pcie_cap_v1_fill(dev
, port
, type
, PCI_EXP_FLAGS_VER2
);
111 /* Filling v2 specific values */
112 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP2
,
113 PCI_EXP_DEVCAP2_EFF
| PCI_EXP_DEVCAP2_EETLPP
);
115 pci_set_word(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL2
, PCI_EXP_DEVCTL2_EETLPPB
);
117 if (dev
->cap_present
& QEMU_PCIE_EXTCAP_INIT
) {
118 /* read-only to behave like a 'NULL' Extended Capability Header */
119 pci_set_long(dev
->wmask
+ PCI_CONFIG_SPACE_SIZE
, 0);
125 int pcie_cap_v1_init(PCIDevice
*dev
, uint8_t offset
, uint8_t type
,
128 /* PCIe cap v1 init */
130 Error
*local_err
= NULL
;
132 assert(pci_is_express(dev
));
134 pos
= pci_add_capability(dev
, PCI_CAP_ID_EXP
, offset
,
135 PCI_EXP_VER1_SIZEOF
, &local_err
);
137 error_report_err(local_err
);
140 dev
->exp
.exp_cap
= pos
;
142 pcie_cap_v1_fill(dev
, port
, type
, PCI_EXP_FLAGS_VER1
);
148 pcie_endpoint_cap_common_init(PCIDevice
*dev
, uint8_t offset
, uint8_t cap_size
)
150 uint8_t type
= PCI_EXP_TYPE_ENDPOINT
;
151 Error
*local_err
= NULL
;
155 * Windows guests will report Code 10, device cannot start, if
156 * a regular Endpoint type is exposed on a root complex. These
157 * should instead be Root Complex Integrated Endpoints.
159 if (pci_bus_is_express(pci_get_bus(dev
))
160 && pci_bus_is_root(pci_get_bus(dev
))) {
161 type
= PCI_EXP_TYPE_RC_END
;
164 if (cap_size
== PCI_EXP_VER1_SIZEOF
) {
165 return pcie_cap_v1_init(dev
, offset
, type
, 0);
167 ret
= pcie_cap_init(dev
, offset
, type
, 0, &local_err
);
170 error_report_err(local_err
);
177 int pcie_endpoint_cap_init(PCIDevice
*dev
, uint8_t offset
)
179 return pcie_endpoint_cap_common_init(dev
, offset
, PCI_EXP_VER2_SIZEOF
);
182 int pcie_endpoint_cap_v1_init(PCIDevice
*dev
, uint8_t offset
)
184 return pcie_endpoint_cap_common_init(dev
, offset
, PCI_EXP_VER1_SIZEOF
);
187 void pcie_cap_exit(PCIDevice
*dev
)
189 pci_del_capability(dev
, PCI_CAP_ID_EXP
, PCI_EXP_VER2_SIZEOF
);
192 void pcie_cap_v1_exit(PCIDevice
*dev
)
194 pci_del_capability(dev
, PCI_CAP_ID_EXP
, PCI_EXP_VER1_SIZEOF
);
197 uint8_t pcie_cap_get_type(const PCIDevice
*dev
)
199 uint32_t pos
= dev
->exp
.exp_cap
;
201 return (pci_get_word(dev
->config
+ pos
+ PCI_EXP_FLAGS
) &
202 PCI_EXP_FLAGS_TYPE
) >> PCI_EXP_FLAGS_TYPE_SHIFT
;
206 /* pci express interrupt message number */
207 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
208 void pcie_cap_flags_set_vector(PCIDevice
*dev
, uint8_t vector
)
210 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
212 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_FLAGS
, PCI_EXP_FLAGS_IRQ
);
213 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_FLAGS
,
214 vector
<< PCI_EXP_FLAGS_IRQ_SHIFT
);
217 uint8_t pcie_cap_flags_get_vector(PCIDevice
*dev
)
219 return (pci_get_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_FLAGS
) &
220 PCI_EXP_FLAGS_IRQ
) >> PCI_EXP_FLAGS_IRQ_SHIFT
;
223 void pcie_cap_deverr_init(PCIDevice
*dev
)
225 uint32_t pos
= dev
->exp
.exp_cap
;
226 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP
,
227 PCI_EXP_DEVCAP_RBER
);
228 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL
,
229 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
230 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
231 pci_long_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_DEVSTA
,
232 PCI_EXP_DEVSTA_CED
| PCI_EXP_DEVSTA_NFED
|
233 PCI_EXP_DEVSTA_FED
| PCI_EXP_DEVSTA_URD
);
236 void pcie_cap_deverr_reset(PCIDevice
*dev
)
238 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
239 pci_long_test_and_clear_mask(devctl
,
240 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
241 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
244 void pcie_cap_lnkctl_init(PCIDevice
*dev
)
246 uint32_t pos
= dev
->exp
.exp_cap
;
247 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_LNKCTL
,
248 PCI_EXP_LNKCTL_CCC
| PCI_EXP_LNKCTL_ES
);
251 void pcie_cap_lnkctl_reset(PCIDevice
*dev
)
253 uint8_t *lnkctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_LNKCTL
;
254 pci_long_test_and_clear_mask(lnkctl
,
255 PCI_EXP_LNKCTL_CCC
| PCI_EXP_LNKCTL_ES
);
258 static void hotplug_event_update_event_status(PCIDevice
*dev
)
260 uint32_t pos
= dev
->exp
.exp_cap
;
261 uint8_t *exp_cap
= dev
->config
+ pos
;
262 uint16_t sltctl
= pci_get_word(exp_cap
+ PCI_EXP_SLTCTL
);
263 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
265 dev
->exp
.hpev_notified
= (sltctl
& PCI_EXP_SLTCTL_HPIE
) &&
266 (sltsta
& sltctl
& PCI_EXP_HP_EV_SUPPORTED
);
269 static void hotplug_event_notify(PCIDevice
*dev
)
271 bool prev
= dev
->exp
.hpev_notified
;
273 hotplug_event_update_event_status(dev
);
275 if (prev
== dev
->exp
.hpev_notified
) {
279 /* Note: the logic above does not take into account whether interrupts
280 * are masked. The result is that interrupt will be sent when it is
281 * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
282 * The Port may optionally send an MSI when there are hot-plug events that
283 * occur while interrupt generation is disabled, and interrupt generation is
284 * subsequently enabled. */
285 if (msix_enabled(dev
)) {
286 msix_notify(dev
, pcie_cap_flags_get_vector(dev
));
287 } else if (msi_enabled(dev
)) {
288 msi_notify(dev
, pcie_cap_flags_get_vector(dev
));
290 pci_set_irq(dev
, dev
->exp
.hpev_notified
);
294 static void hotplug_event_clear(PCIDevice
*dev
)
296 hotplug_event_update_event_status(dev
);
297 if (!msix_enabled(dev
) && !msi_enabled(dev
) && !dev
->exp
.hpev_notified
) {
298 pci_irq_deassert(dev
);
303 * A PCI Express Hot-Plug Event has occurred, so update slot status register
304 * and notify OS of the event if necessary.
306 * 6.7.3 PCI Express Hot-Plug Events
307 * 6.7.3.4 Software Notification of Hot-Plug Events
309 static void pcie_cap_slot_event(PCIDevice
*dev
, PCIExpressHotPlugEvent event
)
311 /* Minor optimization: if nothing changed - no event is needed. */
312 if (pci_word_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+
313 PCI_EXP_SLTSTA
, event
)) {
316 hotplug_event_notify(dev
);
319 static void pcie_cap_slot_hotplug_common(PCIDevice
*hotplug_dev
,
321 uint8_t **exp_cap
, Error
**errp
)
323 *exp_cap
= hotplug_dev
->config
+ hotplug_dev
->exp
.exp_cap
;
324 uint16_t sltsta
= pci_get_word(*exp_cap
+ PCI_EXP_SLTSTA
);
326 PCIE_DEV_PRINTF(PCI_DEVICE(dev
), "hotplug state: 0x%x\n", sltsta
);
327 if (sltsta
& PCI_EXP_SLTSTA_EIS
) {
328 /* the slot is electromechanically locked.
329 * This error is propagated up to qdev and then to HMP/QMP.
331 error_setg_errno(errp
, EBUSY
, "slot is electromechanically locked");
335 void pcie_cap_slot_hotplug_cb(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
339 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
341 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev
), dev
, &exp_cap
, errp
);
343 /* Don't send event when device is enabled during qemu machine creation:
344 * it is present on boot, no hotplug event is necessary. We do send an
345 * event when the device is disabled later. */
346 if (!dev
->hotplugged
) {
347 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
349 if (pci_dev
->cap_present
& QEMU_PCIE_LNKSTA_DLLLA
) {
350 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKSTA
,
351 PCI_EXP_LNKSTA_DLLLA
);
356 /* To enable multifunction hot-plug, we just ensure the function
357 * 0 added last. When function 0 is added, we set the sltsta and
358 * inform OS via event notification.
360 if (pci_get_function_0(pci_dev
)) {
361 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
363 if (pci_dev
->cap_present
& QEMU_PCIE_LNKSTA_DLLLA
) {
364 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKSTA
,
365 PCI_EXP_LNKSTA_DLLLA
);
367 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev
),
368 PCI_EXP_HP_EV_PDC
| PCI_EXP_HP_EV_ABP
);
372 static void pcie_unplug_device(PCIBus
*bus
, PCIDevice
*dev
, void *opaque
)
374 object_unparent(OBJECT(dev
));
377 void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler
*hotplug_dev
,
378 DeviceState
*dev
, Error
**errp
)
381 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
382 PCIBus
*bus
= pci_get_bus(pci_dev
);
384 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev
), dev
, &exp_cap
, errp
);
386 /* In case user cancel the operation of multi-function hot-add,
387 * remove the function that is unexposed to guest individually,
388 * without interaction with guest.
390 if (pci_dev
->devfn
&&
392 pcie_unplug_device(bus
, pci_dev
, NULL
);
397 pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev
));
400 /* pci express slot for pci express root/downstream port
401 PCI express capability slot registers */
402 void pcie_cap_slot_init(PCIDevice
*dev
, uint16_t slot
)
404 uint32_t pos
= dev
->exp
.exp_cap
;
406 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_FLAGS
,
409 pci_long_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
410 ~PCI_EXP_SLTCAP_PSN
);
411 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
412 (slot
<< PCI_EXP_SLTCAP_PSN_SHIFT
) |
420 if (dev
->cap_present
& QEMU_PCIE_SLTCAP_PCP
) {
421 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
423 pci_word_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
425 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
429 pci_word_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
432 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
433 PCI_EXP_SLTCTL_PIC_OFF
|
434 PCI_EXP_SLTCTL_AIC_OFF
);
435 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
438 PCI_EXP_SLTCTL_HPIE
|
439 PCI_EXP_SLTCTL_CCIE
|
440 PCI_EXP_SLTCTL_PDCE
|
441 PCI_EXP_SLTCTL_ABPE
);
442 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
443 * make the bit writable here in order to detect 1b is written.
444 * pcie_cap_slot_write_config() test-and-clear the bit, so
445 * this bit always returns 0 to the guest.
447 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
450 pci_word_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_SLTSTA
,
451 PCI_EXP_HP_EV_SUPPORTED
);
453 dev
->exp
.hpev_notified
= false;
455 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev
))),
459 void pcie_cap_slot_reset(PCIDevice
*dev
)
461 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
462 uint8_t port_type
= pcie_cap_get_type(dev
);
464 assert(port_type
== PCI_EXP_TYPE_DOWNSTREAM
||
465 port_type
== PCI_EXP_TYPE_ROOT_PORT
);
467 PCIE_DEV_PRINTF(dev
, "reset\n");
469 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
473 PCI_EXP_SLTCTL_HPIE
|
474 PCI_EXP_SLTCTL_CCIE
|
475 PCI_EXP_SLTCTL_PDCE
|
476 PCI_EXP_SLTCTL_ABPE
);
477 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
,
478 PCI_EXP_SLTCTL_AIC_OFF
);
480 if (dev
->cap_present
& QEMU_PCIE_SLTCAP_PCP
) {
481 /* Downstream ports enforce device number 0. */
482 bool populated
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
))->devices
[0];
486 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
489 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
,
493 pic
= populated
? PCI_EXP_SLTCTL_PIC_ON
: PCI_EXP_SLTCTL_PIC_OFF
;
494 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
, pic
);
497 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
498 PCI_EXP_SLTSTA_EIS
|/* on reset,
499 the lock is released */
504 hotplug_event_update_event_status(dev
);
507 void pcie_cap_slot_write_config(PCIDevice
*dev
,
508 uint32_t addr
, uint32_t val
, int len
)
510 uint32_t pos
= dev
->exp
.exp_cap
;
511 uint8_t *exp_cap
= dev
->config
+ pos
;
512 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
514 if (ranges_overlap(addr
, len
, pos
+ PCI_EXP_SLTSTA
, 2)) {
515 hotplug_event_clear(dev
);
518 if (!ranges_overlap(addr
, len
, pos
+ PCI_EXP_SLTCTL
, 2)) {
522 if (pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
523 PCI_EXP_SLTCTL_EIC
)) {
524 sltsta
^= PCI_EXP_SLTSTA_EIS
; /* toggle PCI_EXP_SLTSTA_EIS bit */
525 pci_set_word(exp_cap
+ PCI_EXP_SLTSTA
, sltsta
);
526 PCIE_DEV_PRINTF(dev
, "PCI_EXP_SLTCTL_EIC: "
527 "sltsta -> 0x%02"PRIx16
"\n",
532 * If the slot is polulated, power indicator is off and power
533 * controller is off, it is safe to detach the devices.
535 if ((sltsta
& PCI_EXP_SLTSTA_PDS
) && (val
& PCI_EXP_SLTCTL_PCC
) &&
536 ((val
& PCI_EXP_SLTCTL_PIC_OFF
) == PCI_EXP_SLTCTL_PIC_OFF
)) {
537 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
));
538 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
539 pcie_unplug_device
, NULL
);
541 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
543 if (dev
->cap_present
& QEMU_PCIE_LNKSTA_DLLLA
) {
544 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_LNKSTA
,
545 PCI_EXP_LNKSTA_DLLLA
);
547 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
551 hotplug_event_notify(dev
);
554 * 6.7.3.2 Command Completed Events
556 * Software issues a command to a hot-plug capable Downstream Port by
557 * issuing a write transaction that targets any portion of the Port’s Slot
558 * Control register. A single write to the Slot Control register is
559 * considered to be a single command, even if the write affects more than
560 * one field in the Slot Control register. In response to this transaction,
561 * the Port must carry out the requested actions and then set the
562 * associated status field for the command completed event. */
564 /* Real hardware might take a while to complete requested command because
565 * physical movement would be involved like locking the electromechanical
566 * lock. However in our case, command is completed instantaneously above,
567 * so send a command completion event right now.
569 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_CCI
);
572 int pcie_cap_slot_post_load(void *opaque
, int version_id
)
574 PCIDevice
*dev
= opaque
;
575 hotplug_event_update_event_status(dev
);
579 void pcie_cap_slot_push_attention_button(PCIDevice
*dev
)
581 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_ABP
);
584 /* root control/capabilities/status. PME isn't emulated for now */
585 void pcie_cap_root_init(PCIDevice
*dev
)
587 pci_set_word(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
,
588 PCI_EXP_RTCTL_SECEE
| PCI_EXP_RTCTL_SENFEE
|
589 PCI_EXP_RTCTL_SEFEE
);
592 void pcie_cap_root_reset(PCIDevice
*dev
)
594 pci_set_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
, 0);
597 /* function level reset(FLR) */
598 void pcie_cap_flr_init(PCIDevice
*dev
)
600 pci_long_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCAP
,
603 /* Although reading BCR_FLR returns always 0,
604 * the bit is made writable here in order to detect the 1b is written
605 * pcie_cap_flr_write_config() test-and-clear the bit, so
606 * this bit always returns 0 to the guest.
608 pci_word_test_and_set_mask(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
,
609 PCI_EXP_DEVCTL_BCR_FLR
);
612 void pcie_cap_flr_write_config(PCIDevice
*dev
,
613 uint32_t addr
, uint32_t val
, int len
)
615 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
616 if (pci_get_word(devctl
) & PCI_EXP_DEVCTL_BCR_FLR
) {
617 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
618 so the handler can detect FLR by looking at this bit. */
619 pci_device_reset(dev
);
620 pci_word_test_and_clear_mask(devctl
, PCI_EXP_DEVCTL_BCR_FLR
);
624 /* Alternative Routing-ID Interpretation (ARI)
625 * forwarding support for root and downstream ports
627 void pcie_cap_arifwd_init(PCIDevice
*dev
)
629 uint32_t pos
= dev
->exp
.exp_cap
;
630 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP2
,
631 PCI_EXP_DEVCAP2_ARI
);
632 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL2
,
633 PCI_EXP_DEVCTL2_ARI
);
636 void pcie_cap_arifwd_reset(PCIDevice
*dev
)
638 uint8_t *devctl2
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
;
639 pci_long_test_and_clear_mask(devctl2
, PCI_EXP_DEVCTL2_ARI
);
642 bool pcie_cap_is_arifwd_enabled(const PCIDevice
*dev
)
644 if (!pci_is_express(dev
)) {
647 if (!dev
->exp
.exp_cap
) {
651 return pci_get_long(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
) &
655 /**************************************************************************
656 * pci express extended capability list management functions
657 * uint16_t ext_cap_id (16 bit)
658 * uint8_t cap_ver (4 bit)
659 * uint16_t cap_offset (12 bit)
660 * uint16_t ext_cap_size
663 /* Passing a cap_id value > 0xffff will return 0 and put end of list in prev */
664 static uint16_t pcie_find_capability_list(PCIDevice
*dev
, uint32_t cap_id
,
669 uint32_t header
= pci_get_long(dev
->config
+ PCI_CONFIG_SPACE_SIZE
);
672 /* no extended capability */
676 for (next
= PCI_CONFIG_SPACE_SIZE
; next
;
677 prev
= next
, next
= PCI_EXT_CAP_NEXT(header
)) {
679 assert(next
>= PCI_CONFIG_SPACE_SIZE
);
680 assert(next
<= PCIE_CONFIG_SPACE_SIZE
- 8);
682 header
= pci_get_long(dev
->config
+ next
);
683 if (PCI_EXT_CAP_ID(header
) == cap_id
) {
695 uint16_t pcie_find_capability(PCIDevice
*dev
, uint16_t cap_id
)
697 return pcie_find_capability_list(dev
, cap_id
, NULL
);
700 static void pcie_ext_cap_set_next(PCIDevice
*dev
, uint16_t pos
, uint16_t next
)
702 uint32_t header
= pci_get_long(dev
->config
+ pos
);
703 assert(!(next
& (PCI_EXT_CAP_ALIGN
- 1)));
704 header
= (header
& ~PCI_EXT_CAP_NEXT_MASK
) |
705 ((next
<< PCI_EXT_CAP_NEXT_SHIFT
) & PCI_EXT_CAP_NEXT_MASK
);
706 pci_set_long(dev
->config
+ pos
, header
);
710 * Caller must supply valid (offset, size) such that the range wouldn't
711 * overlap with other capability or other registers.
712 * This function doesn't check it.
714 void pcie_add_capability(PCIDevice
*dev
,
715 uint16_t cap_id
, uint8_t cap_ver
,
716 uint16_t offset
, uint16_t size
)
718 assert(offset
>= PCI_CONFIG_SPACE_SIZE
);
719 assert(offset
< offset
+ size
);
720 assert(offset
+ size
<= PCIE_CONFIG_SPACE_SIZE
);
722 assert(pci_is_express(dev
));
724 if (offset
!= PCI_CONFIG_SPACE_SIZE
) {
728 * 0xffffffff is not a valid cap id (it's a 16 bit field). use
729 * internally to find the last capability in the linked list.
731 pcie_find_capability_list(dev
, 0xffffffff, &prev
);
732 assert(prev
>= PCI_CONFIG_SPACE_SIZE
);
733 pcie_ext_cap_set_next(dev
, prev
, offset
);
735 pci_set_long(dev
->config
+ offset
, PCI_EXT_CAP(cap_id
, cap_ver
, 0));
737 /* Make capability read-only by default */
738 memset(dev
->wmask
+ offset
, 0, size
);
739 memset(dev
->w1cmask
+ offset
, 0, size
);
740 /* Check capability by default */
741 memset(dev
->cmask
+ offset
, 0xFF, size
);
744 /**************************************************************************
745 * pci express extended capability helper functions
749 void pcie_ari_init(PCIDevice
*dev
, uint16_t offset
, uint16_t nextfn
)
751 pcie_add_capability(dev
, PCI_EXT_CAP_ID_ARI
, PCI_ARI_VER
,
752 offset
, PCI_ARI_SIZEOF
);
753 pci_set_long(dev
->config
+ offset
+ PCI_ARI_CAP
, (nextfn
& 0xff) << 8);
756 void pcie_dev_ser_num_init(PCIDevice
*dev
, uint16_t offset
, uint64_t ser_num
)
758 static const int pci_dsn_ver
= 1;
759 static const int pci_dsn_cap
= 4;
761 pcie_add_capability(dev
, PCI_EXT_CAP_ID_DSN
, pci_dsn_ver
, offset
,
762 PCI_EXT_CAP_DSN_SIZEOF
);
763 pci_set_quad(dev
->config
+ offset
+ pci_dsn_cap
, ser_num
);
766 void pcie_ats_init(PCIDevice
*dev
, uint16_t offset
)
768 pcie_add_capability(dev
, PCI_EXT_CAP_ID_ATS
, 0x1,
769 offset
, PCI_EXT_CAP_ATS_SIZEOF
);
771 dev
->exp
.ats_cap
= offset
;
773 /* Invalidate Queue Depth 0, Page Aligned Request 0 */
774 pci_set_word(dev
->config
+ offset
+ PCI_ATS_CAP
, 0);
775 /* STU 0, Disabled by default */
776 pci_set_word(dev
->config
+ offset
+ PCI_ATS_CTRL
, 0);
778 pci_set_word(dev
->wmask
+ dev
->exp
.ats_cap
+ PCI_ATS_CTRL
, 0x800f);