hw/pci/pcie_port.c

   1 /*
   2  * pcie_port.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/pci/pcie_port.h"
  23 #include "hw/qdev-properties.h"
  24 #include "qemu/module.h"
  25 #include "hw/hotplug.h"
  26
  27 void pcie_port_init_reg(PCIDevice *d)
  28 {
  29     /* Unlike pci bridge,
  30        66MHz and fast back to back don't apply to pci express port. */
  31     pci_set_word(d->config + PCI_STATUS, 0);
  32     pci_set_word(d->config + PCI_SEC_STATUS, 0);
  33
  34     /*
  35      * Unlike conventional pci bridge, for some bits the spec states:
  36      * Does not apply to PCI Express and must be hardwired to 0.
  37      */
  38     pci_word_test_and_clear_mask(d->wmask + PCI_BRIDGE_CONTROL,
  39                                  PCI_BRIDGE_CTL_MASTER_ABORT |
  40                                  PCI_BRIDGE_CTL_FAST_BACK |
  41                                  PCI_BRIDGE_CTL_DISCARD |
  42                                  PCI_BRIDGE_CTL_SEC_DISCARD |
  43                                  PCI_BRIDGE_CTL_DISCARD_STATUS |
  44                                  PCI_BRIDGE_CTL_DISCARD_SERR);
  45 }
  46
  47 /**************************************************************************
  48  * (chassis number, pcie physical slot number) -> pcie slot conversion
  49  */
  50 struct PCIEChassis {
  51     uint8_t     number;
  52
  53     QLIST_HEAD(, PCIESlot) slots;
  54     QLIST_ENTRY(PCIEChassis) next;
  55 };
  56
  57 static QLIST_HEAD(, PCIEChassis) chassis = QLIST_HEAD_INITIALIZER(chassis);
  58
  59 static struct PCIEChassis *pcie_chassis_find(uint8_t chassis_number)
  60 {
  61     struct PCIEChassis *c;
  62     QLIST_FOREACH(c, &chassis, next) {
  63         if (c->number == chassis_number) {
  64             break;
  65         }
  66     }
  67     return c;
  68 }
  69
  70 void pcie_chassis_create(uint8_t chassis_number)
  71 {
  72     struct PCIEChassis *c;
  73     c = pcie_chassis_find(chassis_number);
  74     if (c) {
  75         return;
  76     }
  77     c = g_malloc0(sizeof(*c));
  78     c->number = chassis_number;
  79     QLIST_INIT(&c->slots);
  80     QLIST_INSERT_HEAD(&chassis, c, next);
  81 }
  82
  83 static PCIESlot *pcie_chassis_find_slot_with_chassis(struct PCIEChassis *c,
  84                                                      uint8_t slot)
  85 {
  86     PCIESlot *s;
  87     QLIST_FOREACH(s, &c->slots, next) {
  88         if (s->slot == slot) {
  89             break;
  90         }
  91     }
  92     return s;
  93 }
  94
  95 PCIESlot *pcie_chassis_find_slot(uint8_t chassis_number, uint16_t slot)
  96 {
  97     struct PCIEChassis *c;
  98     c = pcie_chassis_find(chassis_number);
  99     if (!c) {
 100         return NULL;
 101     }
 102     return pcie_chassis_find_slot_with_chassis(c, slot);
 103 }
 104
 105 int pcie_chassis_add_slot(struct PCIESlot *slot)
 106 {
 107     struct PCIEChassis *c;
 108     c = pcie_chassis_find(slot->chassis);
 109     if (!c) {
 110         return -ENODEV;
 111     }
 112     if (pcie_chassis_find_slot_with_chassis(c, slot->slot)) {
 113         return -EBUSY;
 114     }
 115     QLIST_INSERT_HEAD(&c->slots, slot, next);
 116     return 0;
 117 }
 118
 119 void pcie_chassis_del_slot(PCIESlot *s)
 120 {
 121     QLIST_REMOVE(s, next);
 122 }
 123
 124 static Property pcie_port_props[] = {
 125     DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
 126     DEFINE_PROP_UINT16("aer_log_max", PCIEPort,
 127                        parent_obj.parent_obj.exp.aer_log.log_max,
 128                        PCIE_AER_LOG_MAX_DEFAULT),
 129     DEFINE_PROP_END_OF_LIST()
 130 };
 131
 132 static void pcie_port_class_init(ObjectClass *oc, void *data)
 133 {
 134     DeviceClass *dc = DEVICE_CLASS(oc);
 135
 136     device_class_set_props(dc, pcie_port_props);
 137 }
 138
 139 PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn)
 140 {
 141     int devfn;
 142
 143     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
 144         PCIDevice *d = bus->devices[devfn];
 145         PCIEPort *port;
 146
 147         if (!d || !pci_is_express(d) || !d->exp.exp_cap) {
 148             continue;
 149         }
 150
 151         if (!object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) {
 152             continue;
 153         }
 154
 155         port = PCIE_PORT(d);
 156         if (port->port == pn) {
 157             return d;
 158         }
 159     }
 160
 161     return NULL;
 162 }
 163
 164 /* Find first port in devfn number order */
 165 PCIDevice *pcie_find_port_first(PCIBus *bus)
 166 {
 167     int devfn;
 168
 169     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
 170         PCIDevice *d = bus->devices[devfn];
 171
 172         if (!d || !pci_is_express(d) || !d->exp.exp_cap) {
 173             continue;
 174         }
 175
 176         if (object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) {
 177             return d;
 178         }
 179     }
 180
 181     return NULL;
 182 }
 183
 184 int pcie_count_ds_ports(PCIBus *bus)
 185 {
 186     int dsp_count = 0;
 187     int devfn;
 188
 189     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
 190         PCIDevice *d = bus->devices[devfn];
 191
 192         if (!d || !pci_is_express(d) || !d->exp.exp_cap) {
 193             continue;
 194         }
 195         if (object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) {
 196             dsp_count++;
 197         }
 198     }
 199     return dsp_count;
 200 }
 201
 202 static bool pcie_slot_is_hotpluggbale_bus(HotplugHandler *plug_handler,
 203                                           BusState *bus)
 204 {
 205     PCIESlot *s = PCIE_SLOT(bus->parent);
 206     return s->hotplug;
 207 }
 208
 209 static const TypeInfo pcie_port_type_info = {
 210     .name = TYPE_PCIE_PORT,
 211     .parent = TYPE_PCI_BRIDGE,
 212     .instance_size = sizeof(PCIEPort),
 213     .abstract = true,
 214     .class_init = pcie_port_class_init,
 215 };
 216
 217 static Property pcie_slot_props[] = {
 218     DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
 219     DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
 220     DEFINE_PROP_BOOL("hotplug", PCIESlot, hotplug, true),
 221     DEFINE_PROP_BOOL("x-do-not-expose-native-hotplug-cap", PCIESlot,
 222                      hide_native_hotplug_cap, false),
 223     DEFINE_PROP_END_OF_LIST()
 224 };
 225
 226 static void pcie_slot_class_init(ObjectClass *oc, void *data)
 227 {
 228     DeviceClass *dc = DEVICE_CLASS(oc);
 229     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
 230
 231     device_class_set_props(dc, pcie_slot_props);
 232     hc->pre_plug = pcie_cap_slot_pre_plug_cb;
 233     hc->plug = pcie_cap_slot_plug_cb;
 234     hc->unplug = pcie_cap_slot_unplug_cb;
 235     hc->unplug_request = pcie_cap_slot_unplug_request_cb;
 236     hc->is_hotpluggable_bus = pcie_slot_is_hotpluggbale_bus;
 237 }
 238
 239 static const TypeInfo pcie_slot_type_info = {
 240     .name = TYPE_PCIE_SLOT,
 241     .parent = TYPE_PCIE_PORT,
 242     .instance_size = sizeof(PCIESlot),
 243     .abstract = true,
 244     .class_init = pcie_slot_class_init,
 245     .interfaces = (InterfaceInfo[]) {
 246         { TYPE_HOTPLUG_HANDLER },
 247         { }
 248     }
 249 };
 250
 251 static void pcie_port_register_types(void)
 252 {
 253     type_register_static(&pcie_port_type_info);
 254     type_register_static(&pcie_slot_type_info);
 255 }
 256
 257 type_init(pcie_port_register_types)