hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31 #ifdef DEBUG_PCI
  32 # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
  33 #else
  34 # define PCI_DPRINTF(format, ...)       do { } while (0)
  35 #endif
  36
  37 struct PCIBus {
  38     BusState qbus;
  39     int devfn_min;
  40     pci_set_irq_fn set_irq;
  41     pci_map_irq_fn map_irq;
  42     pci_hotplug_fn hotplug;
  43     uint32_t config_reg; /* XXX: suppress */
  44     void *irq_opaque;
  45     PCIDevice *devices[256];
  46     PCIDevice *parent_dev;
  47
  48     QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
  49     QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
  50
  51     /* The bus IRQ state is the logical OR of the connected devices.
  52        Keep a count of the number of devices with raised IRQs.  */
  53     int nirq;
  54     int *irq_count;
  55 };
  56
  57 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  58
  59 static struct BusInfo pci_bus_info = {
  60     .name       = "PCI",
  61     .size       = sizeof(PCIBus),
  62     .print_dev  = pcibus_dev_print,
  63     .props      = (Property[]) {
  64         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  65         DEFINE_PROP_END_OF_LIST()
  66     }
  67 };
  68
  69 static void pci_update_mappings(PCIDevice *d);
  70 static void pci_set_irq(void *opaque, int irq_num, int level);
  71
  72 target_phys_addr_t pci_mem_base;
  73 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  74 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  75
  76 struct PCIHostBus {
  77     int domain;
  78     struct PCIBus *bus;
  79     QLIST_ENTRY(PCIHostBus) next;
  80 };
  81 static QLIST_HEAD(, PCIHostBus) host_buses;
  82
  83 static const VMStateDescription vmstate_pcibus = {
  84     .name = "PCIBUS",
  85     .version_id = 1,
  86     .minimum_version_id = 1,
  87     .minimum_version_id_old = 1,
  88     .fields      = (VMStateField []) {
  89         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  90         VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
  91         VMSTATE_END_OF_LIST()
  92     }
  93 };
  94
  95 static int pci_bar(PCIDevice *d, int reg)
  96 {
  97     uint8_t type;
  98
  99     if (reg != PCI_ROM_SLOT)
 100         return PCI_BASE_ADDRESS_0 + reg * 4;
 101
 102     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
 103     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
 104 }
 105
 106 static void pci_device_reset(PCIDevice *dev)
 107 {
 108     int r;
 109
 110     memset(dev->irq_state, 0, sizeof dev->irq_state);
 111     dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 112                                   PCI_COMMAND_MASTER);
 113     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
 114     dev->config[PCI_INTERRUPT_LINE] = 0x0;
 115     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
 116         if (!dev->io_regions[r].size) {
 117             continue;
 118         }
 119         pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
 120     }
 121     pci_update_mappings(dev);
 122 }
 123
 124 static void pci_bus_reset(void *opaque)
 125 {
 126     PCIBus *bus = opaque;
 127     int i;
 128
 129     for (i = 0; i < bus->nirq; i++) {
 130         bus->irq_count[i] = 0;
 131     }
 132     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 133         if (bus->devices[i]) {
 134             pci_device_reset(bus->devices[i]);
 135         }
 136     }
 137 }
 138
 139 static void pci_host_bus_register(int domain, PCIBus *bus)
 140 {
 141     struct PCIHostBus *host;
 142     host = qemu_mallocz(sizeof(*host));
 143     host->domain = domain;
 144     host->bus = bus;
 145     QLIST_INSERT_HEAD(&host_buses, host, next);
 146 }
 147
 148 PCIBus *pci_find_root_bus(int domain)
 149 {
 150     struct PCIHostBus *host;
 151
 152     QLIST_FOREACH(host, &host_buses, next) {
 153         if (host->domain == domain) {
 154             return host->bus;
 155         }
 156     }
 157
 158     return NULL;
 159 }
 160
 161 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 162                          const char *name, int devfn_min)
 163 {
 164     static int nbus = 0;
 165
 166     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 167     bus->devfn_min = devfn_min;
 168
 169     /* host bridge */
 170     QLIST_INIT(&bus->child);
 171     pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
 172
 173     vmstate_register(nbus++, &vmstate_pcibus, bus);
 174     qemu_register_reset(pci_bus_reset, bus);
 175 }
 176
 177 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 178 {
 179     PCIBus *bus;
 180
 181     bus = qemu_mallocz(sizeof(*bus));
 182     bus->qbus.qdev_allocated = 1;
 183     pci_bus_new_inplace(bus, parent, name, devfn_min);
 184     return bus;
 185 }
 186
 187 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 188                   void *irq_opaque, int nirq)
 189 {
 190     bus->set_irq = set_irq;
 191     bus->map_irq = map_irq;
 192     bus->irq_opaque = irq_opaque;
 193     bus->nirq = nirq;
 194     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 195 }
 196
 197 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
 198 {
 199     bus->qbus.allow_hotplug = 1;
 200     bus->hotplug = hotplug;
 201 }
 202
 203 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 204                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 205                          void *irq_opaque, int devfn_min, int nirq)
 206 {
 207     PCIBus *bus;
 208
 209     bus = pci_bus_new(parent, name, devfn_min);
 210     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 211     return bus;
 212 }
 213
 214 static void pci_register_secondary_bus(PCIBus *parent,
 215                                        PCIBus *bus,
 216                                        PCIDevice *dev,
 217                                        pci_map_irq_fn map_irq,
 218                                        const char *name)
 219 {
 220     qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
 221     bus->map_irq = map_irq;
 222     bus->parent_dev = dev;
 223
 224     QLIST_INIT(&bus->child);
 225     QLIST_INSERT_HEAD(&parent->child, bus, sibling);
 226 }
 227
 228 static void pci_unregister_secondary_bus(PCIBus *bus)
 229 {
 230     assert(QLIST_EMPTY(&bus->child));
 231     QLIST_REMOVE(bus, sibling);
 232 }
 233
 234 int pci_bus_num(PCIBus *s)
 235 {
 236     if (!s->parent_dev)
 237         return 0;       /* pci host bridge */
 238     return s->parent_dev->config[PCI_SECONDARY_BUS];
 239 }
 240
 241 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 242 {
 243     PCIDevice *s = container_of(pv, PCIDevice, config);
 244     uint8_t *config;
 245     int i;
 246
 247     assert(size == pci_config_size(s));
 248     config = qemu_malloc(size);
 249
 250     qemu_get_buffer(f, config, size);
 251     for (i = 0; i < size; ++i) {
 252         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
 253             qemu_free(config);
 254             return -EINVAL;
 255         }
 256     }
 257     memcpy(s->config, config, size);
 258
 259     pci_update_mappings(s);
 260
 261     qemu_free(config);
 262     return 0;
 263 }
 264
 265 /* just put buffer */
 266 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 267 {
 268     const uint8_t **v = pv;
 269     assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
 270     qemu_put_buffer(f, *v, size);
 271 }
 272
 273 static VMStateInfo vmstate_info_pci_config = {
 274     .name = "pci config",
 275     .get  = get_pci_config_device,
 276     .put  = put_pci_config_device,
 277 };
 278
 279 const VMStateDescription vmstate_pci_device = {
 280     .name = "PCIDevice",
 281     .version_id = 2,
 282     .minimum_version_id = 1,
 283     .minimum_version_id_old = 1,
 284     .fields      = (VMStateField []) {
 285         VMSTATE_INT32_LE(version_id, PCIDevice),
 286         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 287                                    vmstate_info_pci_config,
 288                                    PCI_CONFIG_SPACE_SIZE),
 289         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
 290         VMSTATE_END_OF_LIST()
 291     }
 292 };
 293
 294 const VMStateDescription vmstate_pcie_device = {
 295     .name = "PCIDevice",
 296     .version_id = 2,
 297     .minimum_version_id = 1,
 298     .minimum_version_id_old = 1,
 299     .fields      = (VMStateField []) {
 300         VMSTATE_INT32_LE(version_id, PCIDevice),
 301         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 302                                    vmstate_info_pci_config,
 303                                    PCIE_CONFIG_SPACE_SIZE),
 304         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
 305         VMSTATE_END_OF_LIST()
 306     }
 307 };
 308
 309 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
 310 {
 311     return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
 312 }
 313
 314 void pci_device_save(PCIDevice *s, QEMUFile *f)
 315 {
 316     vmstate_save_state(f, pci_get_vmstate(s), s);
 317 }
 318
 319 int pci_device_load(PCIDevice *s, QEMUFile *f)
 320 {
 321     return vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
 322 }
 323
 324 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 325 {
 326     uint16_t *id;
 327
 328     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 329     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 330     id[1] = cpu_to_le16(pci_default_sub_device_id);
 331     return 0;
 332 }
 333
 334 /*
 335  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 336  */
 337 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 338 {
 339     const char *p;
 340     char *e;
 341     unsigned long val;
 342     unsigned long dom = 0, bus = 0;
 343     unsigned slot = 0;
 344
 345     p = addr;
 346     val = strtoul(p, &e, 16);
 347     if (e == p)
 348         return -1;
 349     if (*e == ':') {
 350         bus = val;
 351         p = e + 1;
 352         val = strtoul(p, &e, 16);
 353         if (e == p)
 354             return -1;
 355         if (*e == ':') {
 356             dom = bus;
 357             bus = val;
 358             p = e + 1;
 359             val = strtoul(p, &e, 16);
 360             if (e == p)
 361                 return -1;
 362         }
 363     }
 364
 365     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 366         return -1;
 367
 368     slot = val;
 369
 370     if (*e)
 371         return -1;
 372
 373     /* Note: QEMU doesn't implement domains other than 0 */
 374     if (!pci_find_bus(pci_find_root_bus(dom), bus))
 375         return -1;
 376
 377     *domp = dom;
 378     *busp = bus;
 379     *slotp = slot;
 380     return 0;
 381 }
 382
 383 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 384                      unsigned *slotp)
 385 {
 386     /* strip legacy tag */
 387     if (!strncmp(addr, "pci_addr=", 9)) {
 388         addr += 9;
 389     }
 390     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 391         monitor_printf(mon, "Invalid pci address\n");
 392         return -1;
 393     }
 394     return 0;
 395 }
 396
 397 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 398 {
 399     int dom, bus;
 400     unsigned slot;
 401
 402     if (!devaddr) {
 403         *devfnp = -1;
 404         return pci_find_bus(pci_find_root_bus(0), 0);
 405     }
 406
 407     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 408         return NULL;
 409     }
 410
 411     *devfnp = slot << 3;
 412     return pci_find_bus(pci_find_root_bus(0), bus);
 413 }
 414
 415 static void pci_init_cmask(PCIDevice *dev)
 416 {
 417     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 418     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 419     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 420     dev->cmask[PCI_REVISION_ID] = 0xff;
 421     dev->cmask[PCI_CLASS_PROG] = 0xff;
 422     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 423     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 424     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 425 }
 426
 427 static void pci_init_wmask(PCIDevice *dev)
 428 {
 429     int config_size = pci_config_size(dev);
 430
 431     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 432     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 433     pci_set_word(dev->wmask + PCI_COMMAND,
 434                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 435
 436     memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
 437            config_size - PCI_CONFIG_HEADER_SIZE);
 438 }
 439
 440 static void pci_init_wmask_bridge(PCIDevice *d)
 441 {
 442     /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
 443        PCI_SEC_LETENCY_TIMER */
 444     memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
 445
 446     /* base and limit */
 447     d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
 448     d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
 449     pci_set_word(d->wmask + PCI_MEMORY_BASE,
 450                  PCI_MEMORY_RANGE_MASK & 0xffff);
 451     pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
 452                  PCI_MEMORY_RANGE_MASK & 0xffff);
 453     pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
 454                  PCI_PREF_RANGE_MASK & 0xffff);
 455     pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
 456                  PCI_PREF_RANGE_MASK & 0xffff);
 457
 458     /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
 459     memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
 460
 461     pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
 462 }
 463
 464 static void pci_config_alloc(PCIDevice *pci_dev)
 465 {
 466     int config_size = pci_config_size(pci_dev);
 467
 468     pci_dev->config = qemu_mallocz(config_size);
 469     pci_dev->cmask = qemu_mallocz(config_size);
 470     pci_dev->wmask = qemu_mallocz(config_size);
 471     pci_dev->used = qemu_mallocz(config_size);
 472 }
 473
 474 static void pci_config_free(PCIDevice *pci_dev)
 475 {
 476     qemu_free(pci_dev->config);
 477     qemu_free(pci_dev->cmask);
 478     qemu_free(pci_dev->wmask);
 479     qemu_free(pci_dev->used);
 480 }
 481
 482 /* -1 for devfn means auto assign */
 483 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 484                                          const char *name, int devfn,
 485                                          PCIConfigReadFunc *config_read,
 486                                          PCIConfigWriteFunc *config_write,
 487                                          uint8_t header_type)
 488 {
 489     if (devfn < 0) {
 490         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 491             if (!bus->devices[devfn])
 492                 goto found;
 493         }
 494         hw_error("PCI: no devfn available for %s, all in use\n", name);
 495     found: ;
 496     } else if (bus->devices[devfn]) {
 497         hw_error("PCI: devfn %d not available for %s, in use by %s\n", devfn,
 498                  name, bus->devices[devfn]->name);
 499     }
 500     pci_dev->bus = bus;
 501     pci_dev->devfn = devfn;
 502     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 503     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 504     pci_config_alloc(pci_dev);
 505
 506     header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
 507     if (header_type == PCI_HEADER_TYPE_NORMAL) {
 508         pci_set_default_subsystem_id(pci_dev);
 509     }
 510     pci_init_cmask(pci_dev);
 511     pci_init_wmask(pci_dev);
 512     if (header_type == PCI_HEADER_TYPE_BRIDGE) {
 513         pci_init_wmask_bridge(pci_dev);
 514     }
 515
 516     if (!config_read)
 517         config_read = pci_default_read_config;
 518     if (!config_write)
 519         config_write = pci_default_write_config;
 520     pci_dev->config_read = config_read;
 521     pci_dev->config_write = config_write;
 522     bus->devices[devfn] = pci_dev;
 523     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
 524     pci_dev->version_id = 2; /* Current pci device vmstate version */
 525     return pci_dev;
 526 }
 527
 528 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 529                                int instance_size, int devfn,
 530                                PCIConfigReadFunc *config_read,
 531                                PCIConfigWriteFunc *config_write)
 532 {
 533     PCIDevice *pci_dev;
 534
 535     pci_dev = qemu_mallocz(instance_size);
 536     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 537                                      config_read, config_write,
 538                                      PCI_HEADER_TYPE_NORMAL);
 539     return pci_dev;
 540 }
 541 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 542 {
 543     return addr + pci_mem_base;
 544 }
 545
 546 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 547 {
 548     PCIIORegion *r;
 549     int i;
 550
 551     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 552         r = &pci_dev->io_regions[i];
 553         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
 554             continue;
 555         if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
 556             isa_unassign_ioport(r->addr, r->filtered_size);
 557         } else {
 558             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 559                                                      r->filtered_size,
 560                                                      IO_MEM_UNASSIGNED);
 561         }
 562     }
 563 }
 564
 565 static int pci_unregister_device(DeviceState *dev)
 566 {
 567     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 568     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 569     int ret = 0;
 570
 571     if (info->exit)
 572         ret = info->exit(pci_dev);
 573     if (ret)
 574         return ret;
 575
 576     pci_unregister_io_regions(pci_dev);
 577
 578     qemu_free_irqs(pci_dev->irq);
 579     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 580     pci_config_free(pci_dev);
 581     return 0;
 582 }
 583
 584 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 585                             pcibus_t size, int type,
 586                             PCIMapIORegionFunc *map_func)
 587 {
 588     PCIIORegion *r;
 589     uint32_t addr;
 590     pcibus_t wmask;
 591
 592     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 593         return;
 594
 595     if (size & (size-1)) {
 596         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 597                     "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
 598         exit(1);
 599     }
 600
 601     r = &pci_dev->io_regions[region_num];
 602     r->addr = PCI_BAR_UNMAPPED;
 603     r->size = size;
 604     r->filtered_size = size;
 605     r->type = type;
 606     r->map_func = map_func;
 607
 608     wmask = ~(size - 1);
 609     addr = pci_bar(pci_dev, region_num);
 610     if (region_num == PCI_ROM_SLOT) {
 611         /* ROM enable bit is writeable */
 612         wmask |= PCI_ROM_ADDRESS_ENABLE;
 613     }
 614     pci_set_long(pci_dev->config + addr, type);
 615     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 616         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 617         pci_set_quad(pci_dev->wmask + addr, wmask);
 618         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
 619     } else {
 620         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
 621         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
 622     }
 623 }
 624
 625 static uint32_t pci_config_get_io_base(PCIDevice *d,
 626                                        uint32_t base, uint32_t base_upper16)
 627 {
 628     uint32_t val;
 629
 630     val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
 631     if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
 632         val |= (uint32_t)pci_get_word(d->config + PCI_IO_BASE_UPPER16) << 16;
 633     }
 634     return val;
 635 }
 636
 637 static uint64_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
 638 {
 639     return ((uint64_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
 640         << 16;
 641 }
 642
 643 static uint64_t pci_config_get_pref_base(PCIDevice *d,
 644                                          uint32_t base, uint32_t upper)
 645 {
 646     uint64_t val;
 647     val = ((uint64_t)pci_get_word(d->config + base) &
 648            PCI_PREF_RANGE_MASK) << 16;
 649     val |= (uint64_t)pci_get_long(d->config + upper) << 32;
 650     return val;
 651 }
 652
 653 static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
 654 {
 655     pcibus_t base;
 656     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 657         base = pci_config_get_io_base(bridge,
 658                                       PCI_IO_BASE, PCI_IO_BASE_UPPER16);
 659     } else {
 660         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 661             base = pci_config_get_pref_base(
 662                 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
 663         } else {
 664             base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
 665         }
 666     }
 667
 668     return base;
 669 }
 670
 671 static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
 672 {
 673     pcibus_t limit;
 674     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 675         limit = pci_config_get_io_base(bridge,
 676                                       PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
 677         limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
 678     } else {
 679         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 680             limit = pci_config_get_pref_base(
 681                 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
 682         } else {
 683             limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
 684         }
 685         limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
 686     }
 687     return limit;
 688 }
 689
 690 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
 691                               uint8_t type)
 692 {
 693     pcibus_t base = *addr;
 694     pcibus_t limit = *addr + *size - 1;
 695     PCIDevice *br;
 696
 697     for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
 698         uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 699
 700         if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 701             if (!(cmd & PCI_COMMAND_IO)) {
 702                 goto no_map;
 703             }
 704         } else {
 705             if (!(cmd & PCI_COMMAND_MEMORY)) {
 706                 goto no_map;
 707             }
 708         }
 709
 710         base = MAX(base, pci_bridge_get_base(br, type));
 711         limit = MIN(limit, pci_bridge_get_limit(br, type));
 712     }
 713
 714     if (base > limit) {
 715     no_map:
 716         *addr = PCI_BAR_UNMAPPED;
 717         *size = 0;
 718     } else {
 719         *addr = base;
 720         *size = limit - base + 1;
 721     }
 722 }
 723
 724 static void pci_update_mappings(PCIDevice *d)
 725 {
 726     PCIIORegion *r;
 727     int cmd, i;
 728     pcibus_t last_addr, new_addr;
 729     pcibus_t filtered_size;
 730
 731     cmd = pci_get_word(d->config + PCI_COMMAND);
 732     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 733         r = &d->io_regions[i];
 734
 735         /* this region isn't registered */
 736         if (r->size == 0)
 737             continue;
 738
 739         if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 740             if (cmd & PCI_COMMAND_IO) {
 741                 new_addr = pci_get_long(d->config + pci_bar(d, i));
 742                 new_addr = new_addr & ~(r->size - 1);
 743                 last_addr = new_addr + r->size - 1;
 744                 /* NOTE: we have only 64K ioports on PC */
 745                 if (last_addr <= new_addr || new_addr == 0 ||
 746                     last_addr >= 0x10000) {
 747                     new_addr = PCI_BAR_UNMAPPED;
 748                 }
 749             } else {
 750                 new_addr = PCI_BAR_UNMAPPED;
 751             }
 752         } else {
 753             if (cmd & PCI_COMMAND_MEMORY) {
 754                 if (r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 755                     new_addr = pci_get_quad(d->config + pci_bar(d, i));
 756                 } else {
 757                     new_addr = pci_get_long(d->config + pci_bar(d, i));
 758                 }
 759                 /* the ROM slot has a specific enable bit */
 760                 if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE))
 761                     goto no_mem_map;
 762                 new_addr = new_addr & ~(r->size - 1);
 763                 last_addr = new_addr + r->size - 1;
 764                 /* NOTE: we do not support wrapping */
 765                 /* XXX: as we cannot support really dynamic
 766                    mappings, we handle specific values as invalid
 767                    mappings. */
 768                 if (last_addr <= new_addr || new_addr == 0 ||
 769                     last_addr == PCI_BAR_UNMAPPED ||
 770
 771                     /* Now pcibus_t is 64bit.
 772                      * Check if 32 bit BAR wrap around explicitly.
 773                      * Without this, PC ide doesn't work well.
 774                      * TODO: remove this work around.
 775                      */
 776                     (!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) &&
 777                      last_addr >= UINT32_MAX) ||
 778
 779                     /*
 780                      * OS is allowed to set BAR beyond its addressable
 781                      * bits. For example, 32 bit OS can set 64bit bar
 782                      * to >4G. Check it.
 783                      */
 784                     last_addr >= TARGET_PHYS_ADDR_MAX) {
 785                     new_addr = PCI_BAR_UNMAPPED;
 786                 }
 787             } else {
 788             no_mem_map:
 789                 new_addr = PCI_BAR_UNMAPPED;
 790             }
 791         }
 792
 793         /* bridge filtering */
 794         filtered_size = r->size;
 795         if (new_addr != PCI_BAR_UNMAPPED) {
 796             pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
 797         }
 798
 799         /* This bar isn't changed */
 800         if (new_addr == r->addr && filtered_size == r->filtered_size)
 801             continue;
 802
 803         /* now do the real mapping */
 804         if (r->addr != PCI_BAR_UNMAPPED) {
 805             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 806                 int class;
 807                 /* NOTE: specific hack for IDE in PC case:
 808                    only one byte must be mapped. */
 809                 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 810                 if (class == 0x0101 && r->size == 4) {
 811                     isa_unassign_ioport(r->addr + 2, 1);
 812                 } else {
 813                     isa_unassign_ioport(r->addr, r->filtered_size);
 814                 }
 815             } else {
 816                 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 817                                              r->filtered_size,
 818                                              IO_MEM_UNASSIGNED);
 819                 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
 820             }
 821         }
 822         r->addr = new_addr;
 823         r->filtered_size = filtered_size;
 824         if (r->addr != PCI_BAR_UNMAPPED) {
 825             /*
 826              * TODO: currently almost all the map funcions assumes
 827              * filtered_size == size and addr & ~(size - 1) == addr.
 828              * However with bridge filtering, they aren't always true.
 829              * Teach them such cases, such that filtered_size < size and
 830              * addr & (size - 1) != 0.
 831              */
 832             r->map_func(d, i, r->addr, r->filtered_size, r->type);
 833         }
 834     }
 835 }
 836
 837 uint32_t pci_default_read_config(PCIDevice *d,
 838                                  uint32_t address, int len)
 839 {
 840     uint32_t val = 0;
 841     assert(len == 1 || len == 2 || len == 4);
 842     len = MIN(len, pci_config_size(d) - address);
 843     memcpy(&val, d->config + address, len);
 844     return le32_to_cpu(val);
 845 }
 846
 847 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 848 {
 849     int i;
 850     uint32_t config_size = pci_config_size(d);
 851
 852     for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
 853         uint8_t wmask = d->wmask[addr + i];
 854         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
 855     }
 856     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
 857         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
 858         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
 859         range_covers_byte(addr, l, PCI_COMMAND))
 860         pci_update_mappings(d);
 861 }
 862
 863 /***********************************************************/
 864 /* generic PCI irq support */
 865
 866 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 867 static void pci_set_irq(void *opaque, int irq_num, int level)
 868 {
 869     PCIDevice *pci_dev = opaque;
 870     PCIBus *bus;
 871     int change;
 872
 873     change = level - pci_dev->irq_state[irq_num];
 874     if (!change)
 875         return;
 876
 877     pci_dev->irq_state[irq_num] = level;
 878     for (;;) {
 879         bus = pci_dev->bus;
 880         irq_num = bus->map_irq(pci_dev, irq_num);
 881         if (bus->set_irq)
 882             break;
 883         pci_dev = bus->parent_dev;
 884     }
 885     bus->irq_count[irq_num] += change;
 886     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 887 }
 888
 889 /***********************************************************/
 890 /* monitor info on PCI */
 891
 892 typedef struct {
 893     uint16_t class;
 894     const char *desc;
 895 } pci_class_desc;
 896
 897 static const pci_class_desc pci_class_descriptions[] =
 898 {
 899     { 0x0100, "SCSI controller"},
 900     { 0x0101, "IDE controller"},
 901     { 0x0102, "Floppy controller"},
 902     { 0x0103, "IPI controller"},
 903     { 0x0104, "RAID controller"},
 904     { 0x0106, "SATA controller"},
 905     { 0x0107, "SAS controller"},
 906     { 0x0180, "Storage controller"},
 907     { 0x0200, "Ethernet controller"},
 908     { 0x0201, "Token Ring controller"},
 909     { 0x0202, "FDDI controller"},
 910     { 0x0203, "ATM controller"},
 911     { 0x0280, "Network controller"},
 912     { 0x0300, "VGA controller"},
 913     { 0x0301, "XGA controller"},
 914     { 0x0302, "3D controller"},
 915     { 0x0380, "Display controller"},
 916     { 0x0400, "Video controller"},
 917     { 0x0401, "Audio controller"},
 918     { 0x0402, "Phone"},
 919     { 0x0480, "Multimedia controller"},
 920     { 0x0500, "RAM controller"},
 921     { 0x0501, "Flash controller"},
 922     { 0x0580, "Memory controller"},
 923     { 0x0600, "Host bridge"},
 924     { 0x0601, "ISA bridge"},
 925     { 0x0602, "EISA bridge"},
 926     { 0x0603, "MC bridge"},
 927     { 0x0604, "PCI bridge"},
 928     { 0x0605, "PCMCIA bridge"},
 929     { 0x0606, "NUBUS bridge"},
 930     { 0x0607, "CARDBUS bridge"},
 931     { 0x0608, "RACEWAY bridge"},
 932     { 0x0680, "Bridge"},
 933     { 0x0c03, "USB controller"},
 934     { 0, NULL}
 935 };
 936
 937 static void pci_info_device(PCIBus *bus, PCIDevice *d)
 938 {
 939     Monitor *mon = cur_mon;
 940     int i, class;
 941     PCIIORegion *r;
 942     const pci_class_desc *desc;
 943
 944     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 945                    pci_bus_num(d->bus),
 946                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
 947     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 948     monitor_printf(mon, "    ");
 949     desc = pci_class_descriptions;
 950     while (desc->desc && class != desc->class)
 951         desc++;
 952     if (desc->desc) {
 953         monitor_printf(mon, "%s", desc->desc);
 954     } else {
 955         monitor_printf(mon, "Class %04x", class);
 956     }
 957     monitor_printf(mon, ": PCI device %04x:%04x\n",
 958            pci_get_word(d->config + PCI_VENDOR_ID),
 959            pci_get_word(d->config + PCI_DEVICE_ID));
 960
 961     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 962         monitor_printf(mon, "      IRQ %d.\n",
 963                        d->config[PCI_INTERRUPT_LINE]);
 964     }
 965     if (class == 0x0604) {
 966         uint64_t base;
 967         uint64_t limit;
 968
 969         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 970         monitor_printf(mon, "      secondary bus %d.\n",
 971                        d->config[PCI_SECONDARY_BUS]);
 972         monitor_printf(mon, "      subordinate bus %d.\n",
 973                        d->config[PCI_SUBORDINATE_BUS]);
 974
 975         base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_IO);
 976         limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_IO);
 977         monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
 978                        base, limit);
 979
 980         base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
 981         limit= pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
 982         monitor_printf(mon,
 983                        "      memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
 984                        base, limit);
 985
 986         base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
 987                                    PCI_BASE_ADDRESS_MEM_PREFETCH);
 988         limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
 989                                      PCI_BASE_ADDRESS_MEM_PREFETCH);
 990         monitor_printf(mon, "      prefetchable memory range "
 991                        "[0x%08"PRIx64", 0x%08"PRIx64"]\n", base, limit);
 992     }
 993     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 994         r = &d->io_regions[i];
 995         if (r->size != 0) {
 996             monitor_printf(mon, "      BAR%d: ", i);
 997             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 998                 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
 999                                " [0x%04"FMT_PCIBUS"].\n",
1000                                r->addr, r->addr + r->size - 1);
1001             } else {
1002                 const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ?
1003                     "64 bit" : "32 bit";
1004                 const char *prefetch =
1005                     r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ?
1006                     " prefetchable" : "";
1007
1008                 monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS
1009                                " [0x%08"FMT_PCIBUS"].\n",
1010                                type, prefetch,
1011                                r->addr, r->addr + r->size - 1);
1012             }
1013         }
1014     }
1015     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
1016     if (class == 0x0604 && d->config[0x19] != 0) {
1017         pci_for_each_device(bus, d->config[0x19], pci_info_device);
1018     }
1019 }
1020
1021 static void pci_for_each_device_under_bus(PCIBus *bus,
1022                                           void (*fn)(PCIBus *b, PCIDevice *d))
1023 {
1024     PCIDevice *d;
1025     int devfn;
1026
1027     for(devfn = 0; devfn < 256; devfn++) {
1028         d = bus->devices[devfn];
1029         if (d)
1030             fn(bus, d);
1031     }
1032 }
1033
1034 void pci_for_each_device(PCIBus *bus, int bus_num,
1035                          void (*fn)(PCIBus *b, PCIDevice *d))
1036 {
1037     bus = pci_find_bus(bus, bus_num);
1038
1039     if (bus) {
1040         pci_for_each_device_under_bus(bus, fn);
1041     }
1042 }
1043
1044 void pci_info(Monitor *mon)
1045 {
1046     struct PCIHostBus *host;
1047     QLIST_FOREACH(host, &host_buses, next) {
1048         pci_for_each_device(host->bus, 0, pci_info_device);
1049     }
1050 }
1051
1052 static const char * const pci_nic_models[] = {
1053     "ne2k_pci",
1054     "i82551",
1055     "i82557b",
1056     "i82559er",
1057     "rtl8139",
1058     "e1000",
1059     "pcnet",
1060     "virtio",
1061     NULL
1062 };
1063
1064 static const char * const pci_nic_names[] = {
1065     "ne2k_pci",
1066     "i82551",
1067     "i82557b",
1068     "i82559er",
1069     "rtl8139",
1070     "e1000",
1071     "pcnet",
1072     "virtio-net-pci",
1073     NULL
1074 };
1075
1076 /* Initialize a PCI NIC.  */
1077 /* FIXME callers should check for failure, but don't */
1078 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1079                         const char *default_devaddr)
1080 {
1081     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1082     PCIBus *bus;
1083     int devfn;
1084     PCIDevice *pci_dev;
1085     DeviceState *dev;
1086     int i;
1087
1088     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1089     if (i < 0)
1090         return NULL;
1091
1092     bus = pci_get_bus_devfn(&devfn, devaddr);
1093     if (!bus) {
1094         qemu_error("Invalid PCI device address %s for device %s\n",
1095                    devaddr, pci_nic_names[i]);
1096         return NULL;
1097     }
1098
1099     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1100     dev = &pci_dev->qdev;
1101     if (nd->name)
1102         dev->id = qemu_strdup(nd->name);
1103     qdev_set_nic_properties(dev, nd);
1104     if (qdev_init(dev) < 0)
1105         return NULL;
1106     return pci_dev;
1107 }
1108
1109 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1110                                const char *default_devaddr)
1111 {
1112     PCIDevice *res;
1113
1114     if (qemu_show_nic_models(nd->model, pci_nic_models))
1115         exit(0);
1116
1117     res = pci_nic_init(nd, default_model, default_devaddr);
1118     if (!res)
1119         exit(1);
1120     return res;
1121 }
1122
1123 typedef struct {
1124     PCIDevice dev;
1125     PCIBus bus;
1126     uint32_t vid;
1127     uint32_t did;
1128 } PCIBridge;
1129
1130
1131 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1132 {
1133     pci_update_mappings(d);
1134 }
1135
1136 static void pci_bridge_update_mappings(PCIBus *b)
1137 {
1138     PCIBus *child;
1139
1140     pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1141
1142     QLIST_FOREACH(child, &b->child, sibling) {
1143         pci_bridge_update_mappings(child);
1144     }
1145 }
1146
1147 static void pci_bridge_write_config(PCIDevice *d,
1148                              uint32_t address, uint32_t val, int len)
1149 {
1150     pci_default_write_config(d, address, val, len);
1151
1152     if (/* io base/limit */
1153         ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1154
1155         /* memory base/limit, prefetchable base/limit and
1156            io base/limit upper 16 */
1157         ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1158         pci_bridge_update_mappings(d->bus);
1159     }
1160 }
1161
1162 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1163 {
1164     PCIBus *sec;
1165
1166     if (!bus)
1167         return NULL;
1168
1169     if (pci_bus_num(bus) == bus_num) {
1170         return bus;
1171     }
1172
1173     /* try child bus */
1174     QLIST_FOREACH(sec, &bus->child, sibling) {
1175
1176         if (!bus->parent_dev /* pci host bridge */
1177             || (pci_bus_num(sec) <= bus_num &&
1178                 bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1179             return pci_find_bus(sec, bus_num);
1180         }
1181     }
1182
1183     return NULL;
1184 }
1185
1186 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1187 {
1188     bus = pci_find_bus(bus, bus_num);
1189
1190     if (!bus)
1191         return NULL;
1192
1193     return bus->devices[PCI_DEVFN(slot, function)];
1194 }
1195
1196 static int pci_bridge_initfn(PCIDevice *dev)
1197 {
1198     PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1199
1200     pci_config_set_vendor_id(s->dev.config, s->vid);
1201     pci_config_set_device_id(s->dev.config, s->did);
1202
1203     /* TODO: intial value
1204      * command register:
1205      * According to PCI bridge spec, after reset
1206      *   bus master bit is off
1207      *   memory space enable bit is off
1208      * According to manual (805-1251.pdf).(See abp_pbi.c for its links.)
1209      *   the reset value should be zero unless the boot pin is tied high
1210      *   (which is tru) and thus it should be PCI_COMMAND_MEMORY.
1211      *
1212      * For now, don't touch the value.
1213      * Later command register will be set to zero and apb_pci.c will
1214      * override the value.
1215      * Same for latency timer, and multi function bit of header type.
1216      */
1217     pci_set_word(dev->config + PCI_COMMAND,
1218                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1219
1220     pci_set_word(dev->config + PCI_STATUS,
1221                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1222     pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1223     dev->config[PCI_LATENCY_TIMER] = 0x10;
1224     dev->config[PCI_HEADER_TYPE] =
1225         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE;
1226     pci_set_word(dev->config + PCI_SEC_STATUS,
1227                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1228     return 0;
1229 }
1230
1231 static int pci_bridge_exitfn(PCIDevice *pci_dev)
1232 {
1233     PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1234     PCIBus *bus = &s->bus;
1235     pci_unregister_secondary_bus(bus);
1236     return 0;
1237 }
1238
1239 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1240                         pci_map_irq_fn map_irq, const char *name)
1241 {
1242     PCIDevice *dev;
1243     PCIBridge *s;
1244
1245     dev = pci_create(bus, devfn, "pci-bridge");
1246     qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1247     qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1248     qdev_init_nofail(&dev->qdev);
1249
1250     s = DO_UPCAST(PCIBridge, dev, dev);
1251     pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1252     return &s->bus;
1253 }
1254
1255 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1256 {
1257     PCIDevice *pci_dev = (PCIDevice *)qdev;
1258     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1259     PCIBus *bus;
1260     int devfn, rc;
1261
1262     /* initialize cap_present for pci_is_express() and pci_config_size() */
1263     if (info->is_express) {
1264         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1265     }
1266
1267     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1268     devfn = pci_dev->devfn;
1269     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1270                                      info->config_read, info->config_write,
1271                                      info->header_type);
1272     rc = info->init(pci_dev);
1273     if (rc != 0)
1274         return rc;
1275     if (qdev->hotplugged)
1276         bus->hotplug(pci_dev, 1);
1277     return 0;
1278 }
1279
1280 static int pci_unplug_device(DeviceState *qdev)
1281 {
1282     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1283
1284     dev->bus->hotplug(dev, 0);
1285     return 0;
1286 }
1287
1288 void pci_qdev_register(PCIDeviceInfo *info)
1289 {
1290     info->qdev.init = pci_qdev_init;
1291     info->qdev.unplug = pci_unplug_device;
1292     info->qdev.exit = pci_unregister_device;
1293     info->qdev.bus_info = &pci_bus_info;
1294     qdev_register(&info->qdev);
1295 }
1296
1297 void pci_qdev_register_many(PCIDeviceInfo *info)
1298 {
1299     while (info->qdev.name) {
1300         pci_qdev_register(info);
1301         info++;
1302     }
1303 }
1304
1305 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1306 {
1307     DeviceState *dev;
1308
1309     dev = qdev_create(&bus->qbus, name);
1310     qdev_prop_set_uint32(dev, "addr", devfn);
1311     return DO_UPCAST(PCIDevice, qdev, dev);
1312 }
1313
1314 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1315 {
1316     PCIDevice *dev = pci_create(bus, devfn, name);
1317     qdev_init_nofail(&dev->qdev);
1318     return dev;
1319 }
1320
1321 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1322 {
1323     int config_size = pci_config_size(pdev);
1324     int offset = PCI_CONFIG_HEADER_SIZE;
1325     int i;
1326     for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1327         if (pdev->used[i])
1328             offset = i + 1;
1329         else if (i - offset + 1 == size)
1330             return offset;
1331     return 0;
1332 }
1333
1334 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1335                                         uint8_t *prev_p)
1336 {
1337     uint8_t next, prev;
1338
1339     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1340         return 0;
1341
1342     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1343          prev = next + PCI_CAP_LIST_NEXT)
1344         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1345             break;
1346
1347     if (prev_p)
1348         *prev_p = prev;
1349     return next;
1350 }
1351
1352 /* Reserve space and add capability to the linked list in pci config space */
1353 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1354 {
1355     uint8_t offset = pci_find_space(pdev, size);
1356     uint8_t *config = pdev->config + offset;
1357     if (!offset)
1358         return -ENOSPC;
1359     config[PCI_CAP_LIST_ID] = cap_id;
1360     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1361     pdev->config[PCI_CAPABILITY_LIST] = offset;
1362     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1363     memset(pdev->used + offset, 0xFF, size);
1364     /* Make capability read-only by default */
1365     memset(pdev->wmask + offset, 0, size);
1366     /* Check capability by default */
1367     memset(pdev->cmask + offset, 0xFF, size);
1368     return offset;
1369 }
1370
1371 /* Unlink capability from the pci config space. */
1372 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1373 {
1374     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1375     if (!offset)
1376         return;
1377     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1378     /* Make capability writeable again */
1379     memset(pdev->wmask + offset, 0xff, size);
1380     /* Clear cmask as device-specific registers can't be checked */
1381     memset(pdev->cmask + offset, 0, size);
1382     memset(pdev->used + offset, 0, size);
1383
1384     if (!pdev->config[PCI_CAPABILITY_LIST])
1385         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1386 }
1387
1388 /* Reserve space for capability at a known offset (to call after load). */
1389 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1390 {
1391     memset(pdev->used + offset, 0xff, size);
1392 }
1393
1394 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1395 {
1396     return pci_find_capability_list(pdev, cap_id, NULL);
1397 }
1398
1399 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1400 {
1401     PCIDevice *d = (PCIDevice *)dev;
1402     const pci_class_desc *desc;
1403     char ctxt[64];
1404     PCIIORegion *r;
1405     int i, class;
1406
1407     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1408     desc = pci_class_descriptions;
1409     while (desc->desc && class != desc->class)
1410         desc++;
1411     if (desc->desc) {
1412         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1413     } else {
1414         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1415     }
1416
1417     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1418                    "pci id %04x:%04x (sub %04x:%04x)\n",
1419                    indent, "", ctxt,
1420                    d->config[PCI_SECONDARY_BUS],
1421                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1422                    pci_get_word(d->config + PCI_VENDOR_ID),
1423                    pci_get_word(d->config + PCI_DEVICE_ID),
1424                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1425                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1426     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1427         r = &d->io_regions[i];
1428         if (!r->size)
1429             continue;
1430         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1431                        " [0x%"FMT_PCIBUS"]\n",
1432                        indent, "",
1433                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1434                        r->addr, r->addr + r->size - 1);
1435     }
1436 }
1437
1438 static PCIDeviceInfo bridge_info = {
1439     .qdev.name    = "pci-bridge",
1440     .qdev.size    = sizeof(PCIBridge),
1441     .init         = pci_bridge_initfn,
1442     .exit         = pci_bridge_exitfn,
1443     .config_write = pci_bridge_write_config,
1444     .qdev.props   = (Property[]) {
1445         DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1446         DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1447         DEFINE_PROP_END_OF_LIST(),
1448     }
1449 };
1450
1451 static void pci_register_devices(void)
1452 {
1453     pci_qdev_register(&bridge_info);
1454 }
1455
1456 device_init(pci_register_devices)