4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
33 #include "qmp-commands.h"
39 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
41 # define PCI_DPRINTF(format, ...) do { } while (0)
44 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
45 static char *pcibus_get_dev_path(DeviceState
*dev
);
46 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
47 static int pcibus_reset(BusState
*qbus
);
49 struct BusInfo pci_bus_info
= {
51 .size
= sizeof(PCIBus
),
52 .print_dev
= pcibus_dev_print
,
53 .get_dev_path
= pcibus_get_dev_path
,
54 .get_fw_dev_path
= pcibus_get_fw_dev_path
,
55 .reset
= pcibus_reset
,
56 .props
= (Property
[]) {
57 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
58 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
59 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
60 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
61 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
62 DEFINE_PROP_BIT("command_serr_enable", PCIDevice
, cap_present
,
63 QEMU_PCI_CAP_SERR_BITNR
, true),
64 DEFINE_PROP_END_OF_LIST()
68 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
);
69 static void pci_update_mappings(PCIDevice
*d
);
70 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
71 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
);
72 static void pci_del_option_rom(PCIDevice
*pdev
);
74 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
75 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
80 QLIST_ENTRY(PCIHostBus
) next
;
82 static QLIST_HEAD(, PCIHostBus
) host_buses
;
84 static const VMStateDescription vmstate_pcibus
= {
87 .minimum_version_id
= 1,
88 .minimum_version_id_old
= 1,
89 .fields
= (VMStateField
[]) {
90 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
91 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
95 static int pci_bar(PCIDevice
*d
, int reg
)
99 if (reg
!= PCI_ROM_SLOT
)
100 return PCI_BASE_ADDRESS_0
+ reg
* 4;
102 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
103 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
106 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
108 return (d
->irq_state
>> irq_num
) & 0x1;
111 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
113 d
->irq_state
&= ~(0x1 << irq_num
);
114 d
->irq_state
|= level
<< irq_num
;
117 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
122 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
125 pci_dev
= bus
->parent_dev
;
127 bus
->irq_count
[irq_num
] += change
;
128 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
131 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
133 assert(irq_num
>= 0);
134 assert(irq_num
< bus
->nirq
);
135 return !!bus
->irq_count
[irq_num
];
138 /* Update interrupt status bit in config space on interrupt
140 static void pci_update_irq_status(PCIDevice
*dev
)
142 if (dev
->irq_state
) {
143 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
145 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
149 void pci_device_deassert_intx(PCIDevice
*dev
)
152 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
153 qemu_set_irq(dev
->irq
[i
], 0);
158 * This function is called on #RST and FLR.
159 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
161 void pci_device_reset(PCIDevice
*dev
)
165 qdev_reset_all(&dev
->qdev
);
168 pci_update_irq_status(dev
);
169 pci_device_deassert_intx(dev
);
170 /* Clear all writable bits */
171 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
172 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
173 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
174 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
175 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
176 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
177 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
178 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
179 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
180 PCIIORegion
*region
= &dev
->io_regions
[r
];
185 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
186 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
187 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
189 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
192 pci_update_mappings(dev
);
199 * Trigger pci bus reset under a given bus.
200 * To be called on RST# assert.
202 void pci_bus_reset(PCIBus
*bus
)
206 for (i
= 0; i
< bus
->nirq
; i
++) {
207 bus
->irq_count
[i
] = 0;
209 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
210 if (bus
->devices
[i
]) {
211 pci_device_reset(bus
->devices
[i
]);
216 static int pcibus_reset(BusState
*qbus
)
218 pci_bus_reset(DO_UPCAST(PCIBus
, qbus
, qbus
));
220 /* topology traverse is done by pci_bus_reset().
221 Tell qbus/qdev walker not to traverse the tree */
225 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
227 struct PCIHostBus
*host
;
228 host
= g_malloc0(sizeof(*host
));
229 host
->domain
= domain
;
231 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
234 PCIBus
*pci_find_root_bus(int domain
)
236 struct PCIHostBus
*host
;
238 QLIST_FOREACH(host
, &host_buses
, next
) {
239 if (host
->domain
== domain
) {
247 int pci_find_domain(const PCIBus
*bus
)
250 struct PCIHostBus
*host
;
252 /* obtain root bus */
253 while ((d
= bus
->parent_dev
) != NULL
) {
257 QLIST_FOREACH(host
, &host_buses
, next
) {
258 if (host
->bus
== bus
) {
263 abort(); /* should not be reached */
267 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
269 MemoryRegion
*address_space_mem
,
270 MemoryRegion
*address_space_io
,
273 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
274 assert(PCI_FUNC(devfn_min
) == 0);
275 bus
->devfn_min
= devfn_min
;
276 bus
->address_space_mem
= address_space_mem
;
277 bus
->address_space_io
= address_space_io
;
280 QLIST_INIT(&bus
->child
);
281 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
283 vmstate_register(NULL
, -1, &vmstate_pcibus
, bus
);
286 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
287 MemoryRegion
*address_space_mem
,
288 MemoryRegion
*address_space_io
,
293 bus
= g_malloc0(sizeof(*bus
));
294 bus
->qbus
.qdev_allocated
= 1;
295 pci_bus_new_inplace(bus
, parent
, name
, address_space_mem
,
296 address_space_io
, devfn_min
);
300 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
301 void *irq_opaque
, int nirq
)
303 bus
->set_irq
= set_irq
;
304 bus
->map_irq
= map_irq
;
305 bus
->irq_opaque
= irq_opaque
;
307 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
310 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*qdev
)
312 bus
->qbus
.allow_hotplug
= 1;
313 bus
->hotplug
= hotplug
;
314 bus
->hotplug_qdev
= qdev
;
317 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
318 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
320 MemoryRegion
*address_space_mem
,
321 MemoryRegion
*address_space_io
,
322 uint8_t devfn_min
, int nirq
)
326 bus
= pci_bus_new(parent
, name
, address_space_mem
,
327 address_space_io
, devfn_min
);
328 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
332 int pci_bus_num(PCIBus
*s
)
335 return 0; /* pci host bridge */
336 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
339 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
341 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
345 assert(size
== pci_config_size(s
));
346 config
= g_malloc(size
);
348 qemu_get_buffer(f
, config
, size
);
349 for (i
= 0; i
< size
; ++i
) {
350 if ((config
[i
] ^ s
->config
[i
]) &
351 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
356 memcpy(s
->config
, config
, size
);
358 pci_update_mappings(s
);
364 /* just put buffer */
365 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
367 const uint8_t **v
= pv
;
368 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
369 qemu_put_buffer(f
, *v
, size
);
372 static VMStateInfo vmstate_info_pci_config
= {
373 .name
= "pci config",
374 .get
= get_pci_config_device
,
375 .put
= put_pci_config_device
,
378 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
380 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
381 uint32_t irq_state
[PCI_NUM_PINS
];
383 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
384 irq_state
[i
] = qemu_get_be32(f
);
385 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
386 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
392 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
393 pci_set_irq_state(s
, i
, irq_state
[i
]);
399 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
402 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
404 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
405 qemu_put_be32(f
, pci_irq_state(s
, i
));
409 static VMStateInfo vmstate_info_pci_irq_state
= {
410 .name
= "pci irq state",
411 .get
= get_pci_irq_state
,
412 .put
= put_pci_irq_state
,
415 const VMStateDescription vmstate_pci_device
= {
418 .minimum_version_id
= 1,
419 .minimum_version_id_old
= 1,
420 .fields
= (VMStateField
[]) {
421 VMSTATE_INT32_LE(version_id
, PCIDevice
),
422 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
423 vmstate_info_pci_config
,
424 PCI_CONFIG_SPACE_SIZE
),
425 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
426 vmstate_info_pci_irq_state
,
427 PCI_NUM_PINS
* sizeof(int32_t)),
428 VMSTATE_END_OF_LIST()
432 const VMStateDescription vmstate_pcie_device
= {
435 .minimum_version_id
= 1,
436 .minimum_version_id_old
= 1,
437 .fields
= (VMStateField
[]) {
438 VMSTATE_INT32_LE(version_id
, PCIDevice
),
439 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
440 vmstate_info_pci_config
,
441 PCIE_CONFIG_SPACE_SIZE
),
442 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
443 vmstate_info_pci_irq_state
,
444 PCI_NUM_PINS
* sizeof(int32_t)),
445 VMSTATE_END_OF_LIST()
449 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
451 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
454 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
456 /* Clear interrupt status bit: it is implicit
457 * in irq_state which we are saving.
458 * This makes us compatible with old devices
459 * which never set or clear this bit. */
460 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
461 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
462 /* Restore the interrupt status bit. */
463 pci_update_irq_status(s
);
466 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
469 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
470 /* Restore the interrupt status bit. */
471 pci_update_irq_status(s
);
475 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
477 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
478 pci_default_sub_vendor_id
);
479 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
480 pci_default_sub_device_id
);
484 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
485 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
487 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
488 unsigned int *slotp
, unsigned int *funcp
)
493 unsigned long dom
= 0, bus
= 0;
494 unsigned int slot
= 0;
495 unsigned int func
= 0;
498 val
= strtoul(p
, &e
, 16);
504 val
= strtoul(p
, &e
, 16);
511 val
= strtoul(p
, &e
, 16);
524 val
= strtoul(p
, &e
, 16);
531 /* if funcp == NULL func is 0 */
532 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
546 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
549 /* strip legacy tag */
550 if (!strncmp(addr
, "pci_addr=", 9)) {
553 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
, NULL
)) {
554 monitor_printf(mon
, "Invalid pci address\n");
560 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
567 return pci_find_bus_nr(pci_find_root_bus(0), 0);
570 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
, NULL
) < 0) {
574 *devfnp
= PCI_DEVFN(slot
, 0);
575 return pci_find_bus_nr(pci_find_root_bus(dom
), bus
);
578 static void pci_init_cmask(PCIDevice
*dev
)
580 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
581 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
582 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
583 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
584 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
585 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
586 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
587 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
590 static void pci_init_wmask(PCIDevice
*dev
)
592 int config_size
= pci_config_size(dev
);
594 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
595 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
596 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
597 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
598 PCI_COMMAND_INTX_DISABLE
);
599 if (dev
->cap_present
& QEMU_PCI_CAP_SERR
) {
600 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
603 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
604 config_size
- PCI_CONFIG_HEADER_SIZE
);
607 static void pci_init_w1cmask(PCIDevice
*dev
)
610 * Note: It's okay to set w1cmask even for readonly bits as
611 * long as their value is hardwired to 0.
613 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
614 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
615 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
616 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
619 static void pci_init_mask_bridge(PCIDevice
*d
)
621 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
622 PCI_SEC_LETENCY_TIMER */
623 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
626 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
627 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
628 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
629 PCI_MEMORY_RANGE_MASK
& 0xffff);
630 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
631 PCI_MEMORY_RANGE_MASK
& 0xffff);
632 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
633 PCI_PREF_RANGE_MASK
& 0xffff);
634 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
635 PCI_PREF_RANGE_MASK
& 0xffff);
637 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
638 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
640 /* Supported memory and i/o types */
641 d
->config
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_16
;
642 d
->config
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_16
;
643 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_BASE
,
644 PCI_PREF_RANGE_TYPE_64
);
645 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_LIMIT
,
646 PCI_PREF_RANGE_TYPE_64
);
648 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
649 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
650 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
651 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
652 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
653 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
654 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
655 PCI_BRIDGE_CTL_PARITY
|
656 PCI_BRIDGE_CTL_SERR
|
659 PCI_BRIDGE_CTL_VGA_16BIT
|
660 PCI_BRIDGE_CTL_MASTER_ABORT
|
661 PCI_BRIDGE_CTL_BUS_RESET
|
662 PCI_BRIDGE_CTL_FAST_BACK
|
663 PCI_BRIDGE_CTL_DISCARD
|
664 PCI_BRIDGE_CTL_SEC_DISCARD
|
665 PCI_BRIDGE_CTL_DISCARD_SERR
);
666 /* Below does not do anything as we never set this bit, put here for
668 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
669 PCI_BRIDGE_CTL_DISCARD_STATUS
);
670 d
->cmask
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_MASK
;
671 d
->cmask
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_MASK
;
672 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_BASE
,
673 PCI_PREF_RANGE_TYPE_MASK
);
674 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_LIMIT
,
675 PCI_PREF_RANGE_TYPE_MASK
);
678 static int pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
)
680 uint8_t slot
= PCI_SLOT(dev
->devfn
);
683 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
684 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
688 * multifunction bit is interpreted in two ways as follows.
689 * - all functions must set the bit to 1.
691 * - function 0 must set the bit, but the rest function (> 0)
692 * is allowed to leave the bit to 0.
693 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
695 * So OS (at least Linux) checks the bit of only function 0,
696 * and doesn't see the bit of function > 0.
698 * The below check allows both interpretation.
700 if (PCI_FUNC(dev
->devfn
)) {
701 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
702 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
703 /* function 0 should set multifunction bit */
704 error_report("PCI: single function device can't be populated "
705 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
711 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
714 /* function 0 indicates single function, so function > 0 must be NULL */
715 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
716 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
717 error_report("PCI: %x.0 indicates single function, "
718 "but %x.%x is already populated.",
726 static void pci_config_alloc(PCIDevice
*pci_dev
)
728 int config_size
= pci_config_size(pci_dev
);
730 pci_dev
->config
= g_malloc0(config_size
);
731 pci_dev
->cmask
= g_malloc0(config_size
);
732 pci_dev
->wmask
= g_malloc0(config_size
);
733 pci_dev
->w1cmask
= g_malloc0(config_size
);
734 pci_dev
->used
= g_malloc0(config_size
);
737 static void pci_config_free(PCIDevice
*pci_dev
)
739 g_free(pci_dev
->config
);
740 g_free(pci_dev
->cmask
);
741 g_free(pci_dev
->wmask
);
742 g_free(pci_dev
->w1cmask
);
743 g_free(pci_dev
->used
);
746 /* -1 for devfn means auto assign */
747 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
748 const char *name
, int devfn
)
750 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
751 PCIConfigReadFunc
*config_read
= pc
->config_read
;
752 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
755 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
756 devfn
+= PCI_FUNC_MAX
) {
757 if (!bus
->devices
[devfn
])
760 error_report("PCI: no slot/function available for %s, all in use", name
);
763 } else if (bus
->devices
[devfn
]) {
764 error_report("PCI: slot %d function %d not available for %s, in use by %s",
765 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
, bus
->devices
[devfn
]->name
);
769 pci_dev
->devfn
= devfn
;
770 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
771 pci_dev
->irq_state
= 0;
772 pci_config_alloc(pci_dev
);
774 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
775 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
776 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
777 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
779 if (!pc
->is_bridge
) {
780 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
781 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
782 pc
->subsystem_vendor_id
);
783 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
786 pci_set_default_subsystem_id(pci_dev
);
789 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
790 assert(!pc
->subsystem_vendor_id
);
791 assert(!pc
->subsystem_id
);
793 pci_init_cmask(pci_dev
);
794 pci_init_wmask(pci_dev
);
795 pci_init_w1cmask(pci_dev
);
797 pci_init_mask_bridge(pci_dev
);
799 if (pci_init_multifunction(bus
, pci_dev
)) {
800 pci_config_free(pci_dev
);
805 config_read
= pci_default_read_config
;
807 config_write
= pci_default_write_config
;
808 pci_dev
->config_read
= config_read
;
809 pci_dev
->config_write
= config_write
;
810 bus
->devices
[devfn
] = pci_dev
;
811 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
812 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
816 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
818 qemu_free_irqs(pci_dev
->irq
);
819 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
820 pci_config_free(pci_dev
);
823 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
828 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
829 r
= &pci_dev
->io_regions
[i
];
830 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
832 memory_region_del_subregion(r
->address_space
, r
->memory
);
836 static int pci_unregister_device(DeviceState
*dev
)
838 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
839 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
843 ret
= pc
->exit(pci_dev
);
847 pci_unregister_io_regions(pci_dev
);
848 pci_del_option_rom(pci_dev
);
849 do_pci_unregister_device(pci_dev
);
853 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
854 uint8_t type
, MemoryRegion
*memory
)
859 pcibus_t size
= memory_region_size(memory
);
861 assert(region_num
>= 0);
862 assert(region_num
< PCI_NUM_REGIONS
);
863 if (size
& (size
-1)) {
864 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
865 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
869 r
= &pci_dev
->io_regions
[region_num
];
870 r
->addr
= PCI_BAR_UNMAPPED
;
876 addr
= pci_bar(pci_dev
, region_num
);
877 if (region_num
== PCI_ROM_SLOT
) {
878 /* ROM enable bit is writable */
879 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
881 pci_set_long(pci_dev
->config
+ addr
, type
);
882 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
883 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
884 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
885 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
887 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
888 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
890 pci_dev
->io_regions
[region_num
].memory
= memory
;
891 pci_dev
->io_regions
[region_num
].address_space
892 = type
& PCI_BASE_ADDRESS_SPACE_IO
893 ? pci_dev
->bus
->address_space_io
894 : pci_dev
->bus
->address_space_mem
;
897 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
899 return pci_dev
->io_regions
[region_num
].addr
;
902 static pcibus_t
pci_bar_address(PCIDevice
*d
,
903 int reg
, uint8_t type
, pcibus_t size
)
905 pcibus_t new_addr
, last_addr
;
906 int bar
= pci_bar(d
, reg
);
907 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
909 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
910 if (!(cmd
& PCI_COMMAND_IO
)) {
911 return PCI_BAR_UNMAPPED
;
913 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
914 last_addr
= new_addr
+ size
- 1;
915 /* NOTE: we have only 64K ioports on PC */
916 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
917 return PCI_BAR_UNMAPPED
;
922 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
923 return PCI_BAR_UNMAPPED
;
925 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
926 new_addr
= pci_get_quad(d
->config
+ bar
);
928 new_addr
= pci_get_long(d
->config
+ bar
);
930 /* the ROM slot has a specific enable bit */
931 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
932 return PCI_BAR_UNMAPPED
;
934 new_addr
&= ~(size
- 1);
935 last_addr
= new_addr
+ size
- 1;
936 /* NOTE: we do not support wrapping */
937 /* XXX: as we cannot support really dynamic
938 mappings, we handle specific values as invalid
940 if (last_addr
<= new_addr
|| new_addr
== 0 ||
941 last_addr
== PCI_BAR_UNMAPPED
) {
942 return PCI_BAR_UNMAPPED
;
945 /* Now pcibus_t is 64bit.
946 * Check if 32 bit BAR wraps around explicitly.
947 * Without this, PC ide doesn't work well.
948 * TODO: remove this work around.
950 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
951 return PCI_BAR_UNMAPPED
;
955 * OS is allowed to set BAR beyond its addressable
956 * bits. For example, 32 bit OS can set 64bit bar
957 * to >4G. Check it. TODO: we might need to support
958 * it in the future for e.g. PAE.
960 if (last_addr
>= TARGET_PHYS_ADDR_MAX
) {
961 return PCI_BAR_UNMAPPED
;
967 static void pci_update_mappings(PCIDevice
*d
)
973 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
974 r
= &d
->io_regions
[i
];
976 /* this region isn't registered */
980 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
982 /* This bar isn't changed */
983 if (new_addr
== r
->addr
)
986 /* now do the real mapping */
987 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
988 memory_region_del_subregion(r
->address_space
, r
->memory
);
991 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
992 memory_region_add_subregion_overlap(r
->address_space
,
993 r
->addr
, r
->memory
, 1);
998 static inline int pci_irq_disabled(PCIDevice
*d
)
1000 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1003 /* Called after interrupt disabled field update in config space,
1004 * assert/deassert interrupts if necessary.
1005 * Gets original interrupt disable bit value (before update). */
1006 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1008 int i
, disabled
= pci_irq_disabled(d
);
1009 if (disabled
== was_irq_disabled
)
1011 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1012 int state
= pci_irq_state(d
, i
);
1013 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1017 uint32_t pci_default_read_config(PCIDevice
*d
,
1018 uint32_t address
, int len
)
1022 memcpy(&val
, d
->config
+ address
, len
);
1023 return le32_to_cpu(val
);
1026 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
1028 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1030 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1031 uint8_t wmask
= d
->wmask
[addr
+ i
];
1032 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1033 assert(!(wmask
& w1cmask
));
1034 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1035 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1037 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1038 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1039 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1040 range_covers_byte(addr
, l
, PCI_COMMAND
))
1041 pci_update_mappings(d
);
1043 if (range_covers_byte(addr
, l
, PCI_COMMAND
))
1044 pci_update_irq_disabled(d
, was_irq_disabled
);
1046 msi_write_config(d
, addr
, val
, l
);
1047 msix_write_config(d
, addr
, val
, l
);
1050 /***********************************************************/
1051 /* generic PCI irq support */
1053 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1054 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
1056 PCIDevice
*pci_dev
= opaque
;
1059 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1063 pci_set_irq_state(pci_dev
, irq_num
, level
);
1064 pci_update_irq_status(pci_dev
);
1065 if (pci_irq_disabled(pci_dev
))
1067 pci_change_irq_level(pci_dev
, irq_num
, change
);
1070 /***********************************************************/
1071 /* monitor info on PCI */
1076 const char *fw_name
;
1077 uint16_t fw_ign_bits
;
1080 static const pci_class_desc pci_class_descriptions
[] =
1082 { 0x0001, "VGA controller", "display"},
1083 { 0x0100, "SCSI controller", "scsi"},
1084 { 0x0101, "IDE controller", "ide"},
1085 { 0x0102, "Floppy controller", "fdc"},
1086 { 0x0103, "IPI controller", "ipi"},
1087 { 0x0104, "RAID controller", "raid"},
1088 { 0x0106, "SATA controller"},
1089 { 0x0107, "SAS controller"},
1090 { 0x0180, "Storage controller"},
1091 { 0x0200, "Ethernet controller", "ethernet"},
1092 { 0x0201, "Token Ring controller", "token-ring"},
1093 { 0x0202, "FDDI controller", "fddi"},
1094 { 0x0203, "ATM controller", "atm"},
1095 { 0x0280, "Network controller"},
1096 { 0x0300, "VGA controller", "display", 0x00ff},
1097 { 0x0301, "XGA controller"},
1098 { 0x0302, "3D controller"},
1099 { 0x0380, "Display controller"},
1100 { 0x0400, "Video controller", "video"},
1101 { 0x0401, "Audio controller", "sound"},
1103 { 0x0403, "Audio controller", "sound"},
1104 { 0x0480, "Multimedia controller"},
1105 { 0x0500, "RAM controller", "memory"},
1106 { 0x0501, "Flash controller", "flash"},
1107 { 0x0580, "Memory controller"},
1108 { 0x0600, "Host bridge", "host"},
1109 { 0x0601, "ISA bridge", "isa"},
1110 { 0x0602, "EISA bridge", "eisa"},
1111 { 0x0603, "MC bridge", "mca"},
1112 { 0x0604, "PCI bridge", "pci"},
1113 { 0x0605, "PCMCIA bridge", "pcmcia"},
1114 { 0x0606, "NUBUS bridge", "nubus"},
1115 { 0x0607, "CARDBUS bridge", "cardbus"},
1116 { 0x0608, "RACEWAY bridge"},
1117 { 0x0680, "Bridge"},
1118 { 0x0700, "Serial port", "serial"},
1119 { 0x0701, "Parallel port", "parallel"},
1120 { 0x0800, "Interrupt controller", "interrupt-controller"},
1121 { 0x0801, "DMA controller", "dma-controller"},
1122 { 0x0802, "Timer", "timer"},
1123 { 0x0803, "RTC", "rtc"},
1124 { 0x0900, "Keyboard", "keyboard"},
1125 { 0x0901, "Pen", "pen"},
1126 { 0x0902, "Mouse", "mouse"},
1127 { 0x0A00, "Dock station", "dock", 0x00ff},
1128 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1129 { 0x0c00, "Fireware contorller", "fireware"},
1130 { 0x0c01, "Access bus controller", "access-bus"},
1131 { 0x0c02, "SSA controller", "ssa"},
1132 { 0x0c03, "USB controller", "usb"},
1133 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1137 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1138 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1143 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1144 d
= bus
->devices
[devfn
];
1151 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1152 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1154 bus
= pci_find_bus_nr(bus
, bus_num
);
1157 pci_for_each_device_under_bus(bus
, fn
);
1161 static const pci_class_desc
*get_class_desc(int class)
1163 const pci_class_desc
*desc
;
1165 desc
= pci_class_descriptions
;
1166 while (desc
->desc
&& class != desc
->class) {
1173 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
);
1175 static PciMemoryRegionList
*qmp_query_pci_regions(const PCIDevice
*dev
)
1177 PciMemoryRegionList
*head
= NULL
, *cur_item
= NULL
;
1180 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1181 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1182 PciMemoryRegionList
*region
;
1188 region
= g_malloc0(sizeof(*region
));
1189 region
->value
= g_malloc0(sizeof(*region
->value
));
1191 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1192 region
->value
->type
= g_strdup("io");
1194 region
->value
->type
= g_strdup("memory");
1195 region
->value
->has_prefetch
= true;
1196 region
->value
->prefetch
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
);
1197 region
->value
->has_mem_type_64
= true;
1198 region
->value
->mem_type_64
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
1201 region
->value
->bar
= i
;
1202 region
->value
->address
= r
->addr
;
1203 region
->value
->size
= r
->size
;
1205 /* XXX: waiting for the qapi to support GSList */
1207 head
= cur_item
= region
;
1209 cur_item
->next
= region
;
1217 static PciBridgeInfo
*qmp_query_pci_bridge(PCIDevice
*dev
, PCIBus
*bus
,
1220 PciBridgeInfo
*info
;
1222 info
= g_malloc0(sizeof(*info
));
1224 info
->bus
.number
= dev
->config
[PCI_PRIMARY_BUS
];
1225 info
->bus
.secondary
= dev
->config
[PCI_SECONDARY_BUS
];
1226 info
->bus
.subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
1228 info
->bus
.io_range
= g_malloc0(sizeof(*info
->bus
.io_range
));
1229 info
->bus
.io_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1230 info
->bus
.io_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1232 info
->bus
.memory_range
= g_malloc0(sizeof(*info
->bus
.memory_range
));
1233 info
->bus
.memory_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1234 info
->bus
.memory_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1236 info
->bus
.prefetchable_range
= g_malloc0(sizeof(*info
->bus
.prefetchable_range
));
1237 info
->bus
.prefetchable_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1238 info
->bus
.prefetchable_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1240 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1241 PCIBus
*child_bus
= pci_find_bus_nr(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1243 info
->has_devices
= true;
1244 info
->devices
= qmp_query_pci_devices(child_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1251 static PciDeviceInfo
*qmp_query_pci_device(PCIDevice
*dev
, PCIBus
*bus
,
1254 const pci_class_desc
*desc
;
1255 PciDeviceInfo
*info
;
1259 info
= g_malloc0(sizeof(*info
));
1260 info
->bus
= bus_num
;
1261 info
->slot
= PCI_SLOT(dev
->devfn
);
1262 info
->function
= PCI_FUNC(dev
->devfn
);
1264 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1265 info
->class_info
.class = class;
1266 desc
= get_class_desc(class);
1268 info
->class_info
.has_desc
= true;
1269 info
->class_info
.desc
= g_strdup(desc
->desc
);
1272 info
->id
.vendor
= pci_get_word(dev
->config
+ PCI_VENDOR_ID
);
1273 info
->id
.device
= pci_get_word(dev
->config
+ PCI_DEVICE_ID
);
1274 info
->regions
= qmp_query_pci_regions(dev
);
1275 info
->qdev_id
= g_strdup(dev
->qdev
.id
? dev
->qdev
.id
: "");
1277 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1278 info
->has_irq
= true;
1279 info
->irq
= dev
->config
[PCI_INTERRUPT_LINE
];
1282 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1283 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1284 info
->has_pci_bridge
= true;
1285 info
->pci_bridge
= qmp_query_pci_bridge(dev
, bus
, bus_num
);
1291 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
)
1293 PciDeviceInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1297 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1298 dev
= bus
->devices
[devfn
];
1300 info
= g_malloc0(sizeof(*info
));
1301 info
->value
= qmp_query_pci_device(dev
, bus
, bus_num
);
1303 /* XXX: waiting for the qapi to support GSList */
1305 head
= cur_item
= info
;
1307 cur_item
->next
= info
;
1316 static PciInfo
*qmp_query_pci_bus(PCIBus
*bus
, int bus_num
)
1318 PciInfo
*info
= NULL
;
1320 bus
= pci_find_bus_nr(bus
, bus_num
);
1322 info
= g_malloc0(sizeof(*info
));
1323 info
->bus
= bus_num
;
1324 info
->devices
= qmp_query_pci_devices(bus
, bus_num
);
1330 PciInfoList
*qmp_query_pci(Error
**errp
)
1332 PciInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1333 struct PCIHostBus
*host
;
1335 QLIST_FOREACH(host
, &host_buses
, next
) {
1336 info
= g_malloc0(sizeof(*info
));
1337 info
->value
= qmp_query_pci_bus(host
->bus
, 0);
1339 /* XXX: waiting for the qapi to support GSList */
1341 head
= cur_item
= info
;
1343 cur_item
->next
= info
;
1351 static const char * const pci_nic_models
[] = {
1363 static const char * const pci_nic_names
[] = {
1375 /* Initialize a PCI NIC. */
1376 /* FIXME callers should check for failure, but don't */
1377 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
1378 const char *default_devaddr
)
1380 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1387 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1391 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
1393 error_report("Invalid PCI device address %s for device %s",
1394 devaddr
, pci_nic_names
[i
]);
1398 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1399 dev
= &pci_dev
->qdev
;
1400 qdev_set_nic_properties(dev
, nd
);
1401 if (qdev_init(dev
) < 0)
1406 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
1407 const char *default_devaddr
)
1411 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1414 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
1420 /* Whether a given bus number is in range of the secondary
1421 * bus of the given bridge device. */
1422 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1424 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1425 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1426 dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1427 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1430 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
)
1438 if (pci_bus_num(bus
) == bus_num
) {
1442 /* Consider all bus numbers in range for the host pci bridge. */
1443 if (bus
->parent_dev
&&
1444 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
1449 for (; bus
; bus
= sec
) {
1450 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1451 assert(sec
->parent_dev
);
1452 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] == bus_num
) {
1455 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
1464 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
1466 bus
= pci_find_bus_nr(bus
, bus_num
);
1471 return bus
->devices
[devfn
];
1474 static int pci_qdev_init(DeviceState
*qdev
)
1476 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1477 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1480 bool is_default_rom
;
1482 /* initialize cap_present for pci_is_express() and pci_config_size() */
1483 if (pc
->is_express
) {
1484 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1487 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1488 pci_dev
= do_pci_register_device(pci_dev
, bus
,
1489 object_get_typename(OBJECT(qdev
)),
1491 if (pci_dev
== NULL
)
1493 if (qdev
->hotplugged
&& pc
->no_hotplug
) {
1494 qerror_report(QERR_DEVICE_NO_HOTPLUG
, object_get_typename(OBJECT(pci_dev
)));
1495 do_pci_unregister_device(pci_dev
);
1499 rc
= pc
->init(pci_dev
);
1501 do_pci_unregister_device(pci_dev
);
1507 is_default_rom
= false;
1508 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
1509 pci_dev
->romfile
= g_strdup(pc
->romfile
);
1510 is_default_rom
= true;
1512 pci_add_option_rom(pci_dev
, is_default_rom
);
1515 /* Let buses differentiate between hotplug and when device is
1516 * enabled during qemu machine creation. */
1517 rc
= bus
->hotplug(bus
->hotplug_qdev
, pci_dev
,
1518 qdev
->hotplugged
? PCI_HOTPLUG_ENABLED
:
1519 PCI_COLDPLUG_ENABLED
);
1521 int r
= pci_unregister_device(&pci_dev
->qdev
);
1529 static int pci_unplug_device(DeviceState
*qdev
)
1531 PCIDevice
*dev
= PCI_DEVICE(qdev
);
1532 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1534 if (pc
->no_hotplug
) {
1535 qerror_report(QERR_DEVICE_NO_HOTPLUG
, object_get_typename(OBJECT(dev
)));
1538 return dev
->bus
->hotplug(dev
->bus
->hotplug_qdev
, dev
,
1539 PCI_HOTPLUG_DISABLED
);
1542 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
1547 dev
= qdev_create(&bus
->qbus
, name
);
1548 qdev_prop_set_int32(dev
, "addr", devfn
);
1549 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1550 return PCI_DEVICE(dev
);
1553 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
1557 PCIDevice
*dev
= pci_create_multifunction(bus
, devfn
, multifunction
, name
);
1558 qdev_init_nofail(&dev
->qdev
);
1562 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1564 return pci_create_multifunction(bus
, devfn
, false, name
);
1567 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1569 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
1572 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1574 int config_size
= pci_config_size(pdev
);
1575 int offset
= PCI_CONFIG_HEADER_SIZE
;
1577 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< config_size
; ++i
)
1580 else if (i
- offset
+ 1 == size
)
1585 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1590 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1593 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1594 prev
= next
+ PCI_CAP_LIST_NEXT
)
1595 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1603 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
1605 uint8_t next
, prev
, found
= 0;
1607 if (!(pdev
->used
[offset
])) {
1611 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
1613 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1614 prev
= next
+ PCI_CAP_LIST_NEXT
) {
1615 if (next
<= offset
&& next
> found
) {
1622 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1623 This is needed for an option rom which is used for more than one device. */
1624 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, int size
)
1628 uint16_t rom_vendor_id
;
1629 uint16_t rom_device_id
;
1631 uint16_t pcir_offset
;
1634 /* Words in rom data are little endian (like in PCI configuration),
1635 so they can be read / written with pci_get_word / pci_set_word. */
1637 /* Only a valid rom will be patched. */
1638 rom_magic
= pci_get_word(ptr
);
1639 if (rom_magic
!= 0xaa55) {
1640 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
1643 pcir_offset
= pci_get_word(ptr
+ 0x18);
1644 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
1645 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
1649 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1650 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
1651 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
1652 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
1654 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
1655 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
1659 if (vendor_id
!= rom_vendor_id
) {
1660 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1661 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
1662 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
1663 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1665 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
1668 if (device_id
!= rom_device_id
) {
1669 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1670 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
1671 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
1672 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1674 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
1678 /* Add an option rom for the device */
1679 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
)
1685 const VMStateDescription
*vmsd
;
1689 if (strlen(pdev
->romfile
) == 0)
1692 if (!pdev
->rom_bar
) {
1694 * Load rom via fw_cfg instead of creating a rom bar,
1695 * for 0.11 compatibility.
1697 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1698 if (class == 0x0300) {
1699 rom_add_vga(pdev
->romfile
);
1701 rom_add_option(pdev
->romfile
, -1);
1706 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
1708 path
= g_strdup(pdev
->romfile
);
1711 size
= get_image_size(path
);
1713 error_report("%s: failed to find romfile \"%s\"",
1714 __FUNCTION__
, pdev
->romfile
);
1718 if (size
& (size
- 1)) {
1719 size
= 1 << qemu_fls(size
);
1722 vmsd
= qdev_get_vmsd(DEVICE(pdev
));
1725 snprintf(name
, sizeof(name
), "%s.rom", vmsd
->name
);
1727 snprintf(name
, sizeof(name
), "%s.rom", object_get_typename(OBJECT(pdev
)));
1729 pdev
->has_rom
= true;
1730 memory_region_init_ram(&pdev
->rom
, name
, size
);
1731 vmstate_register_ram(&pdev
->rom
, &pdev
->qdev
);
1732 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
1733 load_image(path
, ptr
);
1736 if (is_default_rom
) {
1737 /* Only the default rom images will be patched (if needed). */
1738 pci_patch_ids(pdev
, ptr
, size
);
1741 qemu_put_ram_ptr(ptr
);
1743 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
1748 static void pci_del_option_rom(PCIDevice
*pdev
)
1753 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
1754 memory_region_destroy(&pdev
->rom
);
1755 pdev
->has_rom
= false;
1760 * Reserve space and add capability to the linked list in pci config space
1763 * Find and reserve space and add capability to the linked list
1764 * in pci config space */
1765 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
1766 uint8_t offset
, uint8_t size
)
1769 int i
, overlapping_cap
;
1772 offset
= pci_find_space(pdev
, size
);
1777 /* Verify that capabilities don't overlap. Note: device assignment
1778 * depends on this check to verify that the device is not broken.
1779 * Should never trigger for emulated devices, but it's helpful
1780 * for debugging these. */
1781 for (i
= offset
; i
< offset
+ size
; i
++) {
1782 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
1783 if (overlapping_cap
) {
1784 fprintf(stderr
, "ERROR: %04x:%02x:%02x.%x "
1785 "Attempt to add PCI capability %x at offset "
1786 "%x overlaps existing capability %x at offset %x\n",
1787 pci_find_domain(pdev
->bus
), pci_bus_num(pdev
->bus
),
1788 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
1789 cap_id
, offset
, overlapping_cap
, i
);
1795 config
= pdev
->config
+ offset
;
1796 config
[PCI_CAP_LIST_ID
] = cap_id
;
1797 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
1798 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
1799 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1800 memset(pdev
->used
+ offset
, 0xFF, size
);
1801 /* Make capability read-only by default */
1802 memset(pdev
->wmask
+ offset
, 0, size
);
1803 /* Check capability by default */
1804 memset(pdev
->cmask
+ offset
, 0xFF, size
);
1808 /* Unlink capability from the pci config space. */
1809 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1811 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
1814 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
1815 /* Make capability writable again */
1816 memset(pdev
->wmask
+ offset
, 0xff, size
);
1817 memset(pdev
->w1cmask
+ offset
, 0, size
);
1818 /* Clear cmask as device-specific registers can't be checked */
1819 memset(pdev
->cmask
+ offset
, 0, size
);
1820 memset(pdev
->used
+ offset
, 0, size
);
1822 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
1823 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
1826 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
1828 return pci_find_capability_list(pdev
, cap_id
, NULL
);
1831 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
1833 PCIDevice
*d
= (PCIDevice
*)dev
;
1834 const pci_class_desc
*desc
;
1839 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1840 desc
= pci_class_descriptions
;
1841 while (desc
->desc
&& class != desc
->class)
1844 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
1846 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
1849 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
1850 "pci id %04x:%04x (sub %04x:%04x)\n",
1851 indent
, "", ctxt
, pci_bus_num(d
->bus
),
1852 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
1853 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1854 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
1855 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
1856 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
1857 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1858 r
= &d
->io_regions
[i
];
1861 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1862 " [0x%"FMT_PCIBUS
"]\n",
1864 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
1865 r
->addr
, r
->addr
+ r
->size
- 1);
1869 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
1871 PCIDevice
*d
= (PCIDevice
*)dev
;
1872 const char *name
= NULL
;
1873 const pci_class_desc
*desc
= pci_class_descriptions
;
1874 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1876 while (desc
->desc
&&
1877 (class & ~desc
->fw_ign_bits
) !=
1878 (desc
->class & ~desc
->fw_ign_bits
)) {
1883 name
= desc
->fw_name
;
1887 pstrcpy(buf
, len
, name
);
1889 snprintf(buf
, len
, "pci%04x,%04x",
1890 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1891 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
1897 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
1899 PCIDevice
*d
= (PCIDevice
*)dev
;
1900 char path
[50], name
[33];
1903 off
= snprintf(path
, sizeof(path
), "%s@%x",
1904 pci_dev_fw_name(dev
, name
, sizeof name
),
1905 PCI_SLOT(d
->devfn
));
1906 if (PCI_FUNC(d
->devfn
))
1907 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
1908 return strdup(path
);
1911 static char *pcibus_get_dev_path(DeviceState
*dev
)
1913 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
1916 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
1917 * 00 is added here to make this format compatible with
1918 * domain:Bus:Slot.Func for systems without nested PCI bridges.
1919 * Slot.Function list specifies the slot and function numbers for all
1920 * devices on the path from root to the specific device. */
1921 char domain
[] = "DDDD:00";
1922 char slot
[] = ":SS.F";
1923 int domain_len
= sizeof domain
- 1 /* For '\0' */;
1924 int slot_len
= sizeof slot
- 1 /* For '\0' */;
1929 /* Calculate # of slots on path between device and root. */;
1931 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
1935 path_len
= domain_len
+ slot_len
* slot_depth
;
1937 /* Allocate memory, fill in the terminating null byte. */
1938 path
= g_malloc(path_len
+ 1 /* For '\0' */);
1939 path
[path_len
] = '\0';
1941 /* First field is the domain. */
1942 s
= snprintf(domain
, sizeof domain
, "%04x:00", pci_find_domain(d
->bus
));
1943 assert(s
== domain_len
);
1944 memcpy(path
, domain
, domain_len
);
1946 /* Fill in slot numbers. We walk up from device to root, so need to print
1947 * them in the reverse order, last to first. */
1948 p
= path
+ path_len
;
1949 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
1951 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
1952 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
1953 assert(s
== slot_len
);
1954 memcpy(p
, slot
, slot_len
);
1960 static int pci_qdev_find_recursive(PCIBus
*bus
,
1961 const char *id
, PCIDevice
**pdev
)
1963 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
1968 /* roughly check if given qdev is pci device */
1969 if (object_dynamic_cast(OBJECT(qdev
), TYPE_PCI_DEVICE
)) {
1970 *pdev
= PCI_DEVICE(qdev
);
1976 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
1978 struct PCIHostBus
*host
;
1981 QLIST_FOREACH(host
, &host_buses
, next
) {
1982 int tmp
= pci_qdev_find_recursive(host
->bus
, id
, pdev
);
1987 if (tmp
!= -ENODEV
) {
1995 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
1997 return dev
->bus
->address_space_mem
;
2000 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
2002 return dev
->bus
->address_space_io
;
2005 static void pci_device_class_init(ObjectClass
*klass
, void *data
)
2007 DeviceClass
*k
= DEVICE_CLASS(klass
);
2008 k
->init
= pci_qdev_init
;
2009 k
->unplug
= pci_unplug_device
;
2010 k
->exit
= pci_unregister_device
;
2011 k
->bus_info
= &pci_bus_info
;
2014 static TypeInfo pci_device_type_info
= {
2015 .name
= TYPE_PCI_DEVICE
,
2016 .parent
= TYPE_DEVICE
,
2017 .instance_size
= sizeof(PCIDevice
),
2019 .class_size
= sizeof(PCIDeviceClass
),
2020 .class_init
= pci_device_class_init
,
2023 static void pci_register_types(void)
2025 type_register_static(&pci_device_type_info
);
2028 type_init(pci_register_types
)