hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pci_bridge.h"
  27 #include "pci_internals.h"
  28 #include "msix.h"
  29 #include "msi.h"
  30 #include "monitor.h"
  31 #include "net.h"
  32 #include "sysemu.h"
  33 #include "loader.h"
  34 #include "qemu-objects.h"
  35
  36 //#define DEBUG_PCI
  37 #ifdef DEBUG_PCI
  38 # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
  39 #else
  40 # define PCI_DPRINTF(format, ...)       do { } while (0)
  41 #endif
  42
  43 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  44 static char *pcibus_get_dev_path(DeviceState *dev);
  45
  46 struct BusInfo pci_bus_info = {
  47     .name       = "PCI",
  48     .size       = sizeof(PCIBus),
  49     .print_dev  = pcibus_dev_print,
  50     .get_dev_path = pcibus_get_dev_path,
  51     .props      = (Property[]) {
  52         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  53         DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
  54         DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
  55         DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
  56                         QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
  57         DEFINE_PROP_END_OF_LIST()
  58     }
  59 };
  60
  61 static void pci_update_mappings(PCIDevice *d);
  62 static void pci_set_irq(void *opaque, int irq_num, int level);
  63 static int pci_add_option_rom(PCIDevice *pdev);
  64 static void pci_del_option_rom(PCIDevice *pdev);
  65
  66 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  67 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  68
  69 struct PCIHostBus {
  70     int domain;
  71     struct PCIBus *bus;
  72     QLIST_ENTRY(PCIHostBus) next;
  73 };
  74 static QLIST_HEAD(, PCIHostBus) host_buses;
  75
  76 static const VMStateDescription vmstate_pcibus = {
  77     .name = "PCIBUS",
  78     .version_id = 1,
  79     .minimum_version_id = 1,
  80     .minimum_version_id_old = 1,
  81     .fields      = (VMStateField []) {
  82         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  83         VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
  84         VMSTATE_END_OF_LIST()
  85     }
  86 };
  87
  88 static int pci_bar(PCIDevice *d, int reg)
  89 {
  90     uint8_t type;
  91
  92     if (reg != PCI_ROM_SLOT)
  93         return PCI_BASE_ADDRESS_0 + reg * 4;
  94
  95     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
  96     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
  97 }
  98
  99 static inline int pci_irq_state(PCIDevice *d, int irq_num)
 100 {
 101         return (d->irq_state >> irq_num) & 0x1;
 102 }
 103
 104 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
 105 {
 106         d->irq_state &= ~(0x1 << irq_num);
 107         d->irq_state |= level << irq_num;
 108 }
 109
 110 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
 111 {
 112     PCIBus *bus;
 113     for (;;) {
 114         bus = pci_dev->bus;
 115         irq_num = bus->map_irq(pci_dev, irq_num);
 116         if (bus->set_irq)
 117             break;
 118         pci_dev = bus->parent_dev;
 119     }
 120     bus->irq_count[irq_num] += change;
 121     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 122 }
 123
 124 /* Update interrupt status bit in config space on interrupt
 125  * state change. */
 126 static void pci_update_irq_status(PCIDevice *dev)
 127 {
 128     if (dev->irq_state) {
 129         dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
 130     } else {
 131         dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 132     }
 133 }
 134
 135 static void pci_device_reset(PCIDevice *dev)
 136 {
 137     int r;
 138
 139     dev->irq_state = 0;
 140     pci_update_irq_status(dev);
 141     /* Clear all writeable bits */
 142     pci_set_word(dev->config + PCI_COMMAND,
 143                  pci_get_word(dev->config + PCI_COMMAND) &
 144                  ~pci_get_word(dev->wmask + PCI_COMMAND));
 145     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
 146     dev->config[PCI_INTERRUPT_LINE] = 0x0;
 147     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
 148         PCIIORegion *region = &dev->io_regions[r];
 149         if (!region->size) {
 150             continue;
 151         }
 152
 153         if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 154             region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 155             pci_set_quad(dev->config + pci_bar(dev, r), region->type);
 156         } else {
 157             pci_set_long(dev->config + pci_bar(dev, r), region->type);
 158         }
 159     }
 160     pci_update_mappings(dev);
 161 }
 162
 163 static void pci_bus_reset(void *opaque)
 164 {
 165     PCIBus *bus = opaque;
 166     int i;
 167
 168     for (i = 0; i < bus->nirq; i++) {
 169         bus->irq_count[i] = 0;
 170     }
 171     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 172         if (bus->devices[i]) {
 173             pci_device_reset(bus->devices[i]);
 174         }
 175     }
 176 }
 177
 178 static void pci_host_bus_register(int domain, PCIBus *bus)
 179 {
 180     struct PCIHostBus *host;
 181     host = qemu_mallocz(sizeof(*host));
 182     host->domain = domain;
 183     host->bus = bus;
 184     QLIST_INSERT_HEAD(&host_buses, host, next);
 185 }
 186
 187 PCIBus *pci_find_root_bus(int domain)
 188 {
 189     struct PCIHostBus *host;
 190
 191     QLIST_FOREACH(host, &host_buses, next) {
 192         if (host->domain == domain) {
 193             return host->bus;
 194         }
 195     }
 196
 197     return NULL;
 198 }
 199
 200 int pci_find_domain(const PCIBus *bus)
 201 {
 202     PCIDevice *d;
 203     struct PCIHostBus *host;
 204
 205     /* obtain root bus */
 206     while ((d = bus->parent_dev) != NULL) {
 207         bus = d->bus;
 208     }
 209
 210     QLIST_FOREACH(host, &host_buses, next) {
 211         if (host->bus == bus) {
 212             return host->domain;
 213         }
 214     }
 215
 216     abort();    /* should not be reached */
 217     return -1;
 218 }
 219
 220 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 221                          const char *name, int devfn_min)
 222 {
 223     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 224     assert(PCI_FUNC(devfn_min) == 0);
 225     bus->devfn_min = devfn_min;
 226
 227     /* host bridge */
 228     QLIST_INIT(&bus->child);
 229     pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
 230
 231     vmstate_register(NULL, -1, &vmstate_pcibus, bus);
 232     qemu_register_reset(pci_bus_reset, bus);
 233 }
 234
 235 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 236 {
 237     PCIBus *bus;
 238
 239     bus = qemu_mallocz(sizeof(*bus));
 240     bus->qbus.qdev_allocated = 1;
 241     pci_bus_new_inplace(bus, parent, name, devfn_min);
 242     return bus;
 243 }
 244
 245 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 246                   void *irq_opaque, int nirq)
 247 {
 248     bus->set_irq = set_irq;
 249     bus->map_irq = map_irq;
 250     bus->irq_opaque = irq_opaque;
 251     bus->nirq = nirq;
 252     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 253 }
 254
 255 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
 256 {
 257     bus->qbus.allow_hotplug = 1;
 258     bus->hotplug = hotplug;
 259     bus->hotplug_qdev = qdev;
 260 }
 261
 262 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
 263 {
 264     bus->mem_base = base;
 265 }
 266
 267 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 268                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 269                          void *irq_opaque, int devfn_min, int nirq)
 270 {
 271     PCIBus *bus;
 272
 273     bus = pci_bus_new(parent, name, devfn_min);
 274     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 275     return bus;
 276 }
 277
 278 int pci_bus_num(PCIBus *s)
 279 {
 280     if (!s->parent_dev)
 281         return 0;       /* pci host bridge */
 282     return s->parent_dev->config[PCI_SECONDARY_BUS];
 283 }
 284
 285 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 286 {
 287     PCIDevice *s = container_of(pv, PCIDevice, config);
 288     uint8_t *config;
 289     int i;
 290
 291     assert(size == pci_config_size(s));
 292     config = qemu_malloc(size);
 293
 294     qemu_get_buffer(f, config, size);
 295     for (i = 0; i < size; ++i) {
 296         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
 297             qemu_free(config);
 298             return -EINVAL;
 299         }
 300     }
 301     memcpy(s->config, config, size);
 302
 303     pci_update_mappings(s);
 304
 305     qemu_free(config);
 306     return 0;
 307 }
 308
 309 /* just put buffer */
 310 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 311 {
 312     const uint8_t **v = pv;
 313     assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
 314     qemu_put_buffer(f, *v, size);
 315 }
 316
 317 static VMStateInfo vmstate_info_pci_config = {
 318     .name = "pci config",
 319     .get  = get_pci_config_device,
 320     .put  = put_pci_config_device,
 321 };
 322
 323 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 324 {
 325     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
 326     uint32_t irq_state[PCI_NUM_PINS];
 327     int i;
 328     for (i = 0; i < PCI_NUM_PINS; ++i) {
 329         irq_state[i] = qemu_get_be32(f);
 330         if (irq_state[i] != 0x1 && irq_state[i] != 0) {
 331             fprintf(stderr, "irq state %d: must be 0 or 1.\n",
 332                     irq_state[i]);
 333             return -EINVAL;
 334         }
 335     }
 336
 337     for (i = 0; i < PCI_NUM_PINS; ++i) {
 338         pci_set_irq_state(s, i, irq_state[i]);
 339     }
 340
 341     return 0;
 342 }
 343
 344 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 345 {
 346     int i;
 347     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
 348
 349     for (i = 0; i < PCI_NUM_PINS; ++i) {
 350         qemu_put_be32(f, pci_irq_state(s, i));
 351     }
 352 }
 353
 354 static VMStateInfo vmstate_info_pci_irq_state = {
 355     .name = "pci irq state",
 356     .get  = get_pci_irq_state,
 357     .put  = put_pci_irq_state,
 358 };
 359
 360 const VMStateDescription vmstate_pci_device = {
 361     .name = "PCIDevice",
 362     .version_id = 2,
 363     .minimum_version_id = 1,
 364     .minimum_version_id_old = 1,
 365     .fields      = (VMStateField []) {
 366         VMSTATE_INT32_LE(version_id, PCIDevice),
 367         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 368                                    vmstate_info_pci_config,
 369                                    PCI_CONFIG_SPACE_SIZE),
 370         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 371                                    vmstate_info_pci_irq_state,
 372                                    PCI_NUM_PINS * sizeof(int32_t)),
 373         VMSTATE_END_OF_LIST()
 374     }
 375 };
 376
 377 const VMStateDescription vmstate_pcie_device = {
 378     .name = "PCIDevice",
 379     .version_id = 2,
 380     .minimum_version_id = 1,
 381     .minimum_version_id_old = 1,
 382     .fields      = (VMStateField []) {
 383         VMSTATE_INT32_LE(version_id, PCIDevice),
 384         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 385                                    vmstate_info_pci_config,
 386                                    PCIE_CONFIG_SPACE_SIZE),
 387         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 388                                    vmstate_info_pci_irq_state,
 389                                    PCI_NUM_PINS * sizeof(int32_t)),
 390         VMSTATE_END_OF_LIST()
 391     }
 392 };
 393
 394 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
 395 {
 396     return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
 397 }
 398
 399 void pci_device_save(PCIDevice *s, QEMUFile *f)
 400 {
 401     /* Clear interrupt status bit: it is implicit
 402      * in irq_state which we are saving.
 403      * This makes us compatible with old devices
 404      * which never set or clear this bit. */
 405     s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 406     vmstate_save_state(f, pci_get_vmstate(s), s);
 407     /* Restore the interrupt status bit. */
 408     pci_update_irq_status(s);
 409 }
 410
 411 int pci_device_load(PCIDevice *s, QEMUFile *f)
 412 {
 413     int ret;
 414     ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
 415     /* Restore the interrupt status bit. */
 416     pci_update_irq_status(s);
 417     return ret;
 418 }
 419
 420 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
 421 {
 422     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
 423                  pci_default_sub_vendor_id);
 424     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
 425                  pci_default_sub_device_id);
 426 }
 427
 428 /*
 429  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
 430  *       [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
 431  */
 432 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 433                       unsigned int *slotp, unsigned int *funcp)
 434 {
 435     const char *p;
 436     char *e;
 437     unsigned long val;
 438     unsigned long dom = 0, bus = 0;
 439     unsigned int slot = 0;
 440     unsigned int func = 0;
 441
 442     p = addr;
 443     val = strtoul(p, &e, 16);
 444     if (e == p)
 445         return -1;
 446     if (*e == ':') {
 447         bus = val;
 448         p = e + 1;
 449         val = strtoul(p, &e, 16);
 450         if (e == p)
 451             return -1;
 452         if (*e == ':') {
 453             dom = bus;
 454             bus = val;
 455             p = e + 1;
 456             val = strtoul(p, &e, 16);
 457             if (e == p)
 458                 return -1;
 459         }
 460     }
 461
 462     slot = val;
 463
 464     if (funcp != NULL) {
 465         if (*e != '.')
 466             return -1;
 467
 468         p = e + 1;
 469         val = strtoul(p, &e, 16);
 470         if (e == p)
 471             return -1;
 472
 473         func = val;
 474     }
 475
 476     /* if funcp == NULL func is 0 */
 477     if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
 478         return -1;
 479
 480     if (*e)
 481         return -1;
 482
 483     /* Note: QEMU doesn't implement domains other than 0 */
 484     if (!pci_find_bus(pci_find_root_bus(dom), bus))
 485         return -1;
 486
 487     *domp = dom;
 488     *busp = bus;
 489     *slotp = slot;
 490     if (funcp != NULL)
 491         *funcp = func;
 492     return 0;
 493 }
 494
 495 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 496                      unsigned *slotp)
 497 {
 498     /* strip legacy tag */
 499     if (!strncmp(addr, "pci_addr=", 9)) {
 500         addr += 9;
 501     }
 502     if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
 503         monitor_printf(mon, "Invalid pci address\n");
 504         return -1;
 505     }
 506     return 0;
 507 }
 508
 509 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 510 {
 511     int dom, bus;
 512     unsigned slot;
 513
 514     if (!devaddr) {
 515         *devfnp = -1;
 516         return pci_find_bus(pci_find_root_bus(0), 0);
 517     }
 518
 519     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
 520         return NULL;
 521     }
 522
 523     *devfnp = slot << 3;
 524     return pci_find_bus(pci_find_root_bus(dom), bus);
 525 }
 526
 527 static void pci_init_cmask(PCIDevice *dev)
 528 {
 529     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 530     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 531     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 532     dev->cmask[PCI_REVISION_ID] = 0xff;
 533     dev->cmask[PCI_CLASS_PROG] = 0xff;
 534     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 535     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 536     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 537 }
 538
 539 static void pci_init_wmask(PCIDevice *dev)
 540 {
 541     int config_size = pci_config_size(dev);
 542
 543     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 544     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 545     pci_set_word(dev->wmask + PCI_COMMAND,
 546                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 547                  PCI_COMMAND_INTX_DISABLE);
 548
 549     memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
 550            config_size - PCI_CONFIG_HEADER_SIZE);
 551 }
 552
 553 static void pci_init_wmask_bridge(PCIDevice *d)
 554 {
 555     /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
 556        PCI_SEC_LETENCY_TIMER */
 557     memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
 558
 559     /* base and limit */
 560     d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
 561     d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
 562     pci_set_word(d->wmask + PCI_MEMORY_BASE,
 563                  PCI_MEMORY_RANGE_MASK & 0xffff);
 564     pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
 565                  PCI_MEMORY_RANGE_MASK & 0xffff);
 566     pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
 567                  PCI_PREF_RANGE_MASK & 0xffff);
 568     pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
 569                  PCI_PREF_RANGE_MASK & 0xffff);
 570
 571     /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
 572     memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
 573
 574     pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
 575 }
 576
 577 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
 578 {
 579     uint8_t slot = PCI_SLOT(dev->devfn);
 580     uint8_t func;
 581
 582     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
 583         dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
 584     }
 585
 586     /*
 587      * multifuction bit is interpreted in two ways as follows.
 588      *   - all functions must set the bit to 1.
 589      *     Example: Intel X53
 590      *   - function 0 must set the bit, but the rest function (> 0)
 591      *     is allowed to leave the bit to 0.
 592      *     Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
 593      *
 594      * So OS (at least Linux) checks the bit of only function 0,
 595      * and doesn't see the bit of function > 0.
 596      *
 597      * The below check allows both interpretation.
 598      */
 599     if (PCI_FUNC(dev->devfn)) {
 600         PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
 601         if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
 602             /* function 0 should set multifunction bit */
 603             error_report("PCI: single function device can't be populated "
 604                          "in function %x.%x", slot, PCI_FUNC(dev->devfn));
 605             return -1;
 606         }
 607         return 0;
 608     }
 609
 610     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
 611         return 0;
 612     }
 613     /* function 0 indicates single function, so function > 0 must be NULL */
 614     for (func = 1; func < PCI_FUNC_MAX; ++func) {
 615         if (bus->devices[PCI_DEVFN(slot, func)]) {
 616             error_report("PCI: %x.0 indicates single function, "
 617                          "but %x.%x is already populated.",
 618                          slot, slot, func);
 619             return -1;
 620         }
 621     }
 622     return 0;
 623 }
 624
 625 static void pci_config_alloc(PCIDevice *pci_dev)
 626 {
 627     int config_size = pci_config_size(pci_dev);
 628
 629     pci_dev->config = qemu_mallocz(config_size);
 630     pci_dev->cmask = qemu_mallocz(config_size);
 631     pci_dev->wmask = qemu_mallocz(config_size);
 632     pci_dev->w1cmask = qemu_mallocz(config_size);
 633     pci_dev->used = qemu_mallocz(config_size);
 634 }
 635
 636 static void pci_config_free(PCIDevice *pci_dev)
 637 {
 638     qemu_free(pci_dev->config);
 639     qemu_free(pci_dev->cmask);
 640     qemu_free(pci_dev->wmask);
 641     qemu_free(pci_dev->w1cmask);
 642     qemu_free(pci_dev->used);
 643 }
 644
 645 /* -1 for devfn means auto assign */
 646 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 647                                          const char *name, int devfn,
 648                                          PCIConfigReadFunc *config_read,
 649                                          PCIConfigWriteFunc *config_write,
 650                                          bool is_bridge)
 651 {
 652     if (devfn < 0) {
 653         for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
 654             devfn += PCI_FUNC_MAX) {
 655             if (!bus->devices[devfn])
 656                 goto found;
 657         }
 658         error_report("PCI: no slot/function available for %s, all in use", name);
 659         return NULL;
 660     found: ;
 661     } else if (bus->devices[devfn]) {
 662         error_report("PCI: slot %d function %d not available for %s, in use by %s",
 663                      PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
 664         return NULL;
 665     }
 666     pci_dev->bus = bus;
 667     pci_dev->devfn = devfn;
 668     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 669     pci_dev->irq_state = 0;
 670     pci_config_alloc(pci_dev);
 671
 672     if (!is_bridge) {
 673         pci_set_default_subsystem_id(pci_dev);
 674     }
 675     pci_init_cmask(pci_dev);
 676     pci_init_wmask(pci_dev);
 677     if (is_bridge) {
 678         pci_init_wmask_bridge(pci_dev);
 679     }
 680     if (pci_init_multifunction(bus, pci_dev)) {
 681         pci_config_free(pci_dev);
 682         return NULL;
 683     }
 684
 685     if (!config_read)
 686         config_read = pci_default_read_config;
 687     if (!config_write)
 688         config_write = pci_default_write_config;
 689     pci_dev->config_read = config_read;
 690     pci_dev->config_write = config_write;
 691     bus->devices[devfn] = pci_dev;
 692     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
 693     pci_dev->version_id = 2; /* Current pci device vmstate version */
 694     return pci_dev;
 695 }
 696
 697 static void do_pci_unregister_device(PCIDevice *pci_dev)
 698 {
 699     qemu_free_irqs(pci_dev->irq);
 700     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 701     pci_config_free(pci_dev);
 702 }
 703
 704 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 705                                int instance_size, int devfn,
 706                                PCIConfigReadFunc *config_read,
 707                                PCIConfigWriteFunc *config_write)
 708 {
 709     PCIDevice *pci_dev;
 710
 711     pci_dev = qemu_mallocz(instance_size);
 712     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 713                                      config_read, config_write,
 714                                      PCI_HEADER_TYPE_NORMAL);
 715     if (pci_dev == NULL) {
 716         hw_error("PCI: can't register device\n");
 717     }
 718     return pci_dev;
 719 }
 720
 721 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
 722                                           target_phys_addr_t addr)
 723 {
 724     return addr + bus->mem_base;
 725 }
 726
 727 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 728 {
 729     PCIIORegion *r;
 730     int i;
 731
 732     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 733         r = &pci_dev->io_regions[i];
 734         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
 735             continue;
 736         if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
 737             isa_unassign_ioport(r->addr, r->filtered_size);
 738         } else {
 739             cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
 740                                                          r->addr),
 741                                          r->filtered_size,
 742                                          IO_MEM_UNASSIGNED);
 743         }
 744     }
 745 }
 746
 747 static int pci_unregister_device(DeviceState *dev)
 748 {
 749     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 750     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 751     int ret = 0;
 752
 753     if (info->exit)
 754         ret = info->exit(pci_dev);
 755     if (ret)
 756         return ret;
 757
 758     pci_unregister_io_regions(pci_dev);
 759     pci_del_option_rom(pci_dev);
 760     do_pci_unregister_device(pci_dev);
 761     return 0;
 762 }
 763
 764 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 765                             pcibus_t size, uint8_t type,
 766                             PCIMapIORegionFunc *map_func)
 767 {
 768     PCIIORegion *r;
 769     uint32_t addr;
 770     uint64_t wmask;
 771
 772     assert(region_num >= 0);
 773     assert(region_num < PCI_NUM_REGIONS);
 774     if (size & (size-1)) {
 775         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 776                     "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
 777         exit(1);
 778     }
 779
 780     r = &pci_dev->io_regions[region_num];
 781     r->addr = PCI_BAR_UNMAPPED;
 782     r->size = size;
 783     r->filtered_size = size;
 784     r->type = type;
 785     r->map_func = map_func;
 786
 787     wmask = ~(size - 1);
 788     addr = pci_bar(pci_dev, region_num);
 789     if (region_num == PCI_ROM_SLOT) {
 790         /* ROM enable bit is writeable */
 791         wmask |= PCI_ROM_ADDRESS_ENABLE;
 792     }
 793     pci_set_long(pci_dev->config + addr, type);
 794     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 795         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 796         pci_set_quad(pci_dev->wmask + addr, wmask);
 797         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
 798     } else {
 799         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
 800         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
 801     }
 802 }
 803
 804 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
 805                               uint8_t type)
 806 {
 807     pcibus_t base = *addr;
 808     pcibus_t limit = *addr + *size - 1;
 809     PCIDevice *br;
 810
 811     for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
 812         uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 813
 814         if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 815             if (!(cmd & PCI_COMMAND_IO)) {
 816                 goto no_map;
 817             }
 818         } else {
 819             if (!(cmd & PCI_COMMAND_MEMORY)) {
 820                 goto no_map;
 821             }
 822         }
 823
 824         base = MAX(base, pci_bridge_get_base(br, type));
 825         limit = MIN(limit, pci_bridge_get_limit(br, type));
 826     }
 827
 828     if (base > limit) {
 829         goto no_map;
 830     }
 831     *addr = base;
 832     *size = limit - base + 1;
 833     return;
 834 no_map:
 835     *addr = PCI_BAR_UNMAPPED;
 836     *size = 0;
 837 }
 838
 839 static pcibus_t pci_bar_address(PCIDevice *d,
 840                                 int reg, uint8_t type, pcibus_t size)
 841 {
 842     pcibus_t new_addr, last_addr;
 843     int bar = pci_bar(d, reg);
 844     uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 845
 846     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 847         if (!(cmd & PCI_COMMAND_IO)) {
 848             return PCI_BAR_UNMAPPED;
 849         }
 850         new_addr = pci_get_long(d->config + bar) & ~(size - 1);
 851         last_addr = new_addr + size - 1;
 852         /* NOTE: we have only 64K ioports on PC */
 853         if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
 854             return PCI_BAR_UNMAPPED;
 855         }
 856         return new_addr;
 857     }
 858
 859     if (!(cmd & PCI_COMMAND_MEMORY)) {
 860         return PCI_BAR_UNMAPPED;
 861     }
 862     if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 863         new_addr = pci_get_quad(d->config + bar);
 864     } else {
 865         new_addr = pci_get_long(d->config + bar);
 866     }
 867     /* the ROM slot has a specific enable bit */
 868     if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
 869         return PCI_BAR_UNMAPPED;
 870     }
 871     new_addr &= ~(size - 1);
 872     last_addr = new_addr + size - 1;
 873     /* NOTE: we do not support wrapping */
 874     /* XXX: as we cannot support really dynamic
 875        mappings, we handle specific values as invalid
 876        mappings. */
 877     if (last_addr <= new_addr || new_addr == 0 ||
 878         last_addr == PCI_BAR_UNMAPPED) {
 879         return PCI_BAR_UNMAPPED;
 880     }
 881
 882     /* Now pcibus_t is 64bit.
 883      * Check if 32 bit BAR wraps around explicitly.
 884      * Without this, PC ide doesn't work well.
 885      * TODO: remove this work around.
 886      */
 887     if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
 888         return PCI_BAR_UNMAPPED;
 889     }
 890
 891     /*
 892      * OS is allowed to set BAR beyond its addressable
 893      * bits. For example, 32 bit OS can set 64bit bar
 894      * to >4G. Check it. TODO: we might need to support
 895      * it in the future for e.g. PAE.
 896      */
 897     if (last_addr >= TARGET_PHYS_ADDR_MAX) {
 898         return PCI_BAR_UNMAPPED;
 899     }
 900
 901     return new_addr;
 902 }
 903
 904 static void pci_update_mappings(PCIDevice *d)
 905 {
 906     PCIIORegion *r;
 907     int i;
 908     pcibus_t new_addr, filtered_size;
 909
 910     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 911         r = &d->io_regions[i];
 912
 913         /* this region isn't registered */
 914         if (!r->size)
 915             continue;
 916
 917         new_addr = pci_bar_address(d, i, r->type, r->size);
 918
 919         /* bridge filtering */
 920         filtered_size = r->size;
 921         if (new_addr != PCI_BAR_UNMAPPED) {
 922             pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
 923         }
 924
 925         /* This bar isn't changed */
 926         if (new_addr == r->addr && filtered_size == r->filtered_size)
 927             continue;
 928
 929         /* now do the real mapping */
 930         if (r->addr != PCI_BAR_UNMAPPED) {
 931             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 932                 int class;
 933                 /* NOTE: specific hack for IDE in PC case:
 934                    only one byte must be mapped. */
 935                 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 936                 if (class == 0x0101 && r->size == 4) {
 937                     isa_unassign_ioport(r->addr + 2, 1);
 938                 } else {
 939                     isa_unassign_ioport(r->addr, r->filtered_size);
 940                 }
 941             } else {
 942                 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
 943                                              r->filtered_size,
 944                                              IO_MEM_UNASSIGNED);
 945                 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
 946             }
 947         }
 948         r->addr = new_addr;
 949         r->filtered_size = filtered_size;
 950         if (r->addr != PCI_BAR_UNMAPPED) {
 951             /*
 952              * TODO: currently almost all the map funcions assumes
 953              * filtered_size == size and addr & ~(size - 1) == addr.
 954              * However with bridge filtering, they aren't always true.
 955              * Teach them such cases, such that filtered_size < size and
 956              * addr & (size - 1) != 0.
 957              */
 958             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 959                 r->map_func(d, i, r->addr, r->filtered_size, r->type);
 960             } else {
 961                 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
 962                             r->filtered_size, r->type);
 963             }
 964         }
 965     }
 966 }
 967
 968 static inline int pci_irq_disabled(PCIDevice *d)
 969 {
 970     return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
 971 }
 972
 973 /* Called after interrupt disabled field update in config space,
 974  * assert/deassert interrupts if necessary.
 975  * Gets original interrupt disable bit value (before update). */
 976 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
 977 {
 978     int i, disabled = pci_irq_disabled(d);
 979     if (disabled == was_irq_disabled)
 980         return;
 981     for (i = 0; i < PCI_NUM_PINS; ++i) {
 982         int state = pci_irq_state(d, i);
 983         pci_change_irq_level(d, i, disabled ? -state : state);
 984     }
 985 }
 986
 987 uint32_t pci_default_read_config(PCIDevice *d,
 988                                  uint32_t address, int len)
 989 {
 990     uint32_t val = 0;
 991     assert(len == 1 || len == 2 || len == 4);
 992     len = MIN(len, pci_config_size(d) - address);
 993     memcpy(&val, d->config + address, len);
 994     return le32_to_cpu(val);
 995 }
 996
 997 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 998 {
 999     int i, was_irq_disabled = pci_irq_disabled(d);
1000     uint32_t config_size = pci_config_size(d);
1001
1002     for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1003         uint8_t wmask = d->wmask[addr + i];
1004         uint8_t w1cmask = d->w1cmask[addr + i];
1005         assert(!(wmask & w1cmask));
1006         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1007         d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1008     }
1009     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1010         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1011         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1012         range_covers_byte(addr, l, PCI_COMMAND))
1013         pci_update_mappings(d);
1014
1015     if (range_covers_byte(addr, l, PCI_COMMAND))
1016         pci_update_irq_disabled(d, was_irq_disabled);
1017 }
1018
1019 /***********************************************************/
1020 /* generic PCI irq support */
1021
1022 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1023 static void pci_set_irq(void *opaque, int irq_num, int level)
1024 {
1025     PCIDevice *pci_dev = opaque;
1026     int change;
1027
1028     change = level - pci_irq_state(pci_dev, irq_num);
1029     if (!change)
1030         return;
1031
1032     pci_set_irq_state(pci_dev, irq_num, level);
1033     pci_update_irq_status(pci_dev);
1034     if (pci_irq_disabled(pci_dev))
1035         return;
1036     pci_change_irq_level(pci_dev, irq_num, change);
1037 }
1038
1039 bool pci_msi_enabled(PCIDevice *dev)
1040 {
1041     return msix_enabled(dev) || msi_enabled(dev);
1042 }
1043
1044 void pci_msi_notify(PCIDevice *dev, unsigned int vector)
1045 {
1046     if (msix_enabled(dev)) {
1047         msix_notify(dev, vector);
1048     } else if (msi_enabled(dev)) {
1049         msi_notify(dev, vector);
1050     } else {
1051         /* MSI/MSI-X must be enabled */
1052         abort();
1053     }
1054 }
1055
1056 /***********************************************************/
1057 /* monitor info on PCI */
1058
1059 typedef struct {
1060     uint16_t class;
1061     const char *desc;
1062 } pci_class_desc;
1063
1064 static const pci_class_desc pci_class_descriptions[] =
1065 {
1066     { 0x0100, "SCSI controller"},
1067     { 0x0101, "IDE controller"},
1068     { 0x0102, "Floppy controller"},
1069     { 0x0103, "IPI controller"},
1070     { 0x0104, "RAID controller"},
1071     { 0x0106, "SATA controller"},
1072     { 0x0107, "SAS controller"},
1073     { 0x0180, "Storage controller"},
1074     { 0x0200, "Ethernet controller"},
1075     { 0x0201, "Token Ring controller"},
1076     { 0x0202, "FDDI controller"},
1077     { 0x0203, "ATM controller"},
1078     { 0x0280, "Network controller"},
1079     { 0x0300, "VGA controller"},
1080     { 0x0301, "XGA controller"},
1081     { 0x0302, "3D controller"},
1082     { 0x0380, "Display controller"},
1083     { 0x0400, "Video controller"},
1084     { 0x0401, "Audio controller"},
1085     { 0x0402, "Phone"},
1086     { 0x0480, "Multimedia controller"},
1087     { 0x0500, "RAM controller"},
1088     { 0x0501, "Flash controller"},
1089     { 0x0580, "Memory controller"},
1090     { 0x0600, "Host bridge"},
1091     { 0x0601, "ISA bridge"},
1092     { 0x0602, "EISA bridge"},
1093     { 0x0603, "MC bridge"},
1094     { 0x0604, "PCI bridge"},
1095     { 0x0605, "PCMCIA bridge"},
1096     { 0x0606, "NUBUS bridge"},
1097     { 0x0607, "CARDBUS bridge"},
1098     { 0x0608, "RACEWAY bridge"},
1099     { 0x0680, "Bridge"},
1100     { 0x0c03, "USB controller"},
1101     { 0, NULL}
1102 };
1103
1104 static void pci_for_each_device_under_bus(PCIBus *bus,
1105                                           void (*fn)(PCIBus *b, PCIDevice *d))
1106 {
1107     PCIDevice *d;
1108     int devfn;
1109
1110     for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1111         d = bus->devices[devfn];
1112         if (d) {
1113             fn(bus, d);
1114         }
1115     }
1116 }
1117
1118 void pci_for_each_device(PCIBus *bus, int bus_num,
1119                          void (*fn)(PCIBus *b, PCIDevice *d))
1120 {
1121     bus = pci_find_bus(bus, bus_num);
1122
1123     if (bus) {
1124         pci_for_each_device_under_bus(bus, fn);
1125     }
1126 }
1127
1128 static void pci_device_print(Monitor *mon, QDict *device)
1129 {
1130     QDict *qdict;
1131     QListEntry *entry;
1132     uint64_t addr, size;
1133
1134     monitor_printf(mon, "  Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1135     monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1136                         qdict_get_int(device, "slot"),
1137                         qdict_get_int(device, "function"));
1138     monitor_printf(mon, "    ");
1139
1140     qdict = qdict_get_qdict(device, "class_info");
1141     if (qdict_haskey(qdict, "desc")) {
1142         monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1143     } else {
1144         monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1145     }
1146
1147     qdict = qdict_get_qdict(device, "id");
1148     monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1149                         qdict_get_int(qdict, "device"),
1150                         qdict_get_int(qdict, "vendor"));
1151
1152     if (qdict_haskey(device, "irq")) {
1153         monitor_printf(mon, "      IRQ %" PRId64 ".\n",
1154                             qdict_get_int(device, "irq"));
1155     }
1156
1157     if (qdict_haskey(device, "pci_bridge")) {
1158         QDict *info;
1159
1160         qdict = qdict_get_qdict(device, "pci_bridge");
1161
1162         info = qdict_get_qdict(qdict, "bus");
1163         monitor_printf(mon, "      BUS %" PRId64 ".\n",
1164                             qdict_get_int(info, "number"));
1165         monitor_printf(mon, "      secondary bus %" PRId64 ".\n",
1166                             qdict_get_int(info, "secondary"));
1167         monitor_printf(mon, "      subordinate bus %" PRId64 ".\n",
1168                             qdict_get_int(info, "subordinate"));
1169
1170         info = qdict_get_qdict(qdict, "io_range");
1171         monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1172                        qdict_get_int(info, "base"),
1173                        qdict_get_int(info, "limit"));
1174
1175         info = qdict_get_qdict(qdict, "memory_range");
1176         monitor_printf(mon,
1177                        "      memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1178                        qdict_get_int(info, "base"),
1179                        qdict_get_int(info, "limit"));
1180
1181         info = qdict_get_qdict(qdict, "prefetchable_range");
1182         monitor_printf(mon, "      prefetchable memory range "
1183                        "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1184                        qdict_get_int(info, "base"),
1185         qdict_get_int(info, "limit"));
1186     }
1187
1188     QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1189         qdict = qobject_to_qdict(qlist_entry_obj(entry));
1190         monitor_printf(mon, "      BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1191
1192         addr = qdict_get_int(qdict, "address");
1193         size = qdict_get_int(qdict, "size");
1194
1195         if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1196             monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1197                                 " [0x%04"FMT_PCIBUS"].\n",
1198                                 addr, addr + size - 1);
1199         } else {
1200             monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1201                                " [0x%08"FMT_PCIBUS"].\n",
1202                                 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1203                                 qdict_get_bool(qdict, "prefetch") ?
1204                                 " prefetchable" : "", addr, addr + size - 1);
1205         }
1206     }
1207
1208     monitor_printf(mon, "      id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1209
1210     if (qdict_haskey(device, "pci_bridge")) {
1211         qdict = qdict_get_qdict(device, "pci_bridge");
1212         if (qdict_haskey(qdict, "devices")) {
1213             QListEntry *dev;
1214             QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1215                 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1216             }
1217         }
1218     }
1219 }
1220
1221 void do_pci_info_print(Monitor *mon, const QObject *data)
1222 {
1223     QListEntry *bus, *dev;
1224
1225     QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1226         QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1227         QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1228             pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1229         }
1230     }
1231 }
1232
1233 static QObject *pci_get_dev_class(const PCIDevice *dev)
1234 {
1235     int class;
1236     const pci_class_desc *desc;
1237
1238     class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1239     desc = pci_class_descriptions;
1240     while (desc->desc && class != desc->class)
1241         desc++;
1242
1243     if (desc->desc) {
1244         return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1245                                   desc->desc, class);
1246     } else {
1247         return qobject_from_jsonf("{ 'class': %d }", class);
1248     }
1249 }
1250
1251 static QObject *pci_get_dev_id(const PCIDevice *dev)
1252 {
1253     return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1254                               pci_get_word(dev->config + PCI_VENDOR_ID),
1255                               pci_get_word(dev->config + PCI_DEVICE_ID));
1256 }
1257
1258 static QObject *pci_get_regions_list(const PCIDevice *dev)
1259 {
1260     int i;
1261     QList *regions_list;
1262
1263     regions_list = qlist_new();
1264
1265     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1266         QObject *obj;
1267         const PCIIORegion *r = &dev->io_regions[i];
1268
1269         if (!r->size) {
1270             continue;
1271         }
1272
1273         if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1274             obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1275                                      "'address': %" PRId64 ", "
1276                                      "'size': %" PRId64 " }",
1277                                      i, r->addr, r->size);
1278         } else {
1279             int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1280
1281             obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1282                                      "'mem_type_64': %i, 'prefetch': %i, "
1283                                      "'address': %" PRId64 ", "
1284                                      "'size': %" PRId64 " }",
1285                                      i, mem_type_64,
1286                                      r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1287                                      r->addr, r->size);
1288         }
1289
1290         qlist_append_obj(regions_list, obj);
1291     }
1292
1293     return QOBJECT(regions_list);
1294 }
1295
1296 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1297
1298 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1299 {
1300     uint8_t type;
1301     QObject *obj;
1302
1303     obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d,"                                       "'class_info': %p, 'id': %p, 'regions': %p,"
1304                               " 'qdev_id': %s }",
1305                               bus_num,
1306                               PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1307                               pci_get_dev_class(dev), pci_get_dev_id(dev),
1308                               pci_get_regions_list(dev),
1309                               dev->qdev.id ? dev->qdev.id : "");
1310
1311     if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1312         QDict *qdict = qobject_to_qdict(obj);
1313         qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1314     }
1315
1316     type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1317     if (type == PCI_HEADER_TYPE_BRIDGE) {
1318         QDict *qdict;
1319         QObject *pci_bridge;
1320
1321         pci_bridge = qobject_from_jsonf("{ 'bus': "
1322         "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1323         "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1324         "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1325         "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1326         dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1327         dev->config[PCI_SUBORDINATE_BUS],
1328         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1329         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1330         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1331         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1332         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1333                                PCI_BASE_ADDRESS_MEM_PREFETCH),
1334         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1335                                 PCI_BASE_ADDRESS_MEM_PREFETCH));
1336
1337         if (dev->config[PCI_SECONDARY_BUS] != 0) {
1338             PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1339
1340             if (child_bus) {
1341                 qdict = qobject_to_qdict(pci_bridge);
1342                 qdict_put_obj(qdict, "devices",
1343                               pci_get_devices_list(child_bus,
1344                                                    dev->config[PCI_SECONDARY_BUS]));
1345             }
1346         }
1347         qdict = qobject_to_qdict(obj);
1348         qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1349     }
1350
1351     return obj;
1352 }
1353
1354 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1355 {
1356     int devfn;
1357     PCIDevice *dev;
1358     QList *dev_list;
1359
1360     dev_list = qlist_new();
1361
1362     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1363         dev = bus->devices[devfn];
1364         if (dev) {
1365             qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1366         }
1367     }
1368
1369     return QOBJECT(dev_list);
1370 }
1371
1372 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1373 {
1374     bus = pci_find_bus(bus, bus_num);
1375     if (bus) {
1376         return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1377                                   bus_num, pci_get_devices_list(bus, bus_num));
1378     }
1379
1380     return NULL;
1381 }
1382
1383 void do_pci_info(Monitor *mon, QObject **ret_data)
1384 {
1385     QList *bus_list;
1386     struct PCIHostBus *host;
1387
1388     bus_list = qlist_new();
1389
1390     QLIST_FOREACH(host, &host_buses, next) {
1391         QObject *obj = pci_get_bus_dict(host->bus, 0);
1392         if (obj) {
1393             qlist_append_obj(bus_list, obj);
1394         }
1395     }
1396
1397     *ret_data = QOBJECT(bus_list);
1398 }
1399
1400 static const char * const pci_nic_models[] = {
1401     "ne2k_pci",
1402     "i82551",
1403     "i82557b",
1404     "i82559er",
1405     "rtl8139",
1406     "e1000",
1407     "pcnet",
1408     "virtio",
1409     NULL
1410 };
1411
1412 static const char * const pci_nic_names[] = {
1413     "ne2k_pci",
1414     "i82551",
1415     "i82557b",
1416     "i82559er",
1417     "rtl8139",
1418     "e1000",
1419     "pcnet",
1420     "virtio-net-pci",
1421     NULL
1422 };
1423
1424 /* Initialize a PCI NIC.  */
1425 /* FIXME callers should check for failure, but don't */
1426 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1427                         const char *default_devaddr)
1428 {
1429     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1430     PCIBus *bus;
1431     int devfn;
1432     PCIDevice *pci_dev;
1433     DeviceState *dev;
1434     int i;
1435
1436     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1437     if (i < 0)
1438         return NULL;
1439
1440     bus = pci_get_bus_devfn(&devfn, devaddr);
1441     if (!bus) {
1442         error_report("Invalid PCI device address %s for device %s",
1443                      devaddr, pci_nic_names[i]);
1444         return NULL;
1445     }
1446
1447     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1448     dev = &pci_dev->qdev;
1449     qdev_set_nic_properties(dev, nd);
1450     if (qdev_init(dev) < 0)
1451         return NULL;
1452     return pci_dev;
1453 }
1454
1455 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1456                                const char *default_devaddr)
1457 {
1458     PCIDevice *res;
1459
1460     if (qemu_show_nic_models(nd->model, pci_nic_models))
1461         exit(0);
1462
1463     res = pci_nic_init(nd, default_model, default_devaddr);
1464     if (!res)
1465         exit(1);
1466     return res;
1467 }
1468
1469 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1470 {
1471     pci_update_mappings(d);
1472 }
1473
1474 void pci_bridge_update_mappings(PCIBus *b)
1475 {
1476     PCIBus *child;
1477
1478     pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1479
1480     QLIST_FOREACH(child, &b->child, sibling) {
1481         pci_bridge_update_mappings(child);
1482     }
1483 }
1484
1485 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1486 {
1487     PCIBus *sec;
1488
1489     if (!bus) {
1490         return NULL;
1491     }
1492
1493     if (pci_bus_num(bus) == bus_num) {
1494         return bus;
1495     }
1496
1497     /* try child bus */
1498     if (!bus->parent_dev /* host pci bridge */ ||
1499         (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1500          bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1501         for (; bus; bus = sec) {
1502             QLIST_FOREACH(sec, &bus->child, sibling) {
1503                 assert(sec->parent_dev);
1504                 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1505                     return sec;
1506                 }
1507                 if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1508                     bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) {
1509                     break;
1510                 }
1511             }
1512         }
1513     }
1514
1515     return NULL;
1516 }
1517
1518 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1519 {
1520     bus = pci_find_bus(bus, bus_num);
1521
1522     if (!bus)
1523         return NULL;
1524
1525     return bus->devices[PCI_DEVFN(slot, function)];
1526 }
1527
1528 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1529 {
1530     PCIDevice *pci_dev = (PCIDevice *)qdev;
1531     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1532     PCIBus *bus;
1533     int devfn, rc;
1534
1535     /* initialize cap_present for pci_is_express() and pci_config_size() */
1536     if (info->is_express) {
1537         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1538     }
1539
1540     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1541     devfn = pci_dev->devfn;
1542     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1543                                      info->config_read, info->config_write,
1544                                      info->is_bridge);
1545     if (pci_dev == NULL)
1546         return -1;
1547     rc = info->init(pci_dev);
1548     if (rc != 0) {
1549         do_pci_unregister_device(pci_dev);
1550         return rc;
1551     }
1552
1553     /* rom loading */
1554     if (pci_dev->romfile == NULL && info->romfile != NULL)
1555         pci_dev->romfile = qemu_strdup(info->romfile);
1556     pci_add_option_rom(pci_dev);
1557
1558     if (bus->hotplug) {
1559         /* lower layer must check qdev->hotplugged */
1560         rc = bus->hotplug(bus->hotplug_qdev, pci_dev, 1);
1561         if (rc != 0) {
1562             int r = pci_unregister_device(&pci_dev->qdev);
1563             assert(!r);
1564             return rc;
1565         }
1566     }
1567     return 0;
1568 }
1569
1570 static int pci_unplug_device(DeviceState *qdev)
1571 {
1572     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1573
1574     return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0);
1575 }
1576
1577 void pci_qdev_register(PCIDeviceInfo *info)
1578 {
1579     info->qdev.init = pci_qdev_init;
1580     info->qdev.unplug = pci_unplug_device;
1581     info->qdev.exit = pci_unregister_device;
1582     info->qdev.bus_info = &pci_bus_info;
1583     qdev_register(&info->qdev);
1584 }
1585
1586 void pci_qdev_register_many(PCIDeviceInfo *info)
1587 {
1588     while (info->qdev.name) {
1589         pci_qdev_register(info);
1590         info++;
1591     }
1592 }
1593
1594 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1595                                     const char *name)
1596 {
1597     DeviceState *dev;
1598
1599     dev = qdev_create(&bus->qbus, name);
1600     qdev_prop_set_uint32(dev, "addr", devfn);
1601     qdev_prop_set_bit(dev, "multifunction", multifunction);
1602     return DO_UPCAST(PCIDevice, qdev, dev);
1603 }
1604
1605 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1606                                            bool multifunction,
1607                                            const char *name)
1608 {
1609     PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1610     qdev_init_nofail(&dev->qdev);
1611     return dev;
1612 }
1613
1614 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1615 {
1616     return pci_create_multifunction(bus, devfn, false, name);
1617 }
1618
1619 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1620 {
1621     return pci_create_simple_multifunction(bus, devfn, false, name);
1622 }
1623
1624 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1625 {
1626     int config_size = pci_config_size(pdev);
1627     int offset = PCI_CONFIG_HEADER_SIZE;
1628     int i;
1629     for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1630         if (pdev->used[i])
1631             offset = i + 1;
1632         else if (i - offset + 1 == size)
1633             return offset;
1634     return 0;
1635 }
1636
1637 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1638                                         uint8_t *prev_p)
1639 {
1640     uint8_t next, prev;
1641
1642     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1643         return 0;
1644
1645     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1646          prev = next + PCI_CAP_LIST_NEXT)
1647         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1648             break;
1649
1650     if (prev_p)
1651         *prev_p = prev;
1652     return next;
1653 }
1654
1655 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1656 {
1657     cpu_register_physical_memory(addr, size, pdev->rom_offset);
1658 }
1659
1660 /* Add an option rom for the device */
1661 static int pci_add_option_rom(PCIDevice *pdev)
1662 {
1663     int size;
1664     char *path;
1665     void *ptr;
1666     char name[32];
1667
1668     if (!pdev->romfile)
1669         return 0;
1670     if (strlen(pdev->romfile) == 0)
1671         return 0;
1672
1673     if (!pdev->rom_bar) {
1674         /*
1675          * Load rom via fw_cfg instead of creating a rom bar,
1676          * for 0.11 compatibility.
1677          */
1678         int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1679         if (class == 0x0300) {
1680             rom_add_vga(pdev->romfile);
1681         } else {
1682             rom_add_option(pdev->romfile);
1683         }
1684         return 0;
1685     }
1686
1687     path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1688     if (path == NULL) {
1689         path = qemu_strdup(pdev->romfile);
1690     }
1691
1692     size = get_image_size(path);
1693     if (size < 0) {
1694         error_report("%s: failed to find romfile \"%s\"",
1695                      __FUNCTION__, pdev->romfile);
1696         return -1;
1697     }
1698     if (size & (size - 1)) {
1699         size = 1 << qemu_fls(size);
1700     }
1701
1702     if (pdev->qdev.info->vmsd)
1703         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1704     else
1705         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1706     pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1707
1708     ptr = qemu_get_ram_ptr(pdev->rom_offset);
1709     load_image(path, ptr);
1710     qemu_free(path);
1711
1712     pci_register_bar(pdev, PCI_ROM_SLOT, size,
1713                      0, pci_map_option_rom);
1714
1715     return 0;
1716 }
1717
1718 static void pci_del_option_rom(PCIDevice *pdev)
1719 {
1720     if (!pdev->rom_offset)
1721         return;
1722
1723     qemu_ram_free(pdev->rom_offset);
1724     pdev->rom_offset = 0;
1725 }
1726
1727 /*
1728  * if !offset
1729  * Reserve space and add capability to the linked list in pci config space
1730  *
1731  * if offset = 0,
1732  * Find and reserve space and add capability to the linked list
1733  * in pci config space */
1734 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1735                        uint8_t offset, uint8_t size)
1736 {
1737     uint8_t *config;
1738     if (!offset) {
1739         offset = pci_find_space(pdev, size);
1740         if (!offset) {
1741             return -ENOSPC;
1742         }
1743     }
1744
1745     config = pdev->config + offset;
1746     config[PCI_CAP_LIST_ID] = cap_id;
1747     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1748     pdev->config[PCI_CAPABILITY_LIST] = offset;
1749     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1750     memset(pdev->used + offset, 0xFF, size);
1751     /* Make capability read-only by default */
1752     memset(pdev->wmask + offset, 0, size);
1753     /* Check capability by default */
1754     memset(pdev->cmask + offset, 0xFF, size);
1755     return offset;
1756 }
1757
1758 /* Unlink capability from the pci config space. */
1759 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1760 {
1761     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1762     if (!offset)
1763         return;
1764     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1765     /* Make capability writeable again */
1766     memset(pdev->wmask + offset, 0xff, size);
1767     memset(pdev->w1cmask + offset, 0, size);
1768     /* Clear cmask as device-specific registers can't be checked */
1769     memset(pdev->cmask + offset, 0, size);
1770     memset(pdev->used + offset, 0, size);
1771
1772     if (!pdev->config[PCI_CAPABILITY_LIST])
1773         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1774 }
1775
1776 /* Reserve space for capability at a known offset (to call after load). */
1777 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1778 {
1779     memset(pdev->used + offset, 0xff, size);
1780 }
1781
1782 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1783 {
1784     return pci_find_capability_list(pdev, cap_id, NULL);
1785 }
1786
1787 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1788 {
1789     PCIDevice *d = (PCIDevice *)dev;
1790     const pci_class_desc *desc;
1791     char ctxt[64];
1792     PCIIORegion *r;
1793     int i, class;
1794
1795     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1796     desc = pci_class_descriptions;
1797     while (desc->desc && class != desc->class)
1798         desc++;
1799     if (desc->desc) {
1800         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1801     } else {
1802         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1803     }
1804
1805     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1806                    "pci id %04x:%04x (sub %04x:%04x)\n",
1807                    indent, "", ctxt,
1808                    d->config[PCI_SECONDARY_BUS],
1809                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1810                    pci_get_word(d->config + PCI_VENDOR_ID),
1811                    pci_get_word(d->config + PCI_DEVICE_ID),
1812                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1813                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1814     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1815         r = &d->io_regions[i];
1816         if (!r->size)
1817             continue;
1818         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1819                        " [0x%"FMT_PCIBUS"]\n",
1820                        indent, "",
1821                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1822                        r->addr, r->addr + r->size - 1);
1823     }
1824 }
1825
1826 static char *pcibus_get_dev_path(DeviceState *dev)
1827 {
1828     PCIDevice *d = (PCIDevice *)dev;
1829     char path[16];
1830
1831     snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
1832              pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
1833              PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1834
1835     return strdup(path);
1836 }
1837