2 * QEMU PowerPC e500-based platforms
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Yu Liu, <yu.liu@freescale.com>
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
18 #include "qemu-common.h"
20 #include "e500-ccsr.h"
23 #include "hw/serial.h"
24 #include "hw/pci/pci.h"
25 #include "hw/boards.h"
29 #include "device_tree.h"
30 #include "hw/openpic.h"
32 #include "hw/loader.h"
34 #include "hw/sysbus.h"
35 #include "exec-memory.h"
36 #include "host-utils.h"
37 #include "hw/ppce500_pci.h"
39 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
40 #define UIMAGE_LOAD_BASE 0
41 #define DTC_LOAD_PAD 0x1800000
42 #define DTC_PAD_MASK 0xFFFFF
43 #define INITRD_LOAD_PAD 0x2000000
44 #define INITRD_PAD_MASK 0xFFFFFF
46 #define RAM_SIZES_ALIGN (64UL << 20)
48 /* TODO: parameterize */
49 #define MPC8544_CCSRBAR_BASE 0xE0000000ULL
50 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL
51 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
52 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL
53 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
54 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
55 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL
56 #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \
57 MPC8544_PCI_REGS_OFFSET)
58 #define MPC8544_PCI_REGS_SIZE 0x1000ULL
59 #define MPC8544_PCI_IO 0xE1000000ULL
60 #define MPC8544_UTIL_OFFSET 0xe0000ULL
61 #define MPC8544_SPIN_BASE 0xEF000000ULL
70 static uint32_t *pci_map_create(void *fdt
, uint32_t mpic
, int first_slot
,
71 int nr_slots
, int *len
)
77 int last_slot
= first_slot
+ nr_slots
;
80 *len
= nr_slots
* 4 * 7 * sizeof(uint32_t);
81 pci_map
= g_malloc(*len
);
83 for (slot
= first_slot
; slot
< last_slot
; slot
++) {
84 for (pci_irq
= 0; pci_irq
< 4; pci_irq
++) {
85 pci_map
[i
++] = cpu_to_be32(slot
<< 11);
86 pci_map
[i
++] = cpu_to_be32(0x0);
87 pci_map
[i
++] = cpu_to_be32(0x0);
88 pci_map
[i
++] = cpu_to_be32(pci_irq
+ 1);
89 pci_map
[i
++] = cpu_to_be32(mpic
);
90 host_irq
= ppce500_pci_map_irq_slot(slot
, pci_irq
);
91 pci_map
[i
++] = cpu_to_be32(host_irq
+ 1);
92 pci_map
[i
++] = cpu_to_be32(0x1);
96 assert((i
* sizeof(uint32_t)) == *len
);
101 static void dt_serial_create(void *fdt
, unsigned long long offset
,
102 const char *soc
, const char *mpic
,
103 const char *alias
, int idx
, bool defcon
)
107 snprintf(ser
, sizeof(ser
), "%s/serial@%llx", soc
, offset
);
108 qemu_devtree_add_subnode(fdt
, ser
);
109 qemu_devtree_setprop_string(fdt
, ser
, "device_type", "serial");
110 qemu_devtree_setprop_string(fdt
, ser
, "compatible", "ns16550");
111 qemu_devtree_setprop_cells(fdt
, ser
, "reg", offset
, 0x100);
112 qemu_devtree_setprop_cell(fdt
, ser
, "cell-index", idx
);
113 qemu_devtree_setprop_cell(fdt
, ser
, "clock-frequency", 0);
114 qemu_devtree_setprop_cells(fdt
, ser
, "interrupts", 42, 2);
115 qemu_devtree_setprop_phandle(fdt
, ser
, "interrupt-parent", mpic
);
116 qemu_devtree_setprop_string(fdt
, "/aliases", alias
, ser
);
119 qemu_devtree_setprop_string(fdt
, "/chosen", "linux,stdout-path", ser
);
123 static int ppce500_load_device_tree(CPUPPCState
*env
,
124 PPCE500Params
*params
,
130 uint64_t mem_reg_property
[] = { 0, cpu_to_be64(params
->ram_size
) };
133 uint8_t hypercall
[16];
134 uint32_t clock_freq
= 400000000;
135 uint32_t tb_freq
= 400000000;
137 const char *toplevel_compat
= NULL
; /* user override */
138 char compatible_sb
[] = "fsl,mpc8544-immr\0simple-bus";
146 uint32_t *pci_map
= NULL
;
148 uint32_t pci_ranges
[14] =
150 0x2000000, 0x0, 0xc0000000,
158 QemuOpts
*machine_opts
;
159 const char *dtb_file
= NULL
;
161 machine_opts
= qemu_opts_find(qemu_find_opts("machine"), 0);
163 dtb_file
= qemu_opt_get(machine_opts
, "dtb");
164 toplevel_compat
= qemu_opt_get(machine_opts
, "dt_compatible");
169 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, dtb_file
);
174 fdt
= load_device_tree(filename
, &fdt_size
);
181 fdt
= create_device_tree(&fdt_size
);
186 /* Manipulate device tree in memory. */
187 qemu_devtree_setprop_cell(fdt
, "/", "#address-cells", 2);
188 qemu_devtree_setprop_cell(fdt
, "/", "#size-cells", 2);
190 qemu_devtree_add_subnode(fdt
, "/memory");
191 qemu_devtree_setprop_string(fdt
, "/memory", "device_type", "memory");
192 qemu_devtree_setprop(fdt
, "/memory", "reg", mem_reg_property
,
193 sizeof(mem_reg_property
));
195 qemu_devtree_add_subnode(fdt
, "/chosen");
197 ret
= qemu_devtree_setprop_cell(fdt
, "/chosen", "linux,initrd-start",
200 fprintf(stderr
, "couldn't set /chosen/linux,initrd-start\n");
203 ret
= qemu_devtree_setprop_cell(fdt
, "/chosen", "linux,initrd-end",
204 (initrd_base
+ initrd_size
));
206 fprintf(stderr
, "couldn't set /chosen/linux,initrd-end\n");
210 ret
= qemu_devtree_setprop_string(fdt
, "/chosen", "bootargs",
211 params
->kernel_cmdline
);
213 fprintf(stderr
, "couldn't set /chosen/bootargs\n");
216 /* Read out host's frequencies */
217 clock_freq
= kvmppc_get_clockfreq();
218 tb_freq
= kvmppc_get_tbfreq();
220 /* indicate KVM hypercall interface */
221 qemu_devtree_add_subnode(fdt
, "/hypervisor");
222 qemu_devtree_setprop_string(fdt
, "/hypervisor", "compatible",
224 kvmppc_get_hypercall(env
, hypercall
, sizeof(hypercall
));
225 qemu_devtree_setprop(fdt
, "/hypervisor", "hcall-instructions",
226 hypercall
, sizeof(hypercall
));
229 /* Create CPU nodes */
230 qemu_devtree_add_subnode(fdt
, "/cpus");
231 qemu_devtree_setprop_cell(fdt
, "/cpus", "#address-cells", 1);
232 qemu_devtree_setprop_cell(fdt
, "/cpus", "#size-cells", 0);
234 /* We need to generate the cpu nodes in reverse order, so Linux can pick
235 the first node as boot node and be happy */
236 for (i
= smp_cpus
- 1; i
>= 0; i
--) {
238 uint64_t cpu_release_addr
= MPC8544_SPIN_BASE
+ (i
* 0x20);
240 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
241 if (env
->cpu_index
== i
) {
250 snprintf(cpu_name
, sizeof(cpu_name
), "/cpus/PowerPC,8544@%x", env
->cpu_index
);
251 qemu_devtree_add_subnode(fdt
, cpu_name
);
252 qemu_devtree_setprop_cell(fdt
, cpu_name
, "clock-frequency", clock_freq
);
253 qemu_devtree_setprop_cell(fdt
, cpu_name
, "timebase-frequency", tb_freq
);
254 qemu_devtree_setprop_string(fdt
, cpu_name
, "device_type", "cpu");
255 qemu_devtree_setprop_cell(fdt
, cpu_name
, "reg", env
->cpu_index
);
256 qemu_devtree_setprop_cell(fdt
, cpu_name
, "d-cache-line-size",
257 env
->dcache_line_size
);
258 qemu_devtree_setprop_cell(fdt
, cpu_name
, "i-cache-line-size",
259 env
->icache_line_size
);
260 qemu_devtree_setprop_cell(fdt
, cpu_name
, "d-cache-size", 0x8000);
261 qemu_devtree_setprop_cell(fdt
, cpu_name
, "i-cache-size", 0x8000);
262 qemu_devtree_setprop_cell(fdt
, cpu_name
, "bus-frequency", 0);
263 if (env
->cpu_index
) {
264 qemu_devtree_setprop_string(fdt
, cpu_name
, "status", "disabled");
265 qemu_devtree_setprop_string(fdt
, cpu_name
, "enable-method", "spin-table");
266 qemu_devtree_setprop_u64(fdt
, cpu_name
, "cpu-release-addr",
269 qemu_devtree_setprop_string(fdt
, cpu_name
, "status", "okay");
273 qemu_devtree_add_subnode(fdt
, "/aliases");
274 /* XXX These should go into their respective devices' code */
275 snprintf(soc
, sizeof(soc
), "/soc@%llx", MPC8544_CCSRBAR_BASE
);
276 qemu_devtree_add_subnode(fdt
, soc
);
277 qemu_devtree_setprop_string(fdt
, soc
, "device_type", "soc");
278 qemu_devtree_setprop(fdt
, soc
, "compatible", compatible_sb
,
279 sizeof(compatible_sb
));
280 qemu_devtree_setprop_cell(fdt
, soc
, "#address-cells", 1);
281 qemu_devtree_setprop_cell(fdt
, soc
, "#size-cells", 1);
282 qemu_devtree_setprop_cells(fdt
, soc
, "ranges", 0x0,
283 MPC8544_CCSRBAR_BASE
>> 32, MPC8544_CCSRBAR_BASE
,
284 MPC8544_CCSRBAR_SIZE
);
285 /* XXX should contain a reasonable value */
286 qemu_devtree_setprop_cell(fdt
, soc
, "bus-frequency", 0);
288 snprintf(mpic
, sizeof(mpic
), "%s/pic@%llx", soc
, MPC8544_MPIC_REGS_OFFSET
);
289 qemu_devtree_add_subnode(fdt
, mpic
);
290 qemu_devtree_setprop_string(fdt
, mpic
, "device_type", "open-pic");
291 qemu_devtree_setprop_string(fdt
, mpic
, "compatible", "chrp,open-pic");
292 qemu_devtree_setprop_cells(fdt
, mpic
, "reg", MPC8544_MPIC_REGS_OFFSET
,
294 qemu_devtree_setprop_cell(fdt
, mpic
, "#address-cells", 0);
295 qemu_devtree_setprop_cell(fdt
, mpic
, "#interrupt-cells", 2);
296 mpic_ph
= qemu_devtree_alloc_phandle(fdt
);
297 qemu_devtree_setprop_cell(fdt
, mpic
, "phandle", mpic_ph
);
298 qemu_devtree_setprop_cell(fdt
, mpic
, "linux,phandle", mpic_ph
);
299 qemu_devtree_setprop(fdt
, mpic
, "interrupt-controller", NULL
, 0);
302 * We have to generate ser1 first, because Linux takes the first
303 * device it finds in the dt as serial output device. And we generate
304 * devices in reverse order to the dt.
306 dt_serial_create(fdt
, MPC8544_SERIAL1_REGS_OFFSET
,
307 soc
, mpic
, "serial1", 1, false);
308 dt_serial_create(fdt
, MPC8544_SERIAL0_REGS_OFFSET
,
309 soc
, mpic
, "serial0", 0, true);
311 snprintf(gutil
, sizeof(gutil
), "%s/global-utilities@%llx", soc
,
312 MPC8544_UTIL_OFFSET
);
313 qemu_devtree_add_subnode(fdt
, gutil
);
314 qemu_devtree_setprop_string(fdt
, gutil
, "compatible", "fsl,mpc8544-guts");
315 qemu_devtree_setprop_cells(fdt
, gutil
, "reg", MPC8544_UTIL_OFFSET
, 0x1000);
316 qemu_devtree_setprop(fdt
, gutil
, "fsl,has-rstcr", NULL
, 0);
318 snprintf(msi
, sizeof(msi
), "/%s/msi@%llx", soc
, MPC8544_MSI_REGS_OFFSET
);
319 qemu_devtree_add_subnode(fdt
, msi
);
320 qemu_devtree_setprop_string(fdt
, msi
, "compatible", "fsl,mpic-msi");
321 qemu_devtree_setprop_cells(fdt
, msi
, "reg", MPC8544_MSI_REGS_OFFSET
, 0x200);
322 msi_ph
= qemu_devtree_alloc_phandle(fdt
);
323 qemu_devtree_setprop_cells(fdt
, msi
, "msi-available-ranges", 0x0, 0x100);
324 qemu_devtree_setprop_phandle(fdt
, msi
, "interrupt-parent", mpic
);
325 qemu_devtree_setprop_cells(fdt
, msi
, "interrupts",
334 qemu_devtree_setprop_cell(fdt
, msi
, "phandle", msi_ph
);
335 qemu_devtree_setprop_cell(fdt
, msi
, "linux,phandle", msi_ph
);
337 snprintf(pci
, sizeof(pci
), "/pci@%llx", MPC8544_PCI_REGS_BASE
);
338 qemu_devtree_add_subnode(fdt
, pci
);
339 qemu_devtree_setprop_cell(fdt
, pci
, "cell-index", 0);
340 qemu_devtree_setprop_string(fdt
, pci
, "compatible", "fsl,mpc8540-pci");
341 qemu_devtree_setprop_string(fdt
, pci
, "device_type", "pci");
342 qemu_devtree_setprop_cells(fdt
, pci
, "interrupt-map-mask", 0xf800, 0x0,
344 pci_map
= pci_map_create(fdt
, qemu_devtree_get_phandle(fdt
, mpic
),
345 params
->pci_first_slot
, params
->pci_nr_slots
,
347 qemu_devtree_setprop(fdt
, pci
, "interrupt-map", pci_map
, len
);
348 qemu_devtree_setprop_phandle(fdt
, pci
, "interrupt-parent", mpic
);
349 qemu_devtree_setprop_cells(fdt
, pci
, "interrupts", 24, 2);
350 qemu_devtree_setprop_cells(fdt
, pci
, "bus-range", 0, 255);
351 for (i
= 0; i
< 14; i
++) {
352 pci_ranges
[i
] = cpu_to_be32(pci_ranges
[i
]);
354 qemu_devtree_setprop_cell(fdt
, pci
, "fsl,msi", msi_ph
);
355 qemu_devtree_setprop(fdt
, pci
, "ranges", pci_ranges
, sizeof(pci_ranges
));
356 qemu_devtree_setprop_cells(fdt
, pci
, "reg", MPC8544_PCI_REGS_BASE
>> 32,
357 MPC8544_PCI_REGS_BASE
, 0, 0x1000);
358 qemu_devtree_setprop_cell(fdt
, pci
, "clock-frequency", 66666666);
359 qemu_devtree_setprop_cell(fdt
, pci
, "#interrupt-cells", 1);
360 qemu_devtree_setprop_cell(fdt
, pci
, "#size-cells", 2);
361 qemu_devtree_setprop_cell(fdt
, pci
, "#address-cells", 3);
362 qemu_devtree_setprop_string(fdt
, "/aliases", "pci0", pci
);
364 params
->fixup_devtree(params
, fdt
);
366 if (toplevel_compat
) {
367 qemu_devtree_setprop(fdt
, "/", "compatible", toplevel_compat
,
368 strlen(toplevel_compat
) + 1);
372 qemu_devtree_dumpdtb(fdt
, fdt_size
);
373 ret
= rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE
, fdt
, fdt_size
, addr
);
386 /* Create -kernel TLB entries for BookE. */
387 static inline hwaddr
booke206_page_size_to_tlb(uint64_t size
)
389 return 63 - clz64(size
>> 10);
392 static void mmubooke_create_initial_mapping(CPUPPCState
*env
)
394 struct boot_info
*bi
= env
->load_info
;
395 ppcmas_tlb_t
*tlb
= booke206_get_tlbm(env
, 1, 0, 0);
399 /* Our initial TLB entry needs to cover everything from 0 to
400 the device tree top */
401 dt_end
= bi
->dt_base
+ bi
->dt_size
;
402 ps
= booke206_page_size_to_tlb(dt_end
) + 1;
404 /* e500v2 can only do even TLB size bits */
407 size
= (ps
<< MAS1_TSIZE_SHIFT
);
408 tlb
->mas1
= MAS1_VALID
| size
;
411 tlb
->mas7_3
|= MAS3_UR
| MAS3_UW
| MAS3_UX
| MAS3_SR
| MAS3_SW
| MAS3_SX
;
413 env
->tlb_dirty
= true;
416 static void ppce500_cpu_reset_sec(void *opaque
)
418 PowerPCCPU
*cpu
= opaque
;
419 CPUPPCState
*env
= &cpu
->env
;
423 /* Secondary CPU starts in halted state for now. Needs to change when
424 implementing non-kernel boot. */
426 env
->exception_index
= EXCP_HLT
;
429 static void ppce500_cpu_reset(void *opaque
)
431 PowerPCCPU
*cpu
= opaque
;
432 CPUPPCState
*env
= &cpu
->env
;
433 struct boot_info
*bi
= env
->load_info
;
437 /* Set initial guest state. */
439 env
->gpr
[1] = (16<<20) - 8;
440 env
->gpr
[3] = bi
->dt_base
;
441 env
->nip
= bi
->entry
;
442 mmubooke_create_initial_mapping(env
);
445 void ppce500_init(PPCE500Params
*params
)
447 MemoryRegion
*address_space_mem
= get_system_memory();
448 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
450 CPUPPCState
*env
= NULL
;
452 uint64_t elf_lowaddr
;
454 hwaddr loadaddr
=UIMAGE_LOAD_BASE
;
455 target_long kernel_size
=0;
456 target_ulong dt_base
= 0;
457 target_ulong initrd_base
= 0;
458 target_long initrd_size
=0;
460 unsigned int pci_irq_nrs
[4] = {1, 2, 3, 4};
461 qemu_irq
**irqs
, *mpic
;
463 CPUPPCState
*firstenv
= NULL
;
464 MemoryRegion
*ccsr_addr_space
;
466 PPCE500CCSRState
*ccsr
;
469 if (params
->cpu_model
== NULL
) {
470 params
->cpu_model
= "e500v2_v30";
473 irqs
= g_malloc0(smp_cpus
* sizeof(qemu_irq
*));
474 irqs
[0] = g_malloc0(smp_cpus
* sizeof(qemu_irq
) * OPENPIC_OUTPUT_NB
);
475 for (i
= 0; i
< smp_cpus
; i
++) {
479 cpu
= cpu_ppc_init(params
->cpu_model
);
481 fprintf(stderr
, "Unable to initialize CPU!\n");
490 irqs
[i
] = irqs
[0] + (i
* OPENPIC_OUTPUT_NB
);
491 input
= (qemu_irq
*)env
->irq_inputs
;
492 irqs
[i
][OPENPIC_OUTPUT_INT
] = input
[PPCE500_INPUT_INT
];
493 irqs
[i
][OPENPIC_OUTPUT_CINT
] = input
[PPCE500_INPUT_CINT
];
494 env
->spr
[SPR_BOOKE_PIR
] = env
->cpu_index
= i
;
495 env
->mpic_cpu_base
= MPC8544_CCSRBAR_BASE
+
496 MPC8544_MPIC_REGS_OFFSET
+ 0x20000;
498 ppc_booke_timers_init(env
, 400000000, PPC_TIMER_E500
);
500 /* Register reset handler */
503 struct boot_info
*boot_info
;
504 boot_info
= g_malloc0(sizeof(struct boot_info
));
505 qemu_register_reset(ppce500_cpu_reset
, cpu
);
506 env
->load_info
= boot_info
;
509 qemu_register_reset(ppce500_cpu_reset_sec
, cpu
);
515 /* Fixup Memory size on a alignment boundary */
516 ram_size
&= ~(RAM_SIZES_ALIGN
- 1);
518 /* Register Memory */
519 memory_region_init_ram(ram
, "mpc8544ds.ram", ram_size
);
520 vmstate_register_ram_global(ram
);
521 memory_region_add_subregion(address_space_mem
, 0, ram
);
523 dev
= qdev_create(NULL
, "e500-ccsr");
524 object_property_add_child(qdev_get_machine(), "e500-ccsr",
526 qdev_init_nofail(dev
);
528 ccsr_addr_space
= &ccsr
->ccsr_space
;
529 memory_region_add_subregion(address_space_mem
, MPC8544_CCSRBAR_BASE
,
533 mpic
= g_new(qemu_irq
, 256);
534 dev
= qdev_create(NULL
, "openpic");
535 qdev_prop_set_uint32(dev
, "nb_cpus", smp_cpus
);
536 qdev_prop_set_uint32(dev
, "model", OPENPIC_MODEL_FSL_MPIC_20
);
537 qdev_init_nofail(dev
);
538 s
= sysbus_from_qdev(dev
);
541 for (i
= 0; i
< smp_cpus
; i
++) {
542 for (j
= 0; j
< OPENPIC_OUTPUT_NB
; j
++) {
543 sysbus_connect_irq(s
, k
++, irqs
[i
][j
]);
547 for (i
= 0; i
< 256; i
++) {
548 mpic
[i
] = qdev_get_gpio_in(dev
, i
);
551 memory_region_add_subregion(ccsr_addr_space
, MPC8544_MPIC_REGS_OFFSET
,
556 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL0_REGS_OFFSET
,
558 serial_hds
[0], DEVICE_BIG_ENDIAN
);
562 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL1_REGS_OFFSET
,
564 serial_hds
[1], DEVICE_BIG_ENDIAN
);
567 /* General Utility device */
568 dev
= qdev_create(NULL
, "mpc8544-guts");
569 qdev_init_nofail(dev
);
570 s
= SYS_BUS_DEVICE(dev
);
571 memory_region_add_subregion(ccsr_addr_space
, MPC8544_UTIL_OFFSET
,
572 sysbus_mmio_get_region(s
, 0));
575 dev
= qdev_create(NULL
, "e500-pcihost");
576 qdev_prop_set_uint32(dev
, "first_slot", params
->pci_first_slot
);
577 qdev_init_nofail(dev
);
578 s
= SYS_BUS_DEVICE(dev
);
579 sysbus_connect_irq(s
, 0, mpic
[pci_irq_nrs
[0]]);
580 sysbus_connect_irq(s
, 1, mpic
[pci_irq_nrs
[1]]);
581 sysbus_connect_irq(s
, 2, mpic
[pci_irq_nrs
[2]]);
582 sysbus_connect_irq(s
, 3, mpic
[pci_irq_nrs
[3]]);
583 memory_region_add_subregion(ccsr_addr_space
, MPC8544_PCI_REGS_OFFSET
,
584 sysbus_mmio_get_region(s
, 0));
586 pci_bus
= (PCIBus
*)qdev_get_child_bus(dev
, "pci.0");
588 printf("couldn't create PCI controller!\n");
590 sysbus_mmio_map(sysbus_from_qdev(dev
), 1, MPC8544_PCI_IO
);
593 /* Register network interfaces. */
594 for (i
= 0; i
< nb_nics
; i
++) {
595 pci_nic_init_nofail(&nd_table
[i
], "virtio", NULL
);
599 /* Register spinning region */
600 sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE
, NULL
);
603 if (params
->kernel_filename
) {
604 kernel_size
= load_uimage(params
->kernel_filename
, &entry
,
606 if (kernel_size
< 0) {
607 kernel_size
= load_elf(params
->kernel_filename
, NULL
, NULL
,
608 &elf_entry
, &elf_lowaddr
, NULL
, 1,
611 loadaddr
= elf_lowaddr
;
613 /* XXX try again as binary */
614 if (kernel_size
< 0) {
615 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
616 params
->kernel_filename
);
622 if (params
->initrd_filename
) {
623 initrd_base
= (loadaddr
+ kernel_size
+ INITRD_LOAD_PAD
) &
625 initrd_size
= load_image_targphys(params
->initrd_filename
, initrd_base
,
626 ram_size
- initrd_base
);
628 if (initrd_size
< 0) {
629 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
630 params
->initrd_filename
);
635 /* If we're loading a kernel directly, we must load the device tree too. */
636 if (params
->kernel_filename
) {
637 struct boot_info
*boot_info
;
640 dt_base
= (loadaddr
+ kernel_size
+ DTC_LOAD_PAD
) & ~DTC_PAD_MASK
;
641 dt_size
= ppce500_load_device_tree(env
, params
, dt_base
, initrd_base
,
644 fprintf(stderr
, "couldn't load device tree\n");
648 boot_info
= env
->load_info
;
649 boot_info
->entry
= entry
;
650 boot_info
->dt_base
= dt_base
;
651 boot_info
->dt_size
= dt_size
;
659 static int e500_ccsr_initfn(SysBusDevice
*dev
)
661 PPCE500CCSRState
*ccsr
;
664 memory_region_init(&ccsr
->ccsr_space
, "e500-ccsr",
665 MPC8544_CCSRBAR_SIZE
);
669 static void e500_ccsr_class_init(ObjectClass
*klass
, void *data
)
671 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
672 k
->init
= e500_ccsr_initfn
;
675 static const TypeInfo e500_ccsr_info
= {
677 .parent
= TYPE_SYS_BUS_DEVICE
,
678 .instance_size
= sizeof(PPCE500CCSRState
),
679 .class_init
= e500_ccsr_class_init
,
682 static void e500_register_types(void)
684 type_register_static(&e500_ccsr_info
);
687 type_init(e500_register_types
)