2 * QEMU PowerPC PowerNV machine model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/units.h"
23 #include "qapi/error.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/numa.h"
26 #include "sysemu/reset.h"
27 #include "sysemu/runstate.h"
28 #include "sysemu/cpus.h"
29 #include "sysemu/device_tree.h"
30 #include "target/ppc/cpu.h"
32 #include "hw/ppc/fdt.h"
33 #include "hw/ppc/ppc.h"
34 #include "hw/ppc/pnv.h"
35 #include "hw/ppc/pnv_core.h"
36 #include "hw/loader.h"
37 #include "exec/address-spaces.h"
38 #include "qapi/visitor.h"
39 #include "monitor/monitor.h"
40 #include "hw/intc/intc.h"
41 #include "hw/ipmi/ipmi.h"
42 #include "target/ppc/mmu-hash64.h"
44 #include "hw/ppc/xics.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/ppc/pnv_xscom.h"
47 #include "hw/ppc/pnv_pnor.h"
49 #include "hw/isa/isa.h"
50 #include "hw/boards.h"
51 #include "hw/char/serial.h"
52 #include "hw/rtc/mc146818rtc.h"
56 #define FDT_MAX_SIZE (1 * MiB)
58 #define FW_FILE_NAME "skiboot.lid"
59 #define FW_LOAD_ADDR 0x0
60 #define FW_MAX_SIZE (4 * MiB)
62 #define KERNEL_LOAD_ADDR 0x20000000
63 #define KERNEL_MAX_SIZE (256 * MiB)
64 #define INITRD_LOAD_ADDR 0x60000000
65 #define INITRD_MAX_SIZE (256 * MiB)
67 static const char *pnv_chip_core_typename(const PnvChip
*o
)
69 const char *chip_type
= object_class_get_name(object_get_class(OBJECT(o
)));
70 int len
= strlen(chip_type
) - strlen(PNV_CHIP_TYPE_SUFFIX
);
71 char *s
= g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len
, chip_type
);
72 const char *core_type
= object_class_get_name(object_class_by_name(s
));
78 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
79 * 4 * 4 sockets * 12 cores * 8 threads = 1536
85 * Memory nodes are created by hostboot, one for each range of memory
86 * that has a different "affinity". In practice, it means one range
89 static void pnv_dt_memory(void *fdt
, int chip_id
, hwaddr start
, hwaddr size
)
92 uint64_t mem_reg_property
[2];
95 mem_reg_property
[0] = cpu_to_be64(start
);
96 mem_reg_property
[1] = cpu_to_be64(size
);
98 mem_name
= g_strdup_printf("memory@%"HWADDR_PRIx
, start
);
99 off
= fdt_add_subnode(fdt
, 0, mem_name
);
102 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
103 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
104 sizeof(mem_reg_property
))));
105 _FDT((fdt_setprop_cell(fdt
, off
, "ibm,chip-id", chip_id
)));
108 static int get_cpus_node(void *fdt
)
110 int cpus_offset
= fdt_path_offset(fdt
, "/cpus");
112 if (cpus_offset
< 0) {
113 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
115 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
116 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
124 * The PowerNV cores (and threads) need to use real HW ids and not an
125 * incremental index like it has been done on other platforms. This HW
126 * id is stored in the CPU PIR, it is used to create cpu nodes in the
127 * device tree, used in XSCOM to address cores and in interrupt
130 static void pnv_dt_core(PnvChip
*chip
, PnvCore
*pc
, void *fdt
)
132 PowerPCCPU
*cpu
= pc
->threads
[0];
133 CPUState
*cs
= CPU(cpu
);
134 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
135 int smt_threads
= CPU_CORE(pc
)->nr_threads
;
136 CPUPPCState
*env
= &cpu
->env
;
137 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
138 uint32_t servers_prop
[smt_threads
];
140 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
141 0xffffffff, 0xffffffff};
142 uint32_t tbfreq
= PNV_TIMEBASE_FREQ
;
143 uint32_t cpufreq
= 1000000000;
144 uint32_t page_sizes_prop
[64];
145 size_t page_sizes_prop_size
;
146 const uint8_t pa_features
[] = { 24, 0,
147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
153 int cpus_offset
= get_cpus_node(fdt
);
155 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, pc
->pir
);
156 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
160 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id", chip
->chip_id
)));
162 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", pc
->pir
)));
163 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,pir", pc
->pir
)));
164 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
166 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
167 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
168 env
->dcache_line_size
)));
169 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
170 env
->dcache_line_size
)));
171 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
172 env
->icache_line_size
)));
173 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
174 env
->icache_line_size
)));
176 if (pcc
->l1_dcache_size
) {
177 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
178 pcc
->l1_dcache_size
)));
180 warn_report("Unknown L1 dcache size for cpu");
182 if (pcc
->l1_icache_size
) {
183 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
184 pcc
->l1_icache_size
)));
186 warn_report("Unknown L1 icache size for cpu");
189 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
190 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
191 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size",
192 cpu
->hash64_opts
->slb_size
)));
193 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
194 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
196 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
197 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
200 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
201 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
202 segs
, sizeof(segs
))));
206 * Advertise VMX/VSX (vector extensions) if available
207 * 0 / no property == no vector extensions
208 * 1 == VMX / Altivec available
211 if (env
->insns_flags
& PPC_ALTIVEC
) {
212 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
214 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
218 * Advertise DFP (Decimal Floating Point) if available
219 * 0 / no property == no DFP
222 if (env
->insns_flags2
& PPC2_DFP
) {
223 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
226 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
227 sizeof(page_sizes_prop
));
228 if (page_sizes_prop_size
) {
229 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
230 page_sizes_prop
, page_sizes_prop_size
)));
233 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
234 pa_features
, sizeof(pa_features
))));
236 /* Build interrupt servers properties */
237 for (i
= 0; i
< smt_threads
; i
++) {
238 servers_prop
[i
] = cpu_to_be32(pc
->pir
+ i
);
240 _FDT((fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
241 servers_prop
, sizeof(servers_prop
))));
244 static void pnv_dt_icp(PnvChip
*chip
, void *fdt
, uint32_t pir
,
247 uint64_t addr
= PNV_ICP_BASE(chip
) | (pir
<< 12);
249 const char compat
[] = "IBM,power8-icp\0IBM,ppc-xicp";
250 uint32_t irange
[2], i
, rsize
;
254 irange
[0] = cpu_to_be32(pir
);
255 irange
[1] = cpu_to_be32(nr_threads
);
257 rsize
= sizeof(uint64_t) * 2 * nr_threads
;
258 reg
= g_malloc(rsize
);
259 for (i
= 0; i
< nr_threads
; i
++) {
260 reg
[i
* 2] = cpu_to_be64(addr
| ((pir
+ i
) * 0x1000));
261 reg
[i
* 2 + 1] = cpu_to_be64(0x1000);
264 name
= g_strdup_printf("interrupt-controller@%"PRIX64
, addr
);
265 offset
= fdt_add_subnode(fdt
, 0, name
);
269 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
, sizeof(compat
))));
270 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, rsize
)));
271 _FDT((fdt_setprop_string(fdt
, offset
, "device_type",
272 "PowerPC-External-Interrupt-Presentation")));
273 _FDT((fdt_setprop(fdt
, offset
, "interrupt-controller", NULL
, 0)));
274 _FDT((fdt_setprop(fdt
, offset
, "ibm,interrupt-server-ranges",
275 irange
, sizeof(irange
))));
276 _FDT((fdt_setprop_cell(fdt
, offset
, "#interrupt-cells", 1)));
277 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 0)));
281 static void pnv_chip_power8_dt_populate(PnvChip
*chip
, void *fdt
)
283 const char *typename
= pnv_chip_core_typename(chip
);
284 size_t typesize
= object_type_get_instance_size(typename
);
287 pnv_dt_xscom(chip
, fdt
, 0);
289 for (i
= 0; i
< chip
->nr_cores
; i
++) {
290 PnvCore
*pnv_core
= PNV_CORE(chip
->cores
+ i
* typesize
);
292 pnv_dt_core(chip
, pnv_core
, fdt
);
294 /* Interrupt Control Presenters (ICP). One per core. */
295 pnv_dt_icp(chip
, fdt
, pnv_core
->pir
, CPU_CORE(pnv_core
)->nr_threads
);
298 if (chip
->ram_size
) {
299 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
303 static void pnv_chip_power9_dt_populate(PnvChip
*chip
, void *fdt
)
305 const char *typename
= pnv_chip_core_typename(chip
);
306 size_t typesize
= object_type_get_instance_size(typename
);
309 pnv_dt_xscom(chip
, fdt
, 0);
311 for (i
= 0; i
< chip
->nr_cores
; i
++) {
312 PnvCore
*pnv_core
= PNV_CORE(chip
->cores
+ i
* typesize
);
314 pnv_dt_core(chip
, pnv_core
, fdt
);
317 if (chip
->ram_size
) {
318 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
321 pnv_dt_lpc(chip
, fdt
, 0);
324 static void pnv_dt_rtc(ISADevice
*d
, void *fdt
, int lpc_off
)
326 uint32_t io_base
= d
->ioport_id
;
327 uint32_t io_regs
[] = {
329 cpu_to_be32(io_base
),
335 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
336 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
340 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
341 _FDT((fdt_setprop_string(fdt
, node
, "compatible", "pnpPNP,b00")));
344 static void pnv_dt_serial(ISADevice
*d
, void *fdt
, int lpc_off
)
346 const char compatible
[] = "ns16550\0pnpPNP,501";
347 uint32_t io_base
= d
->ioport_id
;
348 uint32_t io_regs
[] = {
350 cpu_to_be32(io_base
),
356 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
357 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
361 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
362 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
363 sizeof(compatible
))));
365 _FDT((fdt_setprop_cell(fdt
, node
, "clock-frequency", 1843200)));
366 _FDT((fdt_setprop_cell(fdt
, node
, "current-speed", 115200)));
367 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", d
->isairq
[0])));
368 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
369 fdt_get_phandle(fdt
, lpc_off
))));
371 /* This is needed by Linux */
372 _FDT((fdt_setprop_string(fdt
, node
, "device_type", "serial")));
375 static void pnv_dt_ipmi_bt(ISADevice
*d
, void *fdt
, int lpc_off
)
377 const char compatible
[] = "bt\0ipmi-bt";
379 uint32_t io_regs
[] = {
381 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
388 io_base
= object_property_get_int(OBJECT(d
), "ioport", &error_fatal
);
389 io_regs
[1] = cpu_to_be32(io_base
);
391 irq
= object_property_get_int(OBJECT(d
), "irq", &error_fatal
);
393 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
394 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
398 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
399 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
400 sizeof(compatible
))));
402 /* Mark it as reserved to avoid Linux trying to claim it */
403 _FDT((fdt_setprop_string(fdt
, node
, "status", "reserved")));
404 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
405 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
406 fdt_get_phandle(fdt
, lpc_off
))));
409 typedef struct ForeachPopulateArgs
{
412 } ForeachPopulateArgs
;
414 static int pnv_dt_isa_device(DeviceState
*dev
, void *opaque
)
416 ForeachPopulateArgs
*args
= opaque
;
417 ISADevice
*d
= ISA_DEVICE(dev
);
419 if (object_dynamic_cast(OBJECT(dev
), TYPE_MC146818_RTC
)) {
420 pnv_dt_rtc(d
, args
->fdt
, args
->offset
);
421 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_ISA_SERIAL
)) {
422 pnv_dt_serial(d
, args
->fdt
, args
->offset
);
423 } else if (object_dynamic_cast(OBJECT(dev
), "isa-ipmi-bt")) {
424 pnv_dt_ipmi_bt(d
, args
->fdt
, args
->offset
);
426 error_report("unknown isa device %s@i%x", qdev_fw_name(dev
),
434 * The default LPC bus of a multichip system is on chip 0. It's
435 * recognized by the firmware (skiboot) using a "primary" property.
437 static void pnv_dt_isa(PnvMachineState
*pnv
, void *fdt
)
439 int isa_offset
= fdt_path_offset(fdt
, pnv
->chips
[0]->dt_isa_nodename
);
440 ForeachPopulateArgs args
= {
442 .offset
= isa_offset
,
446 _FDT((fdt_setprop(fdt
, isa_offset
, "primary", NULL
, 0)));
448 phandle
= qemu_fdt_alloc_phandle(fdt
);
450 _FDT((fdt_setprop_cell(fdt
, isa_offset
, "phandle", phandle
)));
453 * ISA devices are not necessarily parented to the ISA bus so we
454 * can not use object_child_foreach()
456 qbus_walk_children(BUS(pnv
->isa_bus
), pnv_dt_isa_device
, NULL
, NULL
, NULL
,
460 static void pnv_dt_power_mgt(void *fdt
)
464 off
= fdt_add_subnode(fdt
, 0, "ibm,opal");
465 off
= fdt_add_subnode(fdt
, off
, "power-mgt");
467 _FDT(fdt_setprop_cell(fdt
, off
, "ibm,enabled-stop-levels", 0xc0000000));
470 static void *pnv_dt_create(MachineState
*machine
)
472 const char plat_compat8
[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
473 const char plat_compat9
[] = "qemu,powernv9\0ibm,powernv";
474 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
480 fdt
= g_malloc0(FDT_MAX_SIZE
);
481 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
484 _FDT((fdt_add_subnode(fdt
, 0, "qemu")));
487 _FDT((fdt_setprop_cell(fdt
, 0, "#address-cells", 0x2)));
488 _FDT((fdt_setprop_cell(fdt
, 0, "#size-cells", 0x2)));
489 _FDT((fdt_setprop_string(fdt
, 0, "model",
490 "IBM PowerNV (emulated by qemu)")));
491 if (pnv_is_power9(pnv
)) {
492 _FDT((fdt_setprop(fdt
, 0, "compatible", plat_compat9
,
493 sizeof(plat_compat9
))));
495 _FDT((fdt_setprop(fdt
, 0, "compatible", plat_compat8
,
496 sizeof(plat_compat8
))));
500 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
501 _FDT((fdt_setprop_string(fdt
, 0, "vm,uuid", buf
)));
503 _FDT((fdt_property_string(fdt
, "system-id", buf
)));
507 off
= fdt_add_subnode(fdt
, 0, "chosen");
508 if (machine
->kernel_cmdline
) {
509 _FDT((fdt_setprop_string(fdt
, off
, "bootargs",
510 machine
->kernel_cmdline
)));
513 if (pnv
->initrd_size
) {
514 uint32_t start_prop
= cpu_to_be32(pnv
->initrd_base
);
515 uint32_t end_prop
= cpu_to_be32(pnv
->initrd_base
+ pnv
->initrd_size
);
517 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-start",
518 &start_prop
, sizeof(start_prop
))));
519 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-end",
520 &end_prop
, sizeof(end_prop
))));
523 /* Populate device tree for each chip */
524 for (i
= 0; i
< pnv
->num_chips
; i
++) {
525 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->dt_populate(pnv
->chips
[i
], fdt
);
528 /* Populate ISA devices on chip 0 */
529 pnv_dt_isa(pnv
, fdt
);
532 pnv_dt_bmc_sensors(pnv
->bmc
, fdt
);
535 /* Create an extra node for power management on Power9 */
536 if (pnv_is_power9(pnv
)) {
537 pnv_dt_power_mgt(fdt
);
543 static void pnv_powerdown_notify(Notifier
*n
, void *opaque
)
545 PnvMachineState
*pnv
= PNV_MACHINE(qdev_get_machine());
548 pnv_bmc_powerdown(pnv
->bmc
);
552 static void pnv_reset(MachineState
*machine
)
554 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
558 qemu_devices_reset();
561 * OpenPOWER systems have a BMC, which can be defined on the
564 * -device ipmi-bmc-sim,id=bmc0
566 * This is the internal simulator but it could also be an external
569 obj
= object_resolve_path_type("", "ipmi-bmc-sim", NULL
);
571 pnv
->bmc
= IPMI_BMC(obj
);
574 fdt
= pnv_dt_create(machine
);
576 /* Pack resulting tree */
577 _FDT((fdt_pack(fdt
)));
579 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
580 cpu_physical_memory_write(PNV_FDT_ADDR
, fdt
, fdt_totalsize(fdt
));
583 static ISABus
*pnv_chip_power8_isa_create(PnvChip
*chip
, Error
**errp
)
585 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
586 return pnv_lpc_isa_create(&chip8
->lpc
, true, errp
);
589 static ISABus
*pnv_chip_power8nvl_isa_create(PnvChip
*chip
, Error
**errp
)
591 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
592 return pnv_lpc_isa_create(&chip8
->lpc
, false, errp
);
595 static ISABus
*pnv_chip_power9_isa_create(PnvChip
*chip
, Error
**errp
)
597 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
598 return pnv_lpc_isa_create(&chip9
->lpc
, false, errp
);
601 static ISABus
*pnv_isa_create(PnvChip
*chip
, Error
**errp
)
603 return PNV_CHIP_GET_CLASS(chip
)->isa_create(chip
, errp
);
606 static void pnv_chip_power8_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
608 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
610 ics_pic_print_info(&chip8
->psi
.ics
, mon
);
613 static void pnv_chip_power9_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
615 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
617 pnv_xive_pic_print_info(&chip9
->xive
, mon
);
618 pnv_psi_pic_print_info(&chip9
->psi
, mon
);
621 static bool pnv_match_cpu(const char *default_type
, const char *cpu_type
)
623 PowerPCCPUClass
*ppc_default
=
624 POWERPC_CPU_CLASS(object_class_by_name(default_type
));
625 PowerPCCPUClass
*ppc
=
626 POWERPC_CPU_CLASS(object_class_by_name(cpu_type
));
628 return ppc_default
->pvr_match(ppc_default
, ppc
->pvr
);
631 static void pnv_init(MachineState
*machine
)
633 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
634 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
640 DriveInfo
*pnor
= drive_get(IF_MTD
, 0, 0);
644 if (machine
->ram_size
< (1 * GiB
)) {
645 warn_report("skiboot may not work with < 1GB of RAM");
648 ram
= g_new(MemoryRegion
, 1);
649 memory_region_allocate_system_memory(ram
, NULL
, "pnv.ram",
651 memory_region_add_subregion(get_system_memory(), 0, ram
);
654 * Create our simple PNOR device
656 dev
= qdev_create(NULL
, TYPE_PNV_PNOR
);
658 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(pnor
),
661 qdev_init_nofail(dev
);
662 pnv
->pnor
= PNV_PNOR(dev
);
664 /* load skiboot firmware */
665 if (bios_name
== NULL
) {
666 bios_name
= FW_FILE_NAME
;
669 fw_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
671 error_report("Could not find OPAL firmware '%s'", bios_name
);
675 fw_size
= load_image_targphys(fw_filename
, FW_LOAD_ADDR
, FW_MAX_SIZE
);
677 error_report("Could not load OPAL firmware '%s'", fw_filename
);
683 if (machine
->kernel_filename
) {
686 kernel_size
= load_image_targphys(machine
->kernel_filename
,
687 KERNEL_LOAD_ADDR
, KERNEL_MAX_SIZE
);
688 if (kernel_size
< 0) {
689 error_report("Could not load kernel '%s'",
690 machine
->kernel_filename
);
696 if (machine
->initrd_filename
) {
697 pnv
->initrd_base
= INITRD_LOAD_ADDR
;
698 pnv
->initrd_size
= load_image_targphys(machine
->initrd_filename
,
699 pnv
->initrd_base
, INITRD_MAX_SIZE
);
700 if (pnv
->initrd_size
< 0) {
701 error_report("Could not load initial ram disk '%s'",
702 machine
->initrd_filename
);
708 * Check compatibility of the specified CPU with the machine
711 if (!pnv_match_cpu(mc
->default_cpu_type
, machine
->cpu_type
)) {
712 error_report("invalid CPU model '%s' for %s machine",
713 machine
->cpu_type
, mc
->name
);
717 /* Create the processor chips */
718 i
= strlen(machine
->cpu_type
) - strlen(POWERPC_CPU_TYPE_SUFFIX
);
719 chip_typename
= g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
720 i
, machine
->cpu_type
);
721 if (!object_class_by_name(chip_typename
)) {
722 error_report("invalid chip model '%.*s' for %s machine",
723 i
, machine
->cpu_type
, mc
->name
);
727 pnv
->chips
= g_new0(PnvChip
*, pnv
->num_chips
);
728 for (i
= 0; i
< pnv
->num_chips
; i
++) {
730 Object
*chip
= object_new(chip_typename
);
732 pnv
->chips
[i
] = PNV_CHIP(chip
);
735 * TODO: put all the memory in one node on chip 0 until we find a
736 * way to specify different ranges for each chip
739 object_property_set_int(chip
, machine
->ram_size
, "ram-size",
743 snprintf(chip_name
, sizeof(chip_name
), "chip[%d]", PNV_CHIP_HWID(i
));
744 object_property_add_child(OBJECT(pnv
), chip_name
, chip
, &error_fatal
);
745 object_property_set_int(chip
, PNV_CHIP_HWID(i
), "chip-id",
747 object_property_set_int(chip
, machine
->smp
.cores
,
748 "nr-cores", &error_fatal
);
749 object_property_set_bool(chip
, true, "realized", &error_fatal
);
751 g_free(chip_typename
);
753 /* Instantiate ISA bus on chip 0 */
754 pnv
->isa_bus
= pnv_isa_create(pnv
->chips
[0], &error_fatal
);
756 /* Create serial port */
757 serial_hds_isa_init(pnv
->isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
759 /* Create an RTC ISA device too */
760 mc146818_rtc_init(pnv
->isa_bus
, 2000, NULL
);
763 * OpenPOWER systems use a IPMI SEL Event message to notify the
766 pnv
->powerdown_notifier
.notify
= pnv_powerdown_notify
;
767 qemu_register_powerdown_notifier(&pnv
->powerdown_notifier
);
771 * 0:21 Reserved - Read as zeros
776 static uint32_t pnv_chip_core_pir_p8(PnvChip
*chip
, uint32_t core_id
)
778 return (chip
->chip_id
<< 7) | (core_id
<< 3);
781 static void pnv_chip_power8_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
784 Error
*local_err
= NULL
;
786 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
788 obj
= icp_create(OBJECT(cpu
), TYPE_PNV_ICP
, XICS_FABRIC(qdev_get_machine()),
791 error_propagate(errp
, local_err
);
799 static void pnv_chip_power8_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
801 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
803 icp_reset(ICP(pnv_cpu
->intc
));
806 static void pnv_chip_power8_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
808 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
810 icp_destroy(ICP(pnv_cpu
->intc
));
811 pnv_cpu
->intc
= NULL
;
815 * 0:48 Reserved - Read as zeroes
818 * 56 Reserved - Read as zero
822 * We only care about the lower bits. uint32_t is fine for the moment.
824 static uint32_t pnv_chip_core_pir_p9(PnvChip
*chip
, uint32_t core_id
)
826 return (chip
->chip_id
<< 8) | (core_id
<< 2);
829 static void pnv_chip_power9_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
832 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
833 Error
*local_err
= NULL
;
835 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
838 * The core creates its interrupt presenter but the XIVE interrupt
839 * controller object is initialized afterwards. Hopefully, it's
840 * only used at runtime.
842 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(&chip9
->xive
), &local_err
);
844 error_propagate(errp
, local_err
);
851 static void pnv_chip_power9_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
853 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
855 xive_tctx_reset(XIVE_TCTX(pnv_cpu
->intc
));
858 static void pnv_chip_power9_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
860 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
862 xive_tctx_destroy(XIVE_TCTX(pnv_cpu
->intc
));
863 pnv_cpu
->intc
= NULL
;
867 * Allowed core identifiers on a POWER8 Processor Chip :
876 * <EX7,8 reserved> <reserved>
885 #define POWER8E_CORE_MASK (0x7070ull)
886 #define POWER8_CORE_MASK (0x7e7eull)
889 * POWER9 has 24 cores, ids starting at 0x0
891 #define POWER9_CORE_MASK (0xffffffffffffffull)
893 static void pnv_chip_power8_instance_init(Object
*obj
)
895 Pnv8Chip
*chip8
= PNV8_CHIP(obj
);
897 object_initialize_child(obj
, "psi", &chip8
->psi
, sizeof(chip8
->psi
),
898 TYPE_PNV8_PSI
, &error_abort
, NULL
);
899 object_property_add_const_link(OBJECT(&chip8
->psi
), "xics",
900 OBJECT(qdev_get_machine()), &error_abort
);
902 object_initialize_child(obj
, "lpc", &chip8
->lpc
, sizeof(chip8
->lpc
),
903 TYPE_PNV8_LPC
, &error_abort
, NULL
);
905 object_initialize_child(obj
, "occ", &chip8
->occ
, sizeof(chip8
->occ
),
906 TYPE_PNV8_OCC
, &error_abort
, NULL
);
907 object_property_add_const_link(OBJECT(&chip8
->occ
), "psi",
908 OBJECT(&chip8
->psi
), &error_abort
);
910 object_initialize_child(obj
, "homer", &chip8
->homer
, sizeof(chip8
->homer
),
911 TYPE_PNV8_HOMER
, &error_abort
, NULL
);
912 object_property_add_const_link(OBJECT(&chip8
->homer
), "chip", obj
,
916 static void pnv_chip_icp_realize(Pnv8Chip
*chip8
, Error
**errp
)
918 PnvChip
*chip
= PNV_CHIP(chip8
);
919 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
920 const char *typename
= pnv_chip_core_typename(chip
);
921 size_t typesize
= object_type_get_instance_size(typename
);
924 XICSFabric
*xi
= XICS_FABRIC(qdev_get_machine());
926 name
= g_strdup_printf("icp-%x", chip
->chip_id
);
927 memory_region_init(&chip8
->icp_mmio
, OBJECT(chip
), name
, PNV_ICP_SIZE
);
928 sysbus_init_mmio(SYS_BUS_DEVICE(chip
), &chip8
->icp_mmio
);
931 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 1, PNV_ICP_BASE(chip
));
933 /* Map the ICP registers for each thread */
934 for (i
= 0; i
< chip
->nr_cores
; i
++) {
935 PnvCore
*pnv_core
= PNV_CORE(chip
->cores
+ i
* typesize
);
936 int core_hwid
= CPU_CORE(pnv_core
)->core_id
;
938 for (j
= 0; j
< CPU_CORE(pnv_core
)->nr_threads
; j
++) {
939 uint32_t pir
= pcc
->core_pir(chip
, core_hwid
) + j
;
940 PnvICPState
*icp
= PNV_ICP(xics_icp_get(xi
, pir
));
942 memory_region_add_subregion(&chip8
->icp_mmio
, pir
<< 12,
948 static void pnv_chip_power8_realize(DeviceState
*dev
, Error
**errp
)
950 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
951 PnvChip
*chip
= PNV_CHIP(dev
);
952 Pnv8Chip
*chip8
= PNV8_CHIP(dev
);
953 Pnv8Psi
*psi8
= &chip8
->psi
;
954 Error
*local_err
= NULL
;
956 /* XSCOM bridge is first */
957 pnv_xscom_realize(chip
, PNV_XSCOM_SIZE
, &local_err
);
959 error_propagate(errp
, local_err
);
962 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV_XSCOM_BASE(chip
));
964 pcc
->parent_realize(dev
, &local_err
);
966 error_propagate(errp
, local_err
);
970 /* Processor Service Interface (PSI) Host Bridge */
971 object_property_set_int(OBJECT(&chip8
->psi
), PNV_PSIHB_BASE(chip
),
972 "bar", &error_fatal
);
973 object_property_set_bool(OBJECT(&chip8
->psi
), true, "realized", &local_err
);
975 error_propagate(errp
, local_err
);
978 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PSIHB_BASE
,
979 &PNV_PSI(psi8
)->xscom_regs
);
981 /* Create LPC controller */
982 object_property_set_link(OBJECT(&chip8
->lpc
), OBJECT(&chip8
->psi
), "psi",
984 object_property_set_bool(OBJECT(&chip8
->lpc
), true, "realized",
986 pnv_xscom_add_subregion(chip
, PNV_XSCOM_LPC_BASE
, &chip8
->lpc
.xscom_regs
);
988 chip
->dt_isa_nodename
= g_strdup_printf("/xscom@%" PRIx64
"/isa@%x",
989 (uint64_t) PNV_XSCOM_BASE(chip
),
993 * Interrupt Management Area. This is the memory region holding
994 * all the Interrupt Control Presenter (ICP) registers
996 pnv_chip_icp_realize(chip8
, &local_err
);
998 error_propagate(errp
, local_err
);
1002 /* Create the simplified OCC model */
1003 object_property_set_bool(OBJECT(&chip8
->occ
), true, "realized", &local_err
);
1005 error_propagate(errp
, local_err
);
1008 pnv_xscom_add_subregion(chip
, PNV_XSCOM_OCC_BASE
, &chip8
->occ
.xscom_regs
);
1010 /* OCC SRAM model */
1011 memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip
),
1012 &chip8
->occ
.sram_regs
);
1015 object_property_set_bool(OBJECT(&chip8
->homer
), true, "realized",
1018 error_propagate(errp
, local_err
);
1021 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip
),
1022 &chip8
->homer
.regs
);
1025 static void pnv_chip_power8e_class_init(ObjectClass
*klass
, void *data
)
1027 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1028 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1030 k
->chip_type
= PNV_CHIP_POWER8E
;
1031 k
->chip_cfam_id
= 0x221ef04980000000ull
; /* P8 Murano DD2.1 */
1032 k
->cores_mask
= POWER8E_CORE_MASK
;
1033 k
->core_pir
= pnv_chip_core_pir_p8
;
1034 k
->intc_create
= pnv_chip_power8_intc_create
;
1035 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1036 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1037 k
->isa_create
= pnv_chip_power8_isa_create
;
1038 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1039 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1040 dc
->desc
= "PowerNV Chip POWER8E";
1042 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1043 &k
->parent_realize
);
1046 static void pnv_chip_power8_class_init(ObjectClass
*klass
, void *data
)
1048 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1049 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1051 k
->chip_type
= PNV_CHIP_POWER8
;
1052 k
->chip_cfam_id
= 0x220ea04980000000ull
; /* P8 Venice DD2.0 */
1053 k
->cores_mask
= POWER8_CORE_MASK
;
1054 k
->core_pir
= pnv_chip_core_pir_p8
;
1055 k
->intc_create
= pnv_chip_power8_intc_create
;
1056 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1057 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1058 k
->isa_create
= pnv_chip_power8_isa_create
;
1059 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1060 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1061 dc
->desc
= "PowerNV Chip POWER8";
1063 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1064 &k
->parent_realize
);
1067 static void pnv_chip_power8nvl_class_init(ObjectClass
*klass
, void *data
)
1069 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1070 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1072 k
->chip_type
= PNV_CHIP_POWER8NVL
;
1073 k
->chip_cfam_id
= 0x120d304980000000ull
; /* P8 Naples DD1.0 */
1074 k
->cores_mask
= POWER8_CORE_MASK
;
1075 k
->core_pir
= pnv_chip_core_pir_p8
;
1076 k
->intc_create
= pnv_chip_power8_intc_create
;
1077 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1078 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1079 k
->isa_create
= pnv_chip_power8nvl_isa_create
;
1080 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1081 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1082 dc
->desc
= "PowerNV Chip POWER8NVL";
1084 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1085 &k
->parent_realize
);
1088 static void pnv_chip_power9_instance_init(Object
*obj
)
1090 Pnv9Chip
*chip9
= PNV9_CHIP(obj
);
1092 object_initialize_child(obj
, "xive", &chip9
->xive
, sizeof(chip9
->xive
),
1093 TYPE_PNV_XIVE
, &error_abort
, NULL
);
1094 object_property_add_const_link(OBJECT(&chip9
->xive
), "chip", obj
,
1097 object_initialize_child(obj
, "psi", &chip9
->psi
, sizeof(chip9
->psi
),
1098 TYPE_PNV9_PSI
, &error_abort
, NULL
);
1100 object_initialize_child(obj
, "lpc", &chip9
->lpc
, sizeof(chip9
->lpc
),
1101 TYPE_PNV9_LPC
, &error_abort
, NULL
);
1103 object_initialize_child(obj
, "occ", &chip9
->occ
, sizeof(chip9
->occ
),
1104 TYPE_PNV9_OCC
, &error_abort
, NULL
);
1105 object_property_add_const_link(OBJECT(&chip9
->occ
), "psi",
1106 OBJECT(&chip9
->psi
), &error_abort
);
1108 object_initialize_child(obj
, "homer", &chip9
->homer
, sizeof(chip9
->homer
),
1109 TYPE_PNV9_HOMER
, &error_abort
, NULL
);
1110 object_property_add_const_link(OBJECT(&chip9
->homer
), "chip", obj
,
1114 static void pnv_chip_quad_realize(Pnv9Chip
*chip9
, Error
**errp
)
1116 PnvChip
*chip
= PNV_CHIP(chip9
);
1117 const char *typename
= pnv_chip_core_typename(chip
);
1118 size_t typesize
= object_type_get_instance_size(typename
);
1121 chip9
->nr_quads
= DIV_ROUND_UP(chip
->nr_cores
, 4);
1122 chip9
->quads
= g_new0(PnvQuad
, chip9
->nr_quads
);
1124 for (i
= 0; i
< chip9
->nr_quads
; i
++) {
1126 PnvQuad
*eq
= &chip9
->quads
[i
];
1127 PnvCore
*pnv_core
= PNV_CORE(chip
->cores
+ (i
* 4) * typesize
);
1128 int core_id
= CPU_CORE(pnv_core
)->core_id
;
1130 snprintf(eq_name
, sizeof(eq_name
), "eq[%d]", core_id
);
1131 object_initialize_child(OBJECT(chip
), eq_name
, eq
, sizeof(*eq
),
1132 TYPE_PNV_QUAD
, &error_fatal
, NULL
);
1134 object_property_set_int(OBJECT(eq
), core_id
, "id", &error_fatal
);
1135 object_property_set_bool(OBJECT(eq
), true, "realized", &error_fatal
);
1137 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_EQ_BASE(eq
->id
),
1142 static void pnv_chip_power9_realize(DeviceState
*dev
, Error
**errp
)
1144 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1145 Pnv9Chip
*chip9
= PNV9_CHIP(dev
);
1146 PnvChip
*chip
= PNV_CHIP(dev
);
1147 Pnv9Psi
*psi9
= &chip9
->psi
;
1148 Error
*local_err
= NULL
;
1150 /* XSCOM bridge is first */
1151 pnv_xscom_realize(chip
, PNV9_XSCOM_SIZE
, &local_err
);
1153 error_propagate(errp
, local_err
);
1156 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV9_XSCOM_BASE(chip
));
1158 pcc
->parent_realize(dev
, &local_err
);
1160 error_propagate(errp
, local_err
);
1164 pnv_chip_quad_realize(chip9
, &local_err
);
1166 error_propagate(errp
, local_err
);
1170 /* XIVE interrupt controller (POWER9) */
1171 object_property_set_int(OBJECT(&chip9
->xive
), PNV9_XIVE_IC_BASE(chip
),
1172 "ic-bar", &error_fatal
);
1173 object_property_set_int(OBJECT(&chip9
->xive
), PNV9_XIVE_VC_BASE(chip
),
1174 "vc-bar", &error_fatal
);
1175 object_property_set_int(OBJECT(&chip9
->xive
), PNV9_XIVE_PC_BASE(chip
),
1176 "pc-bar", &error_fatal
);
1177 object_property_set_int(OBJECT(&chip9
->xive
), PNV9_XIVE_TM_BASE(chip
),
1178 "tm-bar", &error_fatal
);
1179 object_property_set_bool(OBJECT(&chip9
->xive
), true, "realized",
1182 error_propagate(errp
, local_err
);
1185 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_XIVE_BASE
,
1186 &chip9
->xive
.xscom_regs
);
1188 /* Processor Service Interface (PSI) Host Bridge */
1189 object_property_set_int(OBJECT(&chip9
->psi
), PNV9_PSIHB_BASE(chip
),
1190 "bar", &error_fatal
);
1191 object_property_set_bool(OBJECT(&chip9
->psi
), true, "realized", &local_err
);
1193 error_propagate(errp
, local_err
);
1196 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PSIHB_BASE
,
1197 &PNV_PSI(psi9
)->xscom_regs
);
1200 object_property_set_link(OBJECT(&chip9
->lpc
), OBJECT(&chip9
->psi
), "psi",
1202 object_property_set_bool(OBJECT(&chip9
->lpc
), true, "realized", &local_err
);
1204 error_propagate(errp
, local_err
);
1207 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip
),
1208 &chip9
->lpc
.xscom_regs
);
1210 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1211 (uint64_t) PNV9_LPCM_BASE(chip
));
1213 /* Create the simplified OCC model */
1214 object_property_set_bool(OBJECT(&chip9
->occ
), true, "realized", &local_err
);
1216 error_propagate(errp
, local_err
);
1219 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_OCC_BASE
, &chip9
->occ
.xscom_regs
);
1221 /* OCC SRAM model */
1222 memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip
),
1223 &chip9
->occ
.sram_regs
);
1226 object_property_set_bool(OBJECT(&chip9
->homer
), true, "realized",
1229 error_propagate(errp
, local_err
);
1232 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip
),
1233 &chip9
->homer
.regs
);
1236 static void pnv_chip_power9_class_init(ObjectClass
*klass
, void *data
)
1238 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1239 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1241 k
->chip_type
= PNV_CHIP_POWER9
;
1242 k
->chip_cfam_id
= 0x220d104900008000ull
; /* P9 Nimbus DD2.0 */
1243 k
->cores_mask
= POWER9_CORE_MASK
;
1244 k
->core_pir
= pnv_chip_core_pir_p9
;
1245 k
->intc_create
= pnv_chip_power9_intc_create
;
1246 k
->intc_reset
= pnv_chip_power9_intc_reset
;
1247 k
->intc_destroy
= pnv_chip_power9_intc_destroy
;
1248 k
->isa_create
= pnv_chip_power9_isa_create
;
1249 k
->dt_populate
= pnv_chip_power9_dt_populate
;
1250 k
->pic_print_info
= pnv_chip_power9_pic_print_info
;
1251 dc
->desc
= "PowerNV Chip POWER9";
1253 device_class_set_parent_realize(dc
, pnv_chip_power9_realize
,
1254 &k
->parent_realize
);
1257 static void pnv_chip_core_sanitize(PnvChip
*chip
, Error
**errp
)
1259 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1263 * No custom mask for this chip, let's use the default one from *
1266 if (!chip
->cores_mask
) {
1267 chip
->cores_mask
= pcc
->cores_mask
;
1270 /* filter alien core ids ! some are reserved */
1271 if ((chip
->cores_mask
& pcc
->cores_mask
) != chip
->cores_mask
) {
1272 error_setg(errp
, "warning: invalid core mask for chip Ox%"PRIx64
" !",
1276 chip
->cores_mask
&= pcc
->cores_mask
;
1278 /* now that we have a sane layout, let check the number of cores */
1279 cores_max
= ctpop64(chip
->cores_mask
);
1280 if (chip
->nr_cores
> cores_max
) {
1281 error_setg(errp
, "warning: too many cores for chip ! Limit is %d",
1287 static void pnv_chip_core_realize(PnvChip
*chip
, Error
**errp
)
1289 MachineState
*ms
= MACHINE(qdev_get_machine());
1290 Error
*error
= NULL
;
1291 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1292 const char *typename
= pnv_chip_core_typename(chip
);
1293 size_t typesize
= object_type_get_instance_size(typename
);
1296 if (!object_class_by_name(typename
)) {
1297 error_setg(errp
, "Unable to find PowerNV CPU Core '%s'", typename
);
1302 pnv_chip_core_sanitize(chip
, &error
);
1304 error_propagate(errp
, error
);
1308 chip
->cores
= g_malloc0(typesize
* chip
->nr_cores
);
1310 for (i
= 0, core_hwid
= 0; (core_hwid
< sizeof(chip
->cores_mask
) * 8)
1311 && (i
< chip
->nr_cores
); core_hwid
++) {
1313 void *pnv_core
= chip
->cores
+ i
* typesize
;
1314 uint64_t xscom_core_base
;
1316 if (!(chip
->cores_mask
& (1ull << core_hwid
))) {
1320 snprintf(core_name
, sizeof(core_name
), "core[%d]", core_hwid
);
1321 object_initialize_child(OBJECT(chip
), core_name
, pnv_core
, typesize
,
1322 typename
, &error_fatal
, NULL
);
1323 object_property_set_int(OBJECT(pnv_core
), ms
->smp
.threads
, "nr-threads",
1325 object_property_set_int(OBJECT(pnv_core
), core_hwid
,
1326 CPU_CORE_PROP_CORE_ID
, &error_fatal
);
1327 object_property_set_int(OBJECT(pnv_core
),
1328 pcc
->core_pir(chip
, core_hwid
),
1329 "pir", &error_fatal
);
1330 object_property_add_const_link(OBJECT(pnv_core
), "chip",
1331 OBJECT(chip
), &error_fatal
);
1332 object_property_set_bool(OBJECT(pnv_core
), true, "realized",
1335 /* Each core has an XSCOM MMIO region */
1336 if (!pnv_chip_is_power9(chip
)) {
1337 xscom_core_base
= PNV_XSCOM_EX_BASE(core_hwid
);
1339 xscom_core_base
= PNV9_XSCOM_EC_BASE(core_hwid
);
1342 pnv_xscom_add_subregion(chip
, xscom_core_base
,
1343 &PNV_CORE(pnv_core
)->xscom_regs
);
1348 static void pnv_chip_realize(DeviceState
*dev
, Error
**errp
)
1350 PnvChip
*chip
= PNV_CHIP(dev
);
1351 Error
*error
= NULL
;
1354 pnv_chip_core_realize(chip
, &error
);
1356 error_propagate(errp
, error
);
1361 static Property pnv_chip_properties
[] = {
1362 DEFINE_PROP_UINT32("chip-id", PnvChip
, chip_id
, 0),
1363 DEFINE_PROP_UINT64("ram-start", PnvChip
, ram_start
, 0),
1364 DEFINE_PROP_UINT64("ram-size", PnvChip
, ram_size
, 0),
1365 DEFINE_PROP_UINT32("nr-cores", PnvChip
, nr_cores
, 1),
1366 DEFINE_PROP_UINT64("cores-mask", PnvChip
, cores_mask
, 0x0),
1367 DEFINE_PROP_END_OF_LIST(),
1370 static void pnv_chip_class_init(ObjectClass
*klass
, void *data
)
1372 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1374 set_bit(DEVICE_CATEGORY_CPU
, dc
->categories
);
1375 dc
->realize
= pnv_chip_realize
;
1376 dc
->props
= pnv_chip_properties
;
1377 dc
->desc
= "PowerNV Chip";
1380 static ICSState
*pnv_ics_get(XICSFabric
*xi
, int irq
)
1382 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
1385 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1386 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
1388 if (ics_valid_irq(&chip8
->psi
.ics
, irq
)) {
1389 return &chip8
->psi
.ics
;
1395 static void pnv_ics_resend(XICSFabric
*xi
)
1397 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
1400 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1401 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
1402 ics_resend(&chip8
->psi
.ics
);
1406 static ICPState
*pnv_icp_get(XICSFabric
*xi
, int pir
)
1408 PowerPCCPU
*cpu
= ppc_get_vcpu_by_pir(pir
);
1410 return cpu
? ICP(pnv_cpu_state(cpu
)->intc
) : NULL
;
1413 static void pnv_pic_print_info(InterruptStatsProvider
*obj
,
1416 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1421 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1423 if (pnv_chip_is_power9(pnv
->chips
[0])) {
1424 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu
)->intc
), mon
);
1426 icp_pic_print_info(ICP(pnv_cpu_state(cpu
)->intc
), mon
);
1430 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1431 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->pic_print_info(pnv
->chips
[i
], mon
);
1435 static void pnv_get_num_chips(Object
*obj
, Visitor
*v
, const char *name
,
1436 void *opaque
, Error
**errp
)
1438 visit_type_uint32(v
, name
, &PNV_MACHINE(obj
)->num_chips
, errp
);
1441 static void pnv_set_num_chips(Object
*obj
, Visitor
*v
, const char *name
,
1442 void *opaque
, Error
**errp
)
1444 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1446 Error
*local_err
= NULL
;
1448 visit_type_uint32(v
, name
, &num_chips
, &local_err
);
1450 error_propagate(errp
, local_err
);
1455 * TODO: should we decide on how many chips we can create based
1456 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1458 if (!is_power_of_2(num_chips
) || num_chips
> 4) {
1459 error_setg(errp
, "invalid number of chips: '%d'", num_chips
);
1463 pnv
->num_chips
= num_chips
;
1466 static void pnv_machine_instance_init(Object
*obj
)
1468 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1472 static void pnv_machine_class_props_init(ObjectClass
*oc
)
1474 object_class_property_add(oc
, "num-chips", "uint32",
1475 pnv_get_num_chips
, pnv_set_num_chips
,
1477 object_class_property_set_description(oc
, "num-chips",
1478 "Specifies the number of processor chips",
1482 static void pnv_machine_power8_class_init(ObjectClass
*oc
, void *data
)
1484 MachineClass
*mc
= MACHINE_CLASS(oc
);
1485 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
1487 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER8";
1488 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
1490 xic
->icp_get
= pnv_icp_get
;
1491 xic
->ics_get
= pnv_ics_get
;
1492 xic
->ics_resend
= pnv_ics_resend
;
1495 static void pnv_machine_power9_class_init(ObjectClass
*oc
, void *data
)
1497 MachineClass
*mc
= MACHINE_CLASS(oc
);
1499 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER9";
1500 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
1502 mc
->alias
= "powernv";
1505 static void pnv_machine_class_init(ObjectClass
*oc
, void *data
)
1507 MachineClass
*mc
= MACHINE_CLASS(oc
);
1508 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
1510 mc
->desc
= "IBM PowerNV (Non-Virtualized)";
1511 mc
->init
= pnv_init
;
1512 mc
->reset
= pnv_reset
;
1513 mc
->max_cpus
= MAX_CPUS
;
1514 /* Pnv provides a AHCI device for storage */
1515 mc
->block_default_type
= IF_IDE
;
1516 mc
->no_parallel
= 1;
1517 mc
->default_boot_order
= NULL
;
1519 * RAM defaults to less than 2048 for 32-bit hosts, and large
1520 * enough to fit the maximum initrd size at it's load address
1522 mc
->default_ram_size
= INITRD_LOAD_ADDR
+ INITRD_MAX_SIZE
;
1523 ispc
->print_info
= pnv_pic_print_info
;
1525 pnv_machine_class_props_init(oc
);
1528 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1531 .class_init = class_initfn, \
1532 .parent = TYPE_PNV8_CHIP, \
1535 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1538 .class_init = class_initfn, \
1539 .parent = TYPE_PNV9_CHIP, \
1542 static const TypeInfo types
[] = {
1544 .name
= MACHINE_TYPE_NAME("powernv9"),
1545 .parent
= TYPE_PNV_MACHINE
,
1546 .class_init
= pnv_machine_power9_class_init
,
1549 .name
= MACHINE_TYPE_NAME("powernv8"),
1550 .parent
= TYPE_PNV_MACHINE
,
1551 .class_init
= pnv_machine_power8_class_init
,
1552 .interfaces
= (InterfaceInfo
[]) {
1553 { TYPE_XICS_FABRIC
},
1558 .name
= TYPE_PNV_MACHINE
,
1559 .parent
= TYPE_MACHINE
,
1561 .instance_size
= sizeof(PnvMachineState
),
1562 .instance_init
= pnv_machine_instance_init
,
1563 .class_init
= pnv_machine_class_init
,
1564 .interfaces
= (InterfaceInfo
[]) {
1565 { TYPE_INTERRUPT_STATS_PROVIDER
},
1570 .name
= TYPE_PNV_CHIP
,
1571 .parent
= TYPE_SYS_BUS_DEVICE
,
1572 .class_init
= pnv_chip_class_init
,
1573 .instance_size
= sizeof(PnvChip
),
1574 .class_size
= sizeof(PnvChipClass
),
1579 * P9 chip and variants
1582 .name
= TYPE_PNV9_CHIP
,
1583 .parent
= TYPE_PNV_CHIP
,
1584 .instance_init
= pnv_chip_power9_instance_init
,
1585 .instance_size
= sizeof(Pnv9Chip
),
1587 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9
, pnv_chip_power9_class_init
),
1590 * P8 chip and variants
1593 .name
= TYPE_PNV8_CHIP
,
1594 .parent
= TYPE_PNV_CHIP
,
1595 .instance_init
= pnv_chip_power8_instance_init
,
1596 .instance_size
= sizeof(Pnv8Chip
),
1598 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8
, pnv_chip_power8_class_init
),
1599 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E
, pnv_chip_power8e_class_init
),
1600 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL
,
1601 pnv_chip_power8nvl_class_init
),