hw/ppc/spapr_cpu_core.c

   1 /*
   2  * sPAPR CPU core device, acts as container of CPU thread devices.
   3  *
   4  * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9 #include "qemu/osdep.h"
  10 #include "hw/cpu/core.h"
  11 #include "hw/ppc/spapr_cpu_core.h"
  12 #include "target/ppc/cpu.h"
  13 #include "hw/ppc/spapr.h"
  14 #include "hw/boards.h"
  15 #include "qapi/error.h"
  16 #include "sysemu/cpus.h"
  17 #include "sysemu/kvm.h"
  18 #include "target/ppc/kvm_ppc.h"
  19 #include "hw/ppc/ppc.h"
  20 #include "target/ppc/mmu-hash64.h"
  21 #include "sysemu/numa.h"
  22 #include "sysemu/hw_accel.h"
  23 #include "qemu/error-report.h"
  24
  25 static void spapr_cpu_reset(void *opaque)
  26 {
  27     PowerPCCPU *cpu = opaque;
  28     CPUState *cs = CPU(cpu);
  29     CPUPPCState *env = &cpu->env;
  30     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  31
  32     cpu_reset(cs);
  33
  34     /* Set compatibility mode to match the boot CPU, which was either set
  35      * by the machine reset code or by CAS. This should never fail.
  36      */
  37     ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);
  38
  39     /* All CPUs start halted.  CPU0 is unhalted from the machine level
  40      * reset code and the rest are explicitly started up by the guest
  41      * using an RTAS call */
  42     cs->halted = 1;
  43
  44     env->spr[SPR_HIOR] = 0;
  45
  46     /* Disable Power-saving mode Exit Cause exceptions for the CPU.
  47      * This can cause issues when rebooting the guest if a secondary
  48      * is awaken */
  49     if (cs != first_cpu) {
  50         env->spr[SPR_LPCR] &= ~pcc->lpcr_pm;
  51     }
  52
  53 }
  54
  55 static void spapr_cpu_destroy(PowerPCCPU *cpu)
  56 {
  57     qemu_unregister_reset(spapr_cpu_reset, cpu);
  58 }
  59
  60 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
  61                            Error **errp)
  62 {
  63     CPUPPCState *env = &cpu->env;
  64
  65     /* Set time-base frequency to 512 MHz */
  66     cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
  67
  68     /* Enable PAPR mode in TCG or KVM */
  69     cpu_ppc_set_papr(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
  70
  71     qemu_register_reset(spapr_cpu_reset, cpu);
  72     spapr_cpu_reset(cpu);
  73 }
  74
  75 /*
  76  * Return the sPAPR CPU core type for @model which essentially is the CPU
  77  * model specified with -cpu cmdline option.
  78  */
  79 const char *spapr_get_cpu_core_type(const char *cpu_type)
  80 {
  81     int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
  82     char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
  83                                       len, cpu_type);
  84     ObjectClass *oc = object_class_by_name(core_type);
  85
  86     g_free(core_type);
  87     if (!oc) {
  88         return NULL;
  89     }
  90
  91     return object_class_get_name(oc);
  92 }
  93
  94 static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp)
  95 {
  96     sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
  97     CPUCore *cc = CPU_CORE(dev);
  98     int i;
  99
 100     for (i = 0; i < cc->nr_threads; i++) {
 101         Object *obj = OBJECT(sc->threads[i]);
 102         DeviceState *dev = DEVICE(obj);
 103         CPUState *cs = CPU(dev);
 104         PowerPCCPU *cpu = POWERPC_CPU(cs);
 105
 106         spapr_cpu_destroy(cpu);
 107         object_unparent(cpu->intc);
 108         cpu_remove_sync(cs);
 109         object_unparent(obj);
 110     }
 111     g_free(sc->threads);
 112 }
 113
 114 static void spapr_cpu_core_realize_child(Object *child,
 115                                          sPAPRMachineState *spapr, Error **errp)
 116 {
 117     Error *local_err = NULL;
 118     CPUState *cs = CPU(child);
 119     PowerPCCPU *cpu = POWERPC_CPU(cs);
 120
 121     object_property_set_bool(child, true, "realized", &local_err);
 122     if (local_err) {
 123         goto error;
 124     }
 125
 126     spapr_cpu_init(spapr, cpu, &local_err);
 127     if (local_err) {
 128         goto error;
 129     }
 130
 131     cpu->intc = icp_create(child, spapr->icp_type, XICS_FABRIC(spapr),
 132                            &local_err);
 133     if (local_err) {
 134         goto error;
 135     }
 136
 137     return;
 138
 139 error:
 140     error_propagate(errp, local_err);
 141 }
 142
 143 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
 144 {
 145     /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
 146      * tries to add a sPAPR CPU core to a non-pseries machine.
 147      */
 148     sPAPRMachineState *spapr =
 149         (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(),
 150                                                   TYPE_SPAPR_MACHINE);
 151     sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 152     sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
 153     CPUCore *cc = CPU_CORE(OBJECT(dev));
 154     Error *local_err = NULL;
 155     Object *obj;
 156     int i, j;
 157
 158     if (!spapr) {
 159         error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
 160         return;
 161     }
 162
 163     sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
 164     for (i = 0; i < cc->nr_threads; i++) {
 165         char id[32];
 166         CPUState *cs;
 167         PowerPCCPU *cpu;
 168
 169         obj = object_new(scc->cpu_type);
 170
 171         cs = CPU(obj);
 172         cpu = sc->threads[i] = POWERPC_CPU(obj);
 173         cs->cpu_index = cc->core_id + i;
 174         spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
 175         if (local_err) {
 176             goto err;
 177         }
 178
 179
 180         /* Set NUMA node for the threads belonged to core  */
 181         cpu->node_id = sc->node_id;
 182
 183         snprintf(id, sizeof(id), "thread[%d]", i);
 184         object_property_add_child(OBJECT(sc), id, obj, &local_err);
 185         if (local_err) {
 186             goto err;
 187         }
 188         object_unref(obj);
 189     }
 190
 191     for (j = 0; j < cc->nr_threads; j++) {
 192         obj = OBJECT(sc->threads[j]);
 193
 194         spapr_cpu_core_realize_child(obj, spapr, &local_err);
 195         if (local_err) {
 196             goto err;
 197         }
 198     }
 199     return;
 200
 201 err:
 202     while (--i >= 0) {
 203         obj = OBJECT(sc->threads[i]);
 204         object_unparent(obj);
 205     }
 206     g_free(sc->threads);
 207     error_propagate(errp, local_err);
 208 }
 209
 210 static Property spapr_cpu_core_properties[] = {
 211     DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID),
 212     DEFINE_PROP_END_OF_LIST()
 213 };
 214
 215 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
 216 {
 217     DeviceClass *dc = DEVICE_CLASS(oc);
 218     sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
 219
 220     dc->realize = spapr_cpu_core_realize;
 221     dc->unrealize = spapr_cpu_core_unrealizefn;
 222     dc->props = spapr_cpu_core_properties;
 223     scc->cpu_type = data;
 224 }
 225
 226 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
 227     {                                                   \
 228         .parent = TYPE_SPAPR_CPU_CORE,                  \
 229         .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
 230         .class_init = spapr_cpu_core_class_init,        \
 231         .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model),    \
 232     }
 233
 234 static const TypeInfo spapr_cpu_core_type_infos[] = {
 235     {
 236         .name = TYPE_SPAPR_CPU_CORE,
 237         .parent = TYPE_CPU_CORE,
 238         .abstract = true,
 239         .instance_size = sizeof(sPAPRCPUCore),
 240         .class_size = sizeof(sPAPRCPUCoreClass),
 241     },
 242     DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
 243     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
 244     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
 245     DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
 246     DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
 247     DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
 248     DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
 249     DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
 250     DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
 251     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
 252     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
 253 #ifdef CONFIG_KVM
 254     DEFINE_SPAPR_CPU_CORE_TYPE("host"),
 255 #endif
 256 };
 257
 258 DEFINE_TYPES(spapr_cpu_core_type_infos)