hw/ppc.c

   1 /*
   2  * QEMU generic PowerPC hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25 #include "m48t59.h"
  26
  27 //#define PPC_DEBUG_IRQ
  28 //#define PPC_DEBUG_TB
  29
  30 extern FILE *logfile;
  31 extern int loglevel;
  32
  33 void ppc_set_irq (CPUState *env, int n_IRQ, int level)
  34 {
  35     if (level) {
  36         env->pending_interrupts |= 1 << n_IRQ;
  37         cpu_interrupt(env, CPU_INTERRUPT_HARD);
  38     } else {
  39         env->pending_interrupts &= ~(1 << n_IRQ);
  40         if (env->pending_interrupts == 0)
  41             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  42     }
  43 #if defined(PPC_DEBUG_IRQ)
  44     if (loglevel & CPU_LOG_INT) {
  45         fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n",
  46                 __func__, env, n_IRQ, level,
  47                 env->pending_interrupts, env->interrupt_request);
  48     }
  49 #endif
  50 }
  51
  52 /* PowerPC 6xx / 7xx internal IRQ controller */
  53 static void ppc6xx_set_irq (void *opaque, int pin, int level)
  54 {
  55     CPUState *env = opaque;
  56     int cur_level;
  57
  58 #if defined(PPC_DEBUG_IRQ)
  59     if (loglevel & CPU_LOG_INT) {
  60         fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
  61                 env, pin, level);
  62     }
  63 #endif
  64     cur_level = (env->irq_input_state >> pin) & 1;
  65     /* Don't generate spurious events */
  66     if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
  67         switch (pin) {
  68         case PPC6xx_INPUT_INT:
  69             /* Level sensitive - active high */
  70 #if defined(PPC_DEBUG_IRQ)
  71             if (loglevel & CPU_LOG_INT) {
  72                 fprintf(logfile, "%s: set the external IRQ state to %d\n",
  73                         __func__, level);
  74             }
  75 #endif
  76             ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
  77             break;
  78         case PPC6xx_INPUT_SMI:
  79             /* Level sensitive - active high */
  80 #if defined(PPC_DEBUG_IRQ)
  81             if (loglevel & CPU_LOG_INT) {
  82                 fprintf(logfile, "%s: set the SMI IRQ state to %d\n",
  83                         __func__, level);
  84             }
  85 #endif
  86             ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
  87             break;
  88         case PPC6xx_INPUT_MCP:
  89             /* Negative edge sensitive */
  90             /* XXX: TODO: actual reaction may depends on HID0 status
  91              *            603/604/740/750: check HID0[EMCP]
  92              */
  93             if (cur_level == 1 && level == 0) {
  94 #if defined(PPC_DEBUG_IRQ)
  95                 if (loglevel & CPU_LOG_INT) {
  96                     fprintf(logfile, "%s: raise machine check state\n",
  97                             __func__);
  98                 }
  99 #endif
 100                 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
 101             }
 102             break;
 103         case PPC6xx_INPUT_CKSTP_IN:
 104             /* Level sensitive - active low */
 105             /* XXX: TODO: relay the signal to CKSTP_OUT pin */
 106             if (level) {
 107 #if defined(PPC_DEBUG_IRQ)
 108                 if (loglevel & CPU_LOG_INT) {
 109                     fprintf(logfile, "%s: stop the CPU\n", __func__);
 110                 }
 111 #endif
 112                 env->halted = 1;
 113             } else {
 114 #if defined(PPC_DEBUG_IRQ)
 115                 if (loglevel & CPU_LOG_INT) {
 116                     fprintf(logfile, "%s: restart the CPU\n", __func__);
 117                 }
 118 #endif
 119                 env->halted = 0;
 120             }
 121             break;
 122         case PPC6xx_INPUT_HRESET:
 123             /* Level sensitive - active low */
 124             if (level) {
 125 #if 0 // XXX: TOFIX
 126 #if defined(PPC_DEBUG_IRQ)
 127                 if (loglevel & CPU_LOG_INT) {
 128                     fprintf(logfile, "%s: reset the CPU\n", __func__);
 129                 }
 130 #endif
 131                 cpu_reset(env);
 132 #endif
 133             }
 134             break;
 135         case PPC6xx_INPUT_SRESET:
 136 #if defined(PPC_DEBUG_IRQ)
 137             if (loglevel & CPU_LOG_INT) {
 138                 fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
 139                         __func__, level);
 140             }
 141 #endif
 142             ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
 143             break;
 144         default:
 145             /* Unknown pin - do nothing */
 146 #if defined(PPC_DEBUG_IRQ)
 147             if (loglevel & CPU_LOG_INT) {
 148                 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
 149             }
 150 #endif
 151             return;
 152         }
 153         if (level)
 154             env->irq_input_state |= 1 << pin;
 155         else
 156             env->irq_input_state &= ~(1 << pin);
 157     }
 158 }
 159
 160 void ppc6xx_irq_init (CPUState *env)
 161 {
 162     env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6);
 163 }
 164
 165 /* PowerPC 970 internal IRQ controller */
 166 static void ppc970_set_irq (void *opaque, int pin, int level)
 167 {
 168     CPUState *env = opaque;
 169     int cur_level;
 170
 171 #if defined(PPC_DEBUG_IRQ)
 172     if (loglevel & CPU_LOG_INT) {
 173         fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
 174                 env, pin, level);
 175     }
 176 #endif
 177     cur_level = (env->irq_input_state >> pin) & 1;
 178     /* Don't generate spurious events */
 179     if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
 180         switch (pin) {
 181         case PPC970_INPUT_INT:
 182             /* Level sensitive - active high */
 183 #if defined(PPC_DEBUG_IRQ)
 184             if (loglevel & CPU_LOG_INT) {
 185                 fprintf(logfile, "%s: set the external IRQ state to %d\n",
 186                         __func__, level);
 187             }
 188 #endif
 189             ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
 190             break;
 191         case PPC970_INPUT_THINT:
 192             /* Level sensitive - active high */
 193 #if defined(PPC_DEBUG_IRQ)
 194             if (loglevel & CPU_LOG_INT) {
 195                 fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__,
 196                         level);
 197             }
 198 #endif
 199             ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
 200             break;
 201         case PPC970_INPUT_MCP:
 202             /* Negative edge sensitive */
 203             /* XXX: TODO: actual reaction may depends on HID0 status
 204              *            603/604/740/750: check HID0[EMCP]
 205              */
 206             if (cur_level == 1 && level == 0) {
 207 #if defined(PPC_DEBUG_IRQ)
 208                 if (loglevel & CPU_LOG_INT) {
 209                     fprintf(logfile, "%s: raise machine check state\n",
 210                             __func__);
 211                 }
 212 #endif
 213                 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
 214             }
 215             break;
 216         case PPC970_INPUT_CKSTP:
 217             /* Level sensitive - active low */
 218             /* XXX: TODO: relay the signal to CKSTP_OUT pin */
 219             if (level) {
 220 #if defined(PPC_DEBUG_IRQ)
 221                 if (loglevel & CPU_LOG_INT) {
 222                     fprintf(logfile, "%s: stop the CPU\n", __func__);
 223                 }
 224 #endif
 225                 env->halted = 1;
 226             } else {
 227 #if defined(PPC_DEBUG_IRQ)
 228                 if (loglevel & CPU_LOG_INT) {
 229                     fprintf(logfile, "%s: restart the CPU\n", __func__);
 230                 }
 231 #endif
 232                 env->halted = 0;
 233             }
 234             break;
 235         case PPC970_INPUT_HRESET:
 236             /* Level sensitive - active low */
 237             if (level) {
 238 #if 0 // XXX: TOFIX
 239 #if defined(PPC_DEBUG_IRQ)
 240                 if (loglevel & CPU_LOG_INT) {
 241                     fprintf(logfile, "%s: reset the CPU\n", __func__);
 242                 }
 243 #endif
 244                 cpu_reset(env);
 245 #endif
 246             }
 247             break;
 248         case PPC970_INPUT_SRESET:
 249 #if defined(PPC_DEBUG_IRQ)
 250             if (loglevel & CPU_LOG_INT) {
 251                 fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
 252                         __func__, level);
 253             }
 254 #endif
 255             ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
 256             break;
 257         case PPC970_INPUT_TBEN:
 258 #if defined(PPC_DEBUG_IRQ)
 259             if (loglevel & CPU_LOG_INT) {
 260                 fprintf(logfile, "%s: set the TBEN state to %d\n", __func__,
 261                         level);
 262             }
 263 #endif
 264             /* XXX: TODO */
 265             break;
 266         default:
 267             /* Unknown pin - do nothing */
 268 #if defined(PPC_DEBUG_IRQ)
 269             if (loglevel & CPU_LOG_INT) {
 270                 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
 271             }
 272 #endif
 273             return;
 274         }
 275         if (level)
 276             env->irq_input_state |= 1 << pin;
 277         else
 278             env->irq_input_state &= ~(1 << pin);
 279     }
 280 }
 281
 282 void ppc970_irq_init (CPUState *env)
 283 {
 284     env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
 285 }
 286
 287 /* PowerPC 405 internal IRQ controller */
 288 static void ppc405_set_irq (void *opaque, int pin, int level)
 289 {
 290     CPUState *env = opaque;
 291     int cur_level;
 292
 293 #if defined(PPC_DEBUG_IRQ)
 294     if (loglevel & CPU_LOG_INT) {
 295         fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
 296                 env, pin, level);
 297     }
 298 #endif
 299     cur_level = (env->irq_input_state >> pin) & 1;
 300     /* Don't generate spurious events */
 301     if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
 302         switch (pin) {
 303         case PPC405_INPUT_RESET_SYS:
 304             if (level) {
 305 #if defined(PPC_DEBUG_IRQ)
 306                 if (loglevel & CPU_LOG_INT) {
 307                     fprintf(logfile, "%s: reset the PowerPC system\n",
 308                             __func__);
 309                 }
 310 #endif
 311                 ppc40x_system_reset(env);
 312             }
 313             break;
 314         case PPC405_INPUT_RESET_CHIP:
 315             if (level) {
 316 #if defined(PPC_DEBUG_IRQ)
 317                 if (loglevel & CPU_LOG_INT) {
 318                     fprintf(logfile, "%s: reset the PowerPC chip\n", __func__);
 319                 }
 320 #endif
 321                 ppc40x_chip_reset(env);
 322             }
 323             break;
 324             /* No break here */
 325         case PPC405_INPUT_RESET_CORE:
 326             /* XXX: TODO: update DBSR[MRR] */
 327             if (level) {
 328 #if defined(PPC_DEBUG_IRQ)
 329                 if (loglevel & CPU_LOG_INT) {
 330                     fprintf(logfile, "%s: reset the PowerPC core\n", __func__);
 331                 }
 332 #endif
 333                 ppc40x_core_reset(env);
 334             }
 335             break;
 336         case PPC405_INPUT_CINT:
 337             /* Level sensitive - active high */
 338 #if defined(PPC_DEBUG_IRQ)
 339             if (loglevel & CPU_LOG_INT) {
 340                 fprintf(logfile, "%s: set the critical IRQ state to %d\n",
 341                         __func__, level);
 342             }
 343 #endif
 344             /* XXX: TOFIX */
 345             ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
 346             break;
 347         case PPC405_INPUT_INT:
 348             /* Level sensitive - active high */
 349 #if defined(PPC_DEBUG_IRQ)
 350             if (loglevel & CPU_LOG_INT) {
 351                 fprintf(logfile, "%s: set the external IRQ state to %d\n",
 352                         __func__, level);
 353             }
 354 #endif
 355             ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
 356             break;
 357         case PPC405_INPUT_HALT:
 358             /* Level sensitive - active low */
 359             if (level) {
 360 #if defined(PPC_DEBUG_IRQ)
 361                 if (loglevel & CPU_LOG_INT) {
 362                     fprintf(logfile, "%s: stop the CPU\n", __func__);
 363                 }
 364 #endif
 365                 env->halted = 1;
 366             } else {
 367 #if defined(PPC_DEBUG_IRQ)
 368                 if (loglevel & CPU_LOG_INT) {
 369                     fprintf(logfile, "%s: restart the CPU\n", __func__);
 370                 }
 371 #endif
 372                 env->halted = 0;
 373             }
 374             break;
 375         case PPC405_INPUT_DEBUG:
 376             /* Level sensitive - active high */
 377 #if defined(PPC_DEBUG_IRQ)
 378             if (loglevel & CPU_LOG_INT) {
 379                 fprintf(logfile, "%s: set the debug pin state to %d\n",
 380                         __func__, level);
 381             }
 382 #endif
 383             ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
 384             break;
 385         default:
 386             /* Unknown pin - do nothing */
 387 #if defined(PPC_DEBUG_IRQ)
 388             if (loglevel & CPU_LOG_INT) {
 389                 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
 390             }
 391 #endif
 392             return;
 393         }
 394         if (level)
 395             env->irq_input_state |= 1 << pin;
 396         else
 397             env->irq_input_state &= ~(1 << pin);
 398     }
 399 }
 400
 401 void ppc405_irq_init (CPUState *env)
 402 {
 403     env->irq_inputs = (void **)qemu_allocate_irqs(&ppc405_set_irq, env, 7);
 404 }
 405
 406 /*****************************************************************************/
 407 /* PowerPC time base and decrementer emulation */
 408 struct ppc_tb_t {
 409     /* Time base management */
 410     int64_t  tb_offset;    /* Compensation               */
 411     uint32_t tb_freq;      /* TB frequency               */
 412     /* Decrementer management */
 413     uint64_t decr_next;    /* Tick for next decr interrupt  */
 414     struct QEMUTimer *decr_timer;
 415 #if defined(TARGET_PPC64H)
 416     /* Hypervisor decrementer management */
 417     uint64_t hdecr_next;    /* Tick for next hdecr interrupt  */
 418     struct QEMUTimer *hdecr_timer;
 419     uint64_t purr_load;
 420     uint64_t purr_start;
 421 #endif
 422     void *opaque;
 423 };
 424
 425 static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env)
 426 {
 427     /* TB time in tb periods */
 428     return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
 429                     tb_env->tb_freq, ticks_per_sec);
 430 }
 431
 432 uint32_t cpu_ppc_load_tbl (CPUState *env)
 433 {
 434     ppc_tb_t *tb_env = env->tb_env;
 435     uint64_t tb;
 436
 437     tb = cpu_ppc_get_tb(tb_env);
 438 #ifdef PPC_DEBUG_TB
 439     {
 440         static int last_time;
 441         int now;
 442         now = time(NULL);
 443         if (last_time != now) {
 444             last_time = now;
 445             if (loglevel != 0) {
 446                 fprintf(logfile, "%s: tb=0x%016lx %d %08lx\n",
 447                         __func__, tb, now, tb_env->tb_offset);
 448             }
 449         }
 450     }
 451 #endif
 452
 453     return tb & 0xFFFFFFFF;
 454 }
 455
 456 uint32_t cpu_ppc_load_tbu (CPUState *env)
 457 {
 458     ppc_tb_t *tb_env = env->tb_env;
 459     uint64_t tb;
 460
 461     tb = cpu_ppc_get_tb(tb_env);
 462 #if defined(PPC_DEBUG_TB)
 463     if (loglevel != 0) {
 464         fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
 465     }
 466 #endif
 467
 468     return tb >> 32;
 469 }
 470
 471 static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value)
 472 {
 473     tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
 474         - qemu_get_clock(vm_clock);
 475 #ifdef PPC_DEBUG_TB
 476     if (loglevel != 0) {
 477         fprintf(logfile, "%s: tb=0x%016lx offset=%08lx\n", __func__, value,
 478                 tb_env->tb_offset);
 479     }
 480 #endif
 481 }
 482
 483 void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
 484 {
 485     ppc_tb_t *tb_env = env->tb_env;
 486
 487     cpu_ppc_store_tb(tb_env,
 488                      ((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
 489 }
 490
 491 void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
 492 {
 493     ppc_tb_t *tb_env = env->tb_env;
 494
 495     cpu_ppc_store_tb(tb_env,
 496                      ((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
 497 }
 498
 499 static inline uint32_t _cpu_ppc_load_decr (CPUState *env, uint64_t *next)
 500 {
 501     ppc_tb_t *tb_env = env->tb_env;
 502     uint32_t decr;
 503     int64_t diff;
 504
 505     diff = tb_env->decr_next - qemu_get_clock(vm_clock);
 506     if (diff >= 0)
 507         decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
 508     else
 509         decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
 510 #if defined(PPC_DEBUG_TB)
 511     if (loglevel != 0) {
 512         fprintf(logfile, "%s: 0x%08x\n", __func__, decr);
 513     }
 514 #endif
 515
 516     return decr;
 517 }
 518
 519 uint32_t cpu_ppc_load_decr (CPUState *env)
 520 {
 521     ppc_tb_t *tb_env = env->tb_env;
 522
 523     return _cpu_ppc_load_decr(env, &tb_env->decr_next);
 524 }
 525
 526 #if defined(TARGET_PPC64H)
 527 uint32_t cpu_ppc_load_hdecr (CPUState *env)
 528 {
 529     ppc_tb_t *tb_env = env->tb_env;
 530
 531     return _cpu_ppc_load_decr(env, &tb_env->hdecr_next);
 532 }
 533
 534 uint64_t cpu_ppc_load_purr (CPUState *env)
 535 {
 536     ppc_tb_t *tb_env = env->tb_env;
 537     uint64_t diff;
 538
 539     diff = qemu_get_clock(vm_clock) - tb_env->purr_start;
 540
 541     return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
 542 }
 543 #endif /* defined(TARGET_PPC64H) */
 544
 545 /* When decrementer expires,
 546  * all we need to do is generate or queue a CPU exception
 547  */
 548 static inline void cpu_ppc_decr_excp (CPUState *env)
 549 {
 550     /* Raise it */
 551 #ifdef PPC_DEBUG_TB
 552     if (loglevel != 0) {
 553         fprintf(logfile, "raise decrementer exception\n");
 554     }
 555 #endif
 556     ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
 557 }
 558
 559 static inline void cpu_ppc_hdecr_excp (CPUState *env)
 560 {
 561     /* Raise it */
 562 #ifdef PPC_DEBUG_TB
 563     if (loglevel != 0) {
 564         fprintf(logfile, "raise decrementer exception\n");
 565     }
 566 #endif
 567     ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
 568 }
 569
 570 static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
 571                                  struct QEMUTimer *timer,
 572                                  void (*raise_excp)(CPUState *),
 573                                  uint32_t decr, uint32_t value,
 574                                  int is_excp)
 575 {
 576     ppc_tb_t *tb_env = env->tb_env;
 577     uint64_t now, next;
 578
 579 #ifdef PPC_DEBUG_TB
 580     if (loglevel != 0) {
 581         fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value);
 582     }
 583 #endif
 584     now = qemu_get_clock(vm_clock);
 585     next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
 586     if (is_excp)
 587         next += *nextp - now;
 588     if (next == now)
 589         next++;
 590     *nextp = next;
 591     /* Adjust timer */
 592     qemu_mod_timer(timer, next);
 593     /* If we set a negative value and the decrementer was positive,
 594      * raise an exception.
 595      */
 596     if ((value & 0x80000000) && !(decr & 0x80000000))
 597         (*raise_excp)(env);
 598 }
 599
 600
 601 static inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
 602                                         uint32_t value, int is_excp)
 603 {
 604     ppc_tb_t *tb_env = env->tb_env;
 605
 606     __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer,
 607                          &cpu_ppc_decr_excp, decr, value, is_excp);
 608 }
 609
 610 void cpu_ppc_store_decr (CPUState *env, uint32_t value)
 611 {
 612     _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
 613 }
 614
 615 static void cpu_ppc_decr_cb (void *opaque)
 616 {
 617     _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
 618 }
 619
 620 #if defined(TARGET_PPC64H)
 621 static inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
 622                                         uint32_t value, int is_excp)
 623 {
 624     ppc_tb_t *tb_env = env->tb_env;
 625
 626     __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
 627                          &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
 628 }
 629
 630 void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
 631 {
 632     _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
 633 }
 634
 635 static void cpu_ppc_hdecr_cb (void *opaque)
 636 {
 637     _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1);
 638 }
 639
 640 void cpu_ppc_store_purr (CPUState *env, uint64_t value)
 641 {
 642     ppc_tb_t *tb_env = env->tb_env;
 643
 644     tb_env->purr_load = value;
 645     tb_env->purr_start = qemu_get_clock(vm_clock);
 646 }
 647 #endif /* defined(TARGET_PPC64H) */
 648
 649 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
 650 {
 651     CPUState *env = opaque;
 652     ppc_tb_t *tb_env = env->tb_env;
 653
 654     tb_env->tb_freq = freq;
 655     /* There is a bug in Linux 2.4 kernels:
 656      * if a decrementer exception is pending when it enables msr_ee at startup,
 657      * it's not ready to handle it...
 658      */
 659     _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
 660 #if defined(TARGET_PPC64H)
 661     _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
 662     cpu_ppc_store_purr(env, 0x0000000000000000ULL);
 663 #endif /* defined(TARGET_PPC64H) */
 664 }
 665
 666 /* Set up (once) timebase frequency (in Hz) */
 667 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
 668 {
 669     ppc_tb_t *tb_env;
 670
 671     tb_env = qemu_mallocz(sizeof(ppc_tb_t));
 672     if (tb_env == NULL)
 673         return NULL;
 674     env->tb_env = tb_env;
 675     /* Create new timer */
 676     tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
 677 #if defined(TARGET_PPC64H)
 678     tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);
 679 #endif /* defined(TARGET_PPC64H) */
 680     cpu_ppc_set_tb_clk(env, freq);
 681
 682     return &cpu_ppc_set_tb_clk;
 683 }
 684
 685 /* Specific helpers for POWER & PowerPC 601 RTC */
 686 clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
 687 {
 688     return cpu_ppc_tb_init(env, 7812500);
 689 }
 690
 691 void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
 692 __attribute__ (( alias ("cpu_ppc_store_tbu") ));
 693
 694 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
 695 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
 696
 697 void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
 698 {
 699     cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
 700 }
 701
 702 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
 703 {
 704     return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
 705 }
 706
 707 /*****************************************************************************/
 708 /* Embedded PowerPC timers */
 709
 710 /* PIT, FIT & WDT */
 711 typedef struct ppcemb_timer_t ppcemb_timer_t;
 712 struct ppcemb_timer_t {
 713     uint64_t pit_reload;  /* PIT auto-reload value        */
 714     uint64_t fit_next;    /* Tick for next FIT interrupt  */
 715     struct QEMUTimer *fit_timer;
 716     uint64_t wdt_next;    /* Tick for next WDT interrupt  */
 717     struct QEMUTimer *wdt_timer;
 718 };
 719
 720 /* Fixed interval timer */
 721 static void cpu_4xx_fit_cb (void *opaque)
 722 {
 723     CPUState *env;
 724     ppc_tb_t *tb_env;
 725     ppcemb_timer_t *ppcemb_timer;
 726     uint64_t now, next;
 727
 728     env = opaque;
 729     tb_env = env->tb_env;
 730     ppcemb_timer = tb_env->opaque;
 731     now = qemu_get_clock(vm_clock);
 732     switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
 733     case 0:
 734         next = 1 << 9;
 735         break;
 736     case 1:
 737         next = 1 << 13;
 738         break;
 739     case 2:
 740         next = 1 << 17;
 741         break;
 742     case 3:
 743         next = 1 << 21;
 744         break;
 745     default:
 746         /* Cannot occur, but makes gcc happy */
 747         return;
 748     }
 749     next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
 750     if (next == now)
 751         next++;
 752     qemu_mod_timer(ppcemb_timer->fit_timer, next);
 753     env->spr[SPR_40x_TSR] |= 1 << 26;
 754     if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
 755         ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
 756 #ifdef PPC_DEBUG_TB
 757     if (loglevel != 0) {
 758         fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
 759                 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
 760                 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
 761     }
 762 #endif
 763 }
 764
 765 /* Programmable interval timer */
 766 static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
 767 {
 768     ppcemb_timer_t *ppcemb_timer;
 769     uint64_t now, next;
 770
 771     ppcemb_timer = tb_env->opaque;
 772     if (ppcemb_timer->pit_reload <= 1 ||
 773         !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
 774         (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
 775         /* Stop PIT */
 776 #ifdef PPC_DEBUG_TB
 777         if (loglevel != 0) {
 778             fprintf(logfile, "%s: stop PIT\n", __func__);
 779         }
 780 #endif
 781         qemu_del_timer(tb_env->decr_timer);
 782     } else {
 783 #ifdef PPC_DEBUG_TB
 784         if (loglevel != 0) {
 785             fprintf(logfile, "%s: start PIT 0x" REGX "\n",
 786                     __func__, ppcemb_timer->pit_reload);
 787         }
 788 #endif
 789         now = qemu_get_clock(vm_clock);
 790         next = now + muldiv64(ppcemb_timer->pit_reload,
 791                               ticks_per_sec, tb_env->tb_freq);
 792         if (is_excp)
 793             next += tb_env->decr_next - now;
 794         if (next == now)
 795             next++;
 796         qemu_mod_timer(tb_env->decr_timer, next);
 797         tb_env->decr_next = next;
 798     }
 799 }
 800
 801 static void cpu_4xx_pit_cb (void *opaque)
 802 {
 803     CPUState *env;
 804     ppc_tb_t *tb_env;
 805     ppcemb_timer_t *ppcemb_timer;
 806
 807     env = opaque;
 808     tb_env = env->tb_env;
 809     ppcemb_timer = tb_env->opaque;
 810     env->spr[SPR_40x_TSR] |= 1 << 27;
 811     if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
 812         ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
 813     start_stop_pit(env, tb_env, 1);
 814 #ifdef PPC_DEBUG_TB
 815     if (loglevel != 0) {
 816         fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
 817                 "%016" PRIx64 "\n", __func__,
 818                 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
 819                 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
 820                 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
 821                 ppcemb_timer->pit_reload);
 822     }
 823 #endif
 824 }
 825
 826 /* Watchdog timer */
 827 static void cpu_4xx_wdt_cb (void *opaque)
 828 {
 829     CPUState *env;
 830     ppc_tb_t *tb_env;
 831     ppcemb_timer_t *ppcemb_timer;
 832     uint64_t now, next;
 833
 834     env = opaque;
 835     tb_env = env->tb_env;
 836     ppcemb_timer = tb_env->opaque;
 837     now = qemu_get_clock(vm_clock);
 838     switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
 839     case 0:
 840         next = 1 << 17;
 841         break;
 842     case 1:
 843         next = 1 << 21;
 844         break;
 845     case 2:
 846         next = 1 << 25;
 847         break;
 848     case 3:
 849         next = 1 << 29;
 850         break;
 851     default:
 852         /* Cannot occur, but makes gcc happy */
 853         return;
 854     }
 855     next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
 856     if (next == now)
 857         next++;
 858 #ifdef PPC_DEBUG_TB
 859     if (loglevel != 0) {
 860         fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
 861                 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
 862     }
 863 #endif
 864     switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
 865     case 0x0:
 866     case 0x1:
 867         qemu_mod_timer(ppcemb_timer->wdt_timer, next);
 868         ppcemb_timer->wdt_next = next;
 869         env->spr[SPR_40x_TSR] |= 1 << 31;
 870         break;
 871     case 0x2:
 872         qemu_mod_timer(ppcemb_timer->wdt_timer, next);
 873         ppcemb_timer->wdt_next = next;
 874         env->spr[SPR_40x_TSR] |= 1 << 30;
 875         if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)
 876             ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
 877         break;
 878     case 0x3:
 879         env->spr[SPR_40x_TSR] &= ~0x30000000;
 880         env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
 881         switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
 882         case 0x0:
 883             /* No reset */
 884             break;
 885         case 0x1: /* Core reset */
 886             ppc40x_core_reset(env);
 887             break;
 888         case 0x2: /* Chip reset */
 889             ppc40x_chip_reset(env);
 890             break;
 891         case 0x3: /* System reset */
 892             ppc40x_system_reset(env);
 893             break;
 894         }
 895     }
 896 }
 897
 898 void store_40x_pit (CPUState *env, target_ulong val)
 899 {
 900     ppc_tb_t *tb_env;
 901     ppcemb_timer_t *ppcemb_timer;
 902
 903     tb_env = env->tb_env;
 904     ppcemb_timer = tb_env->opaque;
 905 #ifdef PPC_DEBUG_TB
 906     if (loglevel != 0) {
 907         fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
 908     }
 909 #endif
 910     ppcemb_timer->pit_reload = val;
 911     start_stop_pit(env, tb_env, 0);
 912 }
 913
 914 target_ulong load_40x_pit (CPUState *env)
 915 {
 916     return cpu_ppc_load_decr(env);
 917 }
 918
 919 void store_booke_tsr (CPUState *env, target_ulong val)
 920 {
 921 #ifdef PPC_DEBUG_TB
 922     if (loglevel != 0) {
 923         fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
 924     }
 925 #endif
 926     env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
 927     if (val & 0x80000000)
 928         ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
 929 }
 930
 931 void store_booke_tcr (CPUState *env, target_ulong val)
 932 {
 933     ppc_tb_t *tb_env;
 934
 935     tb_env = env->tb_env;
 936 #ifdef PPC_DEBUG_TB
 937     if (loglevel != 0) {
 938         fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
 939     }
 940 #endif
 941     env->spr[SPR_40x_TCR] = val & 0xFFC00000;
 942     start_stop_pit(env, tb_env, 1);
 943     cpu_4xx_wdt_cb(env);
 944 }
 945
 946 static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq)
 947 {
 948     CPUState *env = opaque;
 949     ppc_tb_t *tb_env = env->tb_env;
 950
 951 #ifdef PPC_DEBUG_TB
 952     if (loglevel != 0) {
 953         fprintf(logfile, "%s set new frequency to %u\n", __func__, freq);
 954     }
 955 #endif
 956     tb_env->tb_freq = freq;
 957     /* XXX: we should also update all timers */
 958 }
 959
 960 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
 961 {
 962     ppc_tb_t *tb_env;
 963     ppcemb_timer_t *ppcemb_timer;
 964
 965     tb_env = qemu_mallocz(sizeof(ppc_tb_t));
 966     if (tb_env == NULL) {
 967         return NULL;
 968     }
 969     env->tb_env = tb_env;
 970     ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
 971     tb_env->tb_freq = freq;
 972     tb_env->opaque = ppcemb_timer;
 973 #ifdef PPC_DEBUG_TB
 974     if (loglevel != 0) {
 975         fprintf(logfile, "%s %p %p %p\n", __func__, tb_env, ppcemb_timer,
 976                 &ppc_emb_set_tb_clk);
 977     }
 978 #endif
 979     if (ppcemb_timer != NULL) {
 980         /* We use decr timer for PIT */
 981         tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);
 982         ppcemb_timer->fit_timer =
 983             qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env);
 984         ppcemb_timer->wdt_timer =
 985             qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env);
 986     }
 987
 988     return &ppc_emb_set_tb_clk;
 989 }
 990
 991 /*****************************************************************************/
 992 /* Embedded PowerPC Device Control Registers */
 993 typedef struct ppc_dcrn_t ppc_dcrn_t;
 994 struct ppc_dcrn_t {
 995     dcr_read_cb dcr_read;
 996     dcr_write_cb dcr_write;
 997     void *opaque;
 998 };
 999
1000 /* XXX: on 460, DCR addresses are 32 bits wide,
1001  *      using DCRIPR to get the 22 upper bits of the DCR address
1002  */
1003 #define DCRN_NB 1024
1004 struct ppc_dcr_t {
1005     ppc_dcrn_t dcrn[DCRN_NB];
1006     int (*read_error)(int dcrn);
1007     int (*write_error)(int dcrn);
1008 };
1009
1010 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
1011 {
1012     ppc_dcrn_t *dcr;
1013
1014     if (dcrn < 0 || dcrn >= DCRN_NB)
1015         goto error;
1016     dcr = &dcr_env->dcrn[dcrn];
1017     if (dcr->dcr_read == NULL)
1018         goto error;
1019     *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1020
1021     return 0;
1022
1023  error:
1024     if (dcr_env->read_error != NULL)
1025         return (*dcr_env->read_error)(dcrn);
1026
1027     return -1;
1028 }
1029
1030 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
1031 {
1032     ppc_dcrn_t *dcr;
1033
1034     if (dcrn < 0 || dcrn >= DCRN_NB)
1035         goto error;
1036     dcr = &dcr_env->dcrn[dcrn];
1037     if (dcr->dcr_write == NULL)
1038         goto error;
1039     (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1040
1041     return 0;
1042
1043  error:
1044     if (dcr_env->write_error != NULL)
1045         return (*dcr_env->write_error)(dcrn);
1046
1047     return -1;
1048 }
1049
1050 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1051                       dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1052 {
1053     ppc_dcr_t *dcr_env;
1054     ppc_dcrn_t *dcr;
1055
1056     dcr_env = env->dcr_env;
1057     if (dcr_env == NULL)
1058         return -1;
1059     if (dcrn < 0 || dcrn >= DCRN_NB)
1060         return -1;
1061     dcr = &dcr_env->dcrn[dcrn];
1062     if (dcr->opaque != NULL ||
1063         dcr->dcr_read != NULL ||
1064         dcr->dcr_write != NULL)
1065         return -1;
1066     dcr->opaque = opaque;
1067     dcr->dcr_read = dcr_read;
1068     dcr->dcr_write = dcr_write;
1069
1070     return 0;
1071 }
1072
1073 int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
1074                   int (*write_error)(int dcrn))
1075 {
1076     ppc_dcr_t *dcr_env;
1077
1078     dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
1079     if (dcr_env == NULL)
1080         return -1;
1081     dcr_env->read_error = read_error;
1082     dcr_env->write_error = write_error;
1083     env->dcr_env = dcr_env;
1084
1085     return 0;
1086 }
1087
1088
1089 #if 0
1090 /*****************************************************************************/
1091 /* Handle system reset (for now, just stop emulation) */
1092 void cpu_ppc_reset (CPUState *env)
1093 {
1094     printf("Reset asked... Stop emulation\n");
1095     abort();
1096 }
1097 #endif
1098
1099 /*****************************************************************************/
1100 /* Debug port */
1101 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
1102 {
1103     addr &= 0xF;
1104     switch (addr) {
1105     case 0:
1106         printf("%c", val);
1107         break;
1108     case 1:
1109         printf("\n");
1110         fflush(stdout);
1111         break;
1112     case 2:
1113         printf("Set loglevel to %04x\n", val);
1114         cpu_set_log(val | 0x100);
1115         break;
1116     }
1117 }
1118
1119 /*****************************************************************************/
1120 /* NVRAM helpers */
1121 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
1122 {
1123     m48t59_write(nvram, addr, value);
1124 }
1125
1126 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
1127 {
1128     return m48t59_read(nvram, addr);
1129 }
1130
1131 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
1132 {
1133     m48t59_write(nvram, addr, value >> 8);
1134     m48t59_write(nvram, addr + 1, value & 0xFF);
1135 }
1136
1137 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
1138 {
1139     uint16_t tmp;
1140
1141     tmp = m48t59_read(nvram, addr) << 8;
1142     tmp |= m48t59_read(nvram, addr + 1);
1143     return tmp;
1144 }
1145
1146 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
1147 {
1148     m48t59_write(nvram, addr, value >> 24);
1149     m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
1150     m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
1151     m48t59_write(nvram, addr + 3, value & 0xFF);
1152 }
1153
1154 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
1155 {
1156     uint32_t tmp;
1157
1158     tmp = m48t59_read(nvram, addr) << 24;
1159     tmp |= m48t59_read(nvram, addr + 1) << 16;
1160     tmp |= m48t59_read(nvram, addr + 2) << 8;
1161     tmp |= m48t59_read(nvram, addr + 3);
1162
1163     return tmp;
1164 }
1165
1166 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1167                        const unsigned char *str, uint32_t max)
1168 {
1169     int i;
1170
1171     for (i = 0; i < max && str[i] != '\0'; i++) {
1172         m48t59_write(nvram, addr + i, str[i]);
1173     }
1174     m48t59_write(nvram, addr + max - 1, '\0');
1175 }
1176
1177 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
1178 {
1179     int i;
1180
1181     memset(dst, 0, max);
1182     for (i = 0; i < max; i++) {
1183         dst[i] = NVRAM_get_byte(nvram, addr + i);
1184         if (dst[i] == '\0')
1185             break;
1186     }
1187
1188     return i;
1189 }
1190
1191 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
1192 {
1193     uint16_t tmp;
1194     uint16_t pd, pd1, pd2;
1195
1196     tmp = prev >> 8;
1197     pd = prev ^ value;
1198     pd1 = pd & 0x000F;
1199     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
1200     tmp ^= (pd1 << 3) | (pd1 << 8);
1201     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
1202
1203     return tmp;
1204 }
1205
1206 uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
1207 {
1208     uint32_t i;
1209     uint16_t crc = 0xFFFF;
1210     int odd;
1211
1212     odd = count & 1;
1213     count &= ~1;
1214     for (i = 0; i != count; i++) {
1215         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
1216     }
1217     if (odd) {
1218         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
1219     }
1220
1221     return crc;
1222 }
1223
1224 #define CMDLINE_ADDR 0x017ff000
1225
1226 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1227                           const unsigned char *arch,
1228                           uint32_t RAM_size, int boot_device,
1229                           uint32_t kernel_image, uint32_t kernel_size,
1230                           const char *cmdline,
1231                           uint32_t initrd_image, uint32_t initrd_size,
1232                           uint32_t NVRAM_image,
1233                           int width, int height, int depth)
1234 {
1235     uint16_t crc;
1236
1237     /* Set parameters for Open Hack'Ware BIOS */
1238     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
1239     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
1240     NVRAM_set_word(nvram,   0x14, NVRAM_size);
1241     NVRAM_set_string(nvram, 0x20, arch, 16);
1242     NVRAM_set_lword(nvram,  0x30, RAM_size);
1243     NVRAM_set_byte(nvram,   0x34, boot_device);
1244     NVRAM_set_lword(nvram,  0x38, kernel_image);
1245     NVRAM_set_lword(nvram,  0x3C, kernel_size);
1246     if (cmdline) {
1247         /* XXX: put the cmdline in NVRAM too ? */
1248         strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
1249         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
1250         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
1251     } else {
1252         NVRAM_set_lword(nvram,  0x40, 0);
1253         NVRAM_set_lword(nvram,  0x44, 0);
1254     }
1255     NVRAM_set_lword(nvram,  0x48, initrd_image);
1256     NVRAM_set_lword(nvram,  0x4C, initrd_size);
1257     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
1258
1259     NVRAM_set_word(nvram,   0x54, width);
1260     NVRAM_set_word(nvram,   0x56, height);
1261     NVRAM_set_word(nvram,   0x58, depth);
1262     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
1263     NVRAM_set_word(nvram,  0xFC, crc);
1264
1265     return 0;
1266 }