2 * QEMU generic PowerPC hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 //#define PPC_DEBUG_IRQ
32 void ppc_set_irq (CPUState
*env
, int n_IRQ
, int level
)
35 env
->pending_interrupts
|= 1 << n_IRQ
;
36 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
38 env
->pending_interrupts
&= ~(1 << n_IRQ
);
39 if (env
->pending_interrupts
== 0)
40 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
42 #if defined(PPC_DEBUG_IRQ)
43 printf("%s: %p n_IRQ %d level %d => pending %08x req %08x\n", __func__
,
44 env
, n_IRQ
, level
, env
->pending_interrupts
, env
->interrupt_request
);
48 /* PowerPC 6xx / 7xx internal IRQ controller */
49 static void ppc6xx_set_irq (void *opaque
, int pin
, int level
)
51 CPUState
*env
= opaque
;
54 #if defined(PPC_DEBUG_IRQ)
55 printf("%s: env %p pin %d level %d\n", __func__
, env
, pin
, level
);
57 cur_level
= (env
->irq_input_state
>> pin
) & 1;
58 /* Don't generate spurious events */
59 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0) || 0) {
62 /* Level sensitive - asserted high */
63 #if defined(PPC_DEBUG_IRQ)
64 printf("%s: set the external IRQ state to %d\n", __func__
, level
);
66 ppc_set_irq(env
, PPC_INTERRUPT_EXT
, level
);
69 /* Level sensitive - active high */
70 #if defined(PPC_DEBUG_IRQ)
71 printf("%s: set the SMI IRQ state to %d\n", __func__
, level
);
73 ppc_set_irq(env
, PPC_INTERRUPT_SMI
, level
);
76 /* Negative edge sensitive */
77 /* XXX: TODO: actual reaction may depends on HID0 status
78 * 603/604/740/750: check HID0[EMCP]
80 if (cur_level
== 1 && level
== 0) {
81 #if defined(PPC_DEBUG_IRQ)
82 printf("%s: raise machine check state\n", __func__
);
84 ppc_set_irq(env
, PPC_INTERRUPT_MCK
, 1);
87 case PPC_INPUT_CKSTP_IN
:
88 /* Level sensitive - active low */
89 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
91 #if defined(PPC_DEBUG_IRQ)
92 printf("%s: stop the CPU\n", __func__
);
96 #if defined(PPC_DEBUG_IRQ)
97 printf("%s: restart the CPU\n", __func__
);
102 case PPC_INPUT_HRESET
:
103 /* Level sensitive - active low */
106 #if defined(PPC_DEBUG_IRQ)
107 printf("%s: reset the CPU\n", __func__
);
113 case PPC_INPUT_SRESET
:
114 #if defined(PPC_DEBUG_IRQ)
115 printf("%s: set the RESET IRQ state to %d\n", __func__
, level
);
117 ppc_set_irq(env
, PPC_INTERRUPT_RESET
, level
);
120 /* Unknown pin - do nothing */
121 #if defined(PPC_DEBUG_IRQ)
122 printf("%s: unknown IRQ pin %d\n", __func__
, pin
);
127 env
->irq_input_state
|= 1 << pin
;
129 env
->irq_input_state
&= ~(1 << pin
);
133 void ppc6xx_irq_init (CPUState
*env
)
135 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppc6xx_set_irq
, env
, 6);
138 /*****************************************************************************/
139 /* PowerPC time base and decrementer emulation */
143 /* Time base management */
144 int64_t tb_offset
; /* Compensation */
145 uint32_t tb_freq
; /* TB frequency */
146 /* Decrementer management */
147 uint64_t decr_next
; /* Tick for next decr interrupt */
148 struct QEMUTimer
*decr_timer
;
152 static inline uint64_t cpu_ppc_get_tb (ppc_tb_t
*tb_env
)
154 /* TB time in tb periods */
155 return muldiv64(qemu_get_clock(vm_clock
) + tb_env
->tb_offset
,
156 tb_env
->tb_freq
, ticks_per_sec
);
159 uint32_t cpu_ppc_load_tbl (CPUState
*env
)
161 ppc_tb_t
*tb_env
= env
->tb_env
;
164 tb
= cpu_ppc_get_tb(tb_env
);
167 static int last_time
;
170 if (last_time
!= now
) {
172 printf("%s: tb=0x%016lx %d %08lx\n",
173 __func__
, tb
, now
, tb_env
->tb_offset
);
178 return tb
& 0xFFFFFFFF;
181 uint32_t cpu_ppc_load_tbu (CPUState
*env
)
183 ppc_tb_t
*tb_env
= env
->tb_env
;
186 tb
= cpu_ppc_get_tb(tb_env
);
188 printf("%s: tb=0x%016lx\n", __func__
, tb
);
194 static void cpu_ppc_store_tb (ppc_tb_t
*tb_env
, uint64_t value
)
196 tb_env
->tb_offset
= muldiv64(value
, ticks_per_sec
, tb_env
->tb_freq
)
197 - qemu_get_clock(vm_clock
);
199 printf("%s: tb=0x%016lx offset=%08x\n", __func__
, value
);
203 void cpu_ppc_store_tbu (CPUState
*env
, uint32_t value
)
205 ppc_tb_t
*tb_env
= env
->tb_env
;
207 cpu_ppc_store_tb(tb_env
,
208 ((uint64_t)value
<< 32) | cpu_ppc_load_tbl(env
));
211 void cpu_ppc_store_tbl (CPUState
*env
, uint32_t value
)
213 ppc_tb_t
*tb_env
= env
->tb_env
;
215 cpu_ppc_store_tb(tb_env
,
216 ((uint64_t)cpu_ppc_load_tbu(env
) << 32) | value
);
219 uint32_t cpu_ppc_load_decr (CPUState
*env
)
221 ppc_tb_t
*tb_env
= env
->tb_env
;
225 diff
= tb_env
->decr_next
- qemu_get_clock(vm_clock
);
227 decr
= muldiv64(diff
, tb_env
->tb_freq
, ticks_per_sec
);
229 decr
= -muldiv64(-diff
, tb_env
->tb_freq
, ticks_per_sec
);
230 #if defined(DEBUG_TB)
231 printf("%s: 0x%08x\n", __func__
, decr
);
237 /* When decrementer expires,
238 * all we need to do is generate or queue a CPU exception
240 static inline void cpu_ppc_decr_excp (CPUState
*env
)
244 printf("raise decrementer exception\n");
246 ppc_set_irq(env
, PPC_INTERRUPT_DECR
, 1);
249 static void _cpu_ppc_store_decr (CPUState
*env
, uint32_t decr
,
250 uint32_t value
, int is_excp
)
252 ppc_tb_t
*tb_env
= env
->tb_env
;
256 printf("%s: 0x%08x => 0x%08x\n", __func__
, decr
, value
);
258 now
= qemu_get_clock(vm_clock
);
259 next
= now
+ muldiv64(value
, ticks_per_sec
, tb_env
->tb_freq
);
261 next
+= tb_env
->decr_next
- now
;
264 tb_env
->decr_next
= next
;
266 qemu_mod_timer(tb_env
->decr_timer
, next
);
267 /* If we set a negative value and the decrementer was positive,
268 * raise an exception.
270 if ((value
& 0x80000000) && !(decr
& 0x80000000))
271 cpu_ppc_decr_excp(env
);
274 void cpu_ppc_store_decr (CPUState
*env
, uint32_t value
)
276 _cpu_ppc_store_decr(env
, cpu_ppc_load_decr(env
), value
, 0);
279 static void cpu_ppc_decr_cb (void *opaque
)
281 _cpu_ppc_store_decr(opaque
, 0x00000000, 0xFFFFFFFF, 1);
284 /* Set up (once) timebase frequency (in Hz) */
285 ppc_tb_t
*cpu_ppc_tb_init (CPUState
*env
, uint32_t freq
)
289 tb_env
= qemu_mallocz(sizeof(ppc_tb_t
));
292 env
->tb_env
= tb_env
;
293 if (tb_env
->tb_freq
== 0 || 1) {
294 tb_env
->tb_freq
= freq
;
295 /* Create new timer */
297 qemu_new_timer(vm_clock
, &cpu_ppc_decr_cb
, env
);
298 /* There is a bug in Linux 2.4 kernels:
299 * if a decrementer exception is pending when it enables msr_ee,
300 * it's not ready to handle it...
302 _cpu_ppc_store_decr(env
, 0xFFFFFFFF, 0xFFFFFFFF, 0);
308 /* Specific helpers for POWER & PowerPC 601 RTC */
309 ppc_tb_t
*cpu_ppc601_rtc_init (CPUState
*env
)
311 return cpu_ppc_tb_init(env
, 7812500);
314 void cpu_ppc601_store_rtcu (CPUState
*env
, uint32_t value
)
315 __attribute__ (( alias ("cpu_ppc_store_tbu") ));
317 uint32_t cpu_ppc601_load_rtcu (CPUState
*env
)
318 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
320 void cpu_ppc601_store_rtcl (CPUState
*env
, uint32_t value
)
322 cpu_ppc_store_tbl(env
, value
& 0x3FFFFF80);
325 uint32_t cpu_ppc601_load_rtcl (CPUState
*env
)
327 return cpu_ppc_load_tbl(env
) & 0x3FFFFF80;
330 /*****************************************************************************/
331 /* Embedded PowerPC timers */
334 typedef struct ppcemb_timer_t ppcemb_timer_t
;
335 struct ppcemb_timer_t
{
336 uint64_t pit_reload
; /* PIT auto-reload value */
337 uint64_t fit_next
; /* Tick for next FIT interrupt */
338 struct QEMUTimer
*fit_timer
;
339 uint64_t wdt_next
; /* Tick for next WDT interrupt */
340 struct QEMUTimer
*wdt_timer
;
343 /* Fixed interval timer */
344 static void cpu_4xx_fit_cb (void *opaque
)
348 ppcemb_timer_t
*ppcemb_timer
;
352 tb_env
= env
->tb_env
;
353 ppcemb_timer
= tb_env
->opaque
;
354 now
= qemu_get_clock(vm_clock
);
355 switch ((env
->spr
[SPR_40x_TCR
] >> 24) & 0x3) {
369 /* Cannot occur, but makes gcc happy */
372 next
= now
+ muldiv64(next
, ticks_per_sec
, tb_env
->tb_freq
);
375 qemu_mod_timer(ppcemb_timer
->fit_timer
, next
);
376 tb_env
->decr_next
= next
;
377 env
->spr
[SPR_40x_TSR
] |= 1 << 26;
378 if ((env
->spr
[SPR_40x_TCR
] >> 23) & 0x1)
379 ppc_set_irq(env
, PPC_INTERRUPT_FIT
, 1);
381 fprintf(logfile
, "%s: ir %d TCR %08x TSR %08x\n", __func__
,
382 (env
->spr
[SPR_40x_TCR
] >> 23) & 0x1,
383 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
]);
387 /* Programmable interval timer */
388 static void cpu_4xx_pit_cb (void *opaque
)
392 ppcemb_timer_t
*ppcemb_timer
;
396 tb_env
= env
->tb_env
;
397 ppcemb_timer
= tb_env
->opaque
;
398 now
= qemu_get_clock(vm_clock
);
399 if ((env
->spr
[SPR_40x_TCR
] >> 22) & 0x1) {
401 next
= now
+ muldiv64(ppcemb_timer
->pit_reload
,
402 ticks_per_sec
, tb_env
->tb_freq
);
405 qemu_mod_timer(tb_env
->decr_timer
, next
);
406 tb_env
->decr_next
= next
;
408 env
->spr
[SPR_40x_TSR
] |= 1 << 27;
409 if ((env
->spr
[SPR_40x_TCR
] >> 26) & 0x1)
410 ppc_set_irq(env
, PPC_INTERRUPT_PIT
, 1);
412 fprintf(logfile
, "%s: ar %d ir %d TCR %08x TSR %08x %08lx\n", __func__
,
413 (env
->spr
[SPR_40x_TCR
] >> 22) & 0x1,
414 (env
->spr
[SPR_40x_TCR
] >> 26) & 0x1,
415 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
],
416 ppcemb_timer
->pit_reload
);
421 static void cpu_4xx_wdt_cb (void *opaque
)
425 ppcemb_timer_t
*ppcemb_timer
;
429 tb_env
= env
->tb_env
;
430 ppcemb_timer
= tb_env
->opaque
;
431 now
= qemu_get_clock(vm_clock
);
432 switch ((env
->spr
[SPR_40x_TCR
] >> 30) & 0x3) {
446 /* Cannot occur, but makes gcc happy */
449 next
= now
+ muldiv64(next
, ticks_per_sec
, tb_env
->tb_freq
);
453 fprintf(logfile
, "%s: TCR %08x TSR %08x\n", __func__
,
454 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
]);
456 switch ((env
->spr
[SPR_40x_TSR
] >> 30) & 0x3) {
459 qemu_mod_timer(ppcemb_timer
->wdt_timer
, next
);
460 ppcemb_timer
->wdt_next
= next
;
461 env
->spr
[SPR_40x_TSR
] |= 1 << 31;
464 qemu_mod_timer(ppcemb_timer
->wdt_timer
, next
);
465 ppcemb_timer
->wdt_next
= next
;
466 env
->spr
[SPR_40x_TSR
] |= 1 << 30;
467 if ((env
->spr
[SPR_40x_TCR
] >> 27) & 0x1)
468 ppc_set_irq(env
, PPC_INTERRUPT_WDT
, 1);
471 env
->spr
[SPR_40x_TSR
] &= ~0x30000000;
472 env
->spr
[SPR_40x_TSR
] |= env
->spr
[SPR_40x_TCR
] & 0x30000000;
473 switch ((env
->spr
[SPR_40x_TCR
] >> 28) & 0x3) {
477 case 0x1: /* Core reset */
478 case 0x2: /* Chip reset */
479 case 0x3: /* System reset */
480 qemu_system_reset_request();
486 void store_40x_pit (CPUState
*env
, target_ulong val
)
489 ppcemb_timer_t
*ppcemb_timer
;
492 tb_env
= env
->tb_env
;
493 ppcemb_timer
= tb_env
->opaque
;
495 fprintf(logfile
, "%s %p %p\n", __func__
, tb_env
, ppcemb_timer
);
496 ppcemb_timer
->pit_reload
= val
;
500 fprintf(logfile
, "%s: stop PIT\n", __func__
);
501 qemu_del_timer(tb_env
->decr_timer
);
504 fprintf(logfile
, "%s: start PIT 0x%08x\n", __func__
, val
);
505 now
= qemu_get_clock(vm_clock
);
506 next
= now
+ muldiv64(val
, ticks_per_sec
, tb_env
->tb_freq
);
509 qemu_mod_timer(tb_env
->decr_timer
, next
);
510 tb_env
->decr_next
= next
;
514 target_ulong
load_40x_pit (CPUState
*env
)
516 return cpu_ppc_load_decr(env
);
519 void store_booke_tsr (CPUState
*env
, target_ulong val
)
521 env
->spr
[SPR_40x_TSR
] = val
& 0xFC000000;
524 void store_booke_tcr (CPUState
*env
, target_ulong val
)
526 /* We don't update timers now. Maybe we should... */
527 env
->spr
[SPR_40x_TCR
] = val
& 0xFF800000;
530 void ppc_emb_timers_init (CPUState
*env
)
533 ppcemb_timer_t
*ppcemb_timer
;
535 tb_env
= env
->tb_env
;
536 ppcemb_timer
= qemu_mallocz(sizeof(ppcemb_timer_t
));
537 tb_env
->opaque
= ppcemb_timer
;
539 fprintf(logfile
, "%s %p %p\n", __func__
, tb_env
, ppcemb_timer
);
540 if (ppcemb_timer
!= NULL
) {
541 /* We use decr timer for PIT */
542 tb_env
->decr_timer
= qemu_new_timer(vm_clock
, &cpu_4xx_pit_cb
, env
);
543 ppcemb_timer
->fit_timer
=
544 qemu_new_timer(vm_clock
, &cpu_4xx_fit_cb
, env
);
545 ppcemb_timer
->wdt_timer
=
546 qemu_new_timer(vm_clock
, &cpu_4xx_wdt_cb
, env
);
551 /*****************************************************************************/
552 /* Handle system reset (for now, just stop emulation) */
553 void cpu_ppc_reset (CPUState
*env
)
555 printf("Reset asked... Stop emulation\n");
560 /*****************************************************************************/
562 void PPC_debug_write (void *opaque
, uint32_t addr
, uint32_t val
)
574 printf("Set loglevel to %04x\n", val
);
575 cpu_set_log(val
| 0x100);
580 /*****************************************************************************/
582 void NVRAM_set_byte (m48t59_t
*nvram
, uint32_t addr
, uint8_t value
)
584 m48t59_write(nvram
, addr
, value
);
587 uint8_t NVRAM_get_byte (m48t59_t
*nvram
, uint32_t addr
)
589 return m48t59_read(nvram
, addr
);
592 void NVRAM_set_word (m48t59_t
*nvram
, uint32_t addr
, uint16_t value
)
594 m48t59_write(nvram
, addr
, value
>> 8);
595 m48t59_write(nvram
, addr
+ 1, value
& 0xFF);
598 uint16_t NVRAM_get_word (m48t59_t
*nvram
, uint32_t addr
)
602 tmp
= m48t59_read(nvram
, addr
) << 8;
603 tmp
|= m48t59_read(nvram
, addr
+ 1);
607 void NVRAM_set_lword (m48t59_t
*nvram
, uint32_t addr
, uint32_t value
)
609 m48t59_write(nvram
, addr
, value
>> 24);
610 m48t59_write(nvram
, addr
+ 1, (value
>> 16) & 0xFF);
611 m48t59_write(nvram
, addr
+ 2, (value
>> 8) & 0xFF);
612 m48t59_write(nvram
, addr
+ 3, value
& 0xFF);
615 uint32_t NVRAM_get_lword (m48t59_t
*nvram
, uint32_t addr
)
619 tmp
= m48t59_read(nvram
, addr
) << 24;
620 tmp
|= m48t59_read(nvram
, addr
+ 1) << 16;
621 tmp
|= m48t59_read(nvram
, addr
+ 2) << 8;
622 tmp
|= m48t59_read(nvram
, addr
+ 3);
627 void NVRAM_set_string (m48t59_t
*nvram
, uint32_t addr
,
628 const unsigned char *str
, uint32_t max
)
632 for (i
= 0; i
< max
&& str
[i
] != '\0'; i
++) {
633 m48t59_write(nvram
, addr
+ i
, str
[i
]);
635 m48t59_write(nvram
, addr
+ max
- 1, '\0');
638 int NVRAM_get_string (m48t59_t
*nvram
, uint8_t *dst
, uint16_t addr
, int max
)
643 for (i
= 0; i
< max
; i
++) {
644 dst
[i
] = NVRAM_get_byte(nvram
, addr
+ i
);
652 static uint16_t NVRAM_crc_update (uint16_t prev
, uint16_t value
)
655 uint16_t pd
, pd1
, pd2
;
660 pd2
= ((pd
>> 4) & 0x000F) ^ pd1
;
661 tmp
^= (pd1
<< 3) | (pd1
<< 8);
662 tmp
^= pd2
| (pd2
<< 7) | (pd2
<< 12);
667 uint16_t NVRAM_compute_crc (m48t59_t
*nvram
, uint32_t start
, uint32_t count
)
670 uint16_t crc
= 0xFFFF;
675 for (i
= 0; i
!= count
; i
++) {
676 crc
= NVRAM_crc_update(crc
, NVRAM_get_word(nvram
, start
+ i
));
679 crc
= NVRAM_crc_update(crc
, NVRAM_get_byte(nvram
, start
+ i
) << 8);
685 #define CMDLINE_ADDR 0x017ff000
687 int PPC_NVRAM_set_params (m48t59_t
*nvram
, uint16_t NVRAM_size
,
688 const unsigned char *arch
,
689 uint32_t RAM_size
, int boot_device
,
690 uint32_t kernel_image
, uint32_t kernel_size
,
692 uint32_t initrd_image
, uint32_t initrd_size
,
693 uint32_t NVRAM_image
,
694 int width
, int height
, int depth
)
698 /* Set parameters for Open Hack'Ware BIOS */
699 NVRAM_set_string(nvram
, 0x00, "QEMU_BIOS", 16);
700 NVRAM_set_lword(nvram
, 0x10, 0x00000002); /* structure v2 */
701 NVRAM_set_word(nvram
, 0x14, NVRAM_size
);
702 NVRAM_set_string(nvram
, 0x20, arch
, 16);
703 NVRAM_set_lword(nvram
, 0x30, RAM_size
);
704 NVRAM_set_byte(nvram
, 0x34, boot_device
);
705 NVRAM_set_lword(nvram
, 0x38, kernel_image
);
706 NVRAM_set_lword(nvram
, 0x3C, kernel_size
);
708 /* XXX: put the cmdline in NVRAM too ? */
709 strcpy(phys_ram_base
+ CMDLINE_ADDR
, cmdline
);
710 NVRAM_set_lword(nvram
, 0x40, CMDLINE_ADDR
);
711 NVRAM_set_lword(nvram
, 0x44, strlen(cmdline
));
713 NVRAM_set_lword(nvram
, 0x40, 0);
714 NVRAM_set_lword(nvram
, 0x44, 0);
716 NVRAM_set_lword(nvram
, 0x48, initrd_image
);
717 NVRAM_set_lword(nvram
, 0x4C, initrd_size
);
718 NVRAM_set_lword(nvram
, 0x50, NVRAM_image
);
720 NVRAM_set_word(nvram
, 0x54, width
);
721 NVRAM_set_word(nvram
, 0x56, height
);
722 NVRAM_set_word(nvram
, 0x58, depth
);
723 crc
= NVRAM_compute_crc(nvram
, 0x00, 0xF8);
724 NVRAM_set_word(nvram
, 0xFC, crc
);