2 * QEMU PowerPC 405 shared definitions
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #if !defined(PPC_405_H)
28 /* Bootinfo as set-up by u-boot */
29 typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t
;
30 struct ppc4xx_bd_info_t
{
33 uint32_t bi_flashstart
;
34 uint32_t bi_flashsize
;
35 uint32_t bi_flashoffset
; /* 0x10 */
36 uint32_t bi_sramstart
;
38 uint32_t bi_bootflags
;
39 uint32_t bi_ipaddr
; /* 0x20 */
40 uint8_t bi_enetaddr
[6];
43 uint32_t bi_busfreq
; /* 0x30 */
45 uint8_t bi_s_version
[4];
46 uint8_t bi_r_version
[32];
48 uint32_t bi_plb_busfreq
;
49 uint32_t bi_pci_busfreq
;
50 uint8_t bi_pci_enetaddr
[6];
51 uint32_t bi_pci_enetaddr2
[6];
53 uint32_t bi_iic_fast
[2];
56 /* PowerPC 405 core */
57 CPUState
*ppc405_init (const unsigned char *cpu_model
,
58 clk_setup_t
*cpu_clk
, clk_setup_t
*tb_clk
,
60 ram_addr_t
ppc405_set_bootinfo (CPUState
*env
, ppc4xx_bd_info_t
*bd
,
64 typedef struct ppc4xx_mmio_t ppc4xx_mmio_t
;
65 int ppc4xx_mmio_register (CPUState
*env
, ppc4xx_mmio_t
*mmio
,
66 target_phys_addr_t offset
, uint32_t len
,
67 CPUReadMemoryFunc
**mem_read
,
68 CPUWriteMemoryFunc
**mem_write
, void *opaque
);
69 ppc4xx_mmio_t
*ppc4xx_mmio_init (CPUState
*env
, target_phys_addr_t base
);
70 /* PowerPC 4xx peripheral local bus arbitrer */
71 void ppc4xx_plb_init (CPUState
*env
);
72 /* PLB to OPB bridge */
73 void ppc4xx_pob_init (CPUState
*env
);
75 void ppc4xx_opba_init (CPUState
*env
, ppc4xx_mmio_t
*mmio
,
76 target_phys_addr_t offset
);
77 /* PowerPC 4xx universal interrupt controller */
79 PPCUIC_OUTPUT_INT
= 0,
80 PPCUIC_OUTPUT_CINT
= 1,
83 qemu_irq
*ppcuic_init (CPUState
*env
, qemu_irq
*irqs
,
84 uint32_t dcr_base
, int has_ssr
, int has_vr
);
85 /* SDRAM controller */
86 void ppc405_sdram_init (CPUState
*env
, qemu_irq irq
, int nbanks
,
87 target_phys_addr_t
*ram_bases
,
88 target_phys_addr_t
*ram_sizes
,
90 /* Peripheral controller */
91 void ppc405_ebc_init (CPUState
*env
);
93 void ppc405_dma_init (CPUState
*env
, qemu_irq irqs
[4]);
95 void ppc405_gpio_init (CPUState
*env
, ppc4xx_mmio_t
*mmio
,
96 target_phys_addr_t offset
);
98 void ppc405_serial_init (CPUState
*env
, ppc4xx_mmio_t
*mmio
,
99 target_phys_addr_t offset
, qemu_irq irq
,
100 CharDriverState
*chr
);
102 void ppc405_ocm_init (CPUState
*env
, unsigned long offset
);
104 void ppc405_i2c_init (CPUState
*env
, ppc4xx_mmio_t
*mmio
,
105 target_phys_addr_t offset
, qemu_irq irq
);
106 /* General purpose timers */
107 void ppc4xx_gpt_init (CPUState
*env
, ppc4xx_mmio_t
*mmio
,
108 target_phys_addr_t offset
, qemu_irq irq
[5]);
109 /* Memory access layer */
110 void ppc405_mal_init (CPUState
*env
, qemu_irq irqs
[4]);
111 /* PowerPC 405 microcontrollers */
112 CPUState
*ppc405cr_init (target_phys_addr_t ram_bases
[4],
113 target_phys_addr_t ram_sizes
[4],
114 uint32_t sysclk
, qemu_irq
**picp
,
115 ram_addr_t
*offsetp
, int do_init
);
116 CPUState
*ppc405ep_init (target_phys_addr_t ram_bases
[2],
117 target_phys_addr_t ram_sizes
[2],
118 uint32_t sysclk
, qemu_irq
**picp
,
119 ram_addr_t
*offsetp
, int do_init
);
120 /* IBM STBxxx microcontrollers */
121 CPUState
*ppc_stb025_init (target_phys_addr_t ram_bases
[2],
122 target_phys_addr_t ram_sizes
[2],
123 uint32_t sysclk
, qemu_irq
**picp
,
124 ram_addr_t
*offsetp
);
126 #endif /* !defined(PPC_405_H) */