2 * QEMU PowerPC 405 evaluation boards emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
34 #define BIOS_FILENAME "ppc405_rom.bin"
36 #define BIOS_SIZE (2048 * 1024)
38 #define KERNEL_LOAD_ADDR 0x00000000
39 #define INITRD_LOAD_ADDR 0x01800000
41 #define USE_FLASH_BIOS
43 #define DEBUG_BOARD_INIT
45 /*****************************************************************************/
46 /* PPC405EP reference board (IBM) */
47 /* Standalone board with:
49 * - SDRAM (0x00000000)
50 * - Flash (0xFFF80000)
52 * - NVRAM (0xF0000000)
55 typedef struct ref405ep_fpga_t ref405ep_fpga_t
;
56 struct ref405ep_fpga_t
{
62 static uint32_t ref405ep_fpga_readb (void *opaque
, target_phys_addr_t addr
)
64 ref405ep_fpga_t
*fpga
;
84 static void ref405ep_fpga_writeb (void *opaque
,
85 target_phys_addr_t addr
, uint32_t value
)
87 ref405ep_fpga_t
*fpga
;
103 static uint32_t ref405ep_fpga_readw (void *opaque
, target_phys_addr_t addr
)
107 ret
= ref405ep_fpga_readb(opaque
, addr
) << 8;
108 ret
|= ref405ep_fpga_readb(opaque
, addr
+ 1);
113 static void ref405ep_fpga_writew (void *opaque
,
114 target_phys_addr_t addr
, uint32_t value
)
116 ref405ep_fpga_writeb(opaque
, addr
, (value
>> 8) & 0xFF);
117 ref405ep_fpga_writeb(opaque
, addr
+ 1, value
& 0xFF);
120 static uint32_t ref405ep_fpga_readl (void *opaque
, target_phys_addr_t addr
)
124 ret
= ref405ep_fpga_readb(opaque
, addr
) << 24;
125 ret
|= ref405ep_fpga_readb(opaque
, addr
+ 1) << 16;
126 ret
|= ref405ep_fpga_readb(opaque
, addr
+ 2) << 8;
127 ret
|= ref405ep_fpga_readb(opaque
, addr
+ 3);
132 static void ref405ep_fpga_writel (void *opaque
,
133 target_phys_addr_t addr
, uint32_t value
)
135 ref405ep_fpga_writel(opaque
, addr
, (value
>> 24) & 0xFF);
136 ref405ep_fpga_writel(opaque
, addr
+ 1, (value
>> 16) & 0xFF);
137 ref405ep_fpga_writel(opaque
, addr
+ 2, (value
>> 8) & 0xFF);
138 ref405ep_fpga_writeb(opaque
, addr
+ 3, value
& 0xFF);
141 static CPUReadMemoryFunc
*ref405ep_fpga_read
[] = {
142 &ref405ep_fpga_readb
,
143 &ref405ep_fpga_readw
,
144 &ref405ep_fpga_readl
,
147 static CPUWriteMemoryFunc
*ref405ep_fpga_write
[] = {
148 &ref405ep_fpga_writeb
,
149 &ref405ep_fpga_writew
,
150 &ref405ep_fpga_writel
,
153 static void ref405ep_fpga_reset (void *opaque
)
155 ref405ep_fpga_t
*fpga
;
162 static void ref405ep_fpga_init (uint32_t base
)
164 ref405ep_fpga_t
*fpga
;
167 fpga
= qemu_mallocz(sizeof(ref405ep_fpga_t
));
170 fpga_memory
= cpu_register_io_memory(0, ref405ep_fpga_read
,
171 ref405ep_fpga_write
, fpga
);
172 cpu_register_physical_memory(base
, 0x00000100, fpga_memory
);
173 ref405ep_fpga_reset(fpga
);
174 qemu_register_reset(&ref405ep_fpga_reset
, fpga
);
178 static void ref405ep_init (ram_addr_t ram_size
, int vga_ram_size
,
179 const char *boot_device
, DisplayState
*ds
,
180 const char *kernel_filename
,
181 const char *kernel_cmdline
,
182 const char *initrd_filename
,
183 const char *cpu_model
)
189 ram_addr_t sram_offset
, bios_offset
, bdloc
;
190 target_phys_addr_t ram_bases
[2], ram_sizes
[2];
191 target_ulong sram_size
, bios_size
;
193 //static int phy_addr = 1;
194 target_ulong kernel_base
, kernel_size
, initrd_base
, initrd_size
;
196 int fl_idx
, fl_sectors
, len
;
197 int ppc_boot_device
= boot_device
[0];
201 ram_bases
[0] = 0x00000000;
202 ram_sizes
[0] = 0x08000000;
203 ram_bases
[1] = 0x00000000;
204 ram_sizes
[1] = 0x00000000;
205 ram_size
= 128 * 1024 * 1024;
206 #ifdef DEBUG_BOARD_INIT
207 printf("%s: register cpu\n", __func__
);
209 env
= ppc405ep_init(ram_bases
, ram_sizes
, 33333333, &pic
, &sram_offset
,
210 kernel_filename
== NULL
? 0 : 1);
212 #ifdef DEBUG_BOARD_INIT
213 printf("%s: register SRAM at offset %08lx\n", __func__
, sram_offset
);
215 sram_size
= 512 * 1024;
216 cpu_register_physical_memory(0xFFF00000, sram_size
,
217 sram_offset
| IO_MEM_RAM
);
218 /* allocate and load BIOS */
219 #ifdef DEBUG_BOARD_INIT
220 printf("%s: register BIOS\n", __func__
);
222 bios_offset
= sram_offset
+ sram_size
;
224 #ifdef USE_FLASH_BIOS
225 index
= drive_get_index(IF_PFLASH
, 0, fl_idx
);
227 bios_size
= bdrv_getlength(drives_table
[index
].bdrv
);
228 fl_sectors
= (bios_size
+ 65535) >> 16;
229 #ifdef DEBUG_BOARD_INIT
230 printf("Register parallel flash %d size " ADDRX
" at offset %08lx "
231 " addr " ADDRX
" '%s' %d\n",
232 fl_idx
, bios_size
, bios_offset
, -bios_size
,
233 bdrv_get_device_name(drives_table
[index
].bdrv
), fl_sectors
);
235 pflash_cfi02_register((uint32_t)(-bios_size
), bios_offset
,
236 drives_table
[index
].bdrv
, 65536, fl_sectors
, 1,
237 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
242 #ifdef DEBUG_BOARD_INIT
243 printf("Load BIOS from file\n");
245 if (bios_name
== NULL
)
246 bios_name
= BIOS_FILENAME
;
247 snprintf(buf
, sizeof(buf
), "%s/%s", bios_dir
, bios_name
);
248 bios_size
= load_image(buf
, phys_ram_base
+ bios_offset
);
249 if (bios_size
< 0 || bios_size
> BIOS_SIZE
) {
250 fprintf(stderr
, "qemu: could not load PowerPC bios '%s'\n", buf
);
253 bios_size
= (bios_size
+ 0xfff) & ~0xfff;
254 cpu_register_physical_memory((uint32_t)(-bios_size
),
255 bios_size
, bios_offset
| IO_MEM_ROM
);
257 bios_offset
+= bios_size
;
259 #ifdef DEBUG_BOARD_INIT
260 printf("%s: register FPGA\n", __func__
);
262 ref405ep_fpga_init(0xF0300000);
264 #ifdef DEBUG_BOARD_INIT
265 printf("%s: register NVRAM\n", __func__
);
267 m48t59_init(NULL
, 0xF0000000, 0, 8192, 8);
269 linux_boot
= (kernel_filename
!= NULL
);
271 #ifdef DEBUG_BOARD_INIT
272 printf("%s: load kernel\n", __func__
);
274 memset(&bd
, 0, sizeof(bd
));
275 bd
.bi_memstart
= 0x00000000;
276 bd
.bi_memsize
= ram_size
;
277 bd
.bi_flashstart
= -bios_size
;
278 bd
.bi_flashsize
= -bios_size
;
279 bd
.bi_flashoffset
= 0;
280 bd
.bi_sramstart
= 0xFFF00000;
281 bd
.bi_sramsize
= sram_size
;
283 bd
.bi_intfreq
= 133333333;
284 bd
.bi_busfreq
= 33333333;
285 bd
.bi_baudrate
= 115200;
286 bd
.bi_s_version
[0] = 'Q';
287 bd
.bi_s_version
[1] = 'M';
288 bd
.bi_s_version
[2] = 'U';
289 bd
.bi_s_version
[3] = '\0';
290 bd
.bi_r_version
[0] = 'Q';
291 bd
.bi_r_version
[1] = 'E';
292 bd
.bi_r_version
[2] = 'M';
293 bd
.bi_r_version
[3] = 'U';
294 bd
.bi_r_version
[4] = '\0';
295 bd
.bi_procfreq
= 133333333;
296 bd
.bi_plb_busfreq
= 33333333;
297 bd
.bi_pci_busfreq
= 33333333;
298 bd
.bi_opbfreq
= 33333333;
299 bdloc
= ppc405_set_bootinfo(env
, &bd
, 0x00000001);
301 kernel_base
= KERNEL_LOAD_ADDR
;
302 /* now we can load the kernel */
303 kernel_size
= load_image(kernel_filename
, phys_ram_base
+ kernel_base
);
304 if (kernel_size
< 0) {
305 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
309 printf("Load kernel size " TARGET_FMT_ld
" at " TARGET_FMT_lx
310 " %02x %02x %02x %02x\n", kernel_size
, kernel_base
,
311 *(char *)(phys_ram_base
+ kernel_base
),
312 *(char *)(phys_ram_base
+ kernel_base
+ 1),
313 *(char *)(phys_ram_base
+ kernel_base
+ 2),
314 *(char *)(phys_ram_base
+ kernel_base
+ 3));
316 if (initrd_filename
) {
317 initrd_base
= INITRD_LOAD_ADDR
;
318 initrd_size
= load_image(initrd_filename
,
319 phys_ram_base
+ initrd_base
);
320 if (initrd_size
< 0) {
321 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
329 env
->gpr
[4] = initrd_base
;
330 env
->gpr
[5] = initrd_size
;
331 ppc_boot_device
= 'm';
332 if (kernel_cmdline
!= NULL
) {
333 len
= strlen(kernel_cmdline
);
334 bdloc
-= ((len
+ 255) & ~255);
335 memcpy(phys_ram_base
+ bdloc
, kernel_cmdline
, len
+ 1);
337 env
->gpr
[7] = bdloc
+ len
;
342 env
->nip
= KERNEL_LOAD_ADDR
;
350 #ifdef DEBUG_BOARD_INIT
351 printf("%s: Done\n", __func__
);
353 printf("bdloc %016lx %s\n",
354 (unsigned long)bdloc
, (char *)(phys_ram_base
+ bdloc
));
357 QEMUMachine ref405ep_machine
= {
361 (128 * 1024 * 1024 + 4096 + 512 * 1024 + BIOS_SIZE
) | RAMSIZE_FIXED
,
364 /*****************************************************************************/
365 /* AMCC Taihu evaluation board */
366 /* - PowerPC 405EP processor
367 * - SDRAM 128 MB at 0x00000000
368 * - Boot flash 2 MB at 0xFFE00000
369 * - Application flash 32 MB at 0xFC000000
372 * - 1 USB 1.1 device 0x50000000
373 * - 1 LCD display 0x50100000
374 * - 1 CPLD 0x50100000
376 * - 1 I2C thermal sensor
378 * - bit-bang SPI port using GPIOs
379 * - 1 EBC interface connector 0 0x50200000
380 * - 1 cardbus controller + expansion slot.
381 * - 1 PCI expansion slot.
383 typedef struct taihu_cpld_t taihu_cpld_t
;
384 struct taihu_cpld_t
{
390 static uint32_t taihu_cpld_readb (void *opaque
, target_phys_addr_t addr
)
412 static void taihu_cpld_writeb (void *opaque
,
413 target_phys_addr_t addr
, uint32_t value
)
431 static uint32_t taihu_cpld_readw (void *opaque
, target_phys_addr_t addr
)
435 ret
= taihu_cpld_readb(opaque
, addr
) << 8;
436 ret
|= taihu_cpld_readb(opaque
, addr
+ 1);
441 static void taihu_cpld_writew (void *opaque
,
442 target_phys_addr_t addr
, uint32_t value
)
444 taihu_cpld_writeb(opaque
, addr
, (value
>> 8) & 0xFF);
445 taihu_cpld_writeb(opaque
, addr
+ 1, value
& 0xFF);
448 static uint32_t taihu_cpld_readl (void *opaque
, target_phys_addr_t addr
)
452 ret
= taihu_cpld_readb(opaque
, addr
) << 24;
453 ret
|= taihu_cpld_readb(opaque
, addr
+ 1) << 16;
454 ret
|= taihu_cpld_readb(opaque
, addr
+ 2) << 8;
455 ret
|= taihu_cpld_readb(opaque
, addr
+ 3);
460 static void taihu_cpld_writel (void *opaque
,
461 target_phys_addr_t addr
, uint32_t value
)
463 taihu_cpld_writel(opaque
, addr
, (value
>> 24) & 0xFF);
464 taihu_cpld_writel(opaque
, addr
+ 1, (value
>> 16) & 0xFF);
465 taihu_cpld_writel(opaque
, addr
+ 2, (value
>> 8) & 0xFF);
466 taihu_cpld_writeb(opaque
, addr
+ 3, value
& 0xFF);
469 static CPUReadMemoryFunc
*taihu_cpld_read
[] = {
475 static CPUWriteMemoryFunc
*taihu_cpld_write
[] = {
481 static void taihu_cpld_reset (void *opaque
)
490 static void taihu_cpld_init (uint32_t base
)
495 cpld
= qemu_mallocz(sizeof(taihu_cpld_t
));
498 cpld_memory
= cpu_register_io_memory(0, taihu_cpld_read
,
499 taihu_cpld_write
, cpld
);
500 cpu_register_physical_memory(base
, 0x00000100, cpld_memory
);
501 taihu_cpld_reset(cpld
);
502 qemu_register_reset(&taihu_cpld_reset
, cpld
);
506 static void taihu_405ep_init(ram_addr_t ram_size
, int vga_ram_size
,
507 const char *boot_device
, DisplayState
*ds
,
508 const char *kernel_filename
,
509 const char *kernel_cmdline
,
510 const char *initrd_filename
,
511 const char *cpu_model
)
516 ram_addr_t bios_offset
;
517 target_phys_addr_t ram_bases
[2], ram_sizes
[2];
518 target_ulong bios_size
;
519 target_ulong kernel_base
, kernel_size
, initrd_base
, initrd_size
;
521 int fl_idx
, fl_sectors
;
522 int ppc_boot_device
= boot_device
[0];
525 /* RAM is soldered to the board so the size cannot be changed */
526 ram_bases
[0] = 0x00000000;
527 ram_sizes
[0] = 0x04000000;
528 ram_bases
[1] = 0x04000000;
529 ram_sizes
[1] = 0x04000000;
530 #ifdef DEBUG_BOARD_INIT
531 printf("%s: register cpu\n", __func__
);
533 env
= ppc405ep_init(ram_bases
, ram_sizes
, 33333333, &pic
, &bios_offset
,
534 kernel_filename
== NULL
? 0 : 1);
535 /* allocate and load BIOS */
536 #ifdef DEBUG_BOARD_INIT
537 printf("%s: register BIOS\n", __func__
);
540 #if defined(USE_FLASH_BIOS)
541 index
= drive_get_index(IF_PFLASH
, 0, fl_idx
);
543 bios_size
= bdrv_getlength(drives_table
[index
].bdrv
);
544 /* XXX: should check that size is 2MB */
545 // bios_size = 2 * 1024 * 1024;
546 fl_sectors
= (bios_size
+ 65535) >> 16;
547 #ifdef DEBUG_BOARD_INIT
548 printf("Register parallel flash %d size " ADDRX
" at offset %08lx "
549 " addr " ADDRX
" '%s' %d\n",
550 fl_idx
, bios_size
, bios_offset
, -bios_size
,
551 bdrv_get_device_name(drives_table
[index
].bdrv
), fl_sectors
);
553 pflash_cfi02_register((uint32_t)(-bios_size
), bios_offset
,
554 drives_table
[index
].bdrv
, 65536, fl_sectors
, 1,
555 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
560 #ifdef DEBUG_BOARD_INIT
561 printf("Load BIOS from file\n");
563 if (bios_name
== NULL
)
564 bios_name
= BIOS_FILENAME
;
565 snprintf(buf
, sizeof(buf
), "%s/%s", bios_dir
, bios_name
);
566 bios_size
= load_image(buf
, phys_ram_base
+ bios_offset
);
567 if (bios_size
< 0 || bios_size
> BIOS_SIZE
) {
568 fprintf(stderr
, "qemu: could not load PowerPC bios '%s'\n", buf
);
571 bios_size
= (bios_size
+ 0xfff) & ~0xfff;
572 cpu_register_physical_memory((uint32_t)(-bios_size
),
573 bios_size
, bios_offset
| IO_MEM_ROM
);
575 bios_offset
+= bios_size
;
576 /* Register Linux flash */
577 index
= drive_get_index(IF_PFLASH
, 0, fl_idx
);
579 bios_size
= bdrv_getlength(drives_table
[index
].bdrv
);
580 /* XXX: should check that size is 32MB */
581 bios_size
= 32 * 1024 * 1024;
582 fl_sectors
= (bios_size
+ 65535) >> 16;
583 #ifdef DEBUG_BOARD_INIT
584 printf("Register parallel flash %d size " ADDRX
" at offset %08lx "
585 " addr " ADDRX
" '%s'\n",
586 fl_idx
, bios_size
, bios_offset
, (target_ulong
)0xfc000000,
587 bdrv_get_device_name(drives_table
[index
].bdrv
));
589 pflash_cfi02_register(0xfc000000, bios_offset
,
590 drives_table
[index
].bdrv
, 65536, fl_sectors
, 1,
591 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
594 /* Register CLPD & LCD display */
595 #ifdef DEBUG_BOARD_INIT
596 printf("%s: register CPLD\n", __func__
);
598 taihu_cpld_init(0x50100000);
600 linux_boot
= (kernel_filename
!= NULL
);
602 #ifdef DEBUG_BOARD_INIT
603 printf("%s: load kernel\n", __func__
);
605 kernel_base
= KERNEL_LOAD_ADDR
;
606 /* now we can load the kernel */
607 kernel_size
= load_image(kernel_filename
, phys_ram_base
+ kernel_base
);
608 if (kernel_size
< 0) {
609 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
614 if (initrd_filename
) {
615 initrd_base
= INITRD_LOAD_ADDR
;
616 initrd_size
= load_image(initrd_filename
,
617 phys_ram_base
+ initrd_base
);
618 if (initrd_size
< 0) {
620 "qemu: could not load initial ram disk '%s'\n",
628 ppc_boot_device
= 'm';
635 #ifdef DEBUG_BOARD_INIT
636 printf("%s: Done\n", __func__
);
640 QEMUMachine taihu_machine
= {
644 (128 * 1024 * 1024 + 4096 + BIOS_SIZE
+ 32 * 1024 * 1024) | RAMSIZE_FIXED
,