2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 * Copyright IBM Corp. 2008
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
20 /* This file implements emulation of the 32-bit PCI controller found in some
21 * 4xx SoCs, such as the 440EP. */
25 typedef target_phys_addr_t pci_addr_t
;
32 #define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
34 #define DPRINTF(fmt, args...)
49 #define PPC4xx_PCI_NR_PMMS 3
50 #define PPC4xx_PCI_NR_PTMS 2
52 struct PPC4xxPCIState
{
53 struct PCIMasterMap pmm
[PPC4xx_PCI_NR_PMMS
];
54 struct PCITargetMap ptm
[PPC4xx_PCI_NR_PTMS
];
56 PCIHostState pci_state
;
59 typedef struct PPC4xxPCIState PPC4xxPCIState
;
61 #define PCIC0_CFGADDR 0x0
62 #define PCIC0_CFGDATA 0x4
64 /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
66 #define PCIL0_PMM0LA 0x0
67 #define PCIL0_PMM0MA 0x4
68 #define PCIL0_PMM0PCILA 0x8
69 #define PCIL0_PMM0PCIHA 0xc
70 #define PCIL0_PMM1LA 0x10
71 #define PCIL0_PMM1MA 0x14
72 #define PCIL0_PMM1PCILA 0x18
73 #define PCIL0_PMM1PCIHA 0x1c
74 #define PCIL0_PMM2LA 0x20
75 #define PCIL0_PMM2MA 0x24
76 #define PCIL0_PMM2PCILA 0x28
77 #define PCIL0_PMM2PCIHA 0x2c
79 /* PCI Target Map (PTM) registers specify which PCI addresses are translated to
81 #define PCIL0_PTM1MS 0x30
82 #define PCIL0_PTM1LA 0x34
83 #define PCIL0_PTM2MS 0x38
84 #define PCIL0_PTM2LA 0x3c
85 #define PCI_REG_SIZE 0x40
88 static uint32_t pci4xx_cfgaddr_readl(void *opaque
, target_phys_addr_t addr
)
90 PPC4xxPCIState
*ppc4xx_pci
= opaque
;
92 return ppc4xx_pci
->pci_state
.config_reg
;
95 static CPUReadMemoryFunc
*pci4xx_cfgaddr_read
[] = {
96 &pci4xx_cfgaddr_readl
,
97 &pci4xx_cfgaddr_readl
,
98 &pci4xx_cfgaddr_readl
,
101 static void pci4xx_cfgaddr_writel(void *opaque
, target_phys_addr_t addr
,
104 PPC4xxPCIState
*ppc4xx_pci
= opaque
;
106 #ifdef TARGET_WORDS_BIGENDIAN
107 value
= bswap32(value
);
110 ppc4xx_pci
->pci_state
.config_reg
= value
& ~0x3;
113 static CPUWriteMemoryFunc
*pci4xx_cfgaddr_write
[] = {
114 &pci4xx_cfgaddr_writel
,
115 &pci4xx_cfgaddr_writel
,
116 &pci4xx_cfgaddr_writel
,
119 static CPUReadMemoryFunc
*pci4xx_cfgdata_read
[] = {
120 &pci_host_data_readb
,
121 &pci_host_data_readw
,
122 &pci_host_data_readl
,
125 static CPUWriteMemoryFunc
*pci4xx_cfgdata_write
[] = {
126 &pci_host_data_writeb
,
127 &pci_host_data_writew
,
128 &pci_host_data_writel
,
131 static void ppc4xx_pci_reg_write4(void *opaque
, target_phys_addr_t offset
,
134 struct PPC4xxPCIState
*pci
= opaque
;
136 #ifdef TARGET_WORDS_BIGENDIAN
137 value
= bswap32(value
);
140 /* We ignore all target attempts at PCI configuration, effectively
141 * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
145 pci
->pmm
[0].la
= value
;
148 pci
->pmm
[0].ma
= value
;
150 case PCIL0_PMM0PCIHA
:
151 pci
->pmm
[0].pciha
= value
;
153 case PCIL0_PMM0PCILA
:
154 pci
->pmm
[0].pcila
= value
;
158 pci
->pmm
[1].la
= value
;
161 pci
->pmm
[1].ma
= value
;
163 case PCIL0_PMM1PCIHA
:
164 pci
->pmm
[1].pciha
= value
;
166 case PCIL0_PMM1PCILA
:
167 pci
->pmm
[1].pcila
= value
;
171 pci
->pmm
[2].la
= value
;
174 pci
->pmm
[2].ma
= value
;
176 case PCIL0_PMM2PCIHA
:
177 pci
->pmm
[2].pciha
= value
;
179 case PCIL0_PMM2PCILA
:
180 pci
->pmm
[2].pcila
= value
;
184 pci
->ptm
[0].ms
= value
;
187 pci
->ptm
[0].la
= value
;
190 pci
->ptm
[1].ms
= value
;
193 pci
->ptm
[1].la
= value
;
197 printf("%s: unhandled PCI internal register 0x%lx\n", __func__
,
198 (unsigned long)offset
);
203 static uint32_t ppc4xx_pci_reg_read4(void *opaque
, target_phys_addr_t offset
)
205 struct PPC4xxPCIState
*pci
= opaque
;
210 value
= pci
->pmm
[0].la
;
213 value
= pci
->pmm
[0].ma
;
215 case PCIL0_PMM0PCIHA
:
216 value
= pci
->pmm
[0].pciha
;
218 case PCIL0_PMM0PCILA
:
219 value
= pci
->pmm
[0].pcila
;
223 value
= pci
->pmm
[1].la
;
226 value
= pci
->pmm
[1].ma
;
228 case PCIL0_PMM1PCIHA
:
229 value
= pci
->pmm
[1].pciha
;
231 case PCIL0_PMM1PCILA
:
232 value
= pci
->pmm
[1].pcila
;
236 value
= pci
->pmm
[2].la
;
239 value
= pci
->pmm
[2].ma
;
241 case PCIL0_PMM2PCIHA
:
242 value
= pci
->pmm
[2].pciha
;
244 case PCIL0_PMM2PCILA
:
245 value
= pci
->pmm
[2].pcila
;
249 value
= pci
->ptm
[0].ms
;
252 value
= pci
->ptm
[0].la
;
255 value
= pci
->ptm
[1].ms
;
258 value
= pci
->ptm
[1].la
;
262 printf("%s: invalid PCI internal register 0x%lx\n", __func__
,
263 (unsigned long)offset
);
267 #ifdef TARGET_WORDS_BIGENDIAN
268 value
= bswap32(value
);
274 static CPUReadMemoryFunc
*pci_reg_read
[] = {
275 &ppc4xx_pci_reg_read4
,
276 &ppc4xx_pci_reg_read4
,
277 &ppc4xx_pci_reg_read4
,
280 static CPUWriteMemoryFunc
*pci_reg_write
[] = {
281 &ppc4xx_pci_reg_write4
,
282 &ppc4xx_pci_reg_write4
,
283 &ppc4xx_pci_reg_write4
,
286 static void ppc4xx_pci_reset(void *opaque
)
288 struct PPC4xxPCIState
*pci
= opaque
;
290 memset(pci
->pmm
, 0, sizeof(pci
->pmm
));
291 memset(pci
->ptm
, 0, sizeof(pci
->ptm
));
294 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
295 * may need further refactoring for other boards. */
296 static int ppc4xx_pci_map_irq(PCIDevice
*pci_dev
, int irq_num
)
298 int slot
= pci_dev
->devfn
>> 3;
300 DPRINTF("%s: devfn %x irq %d -> %d\n", __func__
,
301 pci_dev
->devfn
, irq_num
, slot
);
306 static void ppc4xx_pci_set_irq(qemu_irq
*pci_irqs
, int irq_num
, int level
)
308 DPRINTF("%s: PCI irq %d\n", __func__
, irq_num
);
309 qemu_set_irq(pci_irqs
[irq_num
], level
);
312 static void ppc4xx_pci_save(QEMUFile
*f
, void *opaque
)
314 PPC4xxPCIState
*controller
= opaque
;
317 pci_device_save(controller
->pci_dev
, f
);
319 for (i
= 0; i
< PPC4xx_PCI_NR_PMMS
; i
++) {
320 qemu_put_be32s(f
, &controller
->pmm
[i
].la
);
321 qemu_put_be32s(f
, &controller
->pmm
[i
].ma
);
322 qemu_put_be32s(f
, &controller
->pmm
[i
].pcila
);
323 qemu_put_be32s(f
, &controller
->pmm
[i
].pciha
);
326 for (i
= 0; i
< PPC4xx_PCI_NR_PTMS
; i
++) {
327 qemu_put_be32s(f
, &controller
->ptm
[i
].ms
);
328 qemu_put_be32s(f
, &controller
->ptm
[i
].la
);
332 static int ppc4xx_pci_load(QEMUFile
*f
, void *opaque
, int version_id
)
334 PPC4xxPCIState
*controller
= opaque
;
340 pci_device_load(controller
->pci_dev
, f
);
342 for (i
= 0; i
< PPC4xx_PCI_NR_PMMS
; i
++) {
343 qemu_get_be32s(f
, &controller
->pmm
[i
].la
);
344 qemu_get_be32s(f
, &controller
->pmm
[i
].ma
);
345 qemu_get_be32s(f
, &controller
->pmm
[i
].pcila
);
346 qemu_get_be32s(f
, &controller
->pmm
[i
].pciha
);
349 for (i
= 0; i
< PPC4xx_PCI_NR_PTMS
; i
++) {
350 qemu_get_be32s(f
, &controller
->ptm
[i
].ms
);
351 qemu_get_be32s(f
, &controller
->ptm
[i
].la
);
357 /* XXX Interrupt acknowledge cycles not supported. */
358 PCIBus
*ppc4xx_pci_init(CPUState
*env
, qemu_irq pci_irqs
[4],
359 target_phys_addr_t config_space
,
360 target_phys_addr_t int_ack
,
361 target_phys_addr_t special_cycle
,
362 target_phys_addr_t registers
)
364 PPC4xxPCIState
*controller
;
366 static int ppc4xx_pci_id
;
368 controller
= qemu_mallocz(sizeof(PPC4xxPCIState
));
372 controller
->pci_state
.bus
= pci_register_bus(ppc4xx_pci_set_irq
,
376 controller
->pci_dev
= pci_register_device(controller
->pci_state
.bus
,
377 "host bridge", sizeof(PCIDevice
),
379 controller
->pci_dev
->config
[0x00] = 0x14; // vendor_id
380 controller
->pci_dev
->config
[0x01] = 0x10;
381 controller
->pci_dev
->config
[0x02] = 0x7f; // device_id
382 controller
->pci_dev
->config
[0x03] = 0x02;
383 controller
->pci_dev
->config
[0x0a] = 0x80; // class_sub = other bridge type
384 controller
->pci_dev
->config
[0x0b] = 0x06; // class_base = PCI_bridge
387 index
= cpu_register_io_memory(0, pci4xx_cfgaddr_read
,
388 pci4xx_cfgaddr_write
, controller
);
391 cpu_register_physical_memory(config_space
+ PCIC0_CFGADDR
, 4, index
);
394 index
= cpu_register_io_memory(0, pci4xx_cfgdata_read
,
395 pci4xx_cfgdata_write
,
396 &controller
->pci_state
);
399 cpu_register_physical_memory(config_space
+ PCIC0_CFGDATA
, 4, index
);
401 /* Internal registers */
402 index
= cpu_register_io_memory(0, pci_reg_read
, pci_reg_write
, controller
);
405 cpu_register_physical_memory(registers
, PCI_REG_SIZE
, index
);
407 qemu_register_reset(ppc4xx_pci_reset
, controller
);
409 /* XXX load/save code not tested. */
410 register_savevm("ppc4xx_pci", ppc4xx_pci_id
++, 1,
411 ppc4xx_pci_save
, ppc4xx_pci_load
, controller
);
413 return controller
->pci_state
.bus
;
416 printf("%s error\n", __func__
);
417 qemu_free(controller
);