2 * Intel XScale PXA255/270 GPIO controller emulation.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licensed under the GPL.
12 #define PXA2XX_GPIO_BANKS 4
14 struct pxa2xx_gpio_info_s
{
15 target_phys_addr_t base
;
21 /* XXX: GNU C vectors are more suitable */
22 uint32_t ilevel
[PXA2XX_GPIO_BANKS
];
23 uint32_t olevel
[PXA2XX_GPIO_BANKS
];
24 uint32_t dir
[PXA2XX_GPIO_BANKS
];
25 uint32_t rising
[PXA2XX_GPIO_BANKS
];
26 uint32_t falling
[PXA2XX_GPIO_BANKS
];
27 uint32_t status
[PXA2XX_GPIO_BANKS
];
28 uint32_t gpsr
[PXA2XX_GPIO_BANKS
];
29 uint32_t gafr
[PXA2XX_GPIO_BANKS
* 2];
31 uint32_t prev_level
[PXA2XX_GPIO_BANKS
];
32 qemu_irq handler
[PXA2XX_GPIO_BANKS
* 32];
50 } pxa2xx_gpio_regs
[0x200] = {
51 [0 ... 0x1ff] = { GPIO_NONE
, 0 },
52 #define PXA2XX_REG(reg, a0, a1, a2, a3) \
53 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
55 PXA2XX_REG(GPLR
, 0x000, 0x004, 0x008, 0x100)
56 PXA2XX_REG(GPSR
, 0x018, 0x01c, 0x020, 0x118)
57 PXA2XX_REG(GPCR
, 0x024, 0x028, 0x02c, 0x124)
58 PXA2XX_REG(GPDR
, 0x00c, 0x010, 0x014, 0x10c)
59 PXA2XX_REG(GRER
, 0x030, 0x034, 0x038, 0x130)
60 PXA2XX_REG(GFER
, 0x03c, 0x040, 0x044, 0x13c)
61 PXA2XX_REG(GEDR
, 0x048, 0x04c, 0x050, 0x148)
62 PXA2XX_REG(GAFR_L
, 0x054, 0x05c, 0x064, 0x06c)
63 PXA2XX_REG(GAFR_U
, 0x058, 0x060, 0x068, 0x070)
66 static void pxa2xx_gpio_irq_update(struct pxa2xx_gpio_info_s
*s
)
68 if (s
->status
[0] & (1 << 0))
69 qemu_irq_raise(s
->pic
[PXA2XX_PIC_GPIO_0
]);
71 qemu_irq_lower(s
->pic
[PXA2XX_PIC_GPIO_0
]);
73 if (s
->status
[0] & (1 << 1))
74 qemu_irq_raise(s
->pic
[PXA2XX_PIC_GPIO_1
]);
76 qemu_irq_lower(s
->pic
[PXA2XX_PIC_GPIO_1
]);
78 if ((s
->status
[0] & ~3) | s
->status
[1] | s
->status
[2] | s
->status
[3])
79 qemu_irq_raise(s
->pic
[PXA2XX_PIC_GPIO_X
]);
81 qemu_irq_lower(s
->pic
[PXA2XX_PIC_GPIO_X
]);
84 /* Bitmap of pins used as standby and sleep wake-up sources. */
85 static const int pxa2xx_gpio_wake
[PXA2XX_GPIO_BANKS
] = {
86 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
89 static void pxa2xx_gpio_set(void *opaque
, int line
, int level
)
91 struct pxa2xx_gpio_info_s
*s
= (struct pxa2xx_gpio_info_s
*) opaque
;
95 if (line
>= s
->lines
) {
96 printf("%s: No GPIO pin %i\n", __FUNCTION__
, line
);
101 mask
= 1 << (line
& 31);
104 s
->status
[bank
] |= s
->rising
[bank
] & mask
&
105 ~s
->ilevel
[bank
] & ~s
->dir
[bank
];
106 s
->ilevel
[bank
] |= mask
;
108 s
->status
[bank
] |= s
->falling
[bank
] & mask
&
109 s
->ilevel
[bank
] & ~s
->dir
[bank
];
110 s
->ilevel
[bank
] &= ~mask
;
113 if (s
->status
[bank
] & mask
)
114 pxa2xx_gpio_irq_update(s
);
117 if (s
->cpu_env
->halted
&& (mask
& ~s
->dir
[bank
] & pxa2xx_gpio_wake
[bank
]))
118 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_EXITTB
);
121 static void pxa2xx_gpio_handler_update(struct pxa2xx_gpio_info_s
*s
) {
122 uint32_t level
, diff
;
124 for (i
= 0; i
< PXA2XX_GPIO_BANKS
; i
++) {
125 level
= s
->olevel
[i
] & s
->dir
[i
];
127 for (diff
= s
->prev_level
[i
] ^ level
; diff
; diff
^= 1 << bit
) {
130 qemu_set_irq(s
->handler
[line
], (level
>> bit
) & 1);
133 s
->prev_level
[i
] = level
;
137 static uint32_t pxa2xx_gpio_read(void *opaque
, target_phys_addr_t offset
)
139 struct pxa2xx_gpio_info_s
*s
= (struct pxa2xx_gpio_info_s
*) opaque
;
146 bank
= pxa2xx_gpio_regs
[offset
].bank
;
147 switch (pxa2xx_gpio_regs
[offset
].reg
) {
148 case GPDR
: /* GPIO Pin-Direction registers */
151 case GPSR
: /* GPIO Pin-Output Set registers */
152 printf("%s: Read from a write-only register " REG_FMT
"\n",
153 __FUNCTION__
, offset
);
154 return s
->gpsr
[bank
]; /* Return last written value. */
156 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
157 return s
->rising
[bank
];
159 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
160 return s
->falling
[bank
];
162 case GAFR_L
: /* GPIO Alternate Function registers */
163 return s
->gafr
[bank
* 2];
165 case GAFR_U
: /* GPIO Alternate Function registers */
166 return s
->gafr
[bank
* 2 + 1];
168 case GPLR
: /* GPIO Pin-Level registers */
169 ret
= (s
->olevel
[bank
] & s
->dir
[bank
]) |
170 (s
->ilevel
[bank
] & ~s
->dir
[bank
]);
171 qemu_irq_raise(s
->read_notify
);
174 case GEDR
: /* GPIO Edge Detect Status registers */
175 return s
->status
[bank
];
178 cpu_abort(cpu_single_env
,
179 "%s: Bad offset " REG_FMT
"\n", __FUNCTION__
, offset
);
185 static void pxa2xx_gpio_write(void *opaque
,
186 target_phys_addr_t offset
, uint32_t value
)
188 struct pxa2xx_gpio_info_s
*s
= (struct pxa2xx_gpio_info_s
*) opaque
;
194 bank
= pxa2xx_gpio_regs
[offset
].bank
;
195 switch (pxa2xx_gpio_regs
[offset
].reg
) {
196 case GPDR
: /* GPIO Pin-Direction registers */
197 s
->dir
[bank
] = value
;
198 pxa2xx_gpio_handler_update(s
);
201 case GPSR
: /* GPIO Pin-Output Set registers */
202 s
->olevel
[bank
] |= value
;
203 pxa2xx_gpio_handler_update(s
);
204 s
->gpsr
[bank
] = value
;
207 case GPCR
: /* GPIO Pin-Output Clear registers */
208 s
->olevel
[bank
] &= ~value
;
209 pxa2xx_gpio_handler_update(s
);
212 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
213 s
->rising
[bank
] = value
;
216 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
217 s
->falling
[bank
] = value
;
220 case GAFR_L
: /* GPIO Alternate Function registers */
221 s
->gafr
[bank
* 2] = value
;
224 case GAFR_U
: /* GPIO Alternate Function registers */
225 s
->gafr
[bank
* 2 + 1] = value
;
228 case GEDR
: /* GPIO Edge Detect Status registers */
229 s
->status
[bank
] &= ~value
;
230 pxa2xx_gpio_irq_update(s
);
234 cpu_abort(cpu_single_env
,
235 "%s: Bad offset " REG_FMT
"\n", __FUNCTION__
, offset
);
239 static CPUReadMemoryFunc
*pxa2xx_gpio_readfn
[] = {
245 static CPUWriteMemoryFunc
*pxa2xx_gpio_writefn
[] = {
251 static void pxa2xx_gpio_save(QEMUFile
*f
, void *opaque
)
253 struct pxa2xx_gpio_info_s
*s
= (struct pxa2xx_gpio_info_s
*) opaque
;
256 qemu_put_be32(f
, s
->lines
);
258 for (i
= 0; i
< PXA2XX_GPIO_BANKS
; i
++) {
259 qemu_put_be32s(f
, &s
->ilevel
[i
]);
260 qemu_put_be32s(f
, &s
->olevel
[i
]);
261 qemu_put_be32s(f
, &s
->dir
[i
]);
262 qemu_put_be32s(f
, &s
->rising
[i
]);
263 qemu_put_be32s(f
, &s
->falling
[i
]);
264 qemu_put_be32s(f
, &s
->status
[i
]);
265 qemu_put_be32s(f
, &s
->gafr
[i
* 2 + 0]);
266 qemu_put_be32s(f
, &s
->gafr
[i
* 2 + 1]);
268 qemu_put_be32s(f
, &s
->prev_level
[i
]);
272 static int pxa2xx_gpio_load(QEMUFile
*f
, void *opaque
, int version_id
)
274 struct pxa2xx_gpio_info_s
*s
= (struct pxa2xx_gpio_info_s
*) opaque
;
277 if (qemu_get_be32(f
) != s
->lines
)
280 for (i
= 0; i
< PXA2XX_GPIO_BANKS
; i
++) {
281 qemu_get_be32s(f
, &s
->ilevel
[i
]);
282 qemu_get_be32s(f
, &s
->olevel
[i
]);
283 qemu_get_be32s(f
, &s
->dir
[i
]);
284 qemu_get_be32s(f
, &s
->rising
[i
]);
285 qemu_get_be32s(f
, &s
->falling
[i
]);
286 qemu_get_be32s(f
, &s
->status
[i
]);
287 qemu_get_be32s(f
, &s
->gafr
[i
* 2 + 0]);
288 qemu_get_be32s(f
, &s
->gafr
[i
* 2 + 1]);
290 qemu_get_be32s(f
, &s
->prev_level
[i
]);
296 struct pxa2xx_gpio_info_s
*pxa2xx_gpio_init(target_phys_addr_t base
,
297 CPUState
*env
, qemu_irq
*pic
, int lines
)
300 struct pxa2xx_gpio_info_s
*s
;
302 s
= (struct pxa2xx_gpio_info_s
*)
303 qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s
));
304 memset(s
, 0, sizeof(struct pxa2xx_gpio_info_s
));
309 s
->in
= qemu_allocate_irqs(pxa2xx_gpio_set
, s
, lines
);
311 iomemtype
= cpu_register_io_memory(0, pxa2xx_gpio_readfn
,
312 pxa2xx_gpio_writefn
, s
);
313 cpu_register_physical_memory(base
, 0x00001000, iomemtype
);
315 register_savevm("pxa2xx_gpio", 0, 0,
316 pxa2xx_gpio_save
, pxa2xx_gpio_load
, s
);
321 qemu_irq
*pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s
*s
)
326 void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s
*s
,
327 int line
, qemu_irq handler
)
329 if (line
>= s
->lines
) {
330 printf("%s: No GPIO pin %i\n", __FUNCTION__
, line
);
334 s
->handler
[line
] = handler
;
338 * Registers a callback to notify on GPLR reads. This normally
339 * shouldn't be needed but it is used for the hack on Spitz machines.
341 void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s
*s
, qemu_irq handler
)
343 s
->read_notify
= handler
;