2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu-common.h"
22 #include "qemu-timer.h"
23 #include "qemu-queue.h"
30 #ifndef CONFIG_QXL_IO_MONITORS_CONFIG_ASYNC
31 /* spice-protocol is too old, add missing definitions */
32 #define QXL_IO_MONITORS_CONFIG_ASYNC (QXL_IO_FLUSH_RELEASE + 1)
36 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
37 * such can be changed by the guest, so to avoid a guest trigerrable
38 * abort we just qxl_set_guest_bug and set the return to NULL. Still
39 * it may happen as a result of emulator bug as well.
41 #undef SPICE_RING_PROD_ITEM
42 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
43 typeof(r) start = r; \
44 typeof(r) end = r + 1; \
45 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
46 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
47 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
48 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
49 "! %p <= %p < %p", (uint8_t *)start, \
50 (uint8_t *)m_item, (uint8_t *)end); \
57 #undef SPICE_RING_CONS_ITEM
58 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
59 typeof(r) start = r; \
60 typeof(r) end = r + 1; \
61 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
62 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
63 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
64 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
65 "! %p <= %p < %p", (uint8_t *)start, \
66 (uint8_t *)m_item, (uint8_t *)end); \
74 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
76 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
78 #define QXL_MODE(_x, _y, _b, _o) \
82 .stride = (_x) * (_b) / 8, \
83 .x_mili = PIXEL_SIZE * (_x), \
84 .y_mili = PIXEL_SIZE * (_y), \
88 #define QXL_MODE_16_32(x_res, y_res, orientation) \
89 QXL_MODE(x_res, y_res, 16, orientation), \
90 QXL_MODE(x_res, y_res, 32, orientation)
92 #define QXL_MODE_EX(x_res, y_res) \
93 QXL_MODE_16_32(x_res, y_res, 0), \
94 QXL_MODE_16_32(y_res, x_res, 1), \
95 QXL_MODE_16_32(x_res, y_res, 2), \
96 QXL_MODE_16_32(y_res, x_res, 3)
98 static QXLMode qxl_modes
[] = {
99 QXL_MODE_EX(640, 480),
100 QXL_MODE_EX(800, 480),
101 QXL_MODE_EX(800, 600),
102 QXL_MODE_EX(832, 624),
103 QXL_MODE_EX(960, 640),
104 QXL_MODE_EX(1024, 600),
105 QXL_MODE_EX(1024, 768),
106 QXL_MODE_EX(1152, 864),
107 QXL_MODE_EX(1152, 870),
108 QXL_MODE_EX(1280, 720),
109 QXL_MODE_EX(1280, 760),
110 QXL_MODE_EX(1280, 768),
111 QXL_MODE_EX(1280, 800),
112 QXL_MODE_EX(1280, 960),
113 QXL_MODE_EX(1280, 1024),
114 QXL_MODE_EX(1360, 768),
115 QXL_MODE_EX(1366, 768),
116 QXL_MODE_EX(1400, 1050),
117 QXL_MODE_EX(1440, 900),
118 QXL_MODE_EX(1600, 900),
119 QXL_MODE_EX(1600, 1200),
120 QXL_MODE_EX(1680, 1050),
121 QXL_MODE_EX(1920, 1080),
122 /* these modes need more than 8 MB video memory */
123 QXL_MODE_EX(1920, 1200),
124 QXL_MODE_EX(1920, 1440),
125 QXL_MODE_EX(2048, 1536),
126 QXL_MODE_EX(2560, 1440),
127 QXL_MODE_EX(2560, 1600),
128 /* these modes need more than 16 MB video memory */
129 QXL_MODE_EX(2560, 2048),
130 QXL_MODE_EX(2800, 2100),
131 QXL_MODE_EX(3200, 2400),
134 static PCIQXLDevice
*qxl0
;
136 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
);
137 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
);
138 static void qxl_reset_memslots(PCIQXLDevice
*d
);
139 static void qxl_reset_surfaces(PCIQXLDevice
*d
);
140 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
);
142 void qxl_set_guest_bug(PCIQXLDevice
*qxl
, const char *msg
, ...)
144 qxl_send_events(qxl
, QXL_INTERRUPT_ERROR
);
146 if (qxl
->guestdebug
) {
149 fprintf(stderr
, "qxl-%d: guest bug: ", qxl
->id
);
150 vfprintf(stderr
, msg
, ap
);
151 fprintf(stderr
, "\n");
156 static void qxl_clear_guest_bug(PCIQXLDevice
*qxl
)
161 void qxl_spice_update_area(PCIQXLDevice
*qxl
, uint32_t surface_id
,
162 struct QXLRect
*area
, struct QXLRect
*dirty_rects
,
163 uint32_t num_dirty_rects
,
164 uint32_t clear_dirty_region
,
165 qxl_async_io async
, struct QXLCookie
*cookie
)
167 trace_qxl_spice_update_area(qxl
->id
, surface_id
, area
->left
, area
->right
,
168 area
->top
, area
->bottom
);
169 trace_qxl_spice_update_area_rest(qxl
->id
, num_dirty_rects
,
171 if (async
== QXL_SYNC
) {
172 qxl
->ssd
.worker
->update_area(qxl
->ssd
.worker
, surface_id
, area
,
173 dirty_rects
, num_dirty_rects
, clear_dirty_region
);
175 assert(cookie
!= NULL
);
176 spice_qxl_update_area_async(&qxl
->ssd
.qxl
, surface_id
, area
,
177 clear_dirty_region
, (uintptr_t)cookie
);
181 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice
*qxl
,
184 trace_qxl_spice_destroy_surface_wait_complete(qxl
->id
, id
);
185 qemu_mutex_lock(&qxl
->track_lock
);
186 qxl
->guest_surfaces
.cmds
[id
] = 0;
187 qxl
->guest_surfaces
.count
--;
188 qemu_mutex_unlock(&qxl
->track_lock
);
191 static void qxl_spice_destroy_surface_wait(PCIQXLDevice
*qxl
, uint32_t id
,
196 trace_qxl_spice_destroy_surface_wait(qxl
->id
, id
, async
);
198 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
199 QXL_IO_DESTROY_SURFACE_ASYNC
);
200 cookie
->u
.surface_id
= id
;
201 spice_qxl_destroy_surface_async(&qxl
->ssd
.qxl
, id
, (uintptr_t)cookie
);
203 qxl
->ssd
.worker
->destroy_surface_wait(qxl
->ssd
.worker
, id
);
207 static void qxl_spice_flush_surfaces_async(PCIQXLDevice
*qxl
)
209 trace_qxl_spice_flush_surfaces_async(qxl
->id
, qxl
->guest_surfaces
.count
,
211 spice_qxl_flush_surfaces_async(&qxl
->ssd
.qxl
,
212 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
213 QXL_IO_FLUSH_SURFACES_ASYNC
));
216 void qxl_spice_loadvm_commands(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
,
219 trace_qxl_spice_loadvm_commands(qxl
->id
, ext
, count
);
220 qxl
->ssd
.worker
->loadvm_commands(qxl
->ssd
.worker
, ext
, count
);
223 void qxl_spice_oom(PCIQXLDevice
*qxl
)
225 trace_qxl_spice_oom(qxl
->id
);
226 qxl
->ssd
.worker
->oom(qxl
->ssd
.worker
);
229 void qxl_spice_reset_memslots(PCIQXLDevice
*qxl
)
231 trace_qxl_spice_reset_memslots(qxl
->id
);
232 qxl
->ssd
.worker
->reset_memslots(qxl
->ssd
.worker
);
235 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice
*qxl
)
237 trace_qxl_spice_destroy_surfaces_complete(qxl
->id
);
238 qemu_mutex_lock(&qxl
->track_lock
);
239 memset(&qxl
->guest_surfaces
.cmds
, 0, sizeof(qxl
->guest_surfaces
.cmds
));
240 qxl
->guest_surfaces
.count
= 0;
241 qemu_mutex_unlock(&qxl
->track_lock
);
244 static void qxl_spice_destroy_surfaces(PCIQXLDevice
*qxl
, qxl_async_io async
)
246 trace_qxl_spice_destroy_surfaces(qxl
->id
, async
);
248 spice_qxl_destroy_surfaces_async(&qxl
->ssd
.qxl
,
249 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
250 QXL_IO_DESTROY_ALL_SURFACES_ASYNC
));
252 qxl
->ssd
.worker
->destroy_surfaces(qxl
->ssd
.worker
);
253 qxl_spice_destroy_surfaces_complete(qxl
);
257 static void qxl_spice_monitors_config_async(PCIQXLDevice
*qxl
, int replay
)
259 trace_qxl_spice_monitors_config(qxl
->id
);
260 /* 0x000b01 == 0.11.1 */
261 #if SPICE_SERVER_VERSION >= 0x000b01 && \
262 defined(CONFIG_QXL_IO_MONITORS_CONFIG_ASYNC)
265 * don't use QXL_COOKIE_TYPE_IO:
266 * - we are not running yet (post_load), we will assert
268 * - this is not a guest io, but a reply, so async_io isn't set.
270 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
271 qxl
->guest_monitors_config
,
273 (uintptr_t)qxl_cookie_new(
274 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
,
277 qxl
->guest_monitors_config
= qxl
->ram
->monitors_config
;
278 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
279 qxl
->ram
->monitors_config
,
281 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
282 QXL_IO_MONITORS_CONFIG_ASYNC
));
285 fprintf(stderr
, "qxl: too old spice-protocol/spice-server for "
286 "QXL_IO_MONITORS_CONFIG_ASYNC\n");
290 void qxl_spice_reset_image_cache(PCIQXLDevice
*qxl
)
292 trace_qxl_spice_reset_image_cache(qxl
->id
);
293 qxl
->ssd
.worker
->reset_image_cache(qxl
->ssd
.worker
);
296 void qxl_spice_reset_cursor(PCIQXLDevice
*qxl
)
298 trace_qxl_spice_reset_cursor(qxl
->id
);
299 qxl
->ssd
.worker
->reset_cursor(qxl
->ssd
.worker
);
300 qemu_mutex_lock(&qxl
->track_lock
);
301 qxl
->guest_cursor
= 0;
302 qemu_mutex_unlock(&qxl
->track_lock
);
306 static inline uint32_t msb_mask(uint32_t val
)
311 mask
= ~(val
- 1) & val
;
313 } while (mask
< val
);
318 static ram_addr_t
qxl_rom_size(void)
320 uint32_t rom_size
= sizeof(QXLRom
) + sizeof(QXLModes
) + sizeof(qxl_modes
);
322 rom_size
= MAX(rom_size
, TARGET_PAGE_SIZE
);
323 rom_size
= msb_mask(rom_size
* 2 - 1);
327 static void init_qxl_rom(PCIQXLDevice
*d
)
329 QXLRom
*rom
= memory_region_get_ram_ptr(&d
->rom_bar
);
330 QXLModes
*modes
= (QXLModes
*)(rom
+ 1);
331 uint32_t ram_header_size
;
332 uint32_t surface0_area_size
;
337 memset(rom
, 0, d
->rom_size
);
339 rom
->magic
= cpu_to_le32(QXL_ROM_MAGIC
);
340 rom
->id
= cpu_to_le32(d
->id
);
341 rom
->log_level
= cpu_to_le32(d
->guestdebug
);
342 rom
->modes_offset
= cpu_to_le32(sizeof(QXLRom
));
344 rom
->slot_gen_bits
= MEMSLOT_GENERATION_BITS
;
345 rom
->slot_id_bits
= MEMSLOT_SLOT_BITS
;
346 rom
->slots_start
= 1;
347 rom
->slots_end
= NUM_MEMSLOTS
- 1;
348 rom
->n_surfaces
= cpu_to_le32(NUM_SURFACES
);
350 for (i
= 0, n
= 0; i
< ARRAY_SIZE(qxl_modes
); i
++) {
351 fb
= qxl_modes
[i
].y_res
* qxl_modes
[i
].stride
;
352 if (fb
> d
->vgamem_size
) {
355 modes
->modes
[n
].id
= cpu_to_le32(i
);
356 modes
->modes
[n
].x_res
= cpu_to_le32(qxl_modes
[i
].x_res
);
357 modes
->modes
[n
].y_res
= cpu_to_le32(qxl_modes
[i
].y_res
);
358 modes
->modes
[n
].bits
= cpu_to_le32(qxl_modes
[i
].bits
);
359 modes
->modes
[n
].stride
= cpu_to_le32(qxl_modes
[i
].stride
);
360 modes
->modes
[n
].x_mili
= cpu_to_le32(qxl_modes
[i
].x_mili
);
361 modes
->modes
[n
].y_mili
= cpu_to_le32(qxl_modes
[i
].y_mili
);
362 modes
->modes
[n
].orientation
= cpu_to_le32(qxl_modes
[i
].orientation
);
365 modes
->n_modes
= cpu_to_le32(n
);
367 ram_header_size
= ALIGN(sizeof(QXLRam
), 4096);
368 surface0_area_size
= ALIGN(d
->vgamem_size
, 4096);
369 num_pages
= d
->vga
.vram_size
;
370 num_pages
-= ram_header_size
;
371 num_pages
-= surface0_area_size
;
372 num_pages
= num_pages
/ TARGET_PAGE_SIZE
;
374 rom
->draw_area_offset
= cpu_to_le32(0);
375 rom
->surface0_area_size
= cpu_to_le32(surface0_area_size
);
376 rom
->pages_offset
= cpu_to_le32(surface0_area_size
);
377 rom
->num_pages
= cpu_to_le32(num_pages
);
378 rom
->ram_header_offset
= cpu_to_le32(d
->vga
.vram_size
- ram_header_size
);
380 d
->shadow_rom
= *rom
;
385 static void init_qxl_ram(PCIQXLDevice
*d
)
390 buf
= d
->vga
.vram_ptr
;
391 d
->ram
= (QXLRam
*)(buf
+ le32_to_cpu(d
->shadow_rom
.ram_header_offset
));
392 d
->ram
->magic
= cpu_to_le32(QXL_RAM_MAGIC
);
393 d
->ram
->int_pending
= cpu_to_le32(0);
394 d
->ram
->int_mask
= cpu_to_le32(0);
395 d
->ram
->update_surface
= 0;
396 SPICE_RING_INIT(&d
->ram
->cmd_ring
);
397 SPICE_RING_INIT(&d
->ram
->cursor_ring
);
398 SPICE_RING_INIT(&d
->ram
->release_ring
);
399 SPICE_RING_PROD_ITEM(d
, &d
->ram
->release_ring
, item
);
402 qxl_ring_set_dirty(d
);
405 /* can be called from spice server thread context */
406 static void qxl_set_dirty(MemoryRegion
*mr
, ram_addr_t addr
, ram_addr_t end
)
408 memory_region_set_dirty(mr
, addr
, end
- addr
);
411 static void qxl_rom_set_dirty(PCIQXLDevice
*qxl
)
413 qxl_set_dirty(&qxl
->rom_bar
, 0, qxl
->rom_size
);
416 /* called from spice server thread context only */
417 static void qxl_ram_set_dirty(PCIQXLDevice
*qxl
, void *ptr
)
419 void *base
= qxl
->vga
.vram_ptr
;
423 offset
&= ~(TARGET_PAGE_SIZE
-1);
424 assert(offset
< qxl
->vga
.vram_size
);
425 qxl_set_dirty(&qxl
->vga
.vram
, offset
, offset
+ TARGET_PAGE_SIZE
);
428 /* can be called from spice server thread context */
429 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
)
431 ram_addr_t addr
= qxl
->shadow_rom
.ram_header_offset
;
432 ram_addr_t end
= qxl
->vga
.vram_size
;
433 qxl_set_dirty(&qxl
->vga
.vram
, addr
, end
);
437 * keep track of some command state, for savevm/loadvm.
438 * called from spice server thread context only
440 static int qxl_track_command(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
)
442 switch (le32_to_cpu(ext
->cmd
.type
)) {
443 case QXL_CMD_SURFACE
:
445 QXLSurfaceCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
450 uint32_t id
= le32_to_cpu(cmd
->surface_id
);
452 if (id
>= NUM_SURFACES
) {
453 qxl_set_guest_bug(qxl
, "QXL_CMD_SURFACE id %d >= %d", id
,
457 qemu_mutex_lock(&qxl
->track_lock
);
458 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
) {
459 qxl
->guest_surfaces
.cmds
[id
] = ext
->cmd
.data
;
460 qxl
->guest_surfaces
.count
++;
461 if (qxl
->guest_surfaces
.max
< qxl
->guest_surfaces
.count
)
462 qxl
->guest_surfaces
.max
= qxl
->guest_surfaces
.count
;
464 if (cmd
->type
== QXL_SURFACE_CMD_DESTROY
) {
465 qxl
->guest_surfaces
.cmds
[id
] = 0;
466 qxl
->guest_surfaces
.count
--;
468 qemu_mutex_unlock(&qxl
->track_lock
);
473 QXLCursorCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
478 if (cmd
->type
== QXL_CURSOR_SET
) {
479 qemu_mutex_lock(&qxl
->track_lock
);
480 qxl
->guest_cursor
= ext
->cmd
.data
;
481 qemu_mutex_unlock(&qxl
->track_lock
);
489 /* spice display interface callbacks */
491 static void interface_attach_worker(QXLInstance
*sin
, QXLWorker
*qxl_worker
)
493 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
495 trace_qxl_interface_attach_worker(qxl
->id
);
496 qxl
->ssd
.worker
= qxl_worker
;
499 static void interface_set_compression_level(QXLInstance
*sin
, int level
)
501 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
503 trace_qxl_interface_set_compression_level(qxl
->id
, level
);
504 qxl
->shadow_rom
.compression_level
= cpu_to_le32(level
);
505 qxl
->rom
->compression_level
= cpu_to_le32(level
);
506 qxl_rom_set_dirty(qxl
);
509 static void interface_set_mm_time(QXLInstance
*sin
, uint32_t mm_time
)
511 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
513 trace_qxl_interface_set_mm_time(qxl
->id
, mm_time
);
514 qxl
->shadow_rom
.mm_clock
= cpu_to_le32(mm_time
);
515 qxl
->rom
->mm_clock
= cpu_to_le32(mm_time
);
516 qxl_rom_set_dirty(qxl
);
519 static void interface_get_init_info(QXLInstance
*sin
, QXLDevInitInfo
*info
)
521 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
523 trace_qxl_interface_get_init_info(qxl
->id
);
524 info
->memslot_gen_bits
= MEMSLOT_GENERATION_BITS
;
525 info
->memslot_id_bits
= MEMSLOT_SLOT_BITS
;
526 info
->num_memslots
= NUM_MEMSLOTS
;
527 info
->num_memslots_groups
= NUM_MEMSLOTS_GROUPS
;
528 info
->internal_groupslot_id
= 0;
529 info
->qxl_ram_size
= le32_to_cpu(qxl
->shadow_rom
.num_pages
) << TARGET_PAGE_BITS
;
530 info
->n_surfaces
= NUM_SURFACES
;
533 static const char *qxl_mode_to_string(int mode
)
536 case QXL_MODE_COMPAT
:
538 case QXL_MODE_NATIVE
:
540 case QXL_MODE_UNDEFINED
:
548 static const char *io_port_to_string(uint32_t io_port
)
550 if (io_port
>= QXL_IO_RANGE_SIZE
) {
551 return "out of range";
553 static const char *io_port_to_string
[QXL_IO_RANGE_SIZE
+ 1] = {
554 [QXL_IO_NOTIFY_CMD
] = "QXL_IO_NOTIFY_CMD",
555 [QXL_IO_NOTIFY_CURSOR
] = "QXL_IO_NOTIFY_CURSOR",
556 [QXL_IO_UPDATE_AREA
] = "QXL_IO_UPDATE_AREA",
557 [QXL_IO_UPDATE_IRQ
] = "QXL_IO_UPDATE_IRQ",
558 [QXL_IO_NOTIFY_OOM
] = "QXL_IO_NOTIFY_OOM",
559 [QXL_IO_RESET
] = "QXL_IO_RESET",
560 [QXL_IO_SET_MODE
] = "QXL_IO_SET_MODE",
561 [QXL_IO_LOG
] = "QXL_IO_LOG",
562 [QXL_IO_MEMSLOT_ADD
] = "QXL_IO_MEMSLOT_ADD",
563 [QXL_IO_MEMSLOT_DEL
] = "QXL_IO_MEMSLOT_DEL",
564 [QXL_IO_DETACH_PRIMARY
] = "QXL_IO_DETACH_PRIMARY",
565 [QXL_IO_ATTACH_PRIMARY
] = "QXL_IO_ATTACH_PRIMARY",
566 [QXL_IO_CREATE_PRIMARY
] = "QXL_IO_CREATE_PRIMARY",
567 [QXL_IO_DESTROY_PRIMARY
] = "QXL_IO_DESTROY_PRIMARY",
568 [QXL_IO_DESTROY_SURFACE_WAIT
] = "QXL_IO_DESTROY_SURFACE_WAIT",
569 [QXL_IO_DESTROY_ALL_SURFACES
] = "QXL_IO_DESTROY_ALL_SURFACES",
570 [QXL_IO_UPDATE_AREA_ASYNC
] = "QXL_IO_UPDATE_AREA_ASYNC",
571 [QXL_IO_MEMSLOT_ADD_ASYNC
] = "QXL_IO_MEMSLOT_ADD_ASYNC",
572 [QXL_IO_CREATE_PRIMARY_ASYNC
] = "QXL_IO_CREATE_PRIMARY_ASYNC",
573 [QXL_IO_DESTROY_PRIMARY_ASYNC
] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
574 [QXL_IO_DESTROY_SURFACE_ASYNC
] = "QXL_IO_DESTROY_SURFACE_ASYNC",
575 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC
]
576 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
577 [QXL_IO_FLUSH_SURFACES_ASYNC
] = "QXL_IO_FLUSH_SURFACES_ASYNC",
578 [QXL_IO_FLUSH_RELEASE
] = "QXL_IO_FLUSH_RELEASE",
579 [QXL_IO_MONITORS_CONFIG_ASYNC
] = "QXL_IO_MONITORS_CONFIG_ASYNC",
581 return io_port_to_string
[io_port
];
584 /* called from spice server thread context only */
585 static int interface_get_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
587 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
588 SimpleSpiceUpdate
*update
;
589 QXLCommandRing
*ring
;
593 trace_qxl_ring_command_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
598 qemu_mutex_lock(&qxl
->ssd
.lock
);
599 if (qxl
->ssd
.update
!= NULL
) {
600 update
= qxl
->ssd
.update
;
601 qxl
->ssd
.update
= NULL
;
605 qemu_mutex_unlock(&qxl
->ssd
.lock
);
607 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
608 qxl_log_command(qxl
, "vga", ext
);
611 case QXL_MODE_COMPAT
:
612 case QXL_MODE_NATIVE
:
613 case QXL_MODE_UNDEFINED
:
614 ring
= &qxl
->ram
->cmd_ring
;
615 if (qxl
->guest_bug
|| SPICE_RING_IS_EMPTY(ring
)) {
618 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
623 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
624 ext
->flags
= qxl
->cmdflags
;
625 SPICE_RING_POP(ring
, notify
);
626 qxl_ring_set_dirty(qxl
);
628 qxl_send_events(qxl
, QXL_INTERRUPT_DISPLAY
);
630 qxl
->guest_primary
.commands
++;
631 qxl_track_command(qxl
, ext
);
632 qxl_log_command(qxl
, "cmd", ext
);
633 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
640 /* called from spice server thread context only */
641 static int interface_req_cmd_notification(QXLInstance
*sin
)
643 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
646 trace_qxl_ring_command_req_notification(qxl
->id
);
648 case QXL_MODE_COMPAT
:
649 case QXL_MODE_NATIVE
:
650 case QXL_MODE_UNDEFINED
:
651 SPICE_RING_CONS_WAIT(&qxl
->ram
->cmd_ring
, wait
);
652 qxl_ring_set_dirty(qxl
);
661 /* called from spice server thread context only */
662 static inline void qxl_push_free_res(PCIQXLDevice
*d
, int flush
)
664 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
668 #define QXL_FREE_BUNCH_SIZE 32
670 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
671 /* ring full -- can't push */
674 if (!flush
&& d
->oom_running
) {
675 /* collect everything from oom handler before pushing */
678 if (!flush
&& d
->num_free_res
< QXL_FREE_BUNCH_SIZE
) {
679 /* collect a bit more before pushing */
683 SPICE_RING_PUSH(ring
, notify
);
684 trace_qxl_ring_res_push(d
->id
, qxl_mode_to_string(d
->mode
),
685 d
->guest_surfaces
.count
, d
->num_free_res
,
686 d
->last_release
, notify
? "yes" : "no");
687 trace_qxl_ring_res_push_rest(d
->id
, ring
->prod
- ring
->cons
,
688 ring
->num_items
, ring
->prod
, ring
->cons
);
690 qxl_send_events(d
, QXL_INTERRUPT_DISPLAY
);
692 SPICE_RING_PROD_ITEM(d
, ring
, item
);
698 d
->last_release
= NULL
;
699 qxl_ring_set_dirty(d
);
702 /* called from spice server thread context only */
703 static void interface_release_resource(QXLInstance
*sin
,
704 struct QXLReleaseInfoExt ext
)
706 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
707 QXLReleaseRing
*ring
;
710 if (ext
.group_id
== MEMSLOT_GROUP_HOST
) {
711 /* host group -> vga mode update request */
712 qemu_spice_destroy_update(&qxl
->ssd
, (void *)(intptr_t)ext
.info
->id
);
717 * ext->info points into guest-visible memory
718 * pci bar 0, $command.release_info
720 ring
= &qxl
->ram
->release_ring
;
721 SPICE_RING_PROD_ITEM(qxl
, ring
, item
);
726 /* stick head into the ring */
729 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
731 qxl_ring_set_dirty(qxl
);
733 /* append item to the list */
734 qxl
->last_release
->next
= ext
.info
->id
;
735 qxl_ram_set_dirty(qxl
, &qxl
->last_release
->next
);
737 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
739 qxl
->last_release
= ext
.info
;
741 trace_qxl_ring_res_put(qxl
->id
, qxl
->num_free_res
);
742 qxl_push_free_res(qxl
, 0);
745 /* called from spice server thread context only */
746 static int interface_get_cursor_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
748 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
753 trace_qxl_ring_cursor_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
756 case QXL_MODE_COMPAT
:
757 case QXL_MODE_NATIVE
:
758 case QXL_MODE_UNDEFINED
:
759 ring
= &qxl
->ram
->cursor_ring
;
760 if (SPICE_RING_IS_EMPTY(ring
)) {
763 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
768 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
769 ext
->flags
= qxl
->cmdflags
;
770 SPICE_RING_POP(ring
, notify
);
771 qxl_ring_set_dirty(qxl
);
773 qxl_send_events(qxl
, QXL_INTERRUPT_CURSOR
);
775 qxl
->guest_primary
.commands
++;
776 qxl_track_command(qxl
, ext
);
777 qxl_log_command(qxl
, "csr", ext
);
779 qxl_render_cursor(qxl
, ext
);
781 trace_qxl_ring_cursor_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
788 /* called from spice server thread context only */
789 static int interface_req_cursor_notification(QXLInstance
*sin
)
791 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
794 trace_qxl_ring_cursor_req_notification(qxl
->id
);
796 case QXL_MODE_COMPAT
:
797 case QXL_MODE_NATIVE
:
798 case QXL_MODE_UNDEFINED
:
799 SPICE_RING_CONS_WAIT(&qxl
->ram
->cursor_ring
, wait
);
800 qxl_ring_set_dirty(qxl
);
809 /* called from spice server thread context */
810 static void interface_notify_update(QXLInstance
*sin
, uint32_t update_id
)
813 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
814 * use by xf86-video-qxl and is defined out in the qxl windows driver.
815 * Probably was at some earlier version that is prior to git start (2009),
816 * and is still guest trigerrable.
818 fprintf(stderr
, "%s: deprecated\n", __func__
);
821 /* called from spice server thread context only */
822 static int interface_flush_resources(QXLInstance
*sin
)
824 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
827 ret
= qxl
->num_free_res
;
829 qxl_push_free_res(qxl
, 1);
834 static void qxl_create_guest_primary_complete(PCIQXLDevice
*d
);
836 /* called from spice server thread context only */
837 static void interface_async_complete_io(PCIQXLDevice
*qxl
, QXLCookie
*cookie
)
839 uint32_t current_async
;
841 qemu_mutex_lock(&qxl
->async_lock
);
842 current_async
= qxl
->current_async
;
843 qxl
->current_async
= QXL_UNDEFINED_IO
;
844 qemu_mutex_unlock(&qxl
->async_lock
);
846 trace_qxl_interface_async_complete_io(qxl
->id
, current_async
, cookie
);
848 fprintf(stderr
, "qxl: %s: error, cookie is NULL\n", __func__
);
851 if (cookie
&& current_async
!= cookie
->io
) {
853 "qxl: %s: error: current_async = %d != %"
854 PRId64
" = cookie->io\n", __func__
, current_async
, cookie
->io
);
856 switch (current_async
) {
857 case QXL_IO_MEMSLOT_ADD_ASYNC
:
858 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
859 case QXL_IO_UPDATE_AREA_ASYNC
:
860 case QXL_IO_FLUSH_SURFACES_ASYNC
:
861 case QXL_IO_MONITORS_CONFIG_ASYNC
:
863 case QXL_IO_CREATE_PRIMARY_ASYNC
:
864 qxl_create_guest_primary_complete(qxl
);
866 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
867 qxl_spice_destroy_surfaces_complete(qxl
);
869 case QXL_IO_DESTROY_SURFACE_ASYNC
:
870 qxl_spice_destroy_surface_wait_complete(qxl
, cookie
->u
.surface_id
);
873 fprintf(stderr
, "qxl: %s: unexpected current_async %d\n", __func__
,
876 qxl_send_events(qxl
, QXL_INTERRUPT_IO_CMD
);
879 /* called from spice server thread context only */
880 static void interface_update_area_complete(QXLInstance
*sin
,
882 QXLRect
*dirty
, uint32_t num_updated_rects
)
884 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
888 qemu_mutex_lock(&qxl
->ssd
.lock
);
889 if (surface_id
!= 0 || !qxl
->render_update_cookie_num
) {
890 qemu_mutex_unlock(&qxl
->ssd
.lock
);
893 trace_qxl_interface_update_area_complete(qxl
->id
, surface_id
, dirty
->left
,
894 dirty
->right
, dirty
->top
, dirty
->bottom
);
895 trace_qxl_interface_update_area_complete_rest(qxl
->id
, num_updated_rects
);
896 if (qxl
->num_dirty_rects
+ num_updated_rects
> QXL_NUM_DIRTY_RECTS
) {
898 * overflow - treat this as a full update. Not expected to be common.
900 trace_qxl_interface_update_area_complete_overflow(qxl
->id
,
901 QXL_NUM_DIRTY_RECTS
);
902 qxl
->guest_primary
.resized
= 1;
904 if (qxl
->guest_primary
.resized
) {
906 * Don't bother copying or scheduling the bh since we will flip
907 * the whole area anyway on completion of the update_area async call
909 qemu_mutex_unlock(&qxl
->ssd
.lock
);
912 qxl_i
= qxl
->num_dirty_rects
;
913 for (i
= 0; i
< num_updated_rects
; i
++) {
914 qxl
->dirty
[qxl_i
++] = dirty
[i
];
916 qxl
->num_dirty_rects
+= num_updated_rects
;
917 trace_qxl_interface_update_area_complete_schedule_bh(qxl
->id
,
918 qxl
->num_dirty_rects
);
919 qemu_bh_schedule(qxl
->update_area_bh
);
920 qemu_mutex_unlock(&qxl
->ssd
.lock
);
923 /* called from spice server thread context only */
924 static void interface_async_complete(QXLInstance
*sin
, uint64_t cookie_token
)
926 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
927 QXLCookie
*cookie
= (QXLCookie
*)(uintptr_t)cookie_token
;
929 switch (cookie
->type
) {
930 case QXL_COOKIE_TYPE_IO
:
931 interface_async_complete_io(qxl
, cookie
);
934 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA
:
935 qxl_render_update_area_done(qxl
, cookie
);
937 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
:
940 fprintf(stderr
, "qxl: %s: unexpected cookie type %d\n",
941 __func__
, cookie
->type
);
946 static const QXLInterface qxl_interface
= {
947 .base
.type
= SPICE_INTERFACE_QXL
,
948 .base
.description
= "qxl gpu",
949 .base
.major_version
= SPICE_INTERFACE_QXL_MAJOR
,
950 .base
.minor_version
= SPICE_INTERFACE_QXL_MINOR
,
952 .attache_worker
= interface_attach_worker
,
953 .set_compression_level
= interface_set_compression_level
,
954 .set_mm_time
= interface_set_mm_time
,
955 .get_init_info
= interface_get_init_info
,
957 /* the callbacks below are called from spice server thread context */
958 .get_command
= interface_get_command
,
959 .req_cmd_notification
= interface_req_cmd_notification
,
960 .release_resource
= interface_release_resource
,
961 .get_cursor_command
= interface_get_cursor_command
,
962 .req_cursor_notification
= interface_req_cursor_notification
,
963 .notify_update
= interface_notify_update
,
964 .flush_resources
= interface_flush_resources
,
965 .async_complete
= interface_async_complete
,
966 .update_area_complete
= interface_update_area_complete
,
969 static void qxl_enter_vga_mode(PCIQXLDevice
*d
)
971 if (d
->mode
== QXL_MODE_VGA
) {
974 trace_qxl_enter_vga_mode(d
->id
);
975 qemu_spice_create_host_primary(&d
->ssd
);
976 d
->mode
= QXL_MODE_VGA
;
977 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
978 vga_dirty_log_start(&d
->vga
);
981 static void qxl_exit_vga_mode(PCIQXLDevice
*d
)
983 if (d
->mode
!= QXL_MODE_VGA
) {
986 trace_qxl_exit_vga_mode(d
->id
);
987 vga_dirty_log_stop(&d
->vga
);
988 qxl_destroy_primary(d
, QXL_SYNC
);
991 static void qxl_update_irq(PCIQXLDevice
*d
)
993 uint32_t pending
= le32_to_cpu(d
->ram
->int_pending
);
994 uint32_t mask
= le32_to_cpu(d
->ram
->int_mask
);
995 int level
= !!(pending
& mask
);
996 qemu_set_irq(d
->pci
.irq
[0], level
);
997 qxl_ring_set_dirty(d
);
1000 static void qxl_check_state(PCIQXLDevice
*d
)
1002 QXLRam
*ram
= d
->ram
;
1003 int spice_display_running
= qemu_spice_display_is_running(&d
->ssd
);
1005 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
1006 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
1009 static void qxl_reset_state(PCIQXLDevice
*d
)
1011 QXLRom
*rom
= d
->rom
;
1014 d
->shadow_rom
.update_id
= cpu_to_le32(0);
1015 *rom
= d
->shadow_rom
;
1016 qxl_rom_set_dirty(d
);
1018 d
->num_free_res
= 0;
1019 d
->last_release
= NULL
;
1020 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
1023 static void qxl_soft_reset(PCIQXLDevice
*d
)
1025 trace_qxl_soft_reset(d
->id
);
1027 qxl_clear_guest_bug(d
);
1028 d
->current_async
= QXL_UNDEFINED_IO
;
1031 qxl_enter_vga_mode(d
);
1033 d
->mode
= QXL_MODE_UNDEFINED
;
1037 static void qxl_hard_reset(PCIQXLDevice
*d
, int loadvm
)
1039 trace_qxl_hard_reset(d
->id
, loadvm
);
1041 qxl_spice_reset_cursor(d
);
1042 qxl_spice_reset_image_cache(d
);
1043 qxl_reset_surfaces(d
);
1044 qxl_reset_memslots(d
);
1046 /* pre loadvm reset must not touch QXLRam. This lives in
1047 * device memory, is migrated together with RAM and thus
1048 * already loaded at this point */
1052 qemu_spice_create_host_memslot(&d
->ssd
);
1056 static void qxl_reset_handler(DeviceState
*dev
)
1058 PCIQXLDevice
*d
= DO_UPCAST(PCIQXLDevice
, pci
.qdev
, dev
);
1060 qxl_hard_reset(d
, 0);
1063 static void qxl_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
1065 VGACommonState
*vga
= opaque
;
1066 PCIQXLDevice
*qxl
= container_of(vga
, PCIQXLDevice
, vga
);
1068 trace_qxl_io_write_vga(qxl
->id
, qxl_mode_to_string(qxl
->mode
), addr
, val
);
1069 if (qxl
->mode
!= QXL_MODE_VGA
) {
1070 qxl_destroy_primary(qxl
, QXL_SYNC
);
1071 qxl_soft_reset(qxl
);
1073 vga_ioport_write(opaque
, addr
, val
);
1076 static const MemoryRegionPortio qxl_vga_portio_list
[] = {
1077 { 0x04, 2, 1, .read
= vga_ioport_read
,
1078 .write
= qxl_vga_ioport_write
}, /* 3b4 */
1079 { 0x0a, 1, 1, .read
= vga_ioport_read
,
1080 .write
= qxl_vga_ioport_write
}, /* 3ba */
1081 { 0x10, 16, 1, .read
= vga_ioport_read
,
1082 .write
= qxl_vga_ioport_write
}, /* 3c0 */
1083 { 0x24, 2, 1, .read
= vga_ioport_read
,
1084 .write
= qxl_vga_ioport_write
}, /* 3d4 */
1085 { 0x2a, 1, 1, .read
= vga_ioport_read
,
1086 .write
= qxl_vga_ioport_write
}, /* 3da */
1087 PORTIO_END_OF_LIST(),
1090 static int qxl_add_memslot(PCIQXLDevice
*d
, uint32_t slot_id
, uint64_t delta
,
1093 static const int regions
[] = {
1094 QXL_RAM_RANGE_INDEX
,
1095 QXL_VRAM_RANGE_INDEX
,
1096 QXL_VRAM64_RANGE_INDEX
,
1098 uint64_t guest_start
;
1103 intptr_t virt_start
;
1104 QXLDevMemSlot memslot
;
1107 guest_start
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_start
);
1108 guest_end
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_end
);
1110 trace_qxl_memslot_add_guest(d
->id
, slot_id
, guest_start
, guest_end
);
1112 if (slot_id
>= NUM_MEMSLOTS
) {
1113 qxl_set_guest_bug(d
, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__
,
1114 slot_id
, NUM_MEMSLOTS
);
1117 if (guest_start
> guest_end
) {
1118 qxl_set_guest_bug(d
, "%s: guest_start > guest_end 0x%" PRIx64
1119 " > 0x%" PRIx64
, __func__
, guest_start
, guest_end
);
1123 for (i
= 0; i
< ARRAY_SIZE(regions
); i
++) {
1124 pci_region
= regions
[i
];
1125 pci_start
= d
->pci
.io_regions
[pci_region
].addr
;
1126 pci_end
= pci_start
+ d
->pci
.io_regions
[pci_region
].size
;
1128 if (pci_start
== -1) {
1131 /* start address in range ? */
1132 if (guest_start
< pci_start
|| guest_start
> pci_end
) {
1135 /* end address in range ? */
1136 if (guest_end
> pci_end
) {
1142 if (i
== ARRAY_SIZE(regions
)) {
1143 qxl_set_guest_bug(d
, "%s: finished loop without match", __func__
);
1147 switch (pci_region
) {
1148 case QXL_RAM_RANGE_INDEX
:
1149 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vga
.vram
);
1151 case QXL_VRAM_RANGE_INDEX
:
1152 case 4 /* vram 64bit */:
1153 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vram_bar
);
1156 /* should not happen */
1157 qxl_set_guest_bug(d
, "%s: pci_region = %d", __func__
, pci_region
);
1161 memslot
.slot_id
= slot_id
;
1162 memslot
.slot_group_id
= MEMSLOT_GROUP_GUEST
; /* guest group */
1163 memslot
.virt_start
= virt_start
+ (guest_start
- pci_start
);
1164 memslot
.virt_end
= virt_start
+ (guest_end
- pci_start
);
1165 memslot
.addr_delta
= memslot
.virt_start
- delta
;
1166 memslot
.generation
= d
->rom
->slot_generation
= 0;
1167 qxl_rom_set_dirty(d
);
1169 qemu_spice_add_memslot(&d
->ssd
, &memslot
, async
);
1170 d
->guest_slots
[slot_id
].ptr
= (void*)memslot
.virt_start
;
1171 d
->guest_slots
[slot_id
].size
= memslot
.virt_end
- memslot
.virt_start
;
1172 d
->guest_slots
[slot_id
].delta
= delta
;
1173 d
->guest_slots
[slot_id
].active
= 1;
1177 static void qxl_del_memslot(PCIQXLDevice
*d
, uint32_t slot_id
)
1179 qemu_spice_del_memslot(&d
->ssd
, MEMSLOT_GROUP_HOST
, slot_id
);
1180 d
->guest_slots
[slot_id
].active
= 0;
1183 static void qxl_reset_memslots(PCIQXLDevice
*d
)
1185 qxl_spice_reset_memslots(d
);
1186 memset(&d
->guest_slots
, 0, sizeof(d
->guest_slots
));
1189 static void qxl_reset_surfaces(PCIQXLDevice
*d
)
1191 trace_qxl_reset_surfaces(d
->id
);
1192 d
->mode
= QXL_MODE_UNDEFINED
;
1193 qxl_spice_destroy_surfaces(d
, QXL_SYNC
);
1196 /* can be also called from spice server thread context */
1197 void *qxl_phys2virt(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
, int group_id
)
1199 uint64_t phys
= le64_to_cpu(pqxl
);
1200 uint32_t slot
= (phys
>> (64 - 8)) & 0xff;
1201 uint64_t offset
= phys
& 0xffffffffffff;
1204 case MEMSLOT_GROUP_HOST
:
1205 return (void *)(intptr_t)offset
;
1206 case MEMSLOT_GROUP_GUEST
:
1207 if (slot
>= NUM_MEMSLOTS
) {
1208 qxl_set_guest_bug(qxl
, "slot too large %d >= %d", slot
,
1212 if (!qxl
->guest_slots
[slot
].active
) {
1213 qxl_set_guest_bug(qxl
, "inactive slot %d\n", slot
);
1216 if (offset
< qxl
->guest_slots
[slot
].delta
) {
1217 qxl_set_guest_bug(qxl
,
1218 "slot %d offset %"PRIu64
" < delta %"PRIu64
"\n",
1219 slot
, offset
, qxl
->guest_slots
[slot
].delta
);
1222 offset
-= qxl
->guest_slots
[slot
].delta
;
1223 if (offset
> qxl
->guest_slots
[slot
].size
) {
1224 qxl_set_guest_bug(qxl
,
1225 "slot %d offset %"PRIu64
" > size %"PRIu64
"\n",
1226 slot
, offset
, qxl
->guest_slots
[slot
].size
);
1229 return qxl
->guest_slots
[slot
].ptr
+ offset
;
1234 static void qxl_create_guest_primary_complete(PCIQXLDevice
*qxl
)
1236 /* for local rendering */
1237 qxl_render_resize(qxl
);
1240 static void qxl_create_guest_primary(PCIQXLDevice
*qxl
, int loadvm
,
1243 QXLDevSurfaceCreate surface
;
1244 QXLSurfaceCreate
*sc
= &qxl
->guest_primary
.surface
;
1246 int requested_height
= le32_to_cpu(sc
->height
);
1247 int requested_stride
= le32_to_cpu(sc
->stride
);
1249 size
= abs(requested_stride
) * requested_height
;
1250 if (size
> qxl
->vgamem_size
) {
1251 qxl_set_guest_bug(qxl
, "%s: requested primary larger then framebuffer"
1256 if (qxl
->mode
== QXL_MODE_NATIVE
) {
1257 qxl_set_guest_bug(qxl
, "%s: nop since already in QXL_MODE_NATIVE",
1260 qxl_exit_vga_mode(qxl
);
1262 surface
.format
= le32_to_cpu(sc
->format
);
1263 surface
.height
= le32_to_cpu(sc
->height
);
1264 surface
.mem
= le64_to_cpu(sc
->mem
);
1265 surface
.position
= le32_to_cpu(sc
->position
);
1266 surface
.stride
= le32_to_cpu(sc
->stride
);
1267 surface
.width
= le32_to_cpu(sc
->width
);
1268 surface
.type
= le32_to_cpu(sc
->type
);
1269 surface
.flags
= le32_to_cpu(sc
->flags
);
1270 trace_qxl_create_guest_primary(qxl
->id
, sc
->width
, sc
->height
, sc
->mem
,
1271 sc
->format
, sc
->position
);
1272 trace_qxl_create_guest_primary_rest(qxl
->id
, sc
->stride
, sc
->type
,
1275 surface
.mouse_mode
= true;
1276 surface
.group_id
= MEMSLOT_GROUP_GUEST
;
1278 surface
.flags
|= QXL_SURF_FLAG_KEEP_DATA
;
1281 qxl
->mode
= QXL_MODE_NATIVE
;
1283 qemu_spice_create_primary_surface(&qxl
->ssd
, 0, &surface
, async
);
1285 if (async
== QXL_SYNC
) {
1286 qxl_create_guest_primary_complete(qxl
);
1290 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1291 * done (in QXL_SYNC case), 0 otherwise. */
1292 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
)
1294 if (d
->mode
== QXL_MODE_UNDEFINED
) {
1297 trace_qxl_destroy_primary(d
->id
);
1298 d
->mode
= QXL_MODE_UNDEFINED
;
1299 qemu_spice_destroy_primary_surface(&d
->ssd
, 0, async
);
1300 qxl_spice_reset_cursor(d
);
1304 static void qxl_set_mode(PCIQXLDevice
*d
, int modenr
, int loadvm
)
1306 pcibus_t start
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1307 pcibus_t end
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].size
+ start
;
1308 QXLMode
*mode
= d
->modes
->modes
+ modenr
;
1309 uint64_t devmem
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1314 QXLSurfaceCreate surface
= {
1315 .width
= mode
->x_res
,
1316 .height
= mode
->y_res
,
1317 .stride
= -mode
->x_res
* 4,
1318 .format
= SPICE_SURFACE_FMT_32_xRGB
,
1319 .flags
= loadvm
? QXL_SURF_FLAG_KEEP_DATA
: 0,
1321 .mem
= devmem
+ d
->shadow_rom
.draw_area_offset
,
1324 trace_qxl_set_mode(d
->id
, modenr
, mode
->x_res
, mode
->y_res
, mode
->bits
,
1327 qxl_hard_reset(d
, 0);
1330 d
->guest_slots
[0].slot
= slot
;
1331 assert(qxl_add_memslot(d
, 0, devmem
, QXL_SYNC
) == 0);
1333 d
->guest_primary
.surface
= surface
;
1334 qxl_create_guest_primary(d
, 0, QXL_SYNC
);
1336 d
->mode
= QXL_MODE_COMPAT
;
1337 d
->cmdflags
= QXL_COMMAND_FLAG_COMPAT
;
1338 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1339 if (mode
->bits
== 16) {
1340 d
->cmdflags
|= QXL_COMMAND_FLAG_COMPAT_16BPP
;
1343 d
->shadow_rom
.mode
= cpu_to_le32(modenr
);
1344 d
->rom
->mode
= cpu_to_le32(modenr
);
1345 qxl_rom_set_dirty(d
);
1348 static void ioport_write(void *opaque
, target_phys_addr_t addr
,
1349 uint64_t val
, unsigned size
)
1351 PCIQXLDevice
*d
= opaque
;
1352 uint32_t io_port
= addr
;
1353 qxl_async_io async
= QXL_SYNC
;
1354 uint32_t orig_io_port
= io_port
;
1356 if (d
->guest_bug
&& !io_port
== QXL_IO_RESET
) {
1360 if (d
->revision
<= QXL_REVISION_STABLE_V10
&&
1361 io_port
>= QXL_IO_FLUSH_SURFACES_ASYNC
) {
1362 qxl_set_guest_bug(d
, "unsupported io %d for revision %d\n",
1363 io_port
, d
->revision
);
1369 case QXL_IO_SET_MODE
:
1370 case QXL_IO_MEMSLOT_ADD
:
1371 case QXL_IO_MEMSLOT_DEL
:
1372 case QXL_IO_CREATE_PRIMARY
:
1373 case QXL_IO_UPDATE_IRQ
:
1375 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1376 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1379 if (d
->mode
!= QXL_MODE_VGA
) {
1382 trace_qxl_io_unexpected_vga_mode(d
->id
,
1383 io_port
, io_port_to_string(io_port
));
1384 /* be nice to buggy guest drivers */
1385 if (io_port
>= QXL_IO_UPDATE_AREA_ASYNC
&&
1386 io_port
< QXL_IO_RANGE_SIZE
) {
1387 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1392 /* we change the io_port to avoid ifdeffery in the main switch */
1393 orig_io_port
= io_port
;
1395 case QXL_IO_UPDATE_AREA_ASYNC
:
1396 io_port
= QXL_IO_UPDATE_AREA
;
1398 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1399 io_port
= QXL_IO_MEMSLOT_ADD
;
1401 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1402 io_port
= QXL_IO_CREATE_PRIMARY
;
1404 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
1405 io_port
= QXL_IO_DESTROY_PRIMARY
;
1407 case QXL_IO_DESTROY_SURFACE_ASYNC
:
1408 io_port
= QXL_IO_DESTROY_SURFACE_WAIT
;
1410 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
1411 io_port
= QXL_IO_DESTROY_ALL_SURFACES
;
1413 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1414 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1417 qemu_mutex_lock(&d
->async_lock
);
1418 if (d
->current_async
!= QXL_UNDEFINED_IO
) {
1419 qxl_set_guest_bug(d
, "%d async started before last (%d) complete",
1420 io_port
, d
->current_async
);
1421 qemu_mutex_unlock(&d
->async_lock
);
1424 d
->current_async
= orig_io_port
;
1425 qemu_mutex_unlock(&d
->async_lock
);
1430 trace_qxl_io_write(d
->id
, qxl_mode_to_string(d
->mode
), addr
, val
, size
,
1434 case QXL_IO_UPDATE_AREA
:
1436 QXLCookie
*cookie
= NULL
;
1437 QXLRect update
= d
->ram
->update_area
;
1439 if (d
->ram
->update_surface
> NUM_SURFACES
) {
1440 qxl_set_guest_bug(d
, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1441 d
->ram
->update_surface
);
1444 if (update
.left
>= update
.right
|| update
.top
>= update
.bottom
) {
1445 qxl_set_guest_bug(d
,
1446 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1447 update
.left
, update
.top
, update
.right
, update
.bottom
);
1451 if (update
.left
< 0 || update
.top
< 0 || update
.left
>= update
.right
||
1452 update
.top
>= update
.bottom
) {
1453 qxl_set_guest_bug(d
, "QXL_IO_UPDATE_AREA: "
1454 "invalid area(%d,%d,%d,%d)\n", update
.left
,
1455 update
.right
, update
.top
, update
.bottom
);
1458 if (async
== QXL_ASYNC
) {
1459 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
1460 QXL_IO_UPDATE_AREA_ASYNC
);
1461 cookie
->u
.area
= update
;
1463 qxl_spice_update_area(d
, d
->ram
->update_surface
,
1464 cookie
? &cookie
->u
.area
: &update
,
1465 NULL
, 0, 0, async
, cookie
);
1468 case QXL_IO_NOTIFY_CMD
:
1469 qemu_spice_wakeup(&d
->ssd
);
1471 case QXL_IO_NOTIFY_CURSOR
:
1472 qemu_spice_wakeup(&d
->ssd
);
1474 case QXL_IO_UPDATE_IRQ
:
1477 case QXL_IO_NOTIFY_OOM
:
1478 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1485 case QXL_IO_SET_MODE
:
1486 qxl_set_mode(d
, val
, 0);
1489 if (d
->guestdebug
) {
1490 fprintf(stderr
, "qxl/guest-%d: %" PRId64
": %s", d
->id
,
1491 qemu_get_clock_ns(vm_clock
), d
->ram
->log_buf
);
1495 qxl_hard_reset(d
, 0);
1497 case QXL_IO_MEMSLOT_ADD
:
1498 if (val
>= NUM_MEMSLOTS
) {
1499 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: val out of range");
1502 if (d
->guest_slots
[val
].active
) {
1503 qxl_set_guest_bug(d
,
1504 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1507 d
->guest_slots
[val
].slot
= d
->ram
->mem_slot
;
1508 qxl_add_memslot(d
, val
, 0, async
);
1510 case QXL_IO_MEMSLOT_DEL
:
1511 if (val
>= NUM_MEMSLOTS
) {
1512 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_DEL: val out of range");
1515 qxl_del_memslot(d
, val
);
1517 case QXL_IO_CREATE_PRIMARY
:
1519 qxl_set_guest_bug(d
, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1523 d
->guest_primary
.surface
= d
->ram
->create_surface
;
1524 qxl_create_guest_primary(d
, 0, async
);
1526 case QXL_IO_DESTROY_PRIMARY
:
1528 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1532 if (!qxl_destroy_primary(d
, async
)) {
1533 trace_qxl_io_destroy_primary_ignored(d
->id
,
1534 qxl_mode_to_string(d
->mode
));
1538 case QXL_IO_DESTROY_SURFACE_WAIT
:
1539 if (val
>= NUM_SURFACES
) {
1540 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_SURFACE (async=%d):"
1541 "%" PRIu64
" >= NUM_SURFACES", async
, val
);
1544 qxl_spice_destroy_surface_wait(d
, val
, async
);
1546 case QXL_IO_FLUSH_RELEASE
: {
1547 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
1548 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
1550 "ERROR: no flush, full release ring [p%d,%dc]\n",
1551 ring
->prod
, ring
->cons
);
1553 qxl_push_free_res(d
, 1 /* flush */);
1556 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1557 qxl_spice_flush_surfaces_async(d
);
1559 case QXL_IO_DESTROY_ALL_SURFACES
:
1560 d
->mode
= QXL_MODE_UNDEFINED
;
1561 qxl_spice_destroy_surfaces(d
, async
);
1563 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1564 qxl_spice_monitors_config_async(d
, 0);
1567 qxl_set_guest_bug(d
, "%s: unexpected ioport=0x%x\n", __func__
, io_port
);
1572 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1573 qemu_mutex_lock(&d
->async_lock
);
1574 d
->current_async
= QXL_UNDEFINED_IO
;
1575 qemu_mutex_unlock(&d
->async_lock
);
1579 static uint64_t ioport_read(void *opaque
, target_phys_addr_t addr
,
1582 PCIQXLDevice
*d
= opaque
;
1584 trace_qxl_io_read_unexpected(d
->id
);
1588 static const MemoryRegionOps qxl_io_ops
= {
1589 .read
= ioport_read
,
1590 .write
= ioport_write
,
1592 .min_access_size
= 1,
1593 .max_access_size
= 1,
1597 static void pipe_read(void *opaque
)
1599 PCIQXLDevice
*d
= opaque
;
1604 len
= read(d
->pipe
[0], &dummy
, sizeof(dummy
));
1605 } while (len
== sizeof(dummy
));
1609 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
)
1611 uint32_t old_pending
;
1612 uint32_t le_events
= cpu_to_le32(events
);
1614 assert(qemu_spice_display_is_running(&d
->ssd
));
1615 old_pending
= __sync_fetch_and_or(&d
->ram
->int_pending
, le_events
);
1616 if ((old_pending
& le_events
) == le_events
) {
1619 if (qemu_thread_is_self(&d
->main
)) {
1622 if (write(d
->pipe
[1], d
, 1) != 1) {
1623 dprint(d
, 1, "%s: write to pipe failed\n", __func__
);
1628 static void init_pipe_signaling(PCIQXLDevice
*d
)
1630 if (pipe(d
->pipe
) < 0) {
1631 fprintf(stderr
, "%s:%s: qxl pipe creation failed\n",
1632 __FILE__
, __func__
);
1635 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
);
1636 fcntl(d
->pipe
[1], F_SETFL
, O_NONBLOCK
);
1637 fcntl(d
->pipe
[0], F_SETOWN
, getpid());
1639 qemu_thread_get_self(&d
->main
);
1640 qemu_set_fd_handler(d
->pipe
[0], pipe_read
, NULL
, d
);
1643 /* graphics console */
1645 static void qxl_hw_update(void *opaque
)
1647 PCIQXLDevice
*qxl
= opaque
;
1648 VGACommonState
*vga
= &qxl
->vga
;
1650 switch (qxl
->mode
) {
1654 case QXL_MODE_COMPAT
:
1655 case QXL_MODE_NATIVE
:
1656 qxl_render_update(qxl
);
1663 static void qxl_hw_invalidate(void *opaque
)
1665 PCIQXLDevice
*qxl
= opaque
;
1666 VGACommonState
*vga
= &qxl
->vga
;
1668 vga
->invalidate(vga
);
1671 static void qxl_hw_screen_dump(void *opaque
, const char *filename
, bool cswitch
)
1673 PCIQXLDevice
*qxl
= opaque
;
1674 VGACommonState
*vga
= &qxl
->vga
;
1676 switch (qxl
->mode
) {
1677 case QXL_MODE_COMPAT
:
1678 case QXL_MODE_NATIVE
:
1679 qxl_render_update(qxl
);
1680 ppm_save(filename
, qxl
->ssd
.ds
->surface
);
1683 vga
->screen_dump(vga
, filename
, cswitch
);
1690 static void qxl_hw_text_update(void *opaque
, console_ch_t
*chardata
)
1692 PCIQXLDevice
*qxl
= opaque
;
1693 VGACommonState
*vga
= &qxl
->vga
;
1695 if (qxl
->mode
== QXL_MODE_VGA
) {
1696 vga
->text_update(vga
, chardata
);
1701 static void qxl_dirty_surfaces(PCIQXLDevice
*qxl
)
1703 intptr_t vram_start
;
1706 if (qxl
->mode
!= QXL_MODE_NATIVE
&& qxl
->mode
!= QXL_MODE_COMPAT
) {
1710 /* dirty the primary surface */
1711 qxl_set_dirty(&qxl
->vga
.vram
, qxl
->shadow_rom
.draw_area_offset
,
1712 qxl
->shadow_rom
.surface0_area_size
);
1714 vram_start
= (intptr_t)memory_region_get_ram_ptr(&qxl
->vram_bar
);
1716 /* dirty the off-screen surfaces */
1717 for (i
= 0; i
< NUM_SURFACES
; i
++) {
1719 intptr_t surface_offset
;
1722 if (qxl
->guest_surfaces
.cmds
[i
] == 0) {
1726 cmd
= qxl_phys2virt(qxl
, qxl
->guest_surfaces
.cmds
[i
],
1727 MEMSLOT_GROUP_GUEST
);
1729 assert(cmd
->type
== QXL_SURFACE_CMD_CREATE
);
1730 surface_offset
= (intptr_t)qxl_phys2virt(qxl
,
1731 cmd
->u
.surface_create
.data
,
1732 MEMSLOT_GROUP_GUEST
);
1733 assert(surface_offset
);
1734 surface_offset
-= vram_start
;
1735 surface_size
= cmd
->u
.surface_create
.height
*
1736 abs(cmd
->u
.surface_create
.stride
);
1737 trace_qxl_surfaces_dirty(qxl
->id
, i
, (int)surface_offset
, surface_size
);
1738 qxl_set_dirty(&qxl
->vram_bar
, surface_offset
, surface_size
);
1742 static void qxl_vm_change_state_handler(void *opaque
, int running
,
1745 PCIQXLDevice
*qxl
= opaque
;
1746 qemu_spice_vm_change_state_handler(&qxl
->ssd
, running
, state
);
1750 * if qxl_send_events was called from spice server context before
1751 * migration ended, qxl_update_irq for these events might not have been
1754 qxl_update_irq(qxl
);
1756 /* make sure surfaces are saved before migration */
1757 qxl_dirty_surfaces(qxl
);
1761 /* display change listener */
1763 static void display_update(struct DisplayState
*ds
, int x
, int y
, int w
, int h
)
1765 if (qxl0
->mode
== QXL_MODE_VGA
) {
1766 qemu_spice_display_update(&qxl0
->ssd
, x
, y
, w
, h
);
1770 static void display_resize(struct DisplayState
*ds
)
1772 if (qxl0
->mode
== QXL_MODE_VGA
) {
1773 qemu_spice_display_resize(&qxl0
->ssd
);
1777 static void display_refresh(struct DisplayState
*ds
)
1779 if (qxl0
->mode
== QXL_MODE_VGA
) {
1780 qemu_spice_display_refresh(&qxl0
->ssd
);
1782 qemu_mutex_lock(&qxl0
->ssd
.lock
);
1783 qemu_spice_cursor_refresh_unlocked(&qxl0
->ssd
);
1784 qemu_mutex_unlock(&qxl0
->ssd
.lock
);
1788 static DisplayChangeListener display_listener
= {
1789 .dpy_update
= display_update
,
1790 .dpy_resize
= display_resize
,
1791 .dpy_refresh
= display_refresh
,
1794 static void qxl_init_ramsize(PCIQXLDevice
*qxl
)
1796 /* vga mode framebuffer / primary surface (bar 0, first part) */
1797 if (qxl
->vgamem_size_mb
< 8) {
1798 qxl
->vgamem_size_mb
= 8;
1800 qxl
->vgamem_size
= qxl
->vgamem_size_mb
* 1024 * 1024;
1802 /* vga ram (bar 0, total) */
1803 if (qxl
->ram_size_mb
!= -1) {
1804 qxl
->vga
.vram_size
= qxl
->ram_size_mb
* 1024 * 1024;
1806 if (qxl
->vga
.vram_size
< qxl
->vgamem_size
* 2) {
1807 qxl
->vga
.vram_size
= qxl
->vgamem_size
* 2;
1810 /* vram32 (surfaces, 32bit, bar 1) */
1811 if (qxl
->vram32_size_mb
!= -1) {
1812 qxl
->vram32_size
= qxl
->vram32_size_mb
* 1024 * 1024;
1814 if (qxl
->vram32_size
< 4096) {
1815 qxl
->vram32_size
= 4096;
1818 /* vram (surfaces, 64bit, bar 4+5) */
1819 if (qxl
->vram_size_mb
!= -1) {
1820 qxl
->vram_size
= qxl
->vram_size_mb
* 1024 * 1024;
1822 if (qxl
->vram_size
< qxl
->vram32_size
) {
1823 qxl
->vram_size
= qxl
->vram32_size
;
1826 if (qxl
->revision
== 1) {
1827 qxl
->vram32_size
= 4096;
1828 qxl
->vram_size
= 4096;
1830 qxl
->vgamem_size
= msb_mask(qxl
->vgamem_size
* 2 - 1);
1831 qxl
->vga
.vram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1832 qxl
->vram32_size
= msb_mask(qxl
->vram32_size
* 2 - 1);
1833 qxl
->vram_size
= msb_mask(qxl
->vram_size
* 2 - 1);
1836 static int qxl_init_common(PCIQXLDevice
*qxl
)
1838 uint8_t* config
= qxl
->pci
.config
;
1839 uint32_t pci_device_rev
;
1842 qxl
->mode
= QXL_MODE_UNDEFINED
;
1843 qxl
->generation
= 1;
1844 qxl
->num_memslots
= NUM_MEMSLOTS
;
1845 qxl
->num_surfaces
= NUM_SURFACES
;
1846 qemu_mutex_init(&qxl
->track_lock
);
1847 qemu_mutex_init(&qxl
->async_lock
);
1848 qxl
->current_async
= QXL_UNDEFINED_IO
;
1851 switch (qxl
->revision
) {
1852 case 1: /* spice 0.4 -- qxl-1 */
1853 pci_device_rev
= QXL_REVISION_STABLE_V04
;
1856 case 2: /* spice 0.6 -- qxl-2 */
1857 pci_device_rev
= QXL_REVISION_STABLE_V06
;
1861 pci_device_rev
= QXL_REVISION_STABLE_V10
;
1862 io_size
= 32; /* PCI region size must be pow2 */
1864 /* 0x000b01 == 0.11.1 */
1865 #if SPICE_SERVER_VERSION >= 0x000b01 && \
1866 defined(CONFIG_QXL_IO_MONITORS_CONFIG_ASYNC)
1868 pci_device_rev
= QXL_REVISION_STABLE_V12
;
1869 io_size
= msb_mask(QXL_IO_RANGE_SIZE
* 2 - 1);
1873 pci_device_rev
= QXL_DEFAULT_REVISION
;
1874 io_size
= msb_mask(QXL_IO_RANGE_SIZE
* 2 - 1);
1878 pci_set_byte(&config
[PCI_REVISION_ID
], pci_device_rev
);
1879 pci_set_byte(&config
[PCI_INTERRUPT_PIN
], 1);
1881 qxl
->rom_size
= qxl_rom_size();
1882 memory_region_init_ram(&qxl
->rom_bar
, "qxl.vrom", qxl
->rom_size
);
1883 vmstate_register_ram(&qxl
->rom_bar
, &qxl
->pci
.qdev
);
1887 memory_region_init_ram(&qxl
->vram_bar
, "qxl.vram", qxl
->vram_size
);
1888 vmstate_register_ram(&qxl
->vram_bar
, &qxl
->pci
.qdev
);
1889 memory_region_init_alias(&qxl
->vram32_bar
, "qxl.vram32", &qxl
->vram_bar
,
1890 0, qxl
->vram32_size
);
1892 memory_region_init_io(&qxl
->io_bar
, &qxl_io_ops
, qxl
,
1893 "qxl-ioports", io_size
);
1895 vga_dirty_log_start(&qxl
->vga
);
1899 pci_register_bar(&qxl
->pci
, QXL_IO_RANGE_INDEX
,
1900 PCI_BASE_ADDRESS_SPACE_IO
, &qxl
->io_bar
);
1902 pci_register_bar(&qxl
->pci
, QXL_ROM_RANGE_INDEX
,
1903 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->rom_bar
);
1905 pci_register_bar(&qxl
->pci
, QXL_RAM_RANGE_INDEX
,
1906 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vga
.vram
);
1908 pci_register_bar(&qxl
->pci
, QXL_VRAM_RANGE_INDEX
,
1909 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vram32_bar
);
1911 if (qxl
->vram32_size
< qxl
->vram_size
) {
1913 * Make the 64bit vram bar show up only in case it is
1914 * configured to be larger than the 32bit vram bar.
1916 pci_register_bar(&qxl
->pci
, QXL_VRAM64_RANGE_INDEX
,
1917 PCI_BASE_ADDRESS_SPACE_MEMORY
|
1918 PCI_BASE_ADDRESS_MEM_TYPE_64
|
1919 PCI_BASE_ADDRESS_MEM_PREFETCH
,
1923 /* print pci bar details */
1924 dprint(qxl
, 1, "ram/%s: %d MB [region 0]\n",
1925 qxl
->id
== 0 ? "pri" : "sec",
1926 qxl
->vga
.vram_size
/ (1024*1024));
1927 dprint(qxl
, 1, "vram/32: %d MB [region 1]\n",
1928 qxl
->vram32_size
/ (1024*1024));
1929 dprint(qxl
, 1, "vram/64: %d MB %s\n",
1930 qxl
->vram_size
/ (1024*1024),
1931 qxl
->vram32_size
< qxl
->vram_size
? "[region 4]" : "[unmapped]");
1933 qxl
->ssd
.qxl
.base
.sif
= &qxl_interface
.base
;
1934 qxl
->ssd
.qxl
.id
= qxl
->id
;
1935 qemu_spice_add_interface(&qxl
->ssd
.qxl
.base
);
1936 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler
, qxl
);
1938 init_pipe_signaling(qxl
);
1939 qxl_reset_state(qxl
);
1941 qxl
->update_area_bh
= qemu_bh_new(qxl_render_update_area_bh
, qxl
);
1946 static int qxl_init_primary(PCIDevice
*dev
)
1948 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1949 VGACommonState
*vga
= &qxl
->vga
;
1950 PortioList
*qxl_vga_port_list
= g_new(PortioList
, 1);
1953 qxl_init_ramsize(qxl
);
1954 vga
->vram_size_mb
= qxl
->vga
.vram_size
>> 20;
1955 vga_common_init(vga
);
1956 vga_init(vga
, pci_address_space(dev
), pci_address_space_io(dev
), false);
1957 portio_list_init(qxl_vga_port_list
, qxl_vga_portio_list
, vga
, "vga");
1958 portio_list_add(qxl_vga_port_list
, pci_address_space_io(dev
), 0x3b0);
1960 vga
->ds
= graphic_console_init(qxl_hw_update
, qxl_hw_invalidate
,
1961 qxl_hw_screen_dump
, qxl_hw_text_update
, qxl
);
1962 qemu_spice_display_init_common(&qxl
->ssd
, vga
->ds
);
1965 register_displaychangelistener(vga
->ds
, &display_listener
);
1967 return qxl_init_common(qxl
);
1970 static int qxl_init_secondary(PCIDevice
*dev
)
1972 static int device_id
= 1;
1973 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1975 qxl
->id
= device_id
++;
1976 qxl_init_ramsize(qxl
);
1977 memory_region_init_ram(&qxl
->vga
.vram
, "qxl.vgavram", qxl
->vga
.vram_size
);
1978 vmstate_register_ram(&qxl
->vga
.vram
, &qxl
->pci
.qdev
);
1979 qxl
->vga
.vram_ptr
= memory_region_get_ram_ptr(&qxl
->vga
.vram
);
1981 return qxl_init_common(qxl
);
1984 static void qxl_pre_save(void *opaque
)
1986 PCIQXLDevice
* d
= opaque
;
1987 uint8_t *ram_start
= d
->vga
.vram_ptr
;
1989 trace_qxl_pre_save(d
->id
);
1990 if (d
->last_release
== NULL
) {
1991 d
->last_release_offset
= 0;
1993 d
->last_release_offset
= (uint8_t *)d
->last_release
- ram_start
;
1995 assert(d
->last_release_offset
< d
->vga
.vram_size
);
1998 static int qxl_pre_load(void *opaque
)
2000 PCIQXLDevice
* d
= opaque
;
2002 trace_qxl_pre_load(d
->id
);
2003 qxl_hard_reset(d
, 1);
2004 qxl_exit_vga_mode(d
);
2008 static void qxl_create_memslots(PCIQXLDevice
*d
)
2012 for (i
= 0; i
< NUM_MEMSLOTS
; i
++) {
2013 if (!d
->guest_slots
[i
].active
) {
2016 qxl_add_memslot(d
, i
, 0, QXL_SYNC
);
2020 static int qxl_post_load(void *opaque
, int version
)
2022 PCIQXLDevice
* d
= opaque
;
2023 uint8_t *ram_start
= d
->vga
.vram_ptr
;
2024 QXLCommandExt
*cmds
;
2025 int in
, out
, newmode
;
2027 assert(d
->last_release_offset
< d
->vga
.vram_size
);
2028 if (d
->last_release_offset
== 0) {
2029 d
->last_release
= NULL
;
2031 d
->last_release
= (QXLReleaseInfo
*)(ram_start
+ d
->last_release_offset
);
2034 d
->modes
= (QXLModes
*)((uint8_t*)d
->rom
+ d
->rom
->modes_offset
);
2036 trace_qxl_post_load(d
->id
, qxl_mode_to_string(d
->mode
));
2038 d
->mode
= QXL_MODE_UNDEFINED
;
2041 case QXL_MODE_UNDEFINED
:
2044 qxl_create_memslots(d
);
2045 qxl_enter_vga_mode(d
);
2047 case QXL_MODE_NATIVE
:
2048 qxl_create_memslots(d
);
2049 qxl_create_guest_primary(d
, 1, QXL_SYNC
);
2051 /* replay surface-create and cursor-set commands */
2052 cmds
= g_malloc0(sizeof(QXLCommandExt
) * (NUM_SURFACES
+ 1));
2053 for (in
= 0, out
= 0; in
< NUM_SURFACES
; in
++) {
2054 if (d
->guest_surfaces
.cmds
[in
] == 0) {
2057 cmds
[out
].cmd
.data
= d
->guest_surfaces
.cmds
[in
];
2058 cmds
[out
].cmd
.type
= QXL_CMD_SURFACE
;
2059 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2062 if (d
->guest_cursor
) {
2063 cmds
[out
].cmd
.data
= d
->guest_cursor
;
2064 cmds
[out
].cmd
.type
= QXL_CMD_CURSOR
;
2065 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2068 qxl_spice_loadvm_commands(d
, cmds
, out
);
2070 if (d
->guest_monitors_config
) {
2071 qxl_spice_monitors_config_async(d
, 1);
2074 case QXL_MODE_COMPAT
:
2075 /* note: no need to call qxl_create_memslots, qxl_set_mode
2076 * creates the mem slot. */
2077 qxl_set_mode(d
, d
->shadow_rom
.mode
, 1);
2083 #define QXL_SAVE_VERSION 21
2085 static bool qxl_monitors_config_needed(void *opaque
)
2087 PCIQXLDevice
*qxl
= opaque
;
2089 return qxl
->guest_monitors_config
!= 0;
2093 static VMStateDescription qxl_memslot
= {
2094 .name
= "qxl-memslot",
2095 .version_id
= QXL_SAVE_VERSION
,
2096 .minimum_version_id
= QXL_SAVE_VERSION
,
2097 .fields
= (VMStateField
[]) {
2098 VMSTATE_UINT64(slot
.mem_start
, struct guest_slots
),
2099 VMSTATE_UINT64(slot
.mem_end
, struct guest_slots
),
2100 VMSTATE_UINT32(active
, struct guest_slots
),
2101 VMSTATE_END_OF_LIST()
2105 static VMStateDescription qxl_surface
= {
2106 .name
= "qxl-surface",
2107 .version_id
= QXL_SAVE_VERSION
,
2108 .minimum_version_id
= QXL_SAVE_VERSION
,
2109 .fields
= (VMStateField
[]) {
2110 VMSTATE_UINT32(width
, QXLSurfaceCreate
),
2111 VMSTATE_UINT32(height
, QXLSurfaceCreate
),
2112 VMSTATE_INT32(stride
, QXLSurfaceCreate
),
2113 VMSTATE_UINT32(format
, QXLSurfaceCreate
),
2114 VMSTATE_UINT32(position
, QXLSurfaceCreate
),
2115 VMSTATE_UINT32(mouse_mode
, QXLSurfaceCreate
),
2116 VMSTATE_UINT32(flags
, QXLSurfaceCreate
),
2117 VMSTATE_UINT32(type
, QXLSurfaceCreate
),
2118 VMSTATE_UINT64(mem
, QXLSurfaceCreate
),
2119 VMSTATE_END_OF_LIST()
2123 static VMStateDescription qxl_vmstate_monitors_config
= {
2124 .name
= "qxl/monitors-config",
2126 .minimum_version_id
= 1,
2127 .fields
= (VMStateField
[]) {
2128 VMSTATE_UINT64(guest_monitors_config
, PCIQXLDevice
),
2129 VMSTATE_END_OF_LIST()
2133 static VMStateDescription qxl_vmstate
= {
2135 .version_id
= QXL_SAVE_VERSION
,
2136 .minimum_version_id
= QXL_SAVE_VERSION
,
2137 .pre_save
= qxl_pre_save
,
2138 .pre_load
= qxl_pre_load
,
2139 .post_load
= qxl_post_load
,
2140 .fields
= (VMStateField
[]) {
2141 VMSTATE_PCI_DEVICE(pci
, PCIQXLDevice
),
2142 VMSTATE_STRUCT(vga
, PCIQXLDevice
, 0, vmstate_vga_common
, VGACommonState
),
2143 VMSTATE_UINT32(shadow_rom
.mode
, PCIQXLDevice
),
2144 VMSTATE_UINT32(num_free_res
, PCIQXLDevice
),
2145 VMSTATE_UINT32(last_release_offset
, PCIQXLDevice
),
2146 VMSTATE_UINT32(mode
, PCIQXLDevice
),
2147 VMSTATE_UINT32(ssd
.unique
, PCIQXLDevice
),
2148 VMSTATE_INT32_EQUAL(num_memslots
, PCIQXLDevice
),
2149 VMSTATE_STRUCT_ARRAY(guest_slots
, PCIQXLDevice
, NUM_MEMSLOTS
, 0,
2150 qxl_memslot
, struct guest_slots
),
2151 VMSTATE_STRUCT(guest_primary
.surface
, PCIQXLDevice
, 0,
2152 qxl_surface
, QXLSurfaceCreate
),
2153 VMSTATE_INT32_EQUAL(num_surfaces
, PCIQXLDevice
),
2154 VMSTATE_ARRAY(guest_surfaces
.cmds
, PCIQXLDevice
, NUM_SURFACES
, 0,
2155 vmstate_info_uint64
, uint64_t),
2156 VMSTATE_UINT64(guest_cursor
, PCIQXLDevice
),
2157 VMSTATE_END_OF_LIST()
2159 .subsections
= (VMStateSubsection
[]) {
2161 .vmsd
= &qxl_vmstate_monitors_config
,
2162 .needed
= qxl_monitors_config_needed
,
2169 static Property qxl_properties
[] = {
2170 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
,
2172 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram32_size
,
2174 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
,
2175 QXL_DEFAULT_REVISION
),
2176 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
2177 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
2178 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
2179 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice
, ram_size_mb
, -1),
2180 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice
, vram32_size_mb
, -1),
2181 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice
, vram_size_mb
, -1),
2182 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice
, vgamem_size_mb
, 16),
2183 DEFINE_PROP_END_OF_LIST(),
2186 static void qxl_primary_class_init(ObjectClass
*klass
, void *data
)
2188 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2189 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2192 k
->init
= qxl_init_primary
;
2193 k
->romfile
= "vgabios-qxl.bin";
2194 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
2195 k
->device_id
= QXL_DEVICE_ID_STABLE
;
2196 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
2197 dc
->desc
= "Spice QXL GPU (primary, vga compatible)";
2198 dc
->reset
= qxl_reset_handler
;
2199 dc
->vmsd
= &qxl_vmstate
;
2200 dc
->props
= qxl_properties
;
2203 static TypeInfo qxl_primary_info
= {
2205 .parent
= TYPE_PCI_DEVICE
,
2206 .instance_size
= sizeof(PCIQXLDevice
),
2207 .class_init
= qxl_primary_class_init
,
2210 static void qxl_secondary_class_init(ObjectClass
*klass
, void *data
)
2212 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2213 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2215 k
->init
= qxl_init_secondary
;
2216 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
2217 k
->device_id
= QXL_DEVICE_ID_STABLE
;
2218 k
->class_id
= PCI_CLASS_DISPLAY_OTHER
;
2219 dc
->desc
= "Spice QXL GPU (secondary)";
2220 dc
->reset
= qxl_reset_handler
;
2221 dc
->vmsd
= &qxl_vmstate
;
2222 dc
->props
= qxl_properties
;
2225 static TypeInfo qxl_secondary_info
= {
2227 .parent
= TYPE_PCI_DEVICE
,
2228 .instance_size
= sizeof(PCIQXLDevice
),
2229 .class_init
= qxl_secondary_class_init
,
2232 static void qxl_register_types(void)
2234 type_register_static(&qxl_primary_info
);
2235 type_register_static(&qxl_secondary_info
);
2238 type_init(qxl_register_types
)