2 * QEMU RISC-V VirtIO Board
4 * Copyright (c) 2017 SiFive, Inc.
6 * RISC-V machine with 16550a UART and VirtIO MMIO
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
25 #include "qapi/error.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/sysbus.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial.h"
31 #include "target/riscv/cpu.h"
32 #include "hw/core/sysbus-fdt.h"
33 #include "target/riscv/pmu.h"
34 #include "hw/riscv/riscv_hart.h"
35 #include "hw/riscv/virt.h"
36 #include "hw/riscv/boot.h"
37 #include "hw/riscv/numa.h"
38 #include "hw/intc/riscv_aclint.h"
39 #include "hw/intc/riscv_aplic.h"
40 #include "hw/intc/riscv_imsic.h"
41 #include "hw/intc/sifive_plic.h"
42 #include "hw/misc/sifive_test.h"
43 #include "hw/platform-bus.h"
44 #include "chardev/char.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/sysemu.h"
47 #include "sysemu/kvm.h"
48 #include "sysemu/tpm.h"
49 #include "hw/pci/pci.h"
50 #include "hw/pci-host/gpex.h"
51 #include "hw/display/ramfb.h"
52 #include "hw/acpi/aml-build.h"
53 #include "qapi/qapi-visit-common.h"
56 * The virt machine physical address space used by some of the devices
57 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
58 * number of CPUs, and number of IMSIC guest files.
60 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
61 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
62 * of virt machine physical address space.
65 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
66 #if VIRT_IMSIC_GROUP_MAX_SIZE < \
67 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
68 #error "Can't accomodate single IMSIC group in address space"
71 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \
72 VIRT_IMSIC_GROUP_MAX_SIZE)
73 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE
74 #error "Can't accomodate all IMSIC groups in address space"
77 static const MemMapEntry virt_memmap
[] = {
78 [VIRT_DEBUG
] = { 0x0, 0x100 },
79 [VIRT_MROM
] = { 0x1000, 0xf000 },
80 [VIRT_TEST
] = { 0x100000, 0x1000 },
81 [VIRT_RTC
] = { 0x101000, 0x1000 },
82 [VIRT_CLINT
] = { 0x2000000, 0x10000 },
83 [VIRT_ACLINT_SSWI
] = { 0x2F00000, 0x4000 },
84 [VIRT_PCIE_PIO
] = { 0x3000000, 0x10000 },
85 [VIRT_PLATFORM_BUS
] = { 0x4000000, 0x2000000 },
86 [VIRT_PLIC
] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX
* 2) },
87 [VIRT_APLIC_M
] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX
) },
88 [VIRT_APLIC_S
] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX
) },
89 [VIRT_UART0
] = { 0x10000000, 0x100 },
90 [VIRT_VIRTIO
] = { 0x10001000, 0x1000 },
91 [VIRT_FW_CFG
] = { 0x10100000, 0x18 },
92 [VIRT_FLASH
] = { 0x20000000, 0x4000000 },
93 [VIRT_IMSIC_M
] = { 0x24000000, VIRT_IMSIC_MAX_SIZE
},
94 [VIRT_IMSIC_S
] = { 0x28000000, VIRT_IMSIC_MAX_SIZE
},
95 [VIRT_PCIE_ECAM
] = { 0x30000000, 0x10000000 },
96 [VIRT_PCIE_MMIO
] = { 0x40000000, 0x40000000 },
97 [VIRT_DRAM
] = { 0x80000000, 0x0 },
100 /* PCIe high mmio is fixed for RV32 */
101 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
102 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
104 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
105 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
107 static MemMapEntry virt_high_pcie_memmap
;
109 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
111 static PFlashCFI01
*virt_flash_create1(RISCVVirtState
*s
,
113 const char *alias_prop_name
)
116 * Create a single flash device. We use the same parameters as
117 * the flash devices on the ARM virt board.
119 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
121 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
122 qdev_prop_set_uint8(dev
, "width", 4);
123 qdev_prop_set_uint8(dev
, "device-width", 2);
124 qdev_prop_set_bit(dev
, "big-endian", false);
125 qdev_prop_set_uint16(dev
, "id0", 0x89);
126 qdev_prop_set_uint16(dev
, "id1", 0x18);
127 qdev_prop_set_uint16(dev
, "id2", 0x00);
128 qdev_prop_set_uint16(dev
, "id3", 0x00);
129 qdev_prop_set_string(dev
, "name", name
);
131 object_property_add_child(OBJECT(s
), name
, OBJECT(dev
));
132 object_property_add_alias(OBJECT(s
), alias_prop_name
,
133 OBJECT(dev
), "drive");
135 return PFLASH_CFI01(dev
);
138 static void virt_flash_create(RISCVVirtState
*s
)
140 s
->flash
[0] = virt_flash_create1(s
, "virt.flash0", "pflash0");
141 s
->flash
[1] = virt_flash_create1(s
, "virt.flash1", "pflash1");
144 static void virt_flash_map1(PFlashCFI01
*flash
,
145 hwaddr base
, hwaddr size
,
146 MemoryRegion
*sysmem
)
148 DeviceState
*dev
= DEVICE(flash
);
150 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
151 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
152 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
153 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
155 memory_region_add_subregion(sysmem
, base
,
156 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
160 static void virt_flash_map(RISCVVirtState
*s
,
161 MemoryRegion
*sysmem
)
163 hwaddr flashsize
= virt_memmap
[VIRT_FLASH
].size
/ 2;
164 hwaddr flashbase
= virt_memmap
[VIRT_FLASH
].base
;
166 virt_flash_map1(s
->flash
[0], flashbase
, flashsize
,
168 virt_flash_map1(s
->flash
[1], flashbase
+ flashsize
, flashsize
,
172 static void create_pcie_irq_map(RISCVVirtState
*s
, void *fdt
, char *nodename
,
173 uint32_t irqchip_phandle
)
176 uint32_t irq_map_stride
= 0;
177 uint32_t full_irq_map
[GPEX_NUM_IRQS
* GPEX_NUM_IRQS
*
178 FDT_MAX_INT_MAP_WIDTH
] = {};
179 uint32_t *irq_map
= full_irq_map
;
181 /* This code creates a standard swizzle of interrupts such that
182 * each device's first interrupt is based on it's PCI_SLOT number.
183 * (See pci_swizzle_map_irq_fn())
185 * We only need one entry per interrupt in the table (not one per
186 * possible slot) seeing the interrupt-map-mask will allow the table
187 * to wrap to any number of devices.
189 for (dev
= 0; dev
< GPEX_NUM_IRQS
; dev
++) {
190 int devfn
= dev
* 0x8;
192 for (pin
= 0; pin
< GPEX_NUM_IRQS
; pin
++) {
193 int irq_nr
= PCIE_IRQ
+ ((pin
+ PCI_SLOT(devfn
)) % GPEX_NUM_IRQS
);
196 /* Fill PCI address cells */
197 irq_map
[i
] = cpu_to_be32(devfn
<< 8);
198 i
+= FDT_PCI_ADDR_CELLS
;
200 /* Fill PCI Interrupt cells */
201 irq_map
[i
] = cpu_to_be32(pin
+ 1);
202 i
+= FDT_PCI_INT_CELLS
;
204 /* Fill interrupt controller phandle and cells */
205 irq_map
[i
++] = cpu_to_be32(irqchip_phandle
);
206 irq_map
[i
++] = cpu_to_be32(irq_nr
);
207 if (s
->aia_type
!= VIRT_AIA_TYPE_NONE
) {
208 irq_map
[i
++] = cpu_to_be32(0x4);
211 if (!irq_map_stride
) {
214 irq_map
+= irq_map_stride
;
218 qemu_fdt_setprop(fdt
, nodename
, "interrupt-map", full_irq_map
,
219 GPEX_NUM_IRQS
* GPEX_NUM_IRQS
*
220 irq_map_stride
* sizeof(uint32_t));
222 qemu_fdt_setprop_cells(fdt
, nodename
, "interrupt-map-mask",
226 static void create_fdt_socket_cpus(RISCVVirtState
*s
, int socket
,
227 char *clust_name
, uint32_t *phandle
,
228 uint32_t *intc_phandles
)
231 uint32_t cpu_phandle
;
232 MachineState
*ms
= MACHINE(s
);
233 char *name
, *cpu_name
, *core_name
, *intc_name
, *sv_name
;
234 bool is_32_bit
= riscv_is_32bit(&s
->soc
[0]);
235 uint8_t satp_mode_max
;
237 for (cpu
= s
->soc
[socket
].num_harts
- 1; cpu
>= 0; cpu
--) {
238 RISCVCPU
*cpu_ptr
= &s
->soc
[socket
].harts
[cpu
];
240 cpu_phandle
= (*phandle
)++;
242 cpu_name
= g_strdup_printf("/cpus/cpu@%d",
243 s
->soc
[socket
].hartid_base
+ cpu
);
244 qemu_fdt_add_subnode(ms
->fdt
, cpu_name
);
246 satp_mode_max
= satp_mode_max_from_map(
247 s
->soc
[socket
].harts
[cpu
].cfg
.satp_mode
.map
);
248 sv_name
= g_strdup_printf("riscv,%s",
249 satp_mode_str(satp_mode_max
, is_32_bit
));
250 qemu_fdt_setprop_string(ms
->fdt
, cpu_name
, "mmu-type", sv_name
);
254 name
= riscv_isa_string(cpu_ptr
);
255 qemu_fdt_setprop_string(ms
->fdt
, cpu_name
, "riscv,isa", name
);
258 if (cpu_ptr
->cfg
.ext_icbom
) {
259 qemu_fdt_setprop_cell(ms
->fdt
, cpu_name
, "riscv,cbom-block-size",
260 cpu_ptr
->cfg
.cbom_blocksize
);
263 if (cpu_ptr
->cfg
.ext_icboz
) {
264 qemu_fdt_setprop_cell(ms
->fdt
, cpu_name
, "riscv,cboz-block-size",
265 cpu_ptr
->cfg
.cboz_blocksize
);
268 qemu_fdt_setprop_string(ms
->fdt
, cpu_name
, "compatible", "riscv");
269 qemu_fdt_setprop_string(ms
->fdt
, cpu_name
, "status", "okay");
270 qemu_fdt_setprop_cell(ms
->fdt
, cpu_name
, "reg",
271 s
->soc
[socket
].hartid_base
+ cpu
);
272 qemu_fdt_setprop_string(ms
->fdt
, cpu_name
, "device_type", "cpu");
273 riscv_socket_fdt_write_id(ms
, cpu_name
, socket
);
274 qemu_fdt_setprop_cell(ms
->fdt
, cpu_name
, "phandle", cpu_phandle
);
276 intc_phandles
[cpu
] = (*phandle
)++;
278 intc_name
= g_strdup_printf("%s/interrupt-controller", cpu_name
);
279 qemu_fdt_add_subnode(ms
->fdt
, intc_name
);
280 qemu_fdt_setprop_cell(ms
->fdt
, intc_name
, "phandle",
282 qemu_fdt_setprop_string(ms
->fdt
, intc_name
, "compatible",
284 qemu_fdt_setprop(ms
->fdt
, intc_name
, "interrupt-controller", NULL
, 0);
285 qemu_fdt_setprop_cell(ms
->fdt
, intc_name
, "#interrupt-cells", 1);
287 core_name
= g_strdup_printf("%s/core%d", clust_name
, cpu
);
288 qemu_fdt_add_subnode(ms
->fdt
, core_name
);
289 qemu_fdt_setprop_cell(ms
->fdt
, core_name
, "cpu", cpu_phandle
);
297 static void create_fdt_socket_memory(RISCVVirtState
*s
,
298 const MemMapEntry
*memmap
, int socket
)
302 MachineState
*ms
= MACHINE(s
);
304 addr
= memmap
[VIRT_DRAM
].base
+ riscv_socket_mem_offset(ms
, socket
);
305 size
= riscv_socket_mem_size(ms
, socket
);
306 mem_name
= g_strdup_printf("/memory@%lx", (long)addr
);
307 qemu_fdt_add_subnode(ms
->fdt
, mem_name
);
308 qemu_fdt_setprop_cells(ms
->fdt
, mem_name
, "reg",
309 addr
>> 32, addr
, size
>> 32, size
);
310 qemu_fdt_setprop_string(ms
->fdt
, mem_name
, "device_type", "memory");
311 riscv_socket_fdt_write_id(ms
, mem_name
, socket
);
315 static void create_fdt_socket_clint(RISCVVirtState
*s
,
316 const MemMapEntry
*memmap
, int socket
,
317 uint32_t *intc_phandles
)
321 uint32_t *clint_cells
;
322 unsigned long clint_addr
;
323 MachineState
*ms
= MACHINE(s
);
324 static const char * const clint_compat
[2] = {
325 "sifive,clint0", "riscv,clint0"
328 clint_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 4);
330 for (cpu
= 0; cpu
< s
->soc
[socket
].num_harts
; cpu
++) {
331 clint_cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
332 clint_cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_SOFT
);
333 clint_cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandles
[cpu
]);
334 clint_cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_M_TIMER
);
337 clint_addr
= memmap
[VIRT_CLINT
].base
+ (memmap
[VIRT_CLINT
].size
* socket
);
338 clint_name
= g_strdup_printf("/soc/clint@%lx", clint_addr
);
339 qemu_fdt_add_subnode(ms
->fdt
, clint_name
);
340 qemu_fdt_setprop_string_array(ms
->fdt
, clint_name
, "compatible",
341 (char **)&clint_compat
,
342 ARRAY_SIZE(clint_compat
));
343 qemu_fdt_setprop_cells(ms
->fdt
, clint_name
, "reg",
344 0x0, clint_addr
, 0x0, memmap
[VIRT_CLINT
].size
);
345 qemu_fdt_setprop(ms
->fdt
, clint_name
, "interrupts-extended",
346 clint_cells
, s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 4);
347 riscv_socket_fdt_write_id(ms
, clint_name
, socket
);
353 static void create_fdt_socket_aclint(RISCVVirtState
*s
,
354 const MemMapEntry
*memmap
, int socket
,
355 uint32_t *intc_phandles
)
359 unsigned long addr
, size
;
360 uint32_t aclint_cells_size
;
361 uint32_t *aclint_mswi_cells
;
362 uint32_t *aclint_sswi_cells
;
363 uint32_t *aclint_mtimer_cells
;
364 MachineState
*ms
= MACHINE(s
);
366 aclint_mswi_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
367 aclint_mtimer_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
368 aclint_sswi_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
370 for (cpu
= 0; cpu
< s
->soc
[socket
].num_harts
; cpu
++) {
371 aclint_mswi_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
372 aclint_mswi_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_M_SOFT
);
373 aclint_mtimer_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
374 aclint_mtimer_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_M_TIMER
);
375 aclint_sswi_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
376 aclint_sswi_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_S_SOFT
);
378 aclint_cells_size
= s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 2;
380 if (s
->aia_type
!= VIRT_AIA_TYPE_APLIC_IMSIC
) {
381 addr
= memmap
[VIRT_CLINT
].base
+ (memmap
[VIRT_CLINT
].size
* socket
);
382 name
= g_strdup_printf("/soc/mswi@%lx", addr
);
383 qemu_fdt_add_subnode(ms
->fdt
, name
);
384 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible",
385 "riscv,aclint-mswi");
386 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
387 0x0, addr
, 0x0, RISCV_ACLINT_SWI_SIZE
);
388 qemu_fdt_setprop(ms
->fdt
, name
, "interrupts-extended",
389 aclint_mswi_cells
, aclint_cells_size
);
390 qemu_fdt_setprop(ms
->fdt
, name
, "interrupt-controller", NULL
, 0);
391 qemu_fdt_setprop_cell(ms
->fdt
, name
, "#interrupt-cells", 0);
392 riscv_socket_fdt_write_id(ms
, name
, socket
);
396 if (s
->aia_type
== VIRT_AIA_TYPE_APLIC_IMSIC
) {
397 addr
= memmap
[VIRT_CLINT
].base
+
398 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE
* socket
);
399 size
= RISCV_ACLINT_DEFAULT_MTIMER_SIZE
;
401 addr
= memmap
[VIRT_CLINT
].base
+ RISCV_ACLINT_SWI_SIZE
+
402 (memmap
[VIRT_CLINT
].size
* socket
);
403 size
= memmap
[VIRT_CLINT
].size
- RISCV_ACLINT_SWI_SIZE
;
405 name
= g_strdup_printf("/soc/mtimer@%lx", addr
);
406 qemu_fdt_add_subnode(ms
->fdt
, name
);
407 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible",
408 "riscv,aclint-mtimer");
409 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
410 0x0, addr
+ RISCV_ACLINT_DEFAULT_MTIME
,
411 0x0, size
- RISCV_ACLINT_DEFAULT_MTIME
,
412 0x0, addr
+ RISCV_ACLINT_DEFAULT_MTIMECMP
,
413 0x0, RISCV_ACLINT_DEFAULT_MTIME
);
414 qemu_fdt_setprop(ms
->fdt
, name
, "interrupts-extended",
415 aclint_mtimer_cells
, aclint_cells_size
);
416 riscv_socket_fdt_write_id(ms
, name
, socket
);
419 if (s
->aia_type
!= VIRT_AIA_TYPE_APLIC_IMSIC
) {
420 addr
= memmap
[VIRT_ACLINT_SSWI
].base
+
421 (memmap
[VIRT_ACLINT_SSWI
].size
* socket
);
422 name
= g_strdup_printf("/soc/sswi@%lx", addr
);
423 qemu_fdt_add_subnode(ms
->fdt
, name
);
424 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible",
425 "riscv,aclint-sswi");
426 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
427 0x0, addr
, 0x0, memmap
[VIRT_ACLINT_SSWI
].size
);
428 qemu_fdt_setprop(ms
->fdt
, name
, "interrupts-extended",
429 aclint_sswi_cells
, aclint_cells_size
);
430 qemu_fdt_setprop(ms
->fdt
, name
, "interrupt-controller", NULL
, 0);
431 qemu_fdt_setprop_cell(ms
->fdt
, name
, "#interrupt-cells", 0);
432 riscv_socket_fdt_write_id(ms
, name
, socket
);
436 g_free(aclint_mswi_cells
);
437 g_free(aclint_mtimer_cells
);
438 g_free(aclint_sswi_cells
);
441 static void create_fdt_socket_plic(RISCVVirtState
*s
,
442 const MemMapEntry
*memmap
, int socket
,
443 uint32_t *phandle
, uint32_t *intc_phandles
,
444 uint32_t *plic_phandles
)
448 uint32_t *plic_cells
;
449 unsigned long plic_addr
;
450 MachineState
*ms
= MACHINE(s
);
451 static const char * const plic_compat
[2] = {
452 "sifive,plic-1.0.0", "riscv,plic0"
456 plic_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
458 plic_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 4);
461 for (cpu
= 0; cpu
< s
->soc
[socket
].num_harts
; cpu
++) {
463 plic_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
464 plic_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_S_EXT
);
466 plic_cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
467 plic_cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_EXT
);
468 plic_cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandles
[cpu
]);
469 plic_cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_S_EXT
);
473 plic_phandles
[socket
] = (*phandle
)++;
474 plic_addr
= memmap
[VIRT_PLIC
].base
+ (memmap
[VIRT_PLIC
].size
* socket
);
475 plic_name
= g_strdup_printf("/soc/plic@%lx", plic_addr
);
476 qemu_fdt_add_subnode(ms
->fdt
, plic_name
);
477 qemu_fdt_setprop_cell(ms
->fdt
, plic_name
,
478 "#interrupt-cells", FDT_PLIC_INT_CELLS
);
479 qemu_fdt_setprop_cell(ms
->fdt
, plic_name
,
480 "#address-cells", FDT_PLIC_ADDR_CELLS
);
481 qemu_fdt_setprop_string_array(ms
->fdt
, plic_name
, "compatible",
482 (char **)&plic_compat
,
483 ARRAY_SIZE(plic_compat
));
484 qemu_fdt_setprop(ms
->fdt
, plic_name
, "interrupt-controller", NULL
, 0);
485 qemu_fdt_setprop(ms
->fdt
, plic_name
, "interrupts-extended",
486 plic_cells
, s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 4);
487 qemu_fdt_setprop_cells(ms
->fdt
, plic_name
, "reg",
488 0x0, plic_addr
, 0x0, memmap
[VIRT_PLIC
].size
);
489 qemu_fdt_setprop_cell(ms
->fdt
, plic_name
, "riscv,ndev",
490 VIRT_IRQCHIP_NUM_SOURCES
- 1);
491 riscv_socket_fdt_write_id(ms
, plic_name
, socket
);
492 qemu_fdt_setprop_cell(ms
->fdt
, plic_name
, "phandle",
493 plic_phandles
[socket
]);
496 platform_bus_add_all_fdt_nodes(ms
->fdt
, plic_name
,
497 memmap
[VIRT_PLATFORM_BUS
].base
,
498 memmap
[VIRT_PLATFORM_BUS
].size
,
499 VIRT_PLATFORM_BUS_IRQ
);
507 static uint32_t imsic_num_bits(uint32_t count
)
511 while (BIT(ret
) < count
) {
518 static void create_fdt_imsic(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
519 uint32_t *phandle
, uint32_t *intc_phandles
,
520 uint32_t *msi_m_phandle
, uint32_t *msi_s_phandle
)
524 MachineState
*ms
= MACHINE(s
);
525 int socket_count
= riscv_socket_count(ms
);
526 uint32_t imsic_max_hart_per_socket
, imsic_guest_bits
;
527 uint32_t *imsic_cells
, *imsic_regs
, imsic_addr
, imsic_size
;
529 *msi_m_phandle
= (*phandle
)++;
530 *msi_s_phandle
= (*phandle
)++;
531 imsic_cells
= g_new0(uint32_t, ms
->smp
.cpus
* 2);
532 imsic_regs
= g_new0(uint32_t, socket_count
* 4);
534 /* M-level IMSIC node */
535 for (cpu
= 0; cpu
< ms
->smp
.cpus
; cpu
++) {
536 imsic_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
537 imsic_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_M_EXT
);
539 imsic_max_hart_per_socket
= 0;
540 for (socket
= 0; socket
< socket_count
; socket
++) {
541 imsic_addr
= memmap
[VIRT_IMSIC_M
].base
+
542 socket
* VIRT_IMSIC_GROUP_MAX_SIZE
;
543 imsic_size
= IMSIC_HART_SIZE(0) * s
->soc
[socket
].num_harts
;
544 imsic_regs
[socket
* 4 + 0] = 0;
545 imsic_regs
[socket
* 4 + 1] = cpu_to_be32(imsic_addr
);
546 imsic_regs
[socket
* 4 + 2] = 0;
547 imsic_regs
[socket
* 4 + 3] = cpu_to_be32(imsic_size
);
548 if (imsic_max_hart_per_socket
< s
->soc
[socket
].num_harts
) {
549 imsic_max_hart_per_socket
= s
->soc
[socket
].num_harts
;
552 imsic_name
= g_strdup_printf("/soc/imsics@%lx",
553 (unsigned long)memmap
[VIRT_IMSIC_M
].base
);
554 qemu_fdt_add_subnode(ms
->fdt
, imsic_name
);
555 qemu_fdt_setprop_string(ms
->fdt
, imsic_name
, "compatible",
557 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "#interrupt-cells",
558 FDT_IMSIC_INT_CELLS
);
559 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "interrupt-controller",
561 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "msi-controller",
563 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "interrupts-extended",
564 imsic_cells
, ms
->smp
.cpus
* sizeof(uint32_t) * 2);
565 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "reg", imsic_regs
,
566 socket_count
* sizeof(uint32_t) * 4);
567 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,num-ids",
568 VIRT_IRQCHIP_NUM_MSIS
);
569 if (socket_count
> 1) {
570 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,hart-index-bits",
571 imsic_num_bits(imsic_max_hart_per_socket
));
572 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,group-index-bits",
573 imsic_num_bits(socket_count
));
574 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,group-index-shift",
575 IMSIC_MMIO_GROUP_MIN_SHIFT
);
577 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "phandle", *msi_m_phandle
);
581 /* S-level IMSIC node */
582 for (cpu
= 0; cpu
< ms
->smp
.cpus
; cpu
++) {
583 imsic_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
584 imsic_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_S_EXT
);
586 imsic_guest_bits
= imsic_num_bits(s
->aia_guests
+ 1);
587 imsic_max_hart_per_socket
= 0;
588 for (socket
= 0; socket
< socket_count
; socket
++) {
589 imsic_addr
= memmap
[VIRT_IMSIC_S
].base
+
590 socket
* VIRT_IMSIC_GROUP_MAX_SIZE
;
591 imsic_size
= IMSIC_HART_SIZE(imsic_guest_bits
) *
592 s
->soc
[socket
].num_harts
;
593 imsic_regs
[socket
* 4 + 0] = 0;
594 imsic_regs
[socket
* 4 + 1] = cpu_to_be32(imsic_addr
);
595 imsic_regs
[socket
* 4 + 2] = 0;
596 imsic_regs
[socket
* 4 + 3] = cpu_to_be32(imsic_size
);
597 if (imsic_max_hart_per_socket
< s
->soc
[socket
].num_harts
) {
598 imsic_max_hart_per_socket
= s
->soc
[socket
].num_harts
;
601 imsic_name
= g_strdup_printf("/soc/imsics@%lx",
602 (unsigned long)memmap
[VIRT_IMSIC_S
].base
);
603 qemu_fdt_add_subnode(ms
->fdt
, imsic_name
);
604 qemu_fdt_setprop_string(ms
->fdt
, imsic_name
, "compatible",
606 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "#interrupt-cells",
607 FDT_IMSIC_INT_CELLS
);
608 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "interrupt-controller",
610 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "msi-controller",
612 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "interrupts-extended",
613 imsic_cells
, ms
->smp
.cpus
* sizeof(uint32_t) * 2);
614 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "reg", imsic_regs
,
615 socket_count
* sizeof(uint32_t) * 4);
616 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,num-ids",
617 VIRT_IRQCHIP_NUM_MSIS
);
618 if (imsic_guest_bits
) {
619 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,guest-index-bits",
622 if (socket_count
> 1) {
623 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,hart-index-bits",
624 imsic_num_bits(imsic_max_hart_per_socket
));
625 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,group-index-bits",
626 imsic_num_bits(socket_count
));
627 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,group-index-shift",
628 IMSIC_MMIO_GROUP_MIN_SHIFT
);
630 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "phandle", *msi_s_phandle
);
637 static void create_fdt_socket_aplic(RISCVVirtState
*s
,
638 const MemMapEntry
*memmap
, int socket
,
639 uint32_t msi_m_phandle
,
640 uint32_t msi_s_phandle
,
642 uint32_t *intc_phandles
,
643 uint32_t *aplic_phandles
)
647 uint32_t *aplic_cells
;
648 unsigned long aplic_addr
;
649 MachineState
*ms
= MACHINE(s
);
650 uint32_t aplic_m_phandle
, aplic_s_phandle
;
652 aplic_m_phandle
= (*phandle
)++;
653 aplic_s_phandle
= (*phandle
)++;
654 aplic_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
656 /* M-level APLIC node */
657 for (cpu
= 0; cpu
< s
->soc
[socket
].num_harts
; cpu
++) {
658 aplic_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
659 aplic_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_M_EXT
);
661 aplic_addr
= memmap
[VIRT_APLIC_M
].base
+
662 (memmap
[VIRT_APLIC_M
].size
* socket
);
663 aplic_name
= g_strdup_printf("/soc/aplic@%lx", aplic_addr
);
664 qemu_fdt_add_subnode(ms
->fdt
, aplic_name
);
665 qemu_fdt_setprop_string(ms
->fdt
, aplic_name
, "compatible", "riscv,aplic");
666 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
,
667 "#interrupt-cells", FDT_APLIC_INT_CELLS
);
668 qemu_fdt_setprop(ms
->fdt
, aplic_name
, "interrupt-controller", NULL
, 0);
669 if (s
->aia_type
== VIRT_AIA_TYPE_APLIC
) {
670 qemu_fdt_setprop(ms
->fdt
, aplic_name
, "interrupts-extended",
671 aplic_cells
, s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 2);
673 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "msi-parent",
676 qemu_fdt_setprop_cells(ms
->fdt
, aplic_name
, "reg",
677 0x0, aplic_addr
, 0x0, memmap
[VIRT_APLIC_M
].size
);
678 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "riscv,num-sources",
679 VIRT_IRQCHIP_NUM_SOURCES
);
680 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "riscv,children",
682 qemu_fdt_setprop_cells(ms
->fdt
, aplic_name
, "riscv,delegate",
683 aplic_s_phandle
, 0x1, VIRT_IRQCHIP_NUM_SOURCES
);
684 riscv_socket_fdt_write_id(ms
, aplic_name
, socket
);
685 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "phandle", aplic_m_phandle
);
688 /* S-level APLIC node */
689 for (cpu
= 0; cpu
< s
->soc
[socket
].num_harts
; cpu
++) {
690 aplic_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
691 aplic_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_S_EXT
);
693 aplic_addr
= memmap
[VIRT_APLIC_S
].base
+
694 (memmap
[VIRT_APLIC_S
].size
* socket
);
695 aplic_name
= g_strdup_printf("/soc/aplic@%lx", aplic_addr
);
696 qemu_fdt_add_subnode(ms
->fdt
, aplic_name
);
697 qemu_fdt_setprop_string(ms
->fdt
, aplic_name
, "compatible", "riscv,aplic");
698 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
,
699 "#interrupt-cells", FDT_APLIC_INT_CELLS
);
700 qemu_fdt_setprop(ms
->fdt
, aplic_name
, "interrupt-controller", NULL
, 0);
701 if (s
->aia_type
== VIRT_AIA_TYPE_APLIC
) {
702 qemu_fdt_setprop(ms
->fdt
, aplic_name
, "interrupts-extended",
703 aplic_cells
, s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 2);
705 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "msi-parent",
708 qemu_fdt_setprop_cells(ms
->fdt
, aplic_name
, "reg",
709 0x0, aplic_addr
, 0x0, memmap
[VIRT_APLIC_S
].size
);
710 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "riscv,num-sources",
711 VIRT_IRQCHIP_NUM_SOURCES
);
712 riscv_socket_fdt_write_id(ms
, aplic_name
, socket
);
713 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "phandle", aplic_s_phandle
);
716 platform_bus_add_all_fdt_nodes(ms
->fdt
, aplic_name
,
717 memmap
[VIRT_PLATFORM_BUS
].base
,
718 memmap
[VIRT_PLATFORM_BUS
].size
,
719 VIRT_PLATFORM_BUS_IRQ
);
725 aplic_phandles
[socket
] = aplic_s_phandle
;
728 static void create_fdt_pmu(RISCVVirtState
*s
)
731 MachineState
*ms
= MACHINE(s
);
732 RISCVCPU hart
= s
->soc
[0].harts
[0];
734 pmu_name
= g_strdup_printf("/soc/pmu");
735 qemu_fdt_add_subnode(ms
->fdt
, pmu_name
);
736 qemu_fdt_setprop_string(ms
->fdt
, pmu_name
, "compatible", "riscv,pmu");
737 riscv_pmu_generate_fdt_node(ms
->fdt
, hart
.cfg
.pmu_num
, pmu_name
);
742 static void create_fdt_sockets(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
744 uint32_t *irq_mmio_phandle
,
745 uint32_t *irq_pcie_phandle
,
746 uint32_t *irq_virtio_phandle
,
747 uint32_t *msi_pcie_phandle
)
750 int socket
, phandle_pos
;
751 MachineState
*ms
= MACHINE(s
);
752 uint32_t msi_m_phandle
= 0, msi_s_phandle
= 0;
753 uint32_t *intc_phandles
, xplic_phandles
[MAX_NODES
];
754 int socket_count
= riscv_socket_count(ms
);
756 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
757 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "timebase-frequency",
758 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ
);
759 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
760 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", 0x1);
761 qemu_fdt_add_subnode(ms
->fdt
, "/cpus/cpu-map");
763 intc_phandles
= g_new0(uint32_t, ms
->smp
.cpus
);
765 phandle_pos
= ms
->smp
.cpus
;
766 for (socket
= (socket_count
- 1); socket
>= 0; socket
--) {
767 phandle_pos
-= s
->soc
[socket
].num_harts
;
769 clust_name
= g_strdup_printf("/cpus/cpu-map/cluster%d", socket
);
770 qemu_fdt_add_subnode(ms
->fdt
, clust_name
);
772 create_fdt_socket_cpus(s
, socket
, clust_name
, phandle
,
773 &intc_phandles
[phandle_pos
]);
775 create_fdt_socket_memory(s
, memmap
, socket
);
779 if (!kvm_enabled()) {
780 if (s
->have_aclint
) {
781 create_fdt_socket_aclint(s
, memmap
, socket
,
782 &intc_phandles
[phandle_pos
]);
784 create_fdt_socket_clint(s
, memmap
, socket
,
785 &intc_phandles
[phandle_pos
]);
790 if (s
->aia_type
== VIRT_AIA_TYPE_APLIC_IMSIC
) {
791 create_fdt_imsic(s
, memmap
, phandle
, intc_phandles
,
792 &msi_m_phandle
, &msi_s_phandle
);
793 *msi_pcie_phandle
= msi_s_phandle
;
796 phandle_pos
= ms
->smp
.cpus
;
797 for (socket
= (socket_count
- 1); socket
>= 0; socket
--) {
798 phandle_pos
-= s
->soc
[socket
].num_harts
;
800 if (s
->aia_type
== VIRT_AIA_TYPE_NONE
) {
801 create_fdt_socket_plic(s
, memmap
, socket
, phandle
,
802 &intc_phandles
[phandle_pos
], xplic_phandles
);
804 create_fdt_socket_aplic(s
, memmap
, socket
,
805 msi_m_phandle
, msi_s_phandle
, phandle
,
806 &intc_phandles
[phandle_pos
], xplic_phandles
);
810 g_free(intc_phandles
);
812 for (socket
= 0; socket
< socket_count
; socket
++) {
814 *irq_mmio_phandle
= xplic_phandles
[socket
];
815 *irq_virtio_phandle
= xplic_phandles
[socket
];
816 *irq_pcie_phandle
= xplic_phandles
[socket
];
819 *irq_virtio_phandle
= xplic_phandles
[socket
];
820 *irq_pcie_phandle
= xplic_phandles
[socket
];
823 *irq_pcie_phandle
= xplic_phandles
[socket
];
827 riscv_socket_fdt_write_distance_matrix(ms
);
830 static void create_fdt_virtio(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
831 uint32_t irq_virtio_phandle
)
835 MachineState
*ms
= MACHINE(s
);
837 for (i
= 0; i
< VIRTIO_COUNT
; i
++) {
838 name
= g_strdup_printf("/soc/virtio_mmio@%lx",
839 (long)(memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
));
840 qemu_fdt_add_subnode(ms
->fdt
, name
);
841 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible", "virtio,mmio");
842 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
843 0x0, memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
,
844 0x0, memmap
[VIRT_VIRTIO
].size
);
845 qemu_fdt_setprop_cell(ms
->fdt
, name
, "interrupt-parent",
847 if (s
->aia_type
== VIRT_AIA_TYPE_NONE
) {
848 qemu_fdt_setprop_cell(ms
->fdt
, name
, "interrupts",
851 qemu_fdt_setprop_cells(ms
->fdt
, name
, "interrupts",
852 VIRTIO_IRQ
+ i
, 0x4);
858 static void create_fdt_pcie(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
859 uint32_t irq_pcie_phandle
,
860 uint32_t msi_pcie_phandle
)
863 MachineState
*ms
= MACHINE(s
);
865 name
= g_strdup_printf("/soc/pci@%lx",
866 (long) memmap
[VIRT_PCIE_ECAM
].base
);
867 qemu_fdt_add_subnode(ms
->fdt
, name
);
868 qemu_fdt_setprop_cell(ms
->fdt
, name
, "#address-cells",
870 qemu_fdt_setprop_cell(ms
->fdt
, name
, "#interrupt-cells",
872 qemu_fdt_setprop_cell(ms
->fdt
, name
, "#size-cells", 0x2);
873 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible",
874 "pci-host-ecam-generic");
875 qemu_fdt_setprop_string(ms
->fdt
, name
, "device_type", "pci");
876 qemu_fdt_setprop_cell(ms
->fdt
, name
, "linux,pci-domain", 0);
877 qemu_fdt_setprop_cells(ms
->fdt
, name
, "bus-range", 0,
878 memmap
[VIRT_PCIE_ECAM
].size
/ PCIE_MMCFG_SIZE_MIN
- 1);
879 qemu_fdt_setprop(ms
->fdt
, name
, "dma-coherent", NULL
, 0);
880 if (s
->aia_type
== VIRT_AIA_TYPE_APLIC_IMSIC
) {
881 qemu_fdt_setprop_cell(ms
->fdt
, name
, "msi-parent", msi_pcie_phandle
);
883 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg", 0,
884 memmap
[VIRT_PCIE_ECAM
].base
, 0, memmap
[VIRT_PCIE_ECAM
].size
);
885 qemu_fdt_setprop_sized_cells(ms
->fdt
, name
, "ranges",
886 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
887 2, memmap
[VIRT_PCIE_PIO
].base
, 2, memmap
[VIRT_PCIE_PIO
].size
,
888 1, FDT_PCI_RANGE_MMIO
,
889 2, memmap
[VIRT_PCIE_MMIO
].base
,
890 2, memmap
[VIRT_PCIE_MMIO
].base
, 2, memmap
[VIRT_PCIE_MMIO
].size
,
891 1, FDT_PCI_RANGE_MMIO_64BIT
,
892 2, virt_high_pcie_memmap
.base
,
893 2, virt_high_pcie_memmap
.base
, 2, virt_high_pcie_memmap
.size
);
895 create_pcie_irq_map(s
, ms
->fdt
, name
, irq_pcie_phandle
);
899 static void create_fdt_reset(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
903 uint32_t test_phandle
;
904 MachineState
*ms
= MACHINE(s
);
906 test_phandle
= (*phandle
)++;
907 name
= g_strdup_printf("/soc/test@%lx",
908 (long)memmap
[VIRT_TEST
].base
);
909 qemu_fdt_add_subnode(ms
->fdt
, name
);
911 static const char * const compat
[3] = {
912 "sifive,test1", "sifive,test0", "syscon"
914 qemu_fdt_setprop_string_array(ms
->fdt
, name
, "compatible",
915 (char **)&compat
, ARRAY_SIZE(compat
));
917 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
918 0x0, memmap
[VIRT_TEST
].base
, 0x0, memmap
[VIRT_TEST
].size
);
919 qemu_fdt_setprop_cell(ms
->fdt
, name
, "phandle", test_phandle
);
920 test_phandle
= qemu_fdt_get_phandle(ms
->fdt
, name
);
923 name
= g_strdup_printf("/reboot");
924 qemu_fdt_add_subnode(ms
->fdt
, name
);
925 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible", "syscon-reboot");
926 qemu_fdt_setprop_cell(ms
->fdt
, name
, "regmap", test_phandle
);
927 qemu_fdt_setprop_cell(ms
->fdt
, name
, "offset", 0x0);
928 qemu_fdt_setprop_cell(ms
->fdt
, name
, "value", FINISHER_RESET
);
931 name
= g_strdup_printf("/poweroff");
932 qemu_fdt_add_subnode(ms
->fdt
, name
);
933 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible", "syscon-poweroff");
934 qemu_fdt_setprop_cell(ms
->fdt
, name
, "regmap", test_phandle
);
935 qemu_fdt_setprop_cell(ms
->fdt
, name
, "offset", 0x0);
936 qemu_fdt_setprop_cell(ms
->fdt
, name
, "value", FINISHER_PASS
);
940 static void create_fdt_uart(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
941 uint32_t irq_mmio_phandle
)
944 MachineState
*ms
= MACHINE(s
);
946 name
= g_strdup_printf("/soc/serial@%lx", (long)memmap
[VIRT_UART0
].base
);
947 qemu_fdt_add_subnode(ms
->fdt
, name
);
948 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible", "ns16550a");
949 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
950 0x0, memmap
[VIRT_UART0
].base
,
951 0x0, memmap
[VIRT_UART0
].size
);
952 qemu_fdt_setprop_cell(ms
->fdt
, name
, "clock-frequency", 3686400);
953 qemu_fdt_setprop_cell(ms
->fdt
, name
, "interrupt-parent", irq_mmio_phandle
);
954 if (s
->aia_type
== VIRT_AIA_TYPE_NONE
) {
955 qemu_fdt_setprop_cell(ms
->fdt
, name
, "interrupts", UART0_IRQ
);
957 qemu_fdt_setprop_cells(ms
->fdt
, name
, "interrupts", UART0_IRQ
, 0x4);
960 qemu_fdt_add_subnode(ms
->fdt
, "/chosen");
961 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", name
);
965 static void create_fdt_rtc(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
966 uint32_t irq_mmio_phandle
)
969 MachineState
*ms
= MACHINE(s
);
971 name
= g_strdup_printf("/soc/rtc@%lx", (long)memmap
[VIRT_RTC
].base
);
972 qemu_fdt_add_subnode(ms
->fdt
, name
);
973 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible",
974 "google,goldfish-rtc");
975 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
976 0x0, memmap
[VIRT_RTC
].base
, 0x0, memmap
[VIRT_RTC
].size
);
977 qemu_fdt_setprop_cell(ms
->fdt
, name
, "interrupt-parent",
979 if (s
->aia_type
== VIRT_AIA_TYPE_NONE
) {
980 qemu_fdt_setprop_cell(ms
->fdt
, name
, "interrupts", RTC_IRQ
);
982 qemu_fdt_setprop_cells(ms
->fdt
, name
, "interrupts", RTC_IRQ
, 0x4);
987 static void create_fdt_flash(RISCVVirtState
*s
, const MemMapEntry
*memmap
)
990 MachineState
*ms
= MACHINE(s
);
991 hwaddr flashsize
= virt_memmap
[VIRT_FLASH
].size
/ 2;
992 hwaddr flashbase
= virt_memmap
[VIRT_FLASH
].base
;
994 name
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
995 qemu_fdt_add_subnode(ms
->fdt
, name
);
996 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible", "cfi-flash");
997 qemu_fdt_setprop_sized_cells(ms
->fdt
, name
, "reg",
998 2, flashbase
, 2, flashsize
,
999 2, flashbase
+ flashsize
, 2, flashsize
);
1000 qemu_fdt_setprop_cell(ms
->fdt
, name
, "bank-width", 4);
1004 static void create_fdt_fw_cfg(RISCVVirtState
*s
, const MemMapEntry
*memmap
)
1007 MachineState
*ms
= MACHINE(s
);
1008 hwaddr base
= memmap
[VIRT_FW_CFG
].base
;
1009 hwaddr size
= memmap
[VIRT_FW_CFG
].size
;
1011 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1012 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1013 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1014 "compatible", "qemu,fw-cfg-mmio");
1015 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1017 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1021 static void create_fdt(RISCVVirtState
*s
, const MemMapEntry
*memmap
)
1023 MachineState
*ms
= MACHINE(s
);
1024 uint32_t phandle
= 1, irq_mmio_phandle
= 1, msi_pcie_phandle
= 1;
1025 uint32_t irq_pcie_phandle
= 1, irq_virtio_phandle
= 1;
1026 uint8_t rng_seed
[32];
1028 ms
->fdt
= create_device_tree(&s
->fdt_size
);
1030 error_report("create_device_tree() failed");
1034 qemu_fdt_setprop_string(ms
->fdt
, "/", "model", "riscv-virtio,qemu");
1035 qemu_fdt_setprop_string(ms
->fdt
, "/", "compatible", "riscv-virtio");
1036 qemu_fdt_setprop_cell(ms
->fdt
, "/", "#size-cells", 0x2);
1037 qemu_fdt_setprop_cell(ms
->fdt
, "/", "#address-cells", 0x2);
1039 qemu_fdt_add_subnode(ms
->fdt
, "/soc");
1040 qemu_fdt_setprop(ms
->fdt
, "/soc", "ranges", NULL
, 0);
1041 qemu_fdt_setprop_string(ms
->fdt
, "/soc", "compatible", "simple-bus");
1042 qemu_fdt_setprop_cell(ms
->fdt
, "/soc", "#size-cells", 0x2);
1043 qemu_fdt_setprop_cell(ms
->fdt
, "/soc", "#address-cells", 0x2);
1045 create_fdt_sockets(s
, memmap
, &phandle
, &irq_mmio_phandle
,
1046 &irq_pcie_phandle
, &irq_virtio_phandle
,
1049 create_fdt_virtio(s
, memmap
, irq_virtio_phandle
);
1051 create_fdt_pcie(s
, memmap
, irq_pcie_phandle
, msi_pcie_phandle
);
1053 create_fdt_reset(s
, memmap
, &phandle
);
1055 create_fdt_uart(s
, memmap
, irq_mmio_phandle
);
1057 create_fdt_rtc(s
, memmap
, irq_mmio_phandle
);
1059 create_fdt_flash(s
, memmap
);
1060 create_fdt_fw_cfg(s
, memmap
);
1063 /* Pass seed to RNG */
1064 qemu_guest_getrandom_nofail(rng_seed
, sizeof(rng_seed
));
1065 qemu_fdt_setprop(ms
->fdt
, "/chosen", "rng-seed",
1066 rng_seed
, sizeof(rng_seed
));
1069 static inline DeviceState
*gpex_pcie_init(MemoryRegion
*sys_mem
,
1070 hwaddr ecam_base
, hwaddr ecam_size
,
1071 hwaddr mmio_base
, hwaddr mmio_size
,
1072 hwaddr high_mmio_base
,
1073 hwaddr high_mmio_size
,
1075 DeviceState
*irqchip
)
1078 MemoryRegion
*ecam_alias
, *ecam_reg
;
1079 MemoryRegion
*mmio_alias
, *high_mmio_alias
, *mmio_reg
;
1083 dev
= qdev_new(TYPE_GPEX_HOST
);
1085 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1087 ecam_alias
= g_new0(MemoryRegion
, 1);
1088 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1089 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1090 ecam_reg
, 0, ecam_size
);
1091 memory_region_add_subregion(get_system_memory(), ecam_base
, ecam_alias
);
1093 mmio_alias
= g_new0(MemoryRegion
, 1);
1094 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1095 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1096 mmio_reg
, mmio_base
, mmio_size
);
1097 memory_region_add_subregion(get_system_memory(), mmio_base
, mmio_alias
);
1099 /* Map high MMIO space */
1100 high_mmio_alias
= g_new0(MemoryRegion
, 1);
1101 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1102 mmio_reg
, high_mmio_base
, high_mmio_size
);
1103 memory_region_add_subregion(get_system_memory(), high_mmio_base
,
1106 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, pio_base
);
1108 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1109 irq
= qdev_get_gpio_in(irqchip
, PCIE_IRQ
+ i
);
1111 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, irq
);
1112 gpex_set_irq_num(GPEX_HOST(dev
), i
, PCIE_IRQ
+ i
);
1118 static FWCfgState
*create_fw_cfg(const MachineState
*ms
)
1120 hwaddr base
= virt_memmap
[VIRT_FW_CFG
].base
;
1123 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16,
1124 &address_space_memory
);
1125 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1130 static DeviceState
*virt_create_plic(const MemMapEntry
*memmap
, int socket
,
1131 int base_hartid
, int hart_count
)
1134 char *plic_hart_config
;
1136 /* Per-socket PLIC hart topology configuration string */
1137 plic_hart_config
= riscv_plic_hart_config_string(hart_count
);
1139 /* Per-socket PLIC */
1140 ret
= sifive_plic_create(
1141 memmap
[VIRT_PLIC
].base
+ socket
* memmap
[VIRT_PLIC
].size
,
1142 plic_hart_config
, hart_count
, base_hartid
,
1143 VIRT_IRQCHIP_NUM_SOURCES
,
1144 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS
) - 1),
1145 VIRT_PLIC_PRIORITY_BASE
,
1146 VIRT_PLIC_PENDING_BASE
,
1147 VIRT_PLIC_ENABLE_BASE
,
1148 VIRT_PLIC_ENABLE_STRIDE
,
1149 VIRT_PLIC_CONTEXT_BASE
,
1150 VIRT_PLIC_CONTEXT_STRIDE
,
1151 memmap
[VIRT_PLIC
].size
);
1153 g_free(plic_hart_config
);
1158 static DeviceState
*virt_create_aia(RISCVVirtAIAType aia_type
, int aia_guests
,
1159 const MemMapEntry
*memmap
, int socket
,
1160 int base_hartid
, int hart_count
)
1164 uint32_t guest_bits
;
1165 DeviceState
*aplic_m
;
1166 bool msimode
= (aia_type
== VIRT_AIA_TYPE_APLIC_IMSIC
) ? true : false;
1169 /* Per-socket M-level IMSICs */
1170 addr
= memmap
[VIRT_IMSIC_M
].base
+ socket
* VIRT_IMSIC_GROUP_MAX_SIZE
;
1171 for (i
= 0; i
< hart_count
; i
++) {
1172 riscv_imsic_create(addr
+ i
* IMSIC_HART_SIZE(0),
1173 base_hartid
+ i
, true, 1,
1174 VIRT_IRQCHIP_NUM_MSIS
);
1177 /* Per-socket S-level IMSICs */
1178 guest_bits
= imsic_num_bits(aia_guests
+ 1);
1179 addr
= memmap
[VIRT_IMSIC_S
].base
+ socket
* VIRT_IMSIC_GROUP_MAX_SIZE
;
1180 for (i
= 0; i
< hart_count
; i
++) {
1181 riscv_imsic_create(addr
+ i
* IMSIC_HART_SIZE(guest_bits
),
1182 base_hartid
+ i
, false, 1 + aia_guests
,
1183 VIRT_IRQCHIP_NUM_MSIS
);
1187 /* Per-socket M-level APLIC */
1188 aplic_m
= riscv_aplic_create(
1189 memmap
[VIRT_APLIC_M
].base
+ socket
* memmap
[VIRT_APLIC_M
].size
,
1190 memmap
[VIRT_APLIC_M
].size
,
1191 (msimode
) ? 0 : base_hartid
,
1192 (msimode
) ? 0 : hart_count
,
1193 VIRT_IRQCHIP_NUM_SOURCES
,
1194 VIRT_IRQCHIP_NUM_PRIO_BITS
,
1195 msimode
, true, NULL
);
1198 /* Per-socket S-level APLIC */
1200 memmap
[VIRT_APLIC_S
].base
+ socket
* memmap
[VIRT_APLIC_S
].size
,
1201 memmap
[VIRT_APLIC_S
].size
,
1202 (msimode
) ? 0 : base_hartid
,
1203 (msimode
) ? 0 : hart_count
,
1204 VIRT_IRQCHIP_NUM_SOURCES
,
1205 VIRT_IRQCHIP_NUM_PRIO_BITS
,
1206 msimode
, false, aplic_m
);
1212 static void create_platform_bus(RISCVVirtState
*s
, DeviceState
*irqchip
)
1215 SysBusDevice
*sysbus
;
1216 const MemMapEntry
*memmap
= virt_memmap
;
1218 MemoryRegion
*sysmem
= get_system_memory();
1220 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1221 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1222 qdev_prop_set_uint32(dev
, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS
);
1223 qdev_prop_set_uint32(dev
, "mmio_size", memmap
[VIRT_PLATFORM_BUS
].size
);
1224 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1225 s
->platform_bus_dev
= dev
;
1227 sysbus
= SYS_BUS_DEVICE(dev
);
1228 for (i
= 0; i
< VIRT_PLATFORM_BUS_NUM_IRQS
; i
++) {
1229 int irq
= VIRT_PLATFORM_BUS_IRQ
+ i
;
1230 sysbus_connect_irq(sysbus
, i
, qdev_get_gpio_in(irqchip
, irq
));
1233 memory_region_add_subregion(sysmem
,
1234 memmap
[VIRT_PLATFORM_BUS
].base
,
1235 sysbus_mmio_get_region(sysbus
, 0));
1238 static void virt_machine_done(Notifier
*notifier
, void *data
)
1240 RISCVVirtState
*s
= container_of(notifier
, RISCVVirtState
,
1242 const MemMapEntry
*memmap
= virt_memmap
;
1243 MachineState
*machine
= MACHINE(s
);
1244 target_ulong start_addr
= memmap
[VIRT_DRAM
].base
;
1245 target_ulong firmware_end_addr
, kernel_start_addr
;
1246 const char *firmware_name
= riscv_default_firmware_name(&s
->soc
[0]);
1247 uint32_t fdt_load_addr
;
1248 uint64_t kernel_entry
;
1251 * Only direct boot kernel is currently supported for KVM VM,
1252 * so the "-bios" parameter is not supported when KVM is enabled.
1254 if (kvm_enabled()) {
1255 if (machine
->firmware
) {
1256 if (strcmp(machine
->firmware
, "none")) {
1257 error_report("Machine mode firmware is not supported in "
1258 "combination with KVM.");
1262 machine
->firmware
= g_strdup("none");
1266 firmware_end_addr
= riscv_find_and_load_firmware(machine
, firmware_name
,
1269 if (drive_get(IF_PFLASH
, 0, 1)) {
1271 * S-mode FW like EDK2 will be kept in second plash (unit 1).
1272 * When both kernel, initrd and pflash options are provided in the
1273 * command line, the kernel and initrd will be copied to the fw_cfg
1274 * table and opensbi will jump to the flash address which is the
1275 * entry point of S-mode FW. It is the job of the S-mode FW to load
1276 * the kernel and initrd using fw_cfg table.
1278 * If only pflash is given but not -kernel, then it is the job of
1279 * of the S-mode firmware to locate and load the kernel.
1280 * In either case, the next_addr for opensbi will be the flash address.
1282 riscv_setup_firmware_boot(machine
);
1283 kernel_entry
= virt_memmap
[VIRT_FLASH
].base
+
1284 virt_memmap
[VIRT_FLASH
].size
/ 2;
1285 } else if (machine
->kernel_filename
) {
1286 kernel_start_addr
= riscv_calc_kernel_start_addr(&s
->soc
[0],
1289 kernel_entry
= riscv_load_kernel(machine
, &s
->soc
[0],
1290 kernel_start_addr
, true, NULL
);
1293 * If dynamic firmware is used, it doesn't know where is the next mode
1294 * if kernel argument is not set.
1299 if (drive_get(IF_PFLASH
, 0, 0)) {
1301 * Pflash was supplied, let's overwrite the address we jump to after
1302 * reset to the base of the flash.
1304 start_addr
= virt_memmap
[VIRT_FLASH
].base
;
1307 fdt_load_addr
= riscv_compute_fdt_addr(memmap
[VIRT_DRAM
].base
,
1308 memmap
[VIRT_DRAM
].size
,
1310 riscv_load_fdt(fdt_load_addr
, machine
->fdt
);
1312 /* load the reset vector */
1313 riscv_setup_rom_reset_vec(machine
, &s
->soc
[0], start_addr
,
1314 virt_memmap
[VIRT_MROM
].base
,
1315 virt_memmap
[VIRT_MROM
].size
, kernel_entry
,
1319 * Only direct boot kernel is currently supported for KVM VM,
1320 * So here setup kernel start address and fdt address.
1321 * TODO:Support firmware loading and integrate to TCG start
1323 if (kvm_enabled()) {
1324 riscv_setup_direct_kernel(kernel_entry
, fdt_load_addr
);
1327 if (virt_is_acpi_enabled(s
)) {
1332 static void virt_machine_init(MachineState
*machine
)
1334 const MemMapEntry
*memmap
= virt_memmap
;
1335 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(machine
);
1336 MemoryRegion
*system_memory
= get_system_memory();
1337 MemoryRegion
*mask_rom
= g_new(MemoryRegion
, 1);
1339 DeviceState
*mmio_irqchip
, *virtio_irqchip
, *pcie_irqchip
;
1340 int i
, base_hartid
, hart_count
;
1341 int socket_count
= riscv_socket_count(machine
);
1343 /* Check socket count limit */
1344 if (VIRT_SOCKETS_MAX
< socket_count
) {
1345 error_report("number of sockets/nodes should be less than %d",
1350 /* Initialize sockets */
1351 mmio_irqchip
= virtio_irqchip
= pcie_irqchip
= NULL
;
1352 for (i
= 0; i
< socket_count
; i
++) {
1353 if (!riscv_socket_check_hartids(machine
, i
)) {
1354 error_report("discontinuous hartids in socket%d", i
);
1358 base_hartid
= riscv_socket_first_hartid(machine
, i
);
1359 if (base_hartid
< 0) {
1360 error_report("can't find hartid base for socket%d", i
);
1364 hart_count
= riscv_socket_hart_count(machine
, i
);
1365 if (hart_count
< 0) {
1366 error_report("can't find hart count for socket%d", i
);
1370 soc_name
= g_strdup_printf("soc%d", i
);
1371 object_initialize_child(OBJECT(machine
), soc_name
, &s
->soc
[i
],
1372 TYPE_RISCV_HART_ARRAY
);
1374 object_property_set_str(OBJECT(&s
->soc
[i
]), "cpu-type",
1375 machine
->cpu_type
, &error_abort
);
1376 object_property_set_int(OBJECT(&s
->soc
[i
]), "hartid-base",
1377 base_hartid
, &error_abort
);
1378 object_property_set_int(OBJECT(&s
->soc
[i
]), "num-harts",
1379 hart_count
, &error_abort
);
1380 sysbus_realize(SYS_BUS_DEVICE(&s
->soc
[i
]), &error_fatal
);
1382 if (!kvm_enabled()) {
1383 if (s
->have_aclint
) {
1384 if (s
->aia_type
== VIRT_AIA_TYPE_APLIC_IMSIC
) {
1385 /* Per-socket ACLINT MTIMER */
1386 riscv_aclint_mtimer_create(memmap
[VIRT_CLINT
].base
+
1387 i
* RISCV_ACLINT_DEFAULT_MTIMER_SIZE
,
1388 RISCV_ACLINT_DEFAULT_MTIMER_SIZE
,
1389 base_hartid
, hart_count
,
1390 RISCV_ACLINT_DEFAULT_MTIMECMP
,
1391 RISCV_ACLINT_DEFAULT_MTIME
,
1392 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ
, true);
1394 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
1395 riscv_aclint_swi_create(memmap
[VIRT_CLINT
].base
+
1396 i
* memmap
[VIRT_CLINT
].size
,
1397 base_hartid
, hart_count
, false);
1398 riscv_aclint_mtimer_create(memmap
[VIRT_CLINT
].base
+
1399 i
* memmap
[VIRT_CLINT
].size
+
1400 RISCV_ACLINT_SWI_SIZE
,
1401 RISCV_ACLINT_DEFAULT_MTIMER_SIZE
,
1402 base_hartid
, hart_count
,
1403 RISCV_ACLINT_DEFAULT_MTIMECMP
,
1404 RISCV_ACLINT_DEFAULT_MTIME
,
1405 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ
, true);
1406 riscv_aclint_swi_create(memmap
[VIRT_ACLINT_SSWI
].base
+
1407 i
* memmap
[VIRT_ACLINT_SSWI
].size
,
1408 base_hartid
, hart_count
, true);
1411 /* Per-socket SiFive CLINT */
1412 riscv_aclint_swi_create(
1413 memmap
[VIRT_CLINT
].base
+ i
* memmap
[VIRT_CLINT
].size
,
1414 base_hartid
, hart_count
, false);
1415 riscv_aclint_mtimer_create(memmap
[VIRT_CLINT
].base
+
1416 i
* memmap
[VIRT_CLINT
].size
+ RISCV_ACLINT_SWI_SIZE
,
1417 RISCV_ACLINT_DEFAULT_MTIMER_SIZE
, base_hartid
, hart_count
,
1418 RISCV_ACLINT_DEFAULT_MTIMECMP
, RISCV_ACLINT_DEFAULT_MTIME
,
1419 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ
, true);
1423 /* Per-socket interrupt controller */
1424 if (s
->aia_type
== VIRT_AIA_TYPE_NONE
) {
1425 s
->irqchip
[i
] = virt_create_plic(memmap
, i
,
1426 base_hartid
, hart_count
);
1428 s
->irqchip
[i
] = virt_create_aia(s
->aia_type
, s
->aia_guests
,
1429 memmap
, i
, base_hartid
,
1433 /* Try to use different IRQCHIP instance based device type */
1435 mmio_irqchip
= s
->irqchip
[i
];
1436 virtio_irqchip
= s
->irqchip
[i
];
1437 pcie_irqchip
= s
->irqchip
[i
];
1440 virtio_irqchip
= s
->irqchip
[i
];
1441 pcie_irqchip
= s
->irqchip
[i
];
1444 pcie_irqchip
= s
->irqchip
[i
];
1448 if (riscv_is_32bit(&s
->soc
[0])) {
1449 #if HOST_LONG_BITS == 64
1450 /* limit RAM size in a 32-bit system */
1451 if (machine
->ram_size
> 10 * GiB
) {
1452 machine
->ram_size
= 10 * GiB
;
1453 error_report("Limiting RAM size to 10 GiB");
1456 virt_high_pcie_memmap
.base
= VIRT32_HIGH_PCIE_MMIO_BASE
;
1457 virt_high_pcie_memmap
.size
= VIRT32_HIGH_PCIE_MMIO_SIZE
;
1459 virt_high_pcie_memmap
.size
= VIRT64_HIGH_PCIE_MMIO_SIZE
;
1460 virt_high_pcie_memmap
.base
= memmap
[VIRT_DRAM
].base
+ machine
->ram_size
;
1461 virt_high_pcie_memmap
.base
=
1462 ROUND_UP(virt_high_pcie_memmap
.base
, virt_high_pcie_memmap
.size
);
1465 s
->memmap
= virt_memmap
;
1467 /* register system main memory (actual RAM) */
1468 memory_region_add_subregion(system_memory
, memmap
[VIRT_DRAM
].base
,
1472 memory_region_init_rom(mask_rom
, NULL
, "riscv_virt_board.mrom",
1473 memmap
[VIRT_MROM
].size
, &error_fatal
);
1474 memory_region_add_subregion(system_memory
, memmap
[VIRT_MROM
].base
,
1478 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the
1479 * device tree cannot be altered and we get FDT_ERR_NOSPACE.
1481 s
->fw_cfg
= create_fw_cfg(machine
);
1482 rom_set_fw(s
->fw_cfg
);
1484 /* SiFive Test MMIO device */
1485 sifive_test_create(memmap
[VIRT_TEST
].base
);
1487 /* VirtIO MMIO devices */
1488 for (i
= 0; i
< VIRTIO_COUNT
; i
++) {
1489 sysbus_create_simple("virtio-mmio",
1490 memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
,
1491 qdev_get_gpio_in(virtio_irqchip
, VIRTIO_IRQ
+ i
));
1494 gpex_pcie_init(system_memory
,
1495 memmap
[VIRT_PCIE_ECAM
].base
,
1496 memmap
[VIRT_PCIE_ECAM
].size
,
1497 memmap
[VIRT_PCIE_MMIO
].base
,
1498 memmap
[VIRT_PCIE_MMIO
].size
,
1499 virt_high_pcie_memmap
.base
,
1500 virt_high_pcie_memmap
.size
,
1501 memmap
[VIRT_PCIE_PIO
].base
,
1504 create_platform_bus(s
, mmio_irqchip
);
1506 serial_mm_init(system_memory
, memmap
[VIRT_UART0
].base
,
1507 0, qdev_get_gpio_in(mmio_irqchip
, UART0_IRQ
), 399193,
1508 serial_hd(0), DEVICE_LITTLE_ENDIAN
);
1510 sysbus_create_simple("goldfish_rtc", memmap
[VIRT_RTC
].base
,
1511 qdev_get_gpio_in(mmio_irqchip
, RTC_IRQ
));
1513 virt_flash_create(s
);
1515 for (i
= 0; i
< ARRAY_SIZE(s
->flash
); i
++) {
1516 /* Map legacy -drive if=pflash to machine properties */
1517 pflash_cfi01_legacy_drive(s
->flash
[i
],
1518 drive_get(IF_PFLASH
, 0, i
));
1520 virt_flash_map(s
, system_memory
);
1522 /* load/create device tree */
1524 machine
->fdt
= load_device_tree(machine
->dtb
, &s
->fdt_size
);
1525 if (!machine
->fdt
) {
1526 error_report("load_device_tree() failed");
1530 create_fdt(s
, memmap
);
1533 s
->machine_done
.notify
= virt_machine_done
;
1534 qemu_add_machine_init_done_notifier(&s
->machine_done
);
1537 static void virt_machine_instance_init(Object
*obj
)
1539 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1541 s
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
1542 s
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
1543 s
->acpi
= ON_OFF_AUTO_AUTO
;
1546 static char *virt_get_aia_guests(Object
*obj
, Error
**errp
)
1548 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1551 sprintf(val
, "%d", s
->aia_guests
);
1552 return g_strdup(val
);
1555 static void virt_set_aia_guests(Object
*obj
, const char *val
, Error
**errp
)
1557 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1559 s
->aia_guests
= atoi(val
);
1560 if (s
->aia_guests
< 0 || s
->aia_guests
> VIRT_IRQCHIP_MAX_GUESTS
) {
1561 error_setg(errp
, "Invalid number of AIA IMSIC guests");
1562 error_append_hint(errp
, "Valid values be between 0 and %d.\n",
1563 VIRT_IRQCHIP_MAX_GUESTS
);
1567 static char *virt_get_aia(Object
*obj
, Error
**errp
)
1569 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1572 switch (s
->aia_type
) {
1573 case VIRT_AIA_TYPE_APLIC
:
1576 case VIRT_AIA_TYPE_APLIC_IMSIC
:
1577 val
= "aplic-imsic";
1584 return g_strdup(val
);
1587 static void virt_set_aia(Object
*obj
, const char *val
, Error
**errp
)
1589 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1591 if (!strcmp(val
, "none")) {
1592 s
->aia_type
= VIRT_AIA_TYPE_NONE
;
1593 } else if (!strcmp(val
, "aplic")) {
1594 s
->aia_type
= VIRT_AIA_TYPE_APLIC
;
1595 } else if (!strcmp(val
, "aplic-imsic")) {
1596 s
->aia_type
= VIRT_AIA_TYPE_APLIC_IMSIC
;
1598 error_setg(errp
, "Invalid AIA interrupt controller type");
1599 error_append_hint(errp
, "Valid values are none, aplic, and "
1604 static bool virt_get_aclint(Object
*obj
, Error
**errp
)
1606 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1608 return s
->have_aclint
;
1611 static void virt_set_aclint(Object
*obj
, bool value
, Error
**errp
)
1613 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1615 s
->have_aclint
= value
;
1618 bool virt_is_acpi_enabled(RISCVVirtState
*s
)
1620 return s
->acpi
!= ON_OFF_AUTO_OFF
;
1623 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
1624 void *opaque
, Error
**errp
)
1626 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1627 OnOffAuto acpi
= s
->acpi
;
1629 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
1632 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
1633 void *opaque
, Error
**errp
)
1635 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1637 visit_type_OnOffAuto(v
, name
, &s
->acpi
, errp
);
1640 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
1643 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1645 if (device_is_dynamic_sysbus(mc
, dev
)) {
1646 return HOTPLUG_HANDLER(machine
);
1651 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
1652 DeviceState
*dev
, Error
**errp
)
1654 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(hotplug_dev
);
1656 if (s
->platform_bus_dev
) {
1657 MachineClass
*mc
= MACHINE_GET_CLASS(s
);
1659 if (device_is_dynamic_sysbus(mc
, dev
)) {
1660 platform_bus_link_device(PLATFORM_BUS_DEVICE(s
->platform_bus_dev
),
1661 SYS_BUS_DEVICE(dev
));
1666 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1669 MachineClass
*mc
= MACHINE_CLASS(oc
);
1670 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
1672 mc
->desc
= "RISC-V VirtIO board";
1673 mc
->init
= virt_machine_init
;
1674 mc
->max_cpus
= VIRT_CPUS_MAX
;
1675 mc
->default_cpu_type
= TYPE_RISCV_CPU_BASE
;
1676 mc
->pci_allow_0_address
= true;
1677 mc
->possible_cpu_arch_ids
= riscv_numa_possible_cpu_arch_ids
;
1678 mc
->cpu_index_to_instance_props
= riscv_numa_cpu_index_to_props
;
1679 mc
->get_default_cpu_node_id
= riscv_numa_get_default_cpu_node_id
;
1680 mc
->numa_mem_supported
= true;
1681 mc
->default_ram_id
= "riscv_virt_board.ram";
1682 assert(!mc
->get_hotplug_handler
);
1683 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
1685 hc
->plug
= virt_machine_device_plug_cb
;
1687 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
1689 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
1692 object_class_property_add_bool(oc
, "aclint", virt_get_aclint
,
1694 object_class_property_set_description(oc
, "aclint",
1695 "Set on/off to enable/disable "
1696 "emulating ACLINT devices");
1698 object_class_property_add_str(oc
, "aia", virt_get_aia
,
1700 object_class_property_set_description(oc
, "aia",
1701 "Set type of AIA interrupt "
1702 "conttoller. Valid values are "
1703 "none, aplic, and aplic-imsic.");
1705 object_class_property_add_str(oc
, "aia-guests",
1706 virt_get_aia_guests
,
1707 virt_set_aia_guests
);
1708 sprintf(str
, "Set number of guest MMIO pages for AIA IMSIC. Valid value "
1709 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS
);
1710 object_class_property_set_description(oc
, "aia-guests", str
);
1711 object_class_property_add(oc
, "acpi", "OnOffAuto",
1712 virt_get_acpi
, virt_set_acpi
,
1714 object_class_property_set_description(oc
, "acpi",
1718 static const TypeInfo virt_machine_typeinfo
= {
1719 .name
= MACHINE_TYPE_NAME("virt"),
1720 .parent
= TYPE_MACHINE
,
1721 .class_init
= virt_machine_class_init
,
1722 .instance_init
= virt_machine_instance_init
,
1723 .instance_size
= sizeof(RISCVVirtState
),
1724 .interfaces
= (InterfaceInfo
[]) {
1725 { TYPE_HOTPLUG_HANDLER
},
1730 static void virt_machine_init_register_types(void)
1732 type_register_static(&virt_machine_typeinfo
);
1735 type_init(virt_machine_init_register_types
)