2 * QEMU RTL8139 emulation
4 * Copyright (c) 2006 Igor Kovalenko
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
48 /* debug RTL8139 card */
49 //#define DEBUG_RTL8139 1
51 #define PCI_FREQUENCY 33000000L
53 /* debug RTL8139 card C+ mode only */
54 //#define DEBUG_RTL8139CP 1
56 /* RTL8139 provides frame CRC with received packet, this feature seems to be
57 ignored by most drivers, disabled by default */
58 //#define RTL8139_CALCULATE_RXCRC 1
60 /* Uncomment to enable on-board timer interrupts */
61 //#define RTL8139_ONBOARD_TIMER 1
63 #if defined(RTL8139_CALCULATE_RXCRC)
68 #define SET_MASKED(input, mask, curr) \
69 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
71 /* arg % size for size which is a power of 2 */
72 #define MOD2(input, size) \
73 ( ( input ) & ( size - 1 ) )
75 #if defined (DEBUG_RTL8139)
76 # define DEBUG_PRINT(x) do { printf x ; } while (0)
78 # define DEBUG_PRINT(x)
81 /* Symbolic offsets to registers. */
82 enum RTL8139_registers
{
83 MAC0
= 0, /* Ethernet hardware address. */
84 MAR0
= 8, /* Multicast filter. */
85 TxStatus0
= 0x10,/* Transmit status (Four 32bit registers). C mode only */
86 /* Dump Tally Conter control register(64bit). C+ mode only */
87 TxAddr0
= 0x20, /* Tx descriptors (also four 32bit). */
96 Timer
= 0x48, /* A general-purpose counter. */
97 RxMissed
= 0x4C, /* 24 bits valid, write clears. */
104 Config4
= 0x5A, /* absent on RTL-8139A */
107 PCIRevisionID
= 0x5E,
108 TxSummary
= 0x60, /* TSAD register. Transmit Status of All Descriptors*/
109 BasicModeCtrl
= 0x62,
110 BasicModeStatus
= 0x64,
113 NWayExpansion
= 0x6A,
114 /* Undocumented registers, but required for proper operation. */
115 FIFOTMS
= 0x70, /* FIFO Control and test. */
116 CSCR
= 0x74, /* Chip Status and Configuration Register. */
118 PARA7c
= 0x7c, /* Magic transceiver parameter register. */
119 Config5
= 0xD8, /* absent on RTL-8139A */
121 TxPoll
= 0xD9, /* Tell chip to check Tx descriptors for work */
122 RxMaxSize
= 0xDA, /* Max size of an Rx packet (8169 only) */
123 CpCmd
= 0xE0, /* C+ Command register (C+ mode only) */
124 IntrMitigate
= 0xE2, /* rx/tx interrupt mitigation control */
125 RxRingAddrLO
= 0xE4, /* 64-bit start addr of Rx ring */
126 RxRingAddrHI
= 0xE8, /* 64-bit start addr of Rx ring */
127 TxThresh
= 0xEC, /* Early Tx threshold */
131 MultiIntrClear
= 0xF000,
133 Config1Clear
= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
145 CPlusRxVLAN
= 0x0040, /* enable receive VLAN detagging */
146 CPlusRxChkSum
= 0x0020, /* enable receive checksum offloading */
151 /* Interrupt register bits, using my own meaningful names. */
152 enum IntrStatusBits
{
163 RxAckBits
= RxFIFOOver
| RxOverflow
| RxOK
,
170 TxOutOfWindow
= 0x20000000,
171 TxAborted
= 0x40000000,
172 TxCarrierLost
= 0x80000000,
175 RxMulticast
= 0x8000,
177 RxBroadcast
= 0x2000,
178 RxBadSymbol
= 0x0020,
186 /* Bits in RxConfig. */
190 AcceptBroadcast
= 0x08,
191 AcceptMulticast
= 0x04,
193 AcceptAllPhys
= 0x01,
196 /* Bits in TxConfig. */
197 enum tx_config_bits
{
199 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
201 TxIFG84
= (0 << TxIFGShift
), /* 8.4us / 840ns (10 / 100Mbps) */
202 TxIFG88
= (1 << TxIFGShift
), /* 8.8us / 880ns (10 / 100Mbps) */
203 TxIFG92
= (2 << TxIFGShift
), /* 9.2us / 920ns (10 / 100Mbps) */
204 TxIFG96
= (3 << TxIFGShift
), /* 9.6us / 960ns (10 / 100Mbps) */
206 TxLoopBack
= (1 << 18) | (1 << 17), /* enable loopback test mode */
207 TxCRC
= (1 << 16), /* DISABLE appending CRC to end of Tx packets */
208 TxClearAbt
= (1 << 0), /* Clear abort (WO) */
209 TxDMAShift
= 8, /* DMA burst value (0-7) is shifted this many bits */
210 TxRetryShift
= 4, /* TXRR value (0-15) is shifted this many bits */
212 TxVersionMask
= 0x7C800000, /* mask out version bits 30-26, 23 */
216 /* Transmit Status of All Descriptors (TSAD) Register */
218 TSAD_TOK3
= 1<<15, // TOK bit of Descriptor 3
219 TSAD_TOK2
= 1<<14, // TOK bit of Descriptor 2
220 TSAD_TOK1
= 1<<13, // TOK bit of Descriptor 1
221 TSAD_TOK0
= 1<<12, // TOK bit of Descriptor 0
222 TSAD_TUN3
= 1<<11, // TUN bit of Descriptor 3
223 TSAD_TUN2
= 1<<10, // TUN bit of Descriptor 2
224 TSAD_TUN1
= 1<<9, // TUN bit of Descriptor 1
225 TSAD_TUN0
= 1<<8, // TUN bit of Descriptor 0
226 TSAD_TABT3
= 1<<07, // TABT bit of Descriptor 3
227 TSAD_TABT2
= 1<<06, // TABT bit of Descriptor 2
228 TSAD_TABT1
= 1<<05, // TABT bit of Descriptor 1
229 TSAD_TABT0
= 1<<04, // TABT bit of Descriptor 0
230 TSAD_OWN3
= 1<<03, // OWN bit of Descriptor 3
231 TSAD_OWN2
= 1<<02, // OWN bit of Descriptor 2
232 TSAD_OWN1
= 1<<01, // OWN bit of Descriptor 1
233 TSAD_OWN0
= 1<<00, // OWN bit of Descriptor 0
237 /* Bits in Config1 */
239 Cfg1_PM_Enable
= 0x01,
240 Cfg1_VPD_Enable
= 0x02,
243 LWAKE
= 0x10, /* not on 8139, 8139A */
244 Cfg1_Driver_Load
= 0x20,
247 SLEEP
= (1 << 1), /* only on 8139, 8139A */
248 PWRDN
= (1 << 0), /* only on 8139, 8139A */
251 /* Bits in Config3 */
253 Cfg3_FBtBEn
= (1 << 0), /* 1 = Fast Back to Back */
254 Cfg3_FuncRegEn
= (1 << 1), /* 1 = enable CardBus Function registers */
255 Cfg3_CLKRUN_En
= (1 << 2), /* 1 = enable CLKRUN */
256 Cfg3_CardB_En
= (1 << 3), /* 1 = enable CardBus registers */
257 Cfg3_LinkUp
= (1 << 4), /* 1 = wake up on link up */
258 Cfg3_Magic
= (1 << 5), /* 1 = wake up on Magic Packet (tm) */
259 Cfg3_PARM_En
= (1 << 6), /* 0 = software can set twister parameters */
260 Cfg3_GNTSel
= (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
263 /* Bits in Config4 */
265 LWPTN
= (1 << 2), /* not on 8139, 8139A */
268 /* Bits in Config5 */
270 Cfg5_PME_STS
= (1 << 0), /* 1 = PCI reset resets PME_Status */
271 Cfg5_LANWake
= (1 << 1), /* 1 = enable LANWake signal */
272 Cfg5_LDPS
= (1 << 2), /* 0 = save power when link is down */
273 Cfg5_FIFOAddrPtr
= (1 << 3), /* Realtek internal SRAM testing */
274 Cfg5_UWF
= (1 << 4), /* 1 = accept unicast wakeup frame */
275 Cfg5_MWF
= (1 << 5), /* 1 = accept multicast wakeup frame */
276 Cfg5_BWF
= (1 << 6), /* 1 = accept broadcast wakeup frame */
280 /* rx fifo threshold */
282 RxCfgFIFONone
= (7 << RxCfgFIFOShift
),
286 RxCfgDMAUnlimited
= (7 << RxCfgDMAShift
),
288 /* rx ring buffer length */
290 RxCfgRcv16K
= (1 << 11),
291 RxCfgRcv32K
= (1 << 12),
292 RxCfgRcv64K
= (1 << 11) | (1 << 12),
294 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
298 /* Twister tuning parameters from RealTek.
299 Completely undocumented, but required to tune bad links on some boards. */
302 CSCR_LinkOKBit = 0x0400,
303 CSCR_LinkChangeBit = 0x0800,
304 CSCR_LinkStatusBits = 0x0f000,
305 CSCR_LinkDownOffCmd = 0x003c0,
306 CSCR_LinkDownCmd = 0x0f3c0,
309 CSCR_Testfun
= 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
310 CSCR_LD
= 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
311 CSCR_HEART_BIT
= 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
312 CSCR_JBEN
= 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
313 CSCR_F_LINK_100
= 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
314 CSCR_F_Connect
= 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
315 CSCR_Con_status
= 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
316 CSCR_Con_status_En
= 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
317 CSCR_PASS_SCR
= 1<<0, /* Bypass Scramble, def 0*/
322 Cfg9346_Unlock
= 0xC0,
339 HasHltClk
= (1 << 0),
343 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
344 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
345 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
347 #define RTL8139_PCI_REVID_8139 0x10
348 #define RTL8139_PCI_REVID_8139CPLUS 0x20
350 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
352 /* Size is 64 * 16bit words */
353 #define EEPROM_9346_ADDR_BITS 6
354 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
355 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
357 enum Chip9346Operation
359 Chip9346_op_mask
= 0xc0, /* 10 zzzzzz */
360 Chip9346_op_read
= 0x80, /* 10 AAAAAA */
361 Chip9346_op_write
= 0x40, /* 01 AAAAAA D(15)..D(0) */
362 Chip9346_op_ext_mask
= 0xf0, /* 11 zzzzzz */
363 Chip9346_op_write_enable
= 0x30, /* 00 11zzzz */
364 Chip9346_op_write_all
= 0x10, /* 00 01zzzz */
365 Chip9346_op_write_disable
= 0x00, /* 00 00zzzz */
371 Chip9346_enter_command_mode
,
372 Chip9346_read_command
,
373 Chip9346_data_read
, /* from output register */
374 Chip9346_data_write
, /* to input register, then to contents at specified address */
375 Chip9346_data_write_all
, /* to input register, then filling contents */
378 typedef struct EEprom9346
380 uint16_t contents
[EEPROM_9346_SIZE
];
393 typedef struct RTL8139TallyCounters
409 } RTL8139TallyCounters
;
411 /* Clears all tally counters */
412 static void RTL8139TallyCounters_clear(RTL8139TallyCounters
* counters
);
414 /* Writes tally counters to specified physical memory address */
415 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr
, RTL8139TallyCounters
* counters
);
417 /* Loads values of tally counters from VM state file */
418 static void RTL8139TallyCounters_load(QEMUFile
* f
, RTL8139TallyCounters
*tally_counters
);
420 /* Saves values of tally counters to VM state file */
421 static void RTL8139TallyCounters_save(QEMUFile
* f
, RTL8139TallyCounters
*tally_counters
);
423 typedef struct RTL8139State
{
424 uint8_t phys
[8]; /* mac address */
425 uint8_t mult
[8]; /* multicast mask array */
427 uint32_t TxStatus
[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
428 uint32_t TxAddr
[4]; /* TxAddr0 */
429 uint32_t RxBuf
; /* Receive buffer */
430 uint32_t RxBufferSize
;/* internal variable, receive ring buffer size in C mode */
450 uint8_t clock_enabled
;
451 uint8_t bChipCmdState
;
455 uint16_t BasicModeCtrl
;
456 uint16_t BasicModeStatus
;
459 uint16_t NWayExpansion
;
467 int rtl8139_mmio_io_addr
;
473 uint32_t currCPlusRxDesc
;
474 uint32_t currCPlusTxDesc
;
476 uint32_t RxRingAddrLO
;
477 uint32_t RxRingAddrHI
;
486 RTL8139TallyCounters tally_counters
;
488 /* Non-persistent data */
489 uint8_t *cplus_txbuffer
;
490 int cplus_txbuffer_len
;
491 int cplus_txbuffer_offset
;
493 /* PCI interrupt timer */
498 void prom9346_decode_command(EEprom9346
*eeprom
, uint8_t command
)
500 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command
));
502 switch (command
& Chip9346_op_mask
)
504 case Chip9346_op_read
:
506 eeprom
->address
= command
& EEPROM_9346_ADDR_MASK
;
507 eeprom
->output
= eeprom
->contents
[eeprom
->address
];
510 eeprom
->mode
= Chip9346_data_read
;
511 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
512 eeprom
->address
, eeprom
->output
));
516 case Chip9346_op_write
:
518 eeprom
->address
= command
& EEPROM_9346_ADDR_MASK
;
521 eeprom
->mode
= Chip9346_none
; /* Chip9346_data_write */
522 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
527 eeprom
->mode
= Chip9346_none
;
528 switch (command
& Chip9346_op_ext_mask
)
530 case Chip9346_op_write_enable
:
531 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
533 case Chip9346_op_write_all
:
534 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
536 case Chip9346_op_write_disable
:
537 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
544 void prom9346_shift_clock(EEprom9346
*eeprom
)
546 int bit
= eeprom
->eedi
?1:0;
550 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom
->tick
, eeprom
->eedi
, eeprom
->eedo
));
552 switch (eeprom
->mode
)
554 case Chip9346_enter_command_mode
:
557 eeprom
->mode
= Chip9346_read_command
;
560 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
564 case Chip9346_read_command
:
565 eeprom
->input
= (eeprom
->input
<< 1) | (bit
& 1);
566 if (eeprom
->tick
== 8)
568 prom9346_decode_command(eeprom
, eeprom
->input
& 0xff);
572 case Chip9346_data_read
:
573 eeprom
->eedo
= (eeprom
->output
& 0x8000)?1:0;
574 eeprom
->output
<<= 1;
575 if (eeprom
->tick
== 16)
578 // the FreeBSD drivers (rl and re) don't explicitly toggle
579 // CS between reads (or does setting Cfg9346 to 0 count too?),
580 // so we need to enter wait-for-command state here
581 eeprom
->mode
= Chip9346_enter_command_mode
;
585 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
587 // original behaviour
589 eeprom
->address
&= EEPROM_9346_ADDR_MASK
;
590 eeprom
->output
= eeprom
->contents
[eeprom
->address
];
593 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
594 eeprom
->address
, eeprom
->output
));
599 case Chip9346_data_write
:
600 eeprom
->input
= (eeprom
->input
<< 1) | (bit
& 1);
601 if (eeprom
->tick
== 16)
603 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
604 eeprom
->address
, eeprom
->input
));
606 eeprom
->contents
[eeprom
->address
] = eeprom
->input
;
607 eeprom
->mode
= Chip9346_none
; /* waiting for next command after CS cycle */
613 case Chip9346_data_write_all
:
614 eeprom
->input
= (eeprom
->input
<< 1) | (bit
& 1);
615 if (eeprom
->tick
== 16)
618 for (i
= 0; i
< EEPROM_9346_SIZE
; i
++)
620 eeprom
->contents
[i
] = eeprom
->input
;
622 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
625 eeprom
->mode
= Chip9346_enter_command_mode
;
636 int prom9346_get_wire(RTL8139State
*s
)
638 EEprom9346
*eeprom
= &s
->eeprom
;
645 void prom9346_set_wire(RTL8139State
*s
, int eecs
, int eesk
, int eedi
)
647 EEprom9346
*eeprom
= &s
->eeprom
;
648 uint8_t old_eecs
= eeprom
->eecs
;
649 uint8_t old_eesk
= eeprom
->eesk
;
655 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
656 eeprom
->eecs
, eeprom
->eesk
, eeprom
->eedi
, eeprom
->eedo
));
658 if (!old_eecs
&& eecs
)
660 /* Synchronize start */
664 eeprom
->mode
= Chip9346_enter_command_mode
;
666 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
671 DEBUG_PRINT(("=== eeprom: end access\n"));
675 if (!old_eesk
&& eesk
)
678 prom9346_shift_clock(eeprom
);
682 static void rtl8139_update_irq(RTL8139State
*s
)
685 isr
= (s
->IntrStatus
& s
->IntrMask
) & 0xffff;
687 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
688 isr
? 1 : 0, s
->IntrStatus
, s
->IntrMask
));
690 qemu_set_irq(s
->pci_dev
->irq
[0], (isr
!= 0));
693 #define POLYNOMIAL 0x04c11db6
697 static int compute_mcast_idx(const uint8_t *ep
)
704 for (i
= 0; i
< 6; i
++) {
706 for (j
= 0; j
< 8; j
++) {
707 carry
= ((crc
& 0x80000000L
) ? 1 : 0) ^ (b
& 0x01);
711 crc
= ((crc
^ POLYNOMIAL
) | carry
);
717 static int rtl8139_RxWrap(RTL8139State
*s
)
719 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
720 return (s
->RxConfig
& (1 << 7));
723 static int rtl8139_receiver_enabled(RTL8139State
*s
)
725 return s
->bChipCmdState
& CmdRxEnb
;
728 static int rtl8139_transmitter_enabled(RTL8139State
*s
)
730 return s
->bChipCmdState
& CmdTxEnb
;
733 static int rtl8139_cp_receiver_enabled(RTL8139State
*s
)
735 return s
->CpCmd
& CPlusRxEnb
;
738 static int rtl8139_cp_transmitter_enabled(RTL8139State
*s
)
740 return s
->CpCmd
& CPlusTxEnb
;
743 static void rtl8139_write_buffer(RTL8139State
*s
, const void *buf
, int size
)
745 if (s
->RxBufAddr
+ size
> s
->RxBufferSize
)
747 int wrapped
= MOD2(s
->RxBufAddr
+ size
, s
->RxBufferSize
);
749 /* write packet data */
750 if (wrapped
&& s
->RxBufferSize
< 65536 && !rtl8139_RxWrap(s
))
752 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size
-wrapped
));
756 cpu_physical_memory_write( s
->RxBuf
+ s
->RxBufAddr
,
760 /* reset buffer pointer */
763 cpu_physical_memory_write( s
->RxBuf
+ s
->RxBufAddr
,
764 buf
+ (size
-wrapped
), wrapped
);
766 s
->RxBufAddr
= wrapped
;
772 /* non-wrapping path or overwrapping enabled */
773 cpu_physical_memory_write( s
->RxBuf
+ s
->RxBufAddr
, buf
, size
);
775 s
->RxBufAddr
+= size
;
778 #define MIN_BUF_SIZE 60
779 static inline target_phys_addr_t
rtl8139_addr64(uint32_t low
, uint32_t high
)
781 #if TARGET_PHYS_ADDR_BITS > 32
782 return low
| ((target_phys_addr_t
)high
<< 32);
788 static int rtl8139_can_receive(void *opaque
)
790 RTL8139State
*s
= opaque
;
793 /* Recieve (drop) packets if card is disabled. */
794 if (!s
->clock_enabled
)
796 if (!rtl8139_receiver_enabled(s
))
799 if (rtl8139_cp_receiver_enabled(s
)) {
800 /* ??? Flow control not implemented in c+ mode.
801 This is a hack to work around slirp deficiencies anyway. */
804 avail
= MOD2(s
->RxBufferSize
+ s
->RxBufPtr
- s
->RxBufAddr
,
806 return (avail
== 0 || avail
>= 1514);
810 static void rtl8139_do_receive(void *opaque
, const uint8_t *buf
, int size
, int do_interrupt
)
812 RTL8139State
*s
= opaque
;
814 uint32_t packet_header
= 0;
817 static const uint8_t broadcast_macaddr
[6] =
818 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
820 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size
));
822 /* test if board clock is stopped */
823 if (!s
->clock_enabled
)
825 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
829 /* first check if receiver is enabled */
831 if (!rtl8139_receiver_enabled(s
))
833 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
837 /* XXX: check this */
838 if (s
->RxConfig
& AcceptAllPhys
) {
839 /* promiscuous: receive all */
840 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
843 if (!memcmp(buf
, broadcast_macaddr
, 6)) {
844 /* broadcast address */
845 if (!(s
->RxConfig
& AcceptBroadcast
))
847 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
849 /* update tally counter */
850 ++s
->tally_counters
.RxERR
;
855 packet_header
|= RxBroadcast
;
857 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
859 /* update tally counter */
860 ++s
->tally_counters
.RxOkBrd
;
862 } else if (buf
[0] & 0x01) {
864 if (!(s
->RxConfig
& AcceptMulticast
))
866 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
868 /* update tally counter */
869 ++s
->tally_counters
.RxERR
;
874 int mcast_idx
= compute_mcast_idx(buf
);
876 if (!(s
->mult
[mcast_idx
>> 3] & (1 << (mcast_idx
& 7))))
878 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
880 /* update tally counter */
881 ++s
->tally_counters
.RxERR
;
886 packet_header
|= RxMulticast
;
888 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
890 /* update tally counter */
891 ++s
->tally_counters
.RxOkMul
;
893 } else if (s
->phys
[0] == buf
[0] &&
894 s
->phys
[1] == buf
[1] &&
895 s
->phys
[2] == buf
[2] &&
896 s
->phys
[3] == buf
[3] &&
897 s
->phys
[4] == buf
[4] &&
898 s
->phys
[5] == buf
[5]) {
900 if (!(s
->RxConfig
& AcceptMyPhys
))
902 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
904 /* update tally counter */
905 ++s
->tally_counters
.RxERR
;
910 packet_header
|= RxPhysical
;
912 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
914 /* update tally counter */
915 ++s
->tally_counters
.RxOkPhy
;
919 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
921 /* update tally counter */
922 ++s
->tally_counters
.RxERR
;
928 /* if too small buffer, then expand it */
929 if (size
< MIN_BUF_SIZE
) {
930 memcpy(buf1
, buf
, size
);
931 memset(buf1
+ size
, 0, MIN_BUF_SIZE
- size
);
936 if (rtl8139_cp_receiver_enabled(s
))
938 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
940 /* begin C+ receiver mode */
942 /* w0 ownership flag */
943 #define CP_RX_OWN (1<<31)
944 /* w0 end of ring flag */
945 #define CP_RX_EOR (1<<30)
946 /* w0 bits 0...12 : buffer size */
947 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
948 /* w1 tag available flag */
949 #define CP_RX_TAVA (1<<16)
950 /* w1 bits 0...15 : VLAN tag */
951 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
952 /* w2 low 32bit of Rx buffer ptr */
953 /* w3 high 32bit of Rx buffer ptr */
955 int descriptor
= s
->currCPlusRxDesc
;
956 target_phys_addr_t cplus_rx_ring_desc
;
958 cplus_rx_ring_desc
= rtl8139_addr64(s
->RxRingAddrLO
, s
->RxRingAddrHI
);
959 cplus_rx_ring_desc
+= 16 * descriptor
;
961 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64
"\n",
962 descriptor
, s
->RxRingAddrHI
, s
->RxRingAddrLO
, (uint64_t)cplus_rx_ring_desc
));
964 uint32_t val
, rxdw0
,rxdw1
,rxbufLO
,rxbufHI
;
966 cpu_physical_memory_read(cplus_rx_ring_desc
, (uint8_t *)&val
, 4);
967 rxdw0
= le32_to_cpu(val
);
968 cpu_physical_memory_read(cplus_rx_ring_desc
+4, (uint8_t *)&val
, 4);
969 rxdw1
= le32_to_cpu(val
);
970 cpu_physical_memory_read(cplus_rx_ring_desc
+8, (uint8_t *)&val
, 4);
971 rxbufLO
= le32_to_cpu(val
);
972 cpu_physical_memory_read(cplus_rx_ring_desc
+12, (uint8_t *)&val
, 4);
973 rxbufHI
= le32_to_cpu(val
);
975 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
977 rxdw0
, rxdw1
, rxbufLO
, rxbufHI
));
979 if (!(rxdw0
& CP_RX_OWN
))
981 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor
));
983 s
->IntrStatus
|= RxOverflow
;
986 /* update tally counter */
987 ++s
->tally_counters
.RxERR
;
988 ++s
->tally_counters
.MissPkt
;
990 rtl8139_update_irq(s
);
994 uint32_t rx_space
= rxdw0
& CP_RX_BUFFER_SIZE_MASK
;
996 /* TODO: scatter the packet over available receive ring descriptors space */
998 if (size
+4 > rx_space
)
1000 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1001 descriptor
, rx_space
, size
));
1003 s
->IntrStatus
|= RxOverflow
;
1006 /* update tally counter */
1007 ++s
->tally_counters
.RxERR
;
1008 ++s
->tally_counters
.MissPkt
;
1010 rtl8139_update_irq(s
);
1014 target_phys_addr_t rx_addr
= rtl8139_addr64(rxbufLO
, rxbufHI
);
1016 /* receive/copy to target memory */
1017 cpu_physical_memory_write( rx_addr
, buf
, size
);
1019 if (s
->CpCmd
& CPlusRxChkSum
)
1021 /* do some packet checksumming */
1024 /* write checksum */
1025 #if defined (RTL8139_CALCULATE_RXCRC)
1026 val
= cpu_to_le32(crc32(~0, buf
, size
));
1030 cpu_physical_memory_write( rx_addr
+size
, (uint8_t *)&val
, 4);
1032 /* first segment of received packet flag */
1033 #define CP_RX_STATUS_FS (1<<29)
1034 /* last segment of received packet flag */
1035 #define CP_RX_STATUS_LS (1<<28)
1036 /* multicast packet flag */
1037 #define CP_RX_STATUS_MAR (1<<26)
1038 /* physical-matching packet flag */
1039 #define CP_RX_STATUS_PAM (1<<25)
1040 /* broadcast packet flag */
1041 #define CP_RX_STATUS_BAR (1<<24)
1042 /* runt packet flag */
1043 #define CP_RX_STATUS_RUNT (1<<19)
1044 /* crc error flag */
1045 #define CP_RX_STATUS_CRC (1<<18)
1046 /* IP checksum error flag */
1047 #define CP_RX_STATUS_IPF (1<<15)
1048 /* UDP checksum error flag */
1049 #define CP_RX_STATUS_UDPF (1<<14)
1050 /* TCP checksum error flag */
1051 #define CP_RX_STATUS_TCPF (1<<13)
1053 /* transfer ownership to target */
1054 rxdw0
&= ~CP_RX_OWN
;
1056 /* set first segment bit */
1057 rxdw0
|= CP_RX_STATUS_FS
;
1059 /* set last segment bit */
1060 rxdw0
|= CP_RX_STATUS_LS
;
1062 /* set received packet type flags */
1063 if (packet_header
& RxBroadcast
)
1064 rxdw0
|= CP_RX_STATUS_BAR
;
1065 if (packet_header
& RxMulticast
)
1066 rxdw0
|= CP_RX_STATUS_MAR
;
1067 if (packet_header
& RxPhysical
)
1068 rxdw0
|= CP_RX_STATUS_PAM
;
1070 /* set received size */
1071 rxdw0
&= ~CP_RX_BUFFER_SIZE_MASK
;
1074 /* reset VLAN tag flag */
1075 rxdw1
&= ~CP_RX_TAVA
;
1077 /* update ring data */
1078 val
= cpu_to_le32(rxdw0
);
1079 cpu_physical_memory_write(cplus_rx_ring_desc
, (uint8_t *)&val
, 4);
1080 val
= cpu_to_le32(rxdw1
);
1081 cpu_physical_memory_write(cplus_rx_ring_desc
+4, (uint8_t *)&val
, 4);
1083 /* update tally counter */
1084 ++s
->tally_counters
.RxOk
;
1086 /* seek to next Rx descriptor */
1087 if (rxdw0
& CP_RX_EOR
)
1089 s
->currCPlusRxDesc
= 0;
1093 ++s
->currCPlusRxDesc
;
1096 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
1101 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1103 /* begin ring receiver mode */
1104 int avail
= MOD2(s
->RxBufferSize
+ s
->RxBufPtr
- s
->RxBufAddr
, s
->RxBufferSize
);
1106 /* if receiver buffer is empty then avail == 0 */
1108 if (avail
!= 0 && size
+ 8 >= avail
)
1110 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1111 s
->RxBufferSize
, s
->RxBufAddr
, s
->RxBufPtr
, avail
, size
+ 8));
1113 s
->IntrStatus
|= RxOverflow
;
1115 rtl8139_update_irq(s
);
1119 packet_header
|= RxStatusOK
;
1121 packet_header
|= (((size
+4) << 16) & 0xffff0000);
1124 uint32_t val
= cpu_to_le32(packet_header
);
1126 rtl8139_write_buffer(s
, (uint8_t *)&val
, 4);
1128 rtl8139_write_buffer(s
, buf
, size
);
1130 /* write checksum */
1131 #if defined (RTL8139_CALCULATE_RXCRC)
1132 val
= cpu_to_le32(crc32(~0, buf
, size
));
1137 rtl8139_write_buffer(s
, (uint8_t *)&val
, 4);
1139 /* correct buffer write pointer */
1140 s
->RxBufAddr
= MOD2((s
->RxBufAddr
+ 3) & ~0x3, s
->RxBufferSize
);
1142 /* now we can signal we have received something */
1144 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1145 s
->RxBufferSize
, s
->RxBufAddr
, s
->RxBufPtr
));
1148 s
->IntrStatus
|= RxOK
;
1152 rtl8139_update_irq(s
);
1156 static void rtl8139_receive(void *opaque
, const uint8_t *buf
, int size
)
1158 rtl8139_do_receive(opaque
, buf
, size
, 1);
1161 static void rtl8139_reset_rxring(RTL8139State
*s
, uint32_t bufferSize
)
1163 s
->RxBufferSize
= bufferSize
;
1168 static void rtl8139_reset(RTL8139State
*s
)
1172 /* restore MAC address */
1173 memcpy(s
->phys
, s
->macaddr
, 6);
1175 /* reset interrupt mask */
1179 rtl8139_update_irq(s
);
1181 /* prepare eeprom */
1182 s
->eeprom
.contents
[0] = 0x8129;
1184 // PCI vendor and device ID should be mirrored here
1185 s
->eeprom
.contents
[1] = 0x10ec;
1186 s
->eeprom
.contents
[2] = 0x8139;
1189 s
->eeprom
.contents
[7] = s
->macaddr
[0] | s
->macaddr
[1] << 8;
1190 s
->eeprom
.contents
[8] = s
->macaddr
[2] | s
->macaddr
[3] << 8;
1191 s
->eeprom
.contents
[9] = s
->macaddr
[4] | s
->macaddr
[5] << 8;
1193 /* mark all status registers as owned by host */
1194 for (i
= 0; i
< 4; ++i
)
1196 s
->TxStatus
[i
] = TxHostOwns
;
1200 s
->currCPlusRxDesc
= 0;
1201 s
->currCPlusTxDesc
= 0;
1203 s
->RxRingAddrLO
= 0;
1204 s
->RxRingAddrHI
= 0;
1208 rtl8139_reset_rxring(s
, 8192);
1214 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1215 s
->clock_enabled
= 0;
1217 s
->TxConfig
|= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1218 s
->clock_enabled
= 1;
1221 s
->bChipCmdState
= CmdReset
; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1223 /* set initial state data */
1224 s
->Config0
= 0x0; /* No boot ROM */
1225 s
->Config1
= 0xC; /* IO mapped and MEM mapped registers available */
1226 s
->Config3
= 0x1; /* fast back-to-back compatible */
1229 s
->CSCR
= CSCR_F_LINK_100
| CSCR_HEART_BIT
| CSCR_LD
;
1231 s
->CpCmd
= 0x0; /* reset C+ mode */
1233 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1234 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1235 s
->BasicModeCtrl
= 0x1000; // autonegotiation
1237 s
->BasicModeStatus
= 0x7809;
1238 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1239 s
->BasicModeStatus
|= 0x0020; /* autonegotiation completed */
1240 s
->BasicModeStatus
|= 0x0004; /* link is up */
1242 s
->NWayAdvert
= 0x05e1; /* all modes, full duplex */
1243 s
->NWayLPAR
= 0x05e1; /* all modes, full duplex */
1244 s
->NWayExpansion
= 0x0001; /* autonegotiation supported */
1246 /* also reset timer and disable timer interrupt */
1251 /* reset tally counters */
1252 RTL8139TallyCounters_clear(&s
->tally_counters
);
1255 void RTL8139TallyCounters_clear(RTL8139TallyCounters
* counters
)
1259 counters
->TxERR
= 0;
1260 counters
->RxERR
= 0;
1261 counters
->MissPkt
= 0;
1263 counters
->Tx1Col
= 0;
1264 counters
->TxMCol
= 0;
1265 counters
->RxOkPhy
= 0;
1266 counters
->RxOkBrd
= 0;
1267 counters
->RxOkMul
= 0;
1268 counters
->TxAbt
= 0;
1269 counters
->TxUndrn
= 0;
1272 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr
, RTL8139TallyCounters
* tally_counters
)
1278 val64
= cpu_to_le64(tally_counters
->TxOk
);
1279 cpu_physical_memory_write(tc_addr
+ 0, (uint8_t *)&val64
, 8);
1281 val64
= cpu_to_le64(tally_counters
->RxOk
);
1282 cpu_physical_memory_write(tc_addr
+ 8, (uint8_t *)&val64
, 8);
1284 val64
= cpu_to_le64(tally_counters
->TxERR
);
1285 cpu_physical_memory_write(tc_addr
+ 16, (uint8_t *)&val64
, 8);
1287 val32
= cpu_to_le32(tally_counters
->RxERR
);
1288 cpu_physical_memory_write(tc_addr
+ 24, (uint8_t *)&val32
, 4);
1290 val16
= cpu_to_le16(tally_counters
->MissPkt
);
1291 cpu_physical_memory_write(tc_addr
+ 28, (uint8_t *)&val16
, 2);
1293 val16
= cpu_to_le16(tally_counters
->FAE
);
1294 cpu_physical_memory_write(tc_addr
+ 30, (uint8_t *)&val16
, 2);
1296 val32
= cpu_to_le32(tally_counters
->Tx1Col
);
1297 cpu_physical_memory_write(tc_addr
+ 32, (uint8_t *)&val32
, 4);
1299 val32
= cpu_to_le32(tally_counters
->TxMCol
);
1300 cpu_physical_memory_write(tc_addr
+ 36, (uint8_t *)&val32
, 4);
1302 val64
= cpu_to_le64(tally_counters
->RxOkPhy
);
1303 cpu_physical_memory_write(tc_addr
+ 40, (uint8_t *)&val64
, 8);
1305 val64
= cpu_to_le64(tally_counters
->RxOkBrd
);
1306 cpu_physical_memory_write(tc_addr
+ 48, (uint8_t *)&val64
, 8);
1308 val32
= cpu_to_le32(tally_counters
->RxOkMul
);
1309 cpu_physical_memory_write(tc_addr
+ 56, (uint8_t *)&val32
, 4);
1311 val16
= cpu_to_le16(tally_counters
->TxAbt
);
1312 cpu_physical_memory_write(tc_addr
+ 60, (uint8_t *)&val16
, 2);
1314 val16
= cpu_to_le16(tally_counters
->TxUndrn
);
1315 cpu_physical_memory_write(tc_addr
+ 62, (uint8_t *)&val16
, 2);
1318 /* Loads values of tally counters from VM state file */
1319 static void RTL8139TallyCounters_load(QEMUFile
* f
, RTL8139TallyCounters
*tally_counters
)
1321 qemu_get_be64s(f
, &tally_counters
->TxOk
);
1322 qemu_get_be64s(f
, &tally_counters
->RxOk
);
1323 qemu_get_be64s(f
, &tally_counters
->TxERR
);
1324 qemu_get_be32s(f
, &tally_counters
->RxERR
);
1325 qemu_get_be16s(f
, &tally_counters
->MissPkt
);
1326 qemu_get_be16s(f
, &tally_counters
->FAE
);
1327 qemu_get_be32s(f
, &tally_counters
->Tx1Col
);
1328 qemu_get_be32s(f
, &tally_counters
->TxMCol
);
1329 qemu_get_be64s(f
, &tally_counters
->RxOkPhy
);
1330 qemu_get_be64s(f
, &tally_counters
->RxOkBrd
);
1331 qemu_get_be32s(f
, &tally_counters
->RxOkMul
);
1332 qemu_get_be16s(f
, &tally_counters
->TxAbt
);
1333 qemu_get_be16s(f
, &tally_counters
->TxUndrn
);
1336 /* Saves values of tally counters to VM state file */
1337 static void RTL8139TallyCounters_save(QEMUFile
* f
, RTL8139TallyCounters
*tally_counters
)
1339 qemu_put_be64s(f
, &tally_counters
->TxOk
);
1340 qemu_put_be64s(f
, &tally_counters
->RxOk
);
1341 qemu_put_be64s(f
, &tally_counters
->TxERR
);
1342 qemu_put_be32s(f
, &tally_counters
->RxERR
);
1343 qemu_put_be16s(f
, &tally_counters
->MissPkt
);
1344 qemu_put_be16s(f
, &tally_counters
->FAE
);
1345 qemu_put_be32s(f
, &tally_counters
->Tx1Col
);
1346 qemu_put_be32s(f
, &tally_counters
->TxMCol
);
1347 qemu_put_be64s(f
, &tally_counters
->RxOkPhy
);
1348 qemu_put_be64s(f
, &tally_counters
->RxOkBrd
);
1349 qemu_put_be32s(f
, &tally_counters
->RxOkMul
);
1350 qemu_put_be16s(f
, &tally_counters
->TxAbt
);
1351 qemu_put_be16s(f
, &tally_counters
->TxUndrn
);
1354 static void rtl8139_ChipCmd_write(RTL8139State
*s
, uint32_t val
)
1358 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val
));
1362 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
1367 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
1369 s
->currCPlusRxDesc
= 0;
1373 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
1375 s
->currCPlusTxDesc
= 0;
1378 /* mask unwriteable bits */
1379 val
= SET_MASKED(val
, 0xe3, s
->bChipCmdState
);
1381 /* Deassert reset pin before next read */
1384 s
->bChipCmdState
= val
;
1387 static int rtl8139_RxBufferEmpty(RTL8139State
*s
)
1389 int unread
= MOD2(s
->RxBufferSize
+ s
->RxBufAddr
- s
->RxBufPtr
, s
->RxBufferSize
);
1393 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread
));
1397 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
1402 static uint32_t rtl8139_ChipCmd_read(RTL8139State
*s
)
1404 uint32_t ret
= s
->bChipCmdState
;
1406 if (rtl8139_RxBufferEmpty(s
))
1409 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret
));
1414 static void rtl8139_CpCmd_write(RTL8139State
*s
, uint32_t val
)
1418 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val
));
1420 /* mask unwriteable bits */
1421 val
= SET_MASKED(val
, 0xff84, s
->CpCmd
);
1426 static uint32_t rtl8139_CpCmd_read(RTL8139State
*s
)
1428 uint32_t ret
= s
->CpCmd
;
1430 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret
));
1435 static void rtl8139_IntrMitigate_write(RTL8139State
*s
, uint32_t val
)
1437 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val
));
1440 static uint32_t rtl8139_IntrMitigate_read(RTL8139State
*s
)
1444 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret
));
1449 int rtl8139_config_writeable(RTL8139State
*s
)
1451 if (s
->Cfg9346
& Cfg9346_Unlock
)
1456 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
1461 static void rtl8139_BasicModeCtrl_write(RTL8139State
*s
, uint32_t val
)
1465 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val
));
1467 /* mask unwriteable bits */
1468 uint32 mask
= 0x4cff;
1470 if (1 || !rtl8139_config_writeable(s
))
1472 /* Speed setting and autonegotiation enable bits are read-only */
1474 /* Duplex mode setting is read-only */
1478 val
= SET_MASKED(val
, mask
, s
->BasicModeCtrl
);
1480 s
->BasicModeCtrl
= val
;
1483 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State
*s
)
1485 uint32_t ret
= s
->BasicModeCtrl
;
1487 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret
));
1492 static void rtl8139_BasicModeStatus_write(RTL8139State
*s
, uint32_t val
)
1496 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val
));
1498 /* mask unwriteable bits */
1499 val
= SET_MASKED(val
, 0xff3f, s
->BasicModeStatus
);
1501 s
->BasicModeStatus
= val
;
1504 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State
*s
)
1506 uint32_t ret
= s
->BasicModeStatus
;
1508 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret
));
1513 static void rtl8139_Cfg9346_write(RTL8139State
*s
, uint32_t val
)
1517 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val
));
1519 /* mask unwriteable bits */
1520 val
= SET_MASKED(val
, 0x31, s
->Cfg9346
);
1522 uint32_t opmode
= val
& 0xc0;
1523 uint32_t eeprom_val
= val
& 0xf;
1525 if (opmode
== 0x80) {
1527 int eecs
= (eeprom_val
& 0x08)?1:0;
1528 int eesk
= (eeprom_val
& 0x04)?1:0;
1529 int eedi
= (eeprom_val
& 0x02)?1:0;
1530 prom9346_set_wire(s
, eecs
, eesk
, eedi
);
1531 } else if (opmode
== 0x40) {
1540 static uint32_t rtl8139_Cfg9346_read(RTL8139State
*s
)
1542 uint32_t ret
= s
->Cfg9346
;
1544 uint32_t opmode
= ret
& 0xc0;
1549 int eedo
= prom9346_get_wire(s
);
1560 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret
));
1565 static void rtl8139_Config0_write(RTL8139State
*s
, uint32_t val
)
1569 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val
));
1571 if (!rtl8139_config_writeable(s
))
1574 /* mask unwriteable bits */
1575 val
= SET_MASKED(val
, 0xf8, s
->Config0
);
1580 static uint32_t rtl8139_Config0_read(RTL8139State
*s
)
1582 uint32_t ret
= s
->Config0
;
1584 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret
));
1589 static void rtl8139_Config1_write(RTL8139State
*s
, uint32_t val
)
1593 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val
));
1595 if (!rtl8139_config_writeable(s
))
1598 /* mask unwriteable bits */
1599 val
= SET_MASKED(val
, 0xC, s
->Config1
);
1604 static uint32_t rtl8139_Config1_read(RTL8139State
*s
)
1606 uint32_t ret
= s
->Config1
;
1608 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret
));
1613 static void rtl8139_Config3_write(RTL8139State
*s
, uint32_t val
)
1617 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val
));
1619 if (!rtl8139_config_writeable(s
))
1622 /* mask unwriteable bits */
1623 val
= SET_MASKED(val
, 0x8F, s
->Config3
);
1628 static uint32_t rtl8139_Config3_read(RTL8139State
*s
)
1630 uint32_t ret
= s
->Config3
;
1632 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret
));
1637 static void rtl8139_Config4_write(RTL8139State
*s
, uint32_t val
)
1641 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val
));
1643 if (!rtl8139_config_writeable(s
))
1646 /* mask unwriteable bits */
1647 val
= SET_MASKED(val
, 0x0a, s
->Config4
);
1652 static uint32_t rtl8139_Config4_read(RTL8139State
*s
)
1654 uint32_t ret
= s
->Config4
;
1656 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret
));
1661 static void rtl8139_Config5_write(RTL8139State
*s
, uint32_t val
)
1665 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val
));
1667 /* mask unwriteable bits */
1668 val
= SET_MASKED(val
, 0x80, s
->Config5
);
1673 static uint32_t rtl8139_Config5_read(RTL8139State
*s
)
1675 uint32_t ret
= s
->Config5
;
1677 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret
));
1682 static void rtl8139_TxConfig_write(RTL8139State
*s
, uint32_t val
)
1684 if (!rtl8139_transmitter_enabled(s
))
1686 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val
));
1690 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val
));
1692 val
= SET_MASKED(val
, TxVersionMask
| 0x8070f80f, s
->TxConfig
);
1697 static void rtl8139_TxConfig_writeb(RTL8139State
*s
, uint32_t val
)
1699 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val
));
1701 uint32_t tc
= s
->TxConfig
;
1703 tc
|= (val
& 0x000000FF);
1704 rtl8139_TxConfig_write(s
, tc
);
1707 static uint32_t rtl8139_TxConfig_read(RTL8139State
*s
)
1709 uint32_t ret
= s
->TxConfig
;
1711 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret
));
1716 static void rtl8139_RxConfig_write(RTL8139State
*s
, uint32_t val
)
1718 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val
));
1720 /* mask unwriteable bits */
1721 val
= SET_MASKED(val
, 0xf0fc0040, s
->RxConfig
);
1725 /* reset buffer size and read/write pointers */
1726 rtl8139_reset_rxring(s
, 8192 << ((s
->RxConfig
>> 11) & 0x3));
1728 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s
->RxBufferSize
));
1731 static uint32_t rtl8139_RxConfig_read(RTL8139State
*s
)
1733 uint32_t ret
= s
->RxConfig
;
1735 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret
));
1740 static void rtl8139_transfer_frame(RTL8139State
*s
, const uint8_t *buf
, int size
, int do_interrupt
)
1744 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1748 if (TxLoopBack
== (s
->TxConfig
& TxLoopBack
))
1750 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1751 rtl8139_do_receive(s
, buf
, size
, do_interrupt
);
1755 qemu_send_packet(s
->vc
, buf
, size
);
1759 static int rtl8139_transmit_one(RTL8139State
*s
, int descriptor
)
1761 if (!rtl8139_transmitter_enabled(s
))
1763 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1768 if (s
->TxStatus
[descriptor
] & TxHostOwns
)
1770 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1771 descriptor
, s
->TxStatus
[descriptor
]));
1775 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor
));
1777 int txsize
= s
->TxStatus
[descriptor
] & 0x1fff;
1778 uint8_t txbuffer
[0x2000];
1780 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1781 txsize
, s
->TxAddr
[descriptor
]));
1783 cpu_physical_memory_read(s
->TxAddr
[descriptor
], txbuffer
, txsize
);
1785 /* Mark descriptor as transferred */
1786 s
->TxStatus
[descriptor
] |= TxHostOwns
;
1787 s
->TxStatus
[descriptor
] |= TxStatOK
;
1789 rtl8139_transfer_frame(s
, txbuffer
, txsize
, 0);
1791 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize
, descriptor
));
1793 /* update interrupt */
1794 s
->IntrStatus
|= TxOK
;
1795 rtl8139_update_irq(s
);
1800 /* structures and macros for task offloading */
1801 typedef struct ip_header
1803 uint8_t ip_ver_len
; /* version and header length */
1804 uint8_t ip_tos
; /* type of service */
1805 uint16_t ip_len
; /* total length */
1806 uint16_t ip_id
; /* identification */
1807 uint16_t ip_off
; /* fragment offset field */
1808 uint8_t ip_ttl
; /* time to live */
1809 uint8_t ip_p
; /* protocol */
1810 uint16_t ip_sum
; /* checksum */
1811 uint32_t ip_src
,ip_dst
; /* source and dest address */
1814 #define IP_HEADER_VERSION_4 4
1815 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1816 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1818 typedef struct tcp_header
1820 uint16_t th_sport
; /* source port */
1821 uint16_t th_dport
; /* destination port */
1822 uint32_t th_seq
; /* sequence number */
1823 uint32_t th_ack
; /* acknowledgement number */
1824 uint16_t th_offset_flags
; /* data offset, reserved 6 bits, TCP protocol flags */
1825 uint16_t th_win
; /* window */
1826 uint16_t th_sum
; /* checksum */
1827 uint16_t th_urp
; /* urgent pointer */
1830 typedef struct udp_header
1832 uint16_t uh_sport
; /* source port */
1833 uint16_t uh_dport
; /* destination port */
1834 uint16_t uh_ulen
; /* udp length */
1835 uint16_t uh_sum
; /* udp checksum */
1838 typedef struct ip_pseudo_header
1844 uint16_t ip_payload
;
1847 #define IP_PROTO_TCP 6
1848 #define IP_PROTO_UDP 17
1850 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1851 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1852 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1854 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1856 #define TCP_FLAG_FIN 0x01
1857 #define TCP_FLAG_PUSH 0x08
1859 /* produces ones' complement sum of data */
1860 static uint16_t ones_complement_sum(uint8_t *data
, size_t len
)
1862 uint32_t result
= 0;
1864 for (; len
> 1; data
+=2, len
-=2)
1866 result
+= *(uint16_t*)data
;
1869 /* add the remainder byte */
1872 uint8_t odd
[2] = {*data
, 0};
1873 result
+= *(uint16_t*)odd
;
1877 result
= (result
& 0xffff) + (result
>> 16);
1882 static uint16_t ip_checksum(void *data
, size_t len
)
1884 return ~ones_complement_sum((uint8_t*)data
, len
);
1887 static int rtl8139_cplus_transmit_one(RTL8139State
*s
)
1889 if (!rtl8139_transmitter_enabled(s
))
1891 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
1895 if (!rtl8139_cp_transmitter_enabled(s
))
1897 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
1901 int descriptor
= s
->currCPlusTxDesc
;
1903 target_phys_addr_t cplus_tx_ring_desc
=
1904 rtl8139_addr64(s
->TxAddr
[0], s
->TxAddr
[1]);
1906 /* Normal priority ring */
1907 cplus_tx_ring_desc
+= 16 * descriptor
;
1909 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1910 descriptor
, s
->TxAddr
[1], s
->TxAddr
[0], cplus_tx_ring_desc
));
1912 uint32_t val
, txdw0
,txdw1
,txbufLO
,txbufHI
;
1914 cpu_physical_memory_read(cplus_tx_ring_desc
, (uint8_t *)&val
, 4);
1915 txdw0
= le32_to_cpu(val
);
1916 cpu_physical_memory_read(cplus_tx_ring_desc
+4, (uint8_t *)&val
, 4);
1917 txdw1
= le32_to_cpu(val
);
1918 cpu_physical_memory_read(cplus_tx_ring_desc
+8, (uint8_t *)&val
, 4);
1919 txbufLO
= le32_to_cpu(val
);
1920 cpu_physical_memory_read(cplus_tx_ring_desc
+12, (uint8_t *)&val
, 4);
1921 txbufHI
= le32_to_cpu(val
);
1923 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
1925 txdw0
, txdw1
, txbufLO
, txbufHI
));
1927 /* w0 ownership flag */
1928 #define CP_TX_OWN (1<<31)
1929 /* w0 end of ring flag */
1930 #define CP_TX_EOR (1<<30)
1931 /* first segment of received packet flag */
1932 #define CP_TX_FS (1<<29)
1933 /* last segment of received packet flag */
1934 #define CP_TX_LS (1<<28)
1935 /* large send packet flag */
1936 #define CP_TX_LGSEN (1<<27)
1937 /* large send MSS mask, bits 16...25 */
1938 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1940 /* IP checksum offload flag */
1941 #define CP_TX_IPCS (1<<18)
1942 /* UDP checksum offload flag */
1943 #define CP_TX_UDPCS (1<<17)
1944 /* TCP checksum offload flag */
1945 #define CP_TX_TCPCS (1<<16)
1947 /* w0 bits 0...15 : buffer size */
1948 #define CP_TX_BUFFER_SIZE (1<<16)
1949 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1950 /* w1 tag available flag */
1951 #define CP_RX_TAGC (1<<17)
1952 /* w1 bits 0...15 : VLAN tag */
1953 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1954 /* w2 low 32bit of Rx buffer ptr */
1955 /* w3 high 32bit of Rx buffer ptr */
1957 /* set after transmission */
1958 /* FIFO underrun flag */
1959 #define CP_TX_STATUS_UNF (1<<25)
1960 /* transmit error summary flag, valid if set any of three below */
1961 #define CP_TX_STATUS_TES (1<<23)
1962 /* out-of-window collision flag */
1963 #define CP_TX_STATUS_OWC (1<<22)
1964 /* link failure flag */
1965 #define CP_TX_STATUS_LNKF (1<<21)
1966 /* excessive collisions flag */
1967 #define CP_TX_STATUS_EXC (1<<20)
1969 if (!(txdw0
& CP_TX_OWN
))
1971 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor
));
1975 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor
));
1977 if (txdw0
& CP_TX_FS
)
1979 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor
));
1981 /* reset internal buffer offset */
1982 s
->cplus_txbuffer_offset
= 0;
1985 int txsize
= txdw0
& CP_TX_BUFFER_SIZE_MASK
;
1986 target_phys_addr_t tx_addr
= rtl8139_addr64(txbufLO
, txbufHI
);
1988 /* make sure we have enough space to assemble the packet */
1989 if (!s
->cplus_txbuffer
)
1991 s
->cplus_txbuffer_len
= CP_TX_BUFFER_SIZE
;
1992 s
->cplus_txbuffer
= malloc(s
->cplus_txbuffer_len
);
1993 s
->cplus_txbuffer_offset
= 0;
1995 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s
->cplus_txbuffer_len
));
1998 while (s
->cplus_txbuffer
&& s
->cplus_txbuffer_offset
+ txsize
>= s
->cplus_txbuffer_len
)
2000 s
->cplus_txbuffer_len
+= CP_TX_BUFFER_SIZE
;
2001 s
->cplus_txbuffer
= realloc(s
->cplus_txbuffer
, s
->cplus_txbuffer_len
);
2003 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s
->cplus_txbuffer_len
));
2006 if (!s
->cplus_txbuffer
)
2010 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s
->cplus_txbuffer_len
));
2012 /* update tally counter */
2013 ++s
->tally_counters
.TxERR
;
2014 ++s
->tally_counters
.TxAbt
;
2019 /* append more data to the packet */
2021 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64
" to offset %d\n",
2022 txsize
, (uint64_t)tx_addr
, s
->cplus_txbuffer_offset
));
2024 cpu_physical_memory_read(tx_addr
, s
->cplus_txbuffer
+ s
->cplus_txbuffer_offset
, txsize
);
2025 s
->cplus_txbuffer_offset
+= txsize
;
2027 /* seek to next Rx descriptor */
2028 if (txdw0
& CP_TX_EOR
)
2030 s
->currCPlusTxDesc
= 0;
2034 ++s
->currCPlusTxDesc
;
2035 if (s
->currCPlusTxDesc
>= 64)
2036 s
->currCPlusTxDesc
= 0;
2039 /* transfer ownership to target */
2040 txdw0
&= ~CP_RX_OWN
;
2042 /* reset error indicator bits */
2043 txdw0
&= ~CP_TX_STATUS_UNF
;
2044 txdw0
&= ~CP_TX_STATUS_TES
;
2045 txdw0
&= ~CP_TX_STATUS_OWC
;
2046 txdw0
&= ~CP_TX_STATUS_LNKF
;
2047 txdw0
&= ~CP_TX_STATUS_EXC
;
2049 /* update ring data */
2050 val
= cpu_to_le32(txdw0
);
2051 cpu_physical_memory_write(cplus_tx_ring_desc
, (uint8_t *)&val
, 4);
2052 // val = cpu_to_le32(txdw1);
2053 // cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2055 /* Now decide if descriptor being processed is holding the last segment of packet */
2056 if (txdw0
& CP_TX_LS
)
2058 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor
));
2060 /* can transfer fully assembled packet */
2062 uint8_t *saved_buffer
= s
->cplus_txbuffer
;
2063 int saved_size
= s
->cplus_txbuffer_offset
;
2064 int saved_buffer_len
= s
->cplus_txbuffer_len
;
2066 /* reset the card space to protect from recursive call */
2067 s
->cplus_txbuffer
= NULL
;
2068 s
->cplus_txbuffer_offset
= 0;
2069 s
->cplus_txbuffer_len
= 0;
2071 if (txdw0
& (CP_TX_IPCS
| CP_TX_UDPCS
| CP_TX_TCPCS
| CP_TX_LGSEN
))
2073 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2075 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2077 #define ETH_MTU 1500
2079 /* ip packet header */
2082 uint8_t ip_protocol
= 0;
2083 uint16_t ip_data_len
= 0;
2085 uint8_t *eth_payload_data
= 0;
2086 size_t eth_payload_len
= 0;
2088 int proto
= be16_to_cpu(*(uint16_t *)(saved_buffer
+ 12));
2089 if (proto
== ETH_P_IP
)
2091 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2094 eth_payload_data
= saved_buffer
+ ETH_HLEN
;
2095 eth_payload_len
= saved_size
- ETH_HLEN
;
2097 ip
= (ip_header
*)eth_payload_data
;
2099 if (IP_HEADER_VERSION(ip
) != IP_HEADER_VERSION_4
) {
2100 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip
), IP_HEADER_VERSION_4
));
2103 hlen
= IP_HEADER_LENGTH(ip
);
2104 ip_protocol
= ip
->ip_p
;
2105 ip_data_len
= be16_to_cpu(ip
->ip_len
) - hlen
;
2111 if (txdw0
& CP_TX_IPCS
)
2113 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2115 if (hlen
<sizeof(ip_header
) || hlen
>eth_payload_len
) {/* min header length */
2116 /* bad packet header len */
2117 /* or packet too short */
2122 ip
->ip_sum
= ip_checksum(ip
, hlen
);
2123 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen
, ip
->ip_sum
));
2127 if ((txdw0
& CP_TX_LGSEN
) && ip_protocol
== IP_PROTO_TCP
)
2129 #if defined (DEBUG_RTL8139)
2130 int large_send_mss
= (txdw0
>> 16) & CP_TC_LGSEN_MSS_MASK
;
2132 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2133 ETH_MTU
, ip_data_len
, saved_size
- ETH_HLEN
, large_send_mss
));
2135 int tcp_send_offset
= 0;
2138 /* maximum IP header length is 60 bytes */
2139 uint8_t saved_ip_header
[60];
2141 /* save IP header template; data area is used in tcp checksum calculation */
2142 memcpy(saved_ip_header
, eth_payload_data
, hlen
);
2144 /* a placeholder for checksum calculation routine in tcp case */
2145 uint8_t *data_to_checksum
= eth_payload_data
+ hlen
- 12;
2146 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2148 /* pointer to TCP header */
2149 tcp_header
*p_tcp_hdr
= (tcp_header
*)(eth_payload_data
+ hlen
);
2151 int tcp_hlen
= TCP_HEADER_DATA_OFFSET(p_tcp_hdr
);
2153 /* ETH_MTU = ip header len + tcp header len + payload */
2154 int tcp_data_len
= ip_data_len
- tcp_hlen
;
2155 int tcp_chunk_size
= ETH_MTU
- hlen
- tcp_hlen
;
2157 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2158 ip_data_len
, tcp_hlen
, tcp_data_len
, tcp_chunk_size
));
2160 /* note the cycle below overwrites IP header data,
2161 but restores it from saved_ip_header before sending packet */
2163 int is_last_frame
= 0;
2165 for (tcp_send_offset
= 0; tcp_send_offset
< tcp_data_len
; tcp_send_offset
+= tcp_chunk_size
)
2167 uint16_t chunk_size
= tcp_chunk_size
;
2169 /* check if this is the last frame */
2170 if (tcp_send_offset
+ tcp_chunk_size
>= tcp_data_len
)
2173 chunk_size
= tcp_data_len
- tcp_send_offset
;
2176 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr
->th_seq
)));
2178 /* add 4 TCP pseudoheader fields */
2179 /* copy IP source and destination fields */
2180 memcpy(data_to_checksum
, saved_ip_header
+ 12, 8);
2182 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen
+ chunk_size
));
2184 if (tcp_send_offset
)
2186 memcpy((uint8_t*)p_tcp_hdr
+ tcp_hlen
, (uint8_t*)p_tcp_hdr
+ tcp_hlen
+ tcp_send_offset
, chunk_size
);
2189 /* keep PUSH and FIN flags only for the last frame */
2192 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr
, TCP_FLAG_PUSH
|TCP_FLAG_FIN
);
2195 /* recalculate TCP checksum */
2196 ip_pseudo_header
*p_tcpip_hdr
= (ip_pseudo_header
*)data_to_checksum
;
2197 p_tcpip_hdr
->zeros
= 0;
2198 p_tcpip_hdr
->ip_proto
= IP_PROTO_TCP
;
2199 p_tcpip_hdr
->ip_payload
= cpu_to_be16(tcp_hlen
+ chunk_size
);
2201 p_tcp_hdr
->th_sum
= 0;
2203 int tcp_checksum
= ip_checksum(data_to_checksum
, tcp_hlen
+ chunk_size
+ 12);
2204 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum
));
2206 p_tcp_hdr
->th_sum
= tcp_checksum
;
2208 /* restore IP header */
2209 memcpy(eth_payload_data
, saved_ip_header
, hlen
);
2211 /* set IP data length and recalculate IP checksum */
2212 ip
->ip_len
= cpu_to_be16(hlen
+ tcp_hlen
+ chunk_size
);
2214 /* increment IP id for subsequent frames */
2215 ip
->ip_id
= cpu_to_be16(tcp_send_offset
/tcp_chunk_size
+ be16_to_cpu(ip
->ip_id
));
2218 ip
->ip_sum
= ip_checksum(eth_payload_data
, hlen
);
2219 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen
, ip
->ip_sum
));
2221 int tso_send_size
= ETH_HLEN
+ hlen
+ tcp_hlen
+ chunk_size
;
2222 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size
));
2223 rtl8139_transfer_frame(s
, saved_buffer
, tso_send_size
, 0);
2225 /* add transferred count to TCP sequence number */
2226 p_tcp_hdr
->th_seq
= cpu_to_be32(chunk_size
+ be32_to_cpu(p_tcp_hdr
->th_seq
));
2230 /* Stop sending this frame */
2233 else if (txdw0
& (CP_TX_TCPCS
|CP_TX_UDPCS
))
2235 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2237 /* maximum IP header length is 60 bytes */
2238 uint8_t saved_ip_header
[60];
2239 memcpy(saved_ip_header
, eth_payload_data
, hlen
);
2241 uint8_t *data_to_checksum
= eth_payload_data
+ hlen
- 12;
2242 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2244 /* add 4 TCP pseudoheader fields */
2245 /* copy IP source and destination fields */
2246 memcpy(data_to_checksum
, saved_ip_header
+ 12, 8);
2248 if ((txdw0
& CP_TX_TCPCS
) && ip_protocol
== IP_PROTO_TCP
)
2250 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len
));
2252 ip_pseudo_header
*p_tcpip_hdr
= (ip_pseudo_header
*)data_to_checksum
;
2253 p_tcpip_hdr
->zeros
= 0;
2254 p_tcpip_hdr
->ip_proto
= IP_PROTO_TCP
;
2255 p_tcpip_hdr
->ip_payload
= cpu_to_be16(ip_data_len
);
2257 tcp_header
* p_tcp_hdr
= (tcp_header
*) (data_to_checksum
+12);
2259 p_tcp_hdr
->th_sum
= 0;
2261 int tcp_checksum
= ip_checksum(data_to_checksum
, ip_data_len
+ 12);
2262 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum
));
2264 p_tcp_hdr
->th_sum
= tcp_checksum
;
2266 else if ((txdw0
& CP_TX_UDPCS
) && ip_protocol
== IP_PROTO_UDP
)
2268 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len
));
2270 ip_pseudo_header
*p_udpip_hdr
= (ip_pseudo_header
*)data_to_checksum
;
2271 p_udpip_hdr
->zeros
= 0;
2272 p_udpip_hdr
->ip_proto
= IP_PROTO_UDP
;
2273 p_udpip_hdr
->ip_payload
= cpu_to_be16(ip_data_len
);
2275 udp_header
*p_udp_hdr
= (udp_header
*) (data_to_checksum
+12);
2277 p_udp_hdr
->uh_sum
= 0;
2279 int udp_checksum
= ip_checksum(data_to_checksum
, ip_data_len
+ 12);
2280 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum
));
2282 p_udp_hdr
->uh_sum
= udp_checksum
;
2285 /* restore IP header */
2286 memcpy(eth_payload_data
, saved_ip_header
, hlen
);
2291 /* update tally counter */
2292 ++s
->tally_counters
.TxOk
;
2294 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size
));
2296 rtl8139_transfer_frame(s
, saved_buffer
, saved_size
, 1);
2298 /* restore card space if there was no recursion and reset offset */
2299 if (!s
->cplus_txbuffer
)
2301 s
->cplus_txbuffer
= saved_buffer
;
2302 s
->cplus_txbuffer_len
= saved_buffer_len
;
2303 s
->cplus_txbuffer_offset
= 0;
2312 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
2318 static void rtl8139_cplus_transmit(RTL8139State
*s
)
2322 while (rtl8139_cplus_transmit_one(s
))
2327 /* Mark transfer completed */
2330 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2331 s
->currCPlusTxDesc
));
2335 /* update interrupt status */
2336 s
->IntrStatus
|= TxOK
;
2337 rtl8139_update_irq(s
);
2341 static void rtl8139_transmit(RTL8139State
*s
)
2343 int descriptor
= s
->currTxDesc
, txcount
= 0;
2346 if (rtl8139_transmit_one(s
, descriptor
))
2353 /* Mark transfer completed */
2356 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s
->currTxDesc
));
2360 static void rtl8139_TxStatus_write(RTL8139State
*s
, uint32_t txRegOffset
, uint32_t val
)
2363 int descriptor
= txRegOffset
/4;
2365 /* handle C+ transmit mode register configuration */
2367 if (rtl8139_cp_transmitter_enabled(s
))
2369 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset
, val
, descriptor
));
2371 /* handle Dump Tally Counters command */
2372 s
->TxStatus
[descriptor
] = val
;
2374 if (descriptor
== 0 && (val
& 0x8))
2376 target_phys_addr_t tc_addr
= rtl8139_addr64(s
->TxStatus
[0] & ~0x3f, s
->TxStatus
[1]);
2378 /* dump tally counters to specified memory location */
2379 RTL8139TallyCounters_physical_memory_write( tc_addr
, &s
->tally_counters
);
2381 /* mark dump completed */
2382 s
->TxStatus
[0] &= ~0x8;
2388 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset
, val
, descriptor
));
2390 /* mask only reserved bits */
2391 val
&= ~0xff00c000; /* these bits are reset on write */
2392 val
= SET_MASKED(val
, 0x00c00000, s
->TxStatus
[descriptor
]);
2394 s
->TxStatus
[descriptor
] = val
;
2396 /* attempt to start transmission */
2397 rtl8139_transmit(s
);
2400 static uint32_t rtl8139_TxStatus_read(RTL8139State
*s
, uint32_t txRegOffset
)
2402 uint32_t ret
= s
->TxStatus
[txRegOffset
/4];
2404 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset
, ret
));
2409 static uint16_t rtl8139_TSAD_read(RTL8139State
*s
)
2413 /* Simulate TSAD, it is read only anyway */
2415 ret
= ((s
->TxStatus
[3] & TxStatOK
)?TSAD_TOK3
:0)
2416 |((s
->TxStatus
[2] & TxStatOK
)?TSAD_TOK2
:0)
2417 |((s
->TxStatus
[1] & TxStatOK
)?TSAD_TOK1
:0)
2418 |((s
->TxStatus
[0] & TxStatOK
)?TSAD_TOK0
:0)
2420 |((s
->TxStatus
[3] & TxUnderrun
)?TSAD_TUN3
:0)
2421 |((s
->TxStatus
[2] & TxUnderrun
)?TSAD_TUN2
:0)
2422 |((s
->TxStatus
[1] & TxUnderrun
)?TSAD_TUN1
:0)
2423 |((s
->TxStatus
[0] & TxUnderrun
)?TSAD_TUN0
:0)
2425 |((s
->TxStatus
[3] & TxAborted
)?TSAD_TABT3
:0)
2426 |((s
->TxStatus
[2] & TxAborted
)?TSAD_TABT2
:0)
2427 |((s
->TxStatus
[1] & TxAborted
)?TSAD_TABT1
:0)
2428 |((s
->TxStatus
[0] & TxAborted
)?TSAD_TABT0
:0)
2430 |((s
->TxStatus
[3] & TxHostOwns
)?TSAD_OWN3
:0)
2431 |((s
->TxStatus
[2] & TxHostOwns
)?TSAD_OWN2
:0)
2432 |((s
->TxStatus
[1] & TxHostOwns
)?TSAD_OWN1
:0)
2433 |((s
->TxStatus
[0] & TxHostOwns
)?TSAD_OWN0
:0) ;
2436 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret
));
2441 static uint16_t rtl8139_CSCR_read(RTL8139State
*s
)
2443 uint16_t ret
= s
->CSCR
;
2445 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret
));
2450 static void rtl8139_TxAddr_write(RTL8139State
*s
, uint32_t txAddrOffset
, uint32_t val
)
2452 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset
, val
));
2454 s
->TxAddr
[txAddrOffset
/4] = val
;
2457 static uint32_t rtl8139_TxAddr_read(RTL8139State
*s
, uint32_t txAddrOffset
)
2459 uint32_t ret
= s
->TxAddr
[txAddrOffset
/4];
2461 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset
, ret
));
2466 static void rtl8139_RxBufPtr_write(RTL8139State
*s
, uint32_t val
)
2468 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val
));
2470 /* this value is off by 16 */
2471 s
->RxBufPtr
= MOD2(val
+ 0x10, s
->RxBufferSize
);
2473 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2474 s
->RxBufferSize
, s
->RxBufAddr
, s
->RxBufPtr
));
2477 static uint32_t rtl8139_RxBufPtr_read(RTL8139State
*s
)
2479 /* this value is off by 16 */
2480 uint32_t ret
= s
->RxBufPtr
- 0x10;
2482 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret
));
2487 static uint32_t rtl8139_RxBufAddr_read(RTL8139State
*s
)
2489 /* this value is NOT off by 16 */
2490 uint32_t ret
= s
->RxBufAddr
;
2492 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret
));
2497 static void rtl8139_RxBuf_write(RTL8139State
*s
, uint32_t val
)
2499 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val
));
2503 /* may need to reset rxring here */
2506 static uint32_t rtl8139_RxBuf_read(RTL8139State
*s
)
2508 uint32_t ret
= s
->RxBuf
;
2510 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret
));
2515 static void rtl8139_IntrMask_write(RTL8139State
*s
, uint32_t val
)
2517 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val
));
2519 /* mask unwriteable bits */
2520 val
= SET_MASKED(val
, 0x1e00, s
->IntrMask
);
2524 rtl8139_update_irq(s
);
2527 static uint32_t rtl8139_IntrMask_read(RTL8139State
*s
)
2529 uint32_t ret
= s
->IntrMask
;
2531 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret
));
2536 static void rtl8139_IntrStatus_write(RTL8139State
*s
, uint32_t val
)
2538 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val
));
2542 /* writing to ISR has no effect */
2547 uint16_t newStatus
= s
->IntrStatus
& ~val
;
2549 /* mask unwriteable bits */
2550 newStatus
= SET_MASKED(newStatus
, 0x1e00, s
->IntrStatus
);
2552 /* writing 1 to interrupt status register bit clears it */
2554 rtl8139_update_irq(s
);
2556 s
->IntrStatus
= newStatus
;
2557 rtl8139_update_irq(s
);
2561 static uint32_t rtl8139_IntrStatus_read(RTL8139State
*s
)
2563 uint32_t ret
= s
->IntrStatus
;
2565 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret
));
2569 /* reading ISR clears all interrupts */
2572 rtl8139_update_irq(s
);
2579 static void rtl8139_MultiIntr_write(RTL8139State
*s
, uint32_t val
)
2581 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val
));
2583 /* mask unwriteable bits */
2584 val
= SET_MASKED(val
, 0xf000, s
->MultiIntr
);
2589 static uint32_t rtl8139_MultiIntr_read(RTL8139State
*s
)
2591 uint32_t ret
= s
->MultiIntr
;
2593 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret
));
2598 static void rtl8139_io_writeb(void *opaque
, uint8_t addr
, uint32_t val
)
2600 RTL8139State
*s
= opaque
;
2606 case MAC0
... MAC0
+5:
2607 s
->phys
[addr
- MAC0
] = val
;
2609 case MAC0
+6 ... MAC0
+7:
2612 case MAR0
... MAR0
+7:
2613 s
->mult
[addr
- MAR0
] = val
;
2616 rtl8139_ChipCmd_write(s
, val
);
2619 rtl8139_Cfg9346_write(s
, val
);
2621 case TxConfig
: /* windows driver sometimes writes using byte-lenth call */
2622 rtl8139_TxConfig_writeb(s
, val
);
2625 rtl8139_Config0_write(s
, val
);
2628 rtl8139_Config1_write(s
, val
);
2631 rtl8139_Config3_write(s
, val
);
2634 rtl8139_Config4_write(s
, val
);
2637 rtl8139_Config5_write(s
, val
);
2641 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val
));
2645 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val
));
2648 s
->clock_enabled
= 1;
2650 else if (val
== 'H')
2652 s
->clock_enabled
= 0;
2657 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val
));
2662 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val
));
2665 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
2666 //rtl8139_cplus_transmit(s);
2670 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
2671 rtl8139_cplus_transmit(s
);
2677 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr
, val
));
2682 static void rtl8139_io_writew(void *opaque
, uint8_t addr
, uint32_t val
)
2684 RTL8139State
*s
= opaque
;
2691 rtl8139_IntrMask_write(s
, val
);
2695 rtl8139_IntrStatus_write(s
, val
);
2699 rtl8139_MultiIntr_write(s
, val
);
2703 rtl8139_RxBufPtr_write(s
, val
);
2707 rtl8139_BasicModeCtrl_write(s
, val
);
2709 case BasicModeStatus
:
2710 rtl8139_BasicModeStatus_write(s
, val
);
2713 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val
));
2714 s
->NWayAdvert
= val
;
2717 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val
));
2720 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val
));
2721 s
->NWayExpansion
= val
;
2725 rtl8139_CpCmd_write(s
, val
);
2729 rtl8139_IntrMitigate_write(s
, val
);
2733 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr
, val
));
2735 #ifdef TARGET_WORDS_BIGENDIAN
2736 rtl8139_io_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2737 rtl8139_io_writeb(opaque
, addr
+ 1, val
& 0xff);
2739 rtl8139_io_writeb(opaque
, addr
, val
& 0xff);
2740 rtl8139_io_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2746 static void rtl8139_io_writel(void *opaque
, uint8_t addr
, uint32_t val
)
2748 RTL8139State
*s
= opaque
;
2755 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
2760 rtl8139_TxConfig_write(s
, val
);
2764 rtl8139_RxConfig_write(s
, val
);
2767 case TxStatus0
... TxStatus0
+4*4-1:
2768 rtl8139_TxStatus_write(s
, addr
-TxStatus0
, val
);
2771 case TxAddr0
... TxAddr0
+4*4-1:
2772 rtl8139_TxAddr_write(s
, addr
-TxAddr0
, val
);
2776 rtl8139_RxBuf_write(s
, val
);
2780 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val
));
2781 s
->RxRingAddrLO
= val
;
2785 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val
));
2786 s
->RxRingAddrHI
= val
;
2790 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2792 s
->TCTR_base
= qemu_get_clock(vm_clock
);
2796 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val
));
2801 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr
, val
));
2802 #ifdef TARGET_WORDS_BIGENDIAN
2803 rtl8139_io_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2804 rtl8139_io_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2805 rtl8139_io_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2806 rtl8139_io_writeb(opaque
, addr
+ 3, val
& 0xff);
2808 rtl8139_io_writeb(opaque
, addr
, val
& 0xff);
2809 rtl8139_io_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2810 rtl8139_io_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2811 rtl8139_io_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2817 static uint32_t rtl8139_io_readb(void *opaque
, uint8_t addr
)
2819 RTL8139State
*s
= opaque
;
2826 case MAC0
... MAC0
+5:
2827 ret
= s
->phys
[addr
- MAC0
];
2829 case MAC0
+6 ... MAC0
+7:
2832 case MAR0
... MAR0
+7:
2833 ret
= s
->mult
[addr
- MAR0
];
2836 ret
= rtl8139_ChipCmd_read(s
);
2839 ret
= rtl8139_Cfg9346_read(s
);
2842 ret
= rtl8139_Config0_read(s
);
2845 ret
= rtl8139_Config1_read(s
);
2848 ret
= rtl8139_Config3_read(s
);
2851 ret
= rtl8139_Config4_read(s
);
2854 ret
= rtl8139_Config5_read(s
);
2859 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret
));
2863 ret
= s
->clock_enabled
;
2864 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret
));
2868 ret
= RTL8139_PCI_REVID
;
2869 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret
));
2874 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret
));
2877 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2878 ret
= s
->TxConfig
>> 24;
2879 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret
));
2883 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr
));
2891 static uint32_t rtl8139_io_readw(void *opaque
, uint8_t addr
)
2893 RTL8139State
*s
= opaque
;
2896 addr
&= 0xfe; /* mask lower bit */
2901 ret
= rtl8139_IntrMask_read(s
);
2905 ret
= rtl8139_IntrStatus_read(s
);
2909 ret
= rtl8139_MultiIntr_read(s
);
2913 ret
= rtl8139_RxBufPtr_read(s
);
2917 ret
= rtl8139_RxBufAddr_read(s
);
2921 ret
= rtl8139_BasicModeCtrl_read(s
);
2923 case BasicModeStatus
:
2924 ret
= rtl8139_BasicModeStatus_read(s
);
2927 ret
= s
->NWayAdvert
;
2928 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret
));
2932 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret
));
2935 ret
= s
->NWayExpansion
;
2936 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret
));
2940 ret
= rtl8139_CpCmd_read(s
);
2944 ret
= rtl8139_IntrMitigate_read(s
);
2948 ret
= rtl8139_TSAD_read(s
);
2952 ret
= rtl8139_CSCR_read(s
);
2956 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr
));
2958 #ifdef TARGET_WORDS_BIGENDIAN
2959 ret
= rtl8139_io_readb(opaque
, addr
) << 8;
2960 ret
|= rtl8139_io_readb(opaque
, addr
+ 1);
2962 ret
= rtl8139_io_readb(opaque
, addr
);
2963 ret
|= rtl8139_io_readb(opaque
, addr
+ 1) << 8;
2966 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr
, ret
));
2973 static uint32_t rtl8139_io_readl(void *opaque
, uint8_t addr
)
2975 RTL8139State
*s
= opaque
;
2978 addr
&= 0xfc; /* also mask low 2 bits */
2985 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret
));
2989 ret
= rtl8139_TxConfig_read(s
);
2993 ret
= rtl8139_RxConfig_read(s
);
2996 case TxStatus0
... TxStatus0
+4*4-1:
2997 ret
= rtl8139_TxStatus_read(s
, addr
-TxStatus0
);
3000 case TxAddr0
... TxAddr0
+4*4-1:
3001 ret
= rtl8139_TxAddr_read(s
, addr
-TxAddr0
);
3005 ret
= rtl8139_RxBuf_read(s
);
3009 ret
= s
->RxRingAddrLO
;
3010 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret
));
3014 ret
= s
->RxRingAddrHI
;
3015 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret
));
3020 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret
));
3025 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret
));
3029 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr
));
3031 #ifdef TARGET_WORDS_BIGENDIAN
3032 ret
= rtl8139_io_readb(opaque
, addr
) << 24;
3033 ret
|= rtl8139_io_readb(opaque
, addr
+ 1) << 16;
3034 ret
|= rtl8139_io_readb(opaque
, addr
+ 2) << 8;
3035 ret
|= rtl8139_io_readb(opaque
, addr
+ 3);
3037 ret
= rtl8139_io_readb(opaque
, addr
);
3038 ret
|= rtl8139_io_readb(opaque
, addr
+ 1) << 8;
3039 ret
|= rtl8139_io_readb(opaque
, addr
+ 2) << 16;
3040 ret
|= rtl8139_io_readb(opaque
, addr
+ 3) << 24;
3043 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr
, ret
));
3052 static void rtl8139_ioport_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
3054 rtl8139_io_writeb(opaque
, addr
& 0xFF, val
);
3057 static void rtl8139_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
3059 rtl8139_io_writew(opaque
, addr
& 0xFF, val
);
3062 static void rtl8139_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
3064 rtl8139_io_writel(opaque
, addr
& 0xFF, val
);
3067 static uint32_t rtl8139_ioport_readb(void *opaque
, uint32_t addr
)
3069 return rtl8139_io_readb(opaque
, addr
& 0xFF);
3072 static uint32_t rtl8139_ioport_readw(void *opaque
, uint32_t addr
)
3074 return rtl8139_io_readw(opaque
, addr
& 0xFF);
3077 static uint32_t rtl8139_ioport_readl(void *opaque
, uint32_t addr
)
3079 return rtl8139_io_readl(opaque
, addr
& 0xFF);
3084 static void rtl8139_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
3086 rtl8139_io_writeb(opaque
, addr
& 0xFF, val
);
3089 static void rtl8139_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
3091 rtl8139_io_writew(opaque
, addr
& 0xFF, val
);
3094 static void rtl8139_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
3096 rtl8139_io_writel(opaque
, addr
& 0xFF, val
);
3099 static uint32_t rtl8139_mmio_readb(void *opaque
, target_phys_addr_t addr
)
3101 return rtl8139_io_readb(opaque
, addr
& 0xFF);
3104 static uint32_t rtl8139_mmio_readw(void *opaque
, target_phys_addr_t addr
)
3106 return rtl8139_io_readw(opaque
, addr
& 0xFF);
3109 static uint32_t rtl8139_mmio_readl(void *opaque
, target_phys_addr_t addr
)
3111 return rtl8139_io_readl(opaque
, addr
& 0xFF);
3116 static void rtl8139_save(QEMUFile
* f
,void* opaque
)
3118 RTL8139State
* s
=(RTL8139State
*)opaque
;
3121 pci_device_save(s
->pci_dev
, f
);
3123 qemu_put_buffer(f
, s
->phys
, 6);
3124 qemu_put_buffer(f
, s
->mult
, 8);
3128 qemu_put_be32s(f
, &s
->TxStatus
[i
]); /* TxStatus0 */
3132 qemu_put_be32s(f
, &s
->TxAddr
[i
]); /* TxAddr0 */
3135 qemu_put_be32s(f
, &s
->RxBuf
); /* Receive buffer */
3136 qemu_put_be32s(f
, &s
->RxBufferSize
);/* internal variable, receive ring buffer size in C mode */
3137 qemu_put_be32s(f
, &s
->RxBufPtr
);
3138 qemu_put_be32s(f
, &s
->RxBufAddr
);
3140 qemu_put_be16s(f
, &s
->IntrStatus
);
3141 qemu_put_be16s(f
, &s
->IntrMask
);
3143 qemu_put_be32s(f
, &s
->TxConfig
);
3144 qemu_put_be32s(f
, &s
->RxConfig
);
3145 qemu_put_be32s(f
, &s
->RxMissed
);
3146 qemu_put_be16s(f
, &s
->CSCR
);
3148 qemu_put_8s(f
, &s
->Cfg9346
);
3149 qemu_put_8s(f
, &s
->Config0
);
3150 qemu_put_8s(f
, &s
->Config1
);
3151 qemu_put_8s(f
, &s
->Config3
);
3152 qemu_put_8s(f
, &s
->Config4
);
3153 qemu_put_8s(f
, &s
->Config5
);
3155 qemu_put_8s(f
, &s
->clock_enabled
);
3156 qemu_put_8s(f
, &s
->bChipCmdState
);
3158 qemu_put_be16s(f
, &s
->MultiIntr
);
3160 qemu_put_be16s(f
, &s
->BasicModeCtrl
);
3161 qemu_put_be16s(f
, &s
->BasicModeStatus
);
3162 qemu_put_be16s(f
, &s
->NWayAdvert
);
3163 qemu_put_be16s(f
, &s
->NWayLPAR
);
3164 qemu_put_be16s(f
, &s
->NWayExpansion
);
3166 qemu_put_be16s(f
, &s
->CpCmd
);
3167 qemu_put_8s(f
, &s
->TxThresh
);
3170 qemu_put_be32s(f
, &i
); /* unused. */
3171 qemu_put_buffer(f
, s
->macaddr
, 6);
3172 qemu_put_be32s(f
, &s
->rtl8139_mmio_io_addr
);
3174 qemu_put_be32s(f
, &s
->currTxDesc
);
3175 qemu_put_be32s(f
, &s
->currCPlusRxDesc
);
3176 qemu_put_be32s(f
, &s
->currCPlusTxDesc
);
3177 qemu_put_be32s(f
, &s
->RxRingAddrLO
);
3178 qemu_put_be32s(f
, &s
->RxRingAddrHI
);
3180 for (i
=0; i
<EEPROM_9346_SIZE
; ++i
)
3182 qemu_put_be16s(f
, &s
->eeprom
.contents
[i
]);
3184 qemu_put_be32s(f
, &s
->eeprom
.mode
);
3185 qemu_put_be32s(f
, &s
->eeprom
.tick
);
3186 qemu_put_8s(f
, &s
->eeprom
.address
);
3187 qemu_put_be16s(f
, &s
->eeprom
.input
);
3188 qemu_put_be16s(f
, &s
->eeprom
.output
);
3190 qemu_put_8s(f
, &s
->eeprom
.eecs
);
3191 qemu_put_8s(f
, &s
->eeprom
.eesk
);
3192 qemu_put_8s(f
, &s
->eeprom
.eedi
);
3193 qemu_put_8s(f
, &s
->eeprom
.eedo
);
3195 qemu_put_be32s(f
, &s
->TCTR
);
3196 qemu_put_be32s(f
, &s
->TimerInt
);
3197 qemu_put_be64s(f
, &s
->TCTR_base
);
3199 RTL8139TallyCounters_save(f
, &s
->tally_counters
);
3202 static int rtl8139_load(QEMUFile
* f
,void* opaque
,int version_id
)
3204 RTL8139State
* s
=(RTL8139State
*)opaque
;
3207 /* just 2 versions for now */
3211 if (version_id
>= 3) {
3212 ret
= pci_device_load(s
->pci_dev
, f
);
3217 /* saved since version 1 */
3218 qemu_get_buffer(f
, s
->phys
, 6);
3219 qemu_get_buffer(f
, s
->mult
, 8);
3223 qemu_get_be32s(f
, &s
->TxStatus
[i
]); /* TxStatus0 */
3227 qemu_get_be32s(f
, &s
->TxAddr
[i
]); /* TxAddr0 */
3230 qemu_get_be32s(f
, &s
->RxBuf
); /* Receive buffer */
3231 qemu_get_be32s(f
, &s
->RxBufferSize
);/* internal variable, receive ring buffer size in C mode */
3232 qemu_get_be32s(f
, &s
->RxBufPtr
);
3233 qemu_get_be32s(f
, &s
->RxBufAddr
);
3235 qemu_get_be16s(f
, &s
->IntrStatus
);
3236 qemu_get_be16s(f
, &s
->IntrMask
);
3238 qemu_get_be32s(f
, &s
->TxConfig
);
3239 qemu_get_be32s(f
, &s
->RxConfig
);
3240 qemu_get_be32s(f
, &s
->RxMissed
);
3241 qemu_get_be16s(f
, &s
->CSCR
);
3243 qemu_get_8s(f
, &s
->Cfg9346
);
3244 qemu_get_8s(f
, &s
->Config0
);
3245 qemu_get_8s(f
, &s
->Config1
);
3246 qemu_get_8s(f
, &s
->Config3
);
3247 qemu_get_8s(f
, &s
->Config4
);
3248 qemu_get_8s(f
, &s
->Config5
);
3250 qemu_get_8s(f
, &s
->clock_enabled
);
3251 qemu_get_8s(f
, &s
->bChipCmdState
);
3253 qemu_get_be16s(f
, &s
->MultiIntr
);
3255 qemu_get_be16s(f
, &s
->BasicModeCtrl
);
3256 qemu_get_be16s(f
, &s
->BasicModeStatus
);
3257 qemu_get_be16s(f
, &s
->NWayAdvert
);
3258 qemu_get_be16s(f
, &s
->NWayLPAR
);
3259 qemu_get_be16s(f
, &s
->NWayExpansion
);
3261 qemu_get_be16s(f
, &s
->CpCmd
);
3262 qemu_get_8s(f
, &s
->TxThresh
);
3264 qemu_get_be32s(f
, &i
); /* unused. */
3265 qemu_get_buffer(f
, s
->macaddr
, 6);
3266 qemu_get_be32s(f
, &s
->rtl8139_mmio_io_addr
);
3268 qemu_get_be32s(f
, &s
->currTxDesc
);
3269 qemu_get_be32s(f
, &s
->currCPlusRxDesc
);
3270 qemu_get_be32s(f
, &s
->currCPlusTxDesc
);
3271 qemu_get_be32s(f
, &s
->RxRingAddrLO
);
3272 qemu_get_be32s(f
, &s
->RxRingAddrHI
);
3274 for (i
=0; i
<EEPROM_9346_SIZE
; ++i
)
3276 qemu_get_be16s(f
, &s
->eeprom
.contents
[i
]);
3278 qemu_get_be32s(f
, &s
->eeprom
.mode
);
3279 qemu_get_be32s(f
, &s
->eeprom
.tick
);
3280 qemu_get_8s(f
, &s
->eeprom
.address
);
3281 qemu_get_be16s(f
, &s
->eeprom
.input
);
3282 qemu_get_be16s(f
, &s
->eeprom
.output
);
3284 qemu_get_8s(f
, &s
->eeprom
.eecs
);
3285 qemu_get_8s(f
, &s
->eeprom
.eesk
);
3286 qemu_get_8s(f
, &s
->eeprom
.eedi
);
3287 qemu_get_8s(f
, &s
->eeprom
.eedo
);
3289 /* saved since version 2 */
3290 if (version_id
>= 2)
3292 qemu_get_be32s(f
, &s
->TCTR
);
3293 qemu_get_be32s(f
, &s
->TimerInt
);
3294 qemu_get_be64s(f
, &s
->TCTR_base
);
3296 RTL8139TallyCounters_load(f
, &s
->tally_counters
);
3300 /* not saved, use default */
3305 RTL8139TallyCounters_clear(&s
->tally_counters
);
3311 /***********************************************************/
3312 /* PCI RTL8139 definitions */
3314 typedef struct PCIRTL8139State
{
3316 RTL8139State rtl8139
;
3319 static void rtl8139_mmio_map(PCIDevice
*pci_dev
, int region_num
,
3320 uint32_t addr
, uint32_t size
, int type
)
3322 PCIRTL8139State
*d
= (PCIRTL8139State
*)pci_dev
;
3323 RTL8139State
*s
= &d
->rtl8139
;
3325 cpu_register_physical_memory(addr
+ 0, 0x100, s
->rtl8139_mmio_io_addr
);
3328 static void rtl8139_ioport_map(PCIDevice
*pci_dev
, int region_num
,
3329 uint32_t addr
, uint32_t size
, int type
)
3331 PCIRTL8139State
*d
= (PCIRTL8139State
*)pci_dev
;
3332 RTL8139State
*s
= &d
->rtl8139
;
3334 register_ioport_write(addr
, 0x100, 1, rtl8139_ioport_writeb
, s
);
3335 register_ioport_read( addr
, 0x100, 1, rtl8139_ioport_readb
, s
);
3337 register_ioport_write(addr
, 0x100, 2, rtl8139_ioport_writew
, s
);
3338 register_ioport_read( addr
, 0x100, 2, rtl8139_ioport_readw
, s
);
3340 register_ioport_write(addr
, 0x100, 4, rtl8139_ioport_writel
, s
);
3341 register_ioport_read( addr
, 0x100, 4, rtl8139_ioport_readl
, s
);
3344 static CPUReadMemoryFunc
*rtl8139_mmio_read
[3] = {
3350 static CPUWriteMemoryFunc
*rtl8139_mmio_write
[3] = {
3351 rtl8139_mmio_writeb
,
3352 rtl8139_mmio_writew
,
3353 rtl8139_mmio_writel
,
3356 static inline int64_t rtl8139_get_next_tctr_time(RTL8139State
*s
, int64_t current_time
)
3358 int64_t next_time
= current_time
+
3359 muldiv64(1, ticks_per_sec
, PCI_FREQUENCY
);
3360 if (next_time
<= current_time
)
3361 next_time
= current_time
+ 1;
3365 #if RTL8139_ONBOARD_TIMER
3366 static void rtl8139_timer(void *opaque
)
3368 RTL8139State
*s
= opaque
;
3375 if (!s
->clock_enabled
)
3377 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3381 curr_time
= qemu_get_clock(vm_clock
);
3383 curr_tick
= muldiv64(curr_time
- s
->TCTR_base
, PCI_FREQUENCY
, ticks_per_sec
);
3385 if (s
->TimerInt
&& curr_tick
>= s
->TimerInt
)
3387 if (s
->TCTR
< s
->TimerInt
|| curr_tick
< s
->TCTR
)
3393 s
->TCTR
= curr_tick
;
3395 // DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR));
3399 DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s
->TCTR
));
3400 s
->IntrStatus
|= PCSTimeout
;
3401 rtl8139_update_irq(s
);
3404 qemu_mod_timer(s
->timer
,
3405 rtl8139_get_next_tctr_time(s
,curr_time
));
3407 #endif /* RTL8139_ONBOARD_TIMER */
3409 void pci_rtl8139_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
)
3415 d
= (PCIRTL8139State
*)pci_register_device(bus
,
3416 "RTL8139", sizeof(PCIRTL8139State
),
3419 pci_conf
= d
->dev
.config
;
3420 pci_conf
[0x00] = 0xec; /* Realtek 8139 */
3421 pci_conf
[0x01] = 0x10;
3422 pci_conf
[0x02] = 0x39;
3423 pci_conf
[0x03] = 0x81;
3424 pci_conf
[0x04] = 0x05; /* command = I/O space, Bus Master */
3425 pci_conf
[0x08] = RTL8139_PCI_REVID
; /* PCI revision ID; >=0x20 is for 8139C+ */
3426 pci_conf
[0x0a] = 0x00; /* ethernet network controller */
3427 pci_conf
[0x0b] = 0x02;
3428 pci_conf
[0x0e] = 0x00; /* header_type */
3429 pci_conf
[0x3d] = 1; /* interrupt pin 0 */
3430 pci_conf
[0x34] = 0xdc;
3434 /* I/O handler for memory-mapped I/O */
3435 s
->rtl8139_mmio_io_addr
=
3436 cpu_register_io_memory(0, rtl8139_mmio_read
, rtl8139_mmio_write
, s
);
3438 pci_register_io_region(&d
->dev
, 0, 0x100,
3439 PCI_ADDRESS_SPACE_IO
, rtl8139_ioport_map
);
3441 pci_register_io_region(&d
->dev
, 1, 0x100,
3442 PCI_ADDRESS_SPACE_MEM
, rtl8139_mmio_map
);
3444 s
->pci_dev
= (PCIDevice
*)d
;
3445 memcpy(s
->macaddr
, nd
->macaddr
, 6);
3447 s
->vc
= qemu_new_vlan_client(nd
->vlan
, rtl8139_receive
,
3448 rtl8139_can_receive
, s
);
3450 snprintf(s
->vc
->info_str
, sizeof(s
->vc
->info_str
),
3451 "rtl8139 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
3459 s
->cplus_txbuffer
= NULL
;
3460 s
->cplus_txbuffer_len
= 0;
3461 s
->cplus_txbuffer_offset
= 0;
3463 /* XXX: instance number ? */
3464 register_savevm("rtl8139", 0, 3, rtl8139_save
, rtl8139_load
, s
);
3466 #if RTL8139_ONBOARD_TIMER
3467 s
->timer
= qemu_new_timer(vm_clock
, rtl8139_timer
, s
);
3469 qemu_mod_timer(s
->timer
,
3470 rtl8139_get_next_tctr_time(s
,qemu_get_clock(vm_clock
)));
3471 #endif /* RTL8139_ONBOARD_TIMER */