]>
git.proxmox.com Git - qemu.git/blob - hw/sparc32_dma.c
2 * QEMU Sparc32 DMA controller emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 * This is the DMA controller part of chip STP2000 (Master I/O), also
31 * produced as NCR89C100. See
32 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
34 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
38 #define DPRINTF(fmt, args...) \
39 do { printf("DMA: " fmt , ##args); } while (0)
41 #define DPRINTF(fmt, args...)
45 #define DMA_SIZE (4 * sizeof(uint32_t))
46 #define DMA_MAXADDR (DMA_SIZE - 1)
48 #define DMA_VER 0xa0000000
50 #define DMA_INTREN 0x10
51 #define DMA_WRITE_MEM 0x100
52 #define DMA_LOADED 0x04000000
53 #define DMA_DRAIN_FIFO 0x40
54 #define DMA_RESET 0x80
56 typedef struct DMAState DMAState
;
59 uint32_t dmaregs
[DMA_REGS
];
65 /* Note: on sparc, the lance 16 bit bus is swapped */
66 void ledma_memory_read(void *opaque
, target_phys_addr_t addr
,
67 uint8_t *buf
, int len
, int do_bswap
)
72 DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
73 s
->dmaregs
[0] & DMA_WRITE_MEM
? 'w': 'r', s
->dmaregs
[1]);
74 addr
|= s
->dmaregs
[3];
76 sparc_iommu_memory_read(s
->iommu
, addr
, buf
, len
);
80 sparc_iommu_memory_read(s
->iommu
, addr
, buf
, len
);
81 for(i
= 0; i
< len
; i
+= 2) {
82 bswap16s((uint16_t *)(buf
+ i
));
87 void ledma_memory_write(void *opaque
, target_phys_addr_t addr
,
88 uint8_t *buf
, int len
, int do_bswap
)
94 DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
95 s
->dmaregs
[0] & DMA_WRITE_MEM
? 'w': 'r', s
->dmaregs
[1]);
96 addr
|= s
->dmaregs
[3];
98 sparc_iommu_memory_write(s
->iommu
, addr
, buf
, len
);
104 if (l
> sizeof(tmp_buf
))
106 for(i
= 0; i
< l
; i
+= 2) {
107 tmp_buf
[i
>> 1] = bswap16(*(uint16_t *)(buf
+ i
));
109 sparc_iommu_memory_write(s
->iommu
, addr
, (uint8_t *)tmp_buf
, l
);
117 static void dma_set_irq(void *opaque
, int irq
, int level
)
119 DMAState
*s
= opaque
;
121 DPRINTF("Raise IRQ\n");
122 s
->dmaregs
[0] |= DMA_INTR
;
123 qemu_irq_raise(s
->irq
);
125 s
->dmaregs
[0] &= ~DMA_INTR
;
126 DPRINTF("Lower IRQ\n");
127 qemu_irq_lower(s
->irq
);
131 void espdma_memory_read(void *opaque
, uint8_t *buf
, int len
)
133 DMAState
*s
= opaque
;
135 DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
136 s
->dmaregs
[0] & DMA_WRITE_MEM
? 'w': 'r', s
->dmaregs
[1]);
137 sparc_iommu_memory_read(s
->iommu
, s
->dmaregs
[1], buf
, len
);
138 s
->dmaregs
[0] |= DMA_INTR
;
139 s
->dmaregs
[1] += len
;
142 void espdma_memory_write(void *opaque
, uint8_t *buf
, int len
)
144 DMAState
*s
= opaque
;
146 DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
147 s
->dmaregs
[0] & DMA_WRITE_MEM
? 'w': 'r', s
->dmaregs
[1]);
148 sparc_iommu_memory_write(s
->iommu
, s
->dmaregs
[1], buf
, len
);
149 s
->dmaregs
[0] |= DMA_INTR
;
150 s
->dmaregs
[1] += len
;
153 static uint32_t dma_mem_readl(void *opaque
, target_phys_addr_t addr
)
155 DMAState
*s
= opaque
;
158 saddr
= (addr
& DMA_MAXADDR
) >> 2;
159 DPRINTF("read dmareg " TARGET_FMT_plx
": 0x%8.8x\n", addr
,
162 return s
->dmaregs
[saddr
];
165 static void dma_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
167 DMAState
*s
= opaque
;
170 saddr
= (addr
& DMA_MAXADDR
) >> 2;
171 DPRINTF("write dmareg " TARGET_FMT_plx
": 0x%8.8x -> 0x%8.8x\n", addr
,
172 s
->dmaregs
[saddr
], val
);
175 if (!(val
& DMA_INTREN
)) {
176 DPRINTF("Lower IRQ\n");
177 qemu_irq_lower(s
->irq
);
179 if (val
& DMA_RESET
) {
180 qemu_irq_raise(s
->dev_reset
);
181 qemu_irq_lower(s
->dev_reset
);
182 } else if (val
& DMA_DRAIN_FIFO
) {
183 val
&= ~DMA_DRAIN_FIFO
;
185 val
= DMA_DRAIN_FIFO
;
190 s
->dmaregs
[0] |= DMA_LOADED
;
195 s
->dmaregs
[saddr
] = val
;
198 static CPUReadMemoryFunc
*dma_mem_read
[3] = {
204 static CPUWriteMemoryFunc
*dma_mem_write
[3] = {
210 static void dma_reset(void *opaque
)
212 DMAState
*s
= opaque
;
214 memset(s
->dmaregs
, 0, DMA_SIZE
);
215 s
->dmaregs
[0] = DMA_VER
;
218 static void dma_save(QEMUFile
*f
, void *opaque
)
220 DMAState
*s
= opaque
;
223 for (i
= 0; i
< DMA_REGS
; i
++)
224 qemu_put_be32s(f
, &s
->dmaregs
[i
]);
227 static int dma_load(QEMUFile
*f
, void *opaque
, int version_id
)
229 DMAState
*s
= opaque
;
234 for (i
= 0; i
< DMA_REGS
; i
++)
235 qemu_get_be32s(f
, &s
->dmaregs
[i
]);
240 void *sparc32_dma_init(target_phys_addr_t daddr
, qemu_irq parent_irq
,
241 void *iommu
, qemu_irq
**dev_irq
, qemu_irq
**reset
)
246 s
= qemu_mallocz(sizeof(DMAState
));
253 dma_io_memory
= cpu_register_io_memory(0, dma_mem_read
, dma_mem_write
, s
);
254 cpu_register_physical_memory(daddr
, DMA_SIZE
, dma_io_memory
);
256 register_savevm("sparc32_dma", daddr
, 2, dma_save
, dma_load
, s
);
257 qemu_register_reset(dma_reset
, s
);
258 *dev_irq
= qemu_allocate_irqs(dma_set_irq
, s
, 1);
260 *reset
= &s
->dev_reset
;