2 * Luminary Micro Stellaris peripherals
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
14 #include "qemu-timer.h"
18 #include "exec-memory.h"
28 #define BP_OLED_I2C 0x01
29 #define BP_OLED_SSI 0x02
30 #define BP_GAMEPAD 0x04
32 typedef const struct {
42 } stellaris_board_info
;
44 /* General purpose timer module. */
46 typedef struct gptm_state
{
57 uint32_t match_prescale
[2];
60 struct gptm_state
*opaque
[2];
62 /* The timers have an alternate output used to trigger the ADC. */
67 static void gptm_update_irq(gptm_state
*s
)
70 level
= (s
->state
& s
->mask
) != 0;
71 qemu_set_irq(s
->irq
, level
);
74 static void gptm_stop(gptm_state
*s
, int n
)
76 qemu_del_timer(s
->timer
[n
]);
79 static void gptm_reload(gptm_state
*s
, int n
, int reset
)
83 tick
= qemu_get_clock_ns(vm_clock
);
88 /* 32-bit CountDown. */
90 count
= s
->load
[0] | (s
->load
[1] << 16);
91 tick
+= (int64_t)count
* system_clock_scale
;
92 } else if (s
->config
== 1) {
93 /* 32-bit RTC. 1Hz tick. */
94 tick
+= get_ticks_per_sec();
95 } else if (s
->mode
[n
] == 0xa) {
96 /* PWM mode. Not implemented. */
98 hw_error("TODO: 16-bit timer mode 0x%x\n", s
->mode
[n
]);
101 qemu_mod_timer(s
->timer
[n
], tick
);
104 static void gptm_tick(void *opaque
)
106 gptm_state
**p
= (gptm_state
**)opaque
;
112 if (s
->config
== 0) {
114 if ((s
->control
& 0x20)) {
115 /* Output trigger. */
116 qemu_irq_pulse(s
->trigger
);
118 if (s
->mode
[0] & 1) {
123 gptm_reload(s
, 0, 0);
125 } else if (s
->config
== 1) {
129 match
= s
->match
[0] | (s
->match
[1] << 16);
135 gptm_reload(s
, 0, 0);
136 } else if (s
->mode
[n
] == 0xa) {
137 /* PWM mode. Not implemented. */
139 hw_error("TODO: 16-bit timer mode 0x%x\n", s
->mode
[n
]);
144 static uint64_t gptm_read(void *opaque
, target_phys_addr_t offset
,
147 gptm_state
*s
= (gptm_state
*)opaque
;
152 case 0x04: /* TAMR */
154 case 0x08: /* TBMR */
163 return s
->state
& s
->mask
;
166 case 0x28: /* TAILR */
167 return s
->load
[0] | ((s
->config
< 4) ? (s
->load
[1] << 16) : 0);
168 case 0x2c: /* TBILR */
170 case 0x30: /* TAMARCHR */
171 return s
->match
[0] | ((s
->config
< 4) ? (s
->match
[1] << 16) : 0);
172 case 0x34: /* TBMATCHR */
174 case 0x38: /* TAPR */
175 return s
->prescale
[0];
176 case 0x3c: /* TBPR */
177 return s
->prescale
[1];
178 case 0x40: /* TAPMR */
179 return s
->match_prescale
[0];
180 case 0x44: /* TBPMR */
181 return s
->match_prescale
[1];
186 hw_error("TODO: Timer value read\n");
188 hw_error("gptm_read: Bad offset 0x%x\n", (int)offset
);
193 static void gptm_write(void *opaque
, target_phys_addr_t offset
,
194 uint64_t value
, unsigned size
)
196 gptm_state
*s
= (gptm_state
*)opaque
;
199 /* The timers should be disabled before changing the configuration.
200 We take advantage of this and defer everything until the timer
206 case 0x04: /* TAMR */
209 case 0x08: /* TBMR */
215 /* TODO: Implement pause. */
216 if ((oldval
^ value
) & 1) {
218 gptm_reload(s
, 0, 1);
223 if (((oldval
^ value
) & 0x100) && s
->config
>= 4) {
225 gptm_reload(s
, 1, 1);
232 s
->mask
= value
& 0x77;
238 case 0x28: /* TAILR */
239 s
->load
[0] = value
& 0xffff;
241 s
->load
[1] = value
>> 16;
244 case 0x2c: /* TBILR */
245 s
->load
[1] = value
& 0xffff;
247 case 0x30: /* TAMARCHR */
248 s
->match
[0] = value
& 0xffff;
250 s
->match
[1] = value
>> 16;
253 case 0x34: /* TBMATCHR */
254 s
->match
[1] = value
>> 16;
256 case 0x38: /* TAPR */
257 s
->prescale
[0] = value
;
259 case 0x3c: /* TBPR */
260 s
->prescale
[1] = value
;
262 case 0x40: /* TAPMR */
263 s
->match_prescale
[0] = value
;
265 case 0x44: /* TBPMR */
266 s
->match_prescale
[0] = value
;
269 hw_error("gptm_write: Bad offset 0x%x\n", (int)offset
);
274 static const MemoryRegionOps gptm_ops
= {
277 .endianness
= DEVICE_NATIVE_ENDIAN
,
280 static const VMStateDescription vmstate_stellaris_gptm
= {
281 .name
= "stellaris_gptm",
283 .minimum_version_id
= 1,
284 .minimum_version_id_old
= 1,
285 .fields
= (VMStateField
[]) {
286 VMSTATE_UINT32(config
, gptm_state
),
287 VMSTATE_UINT32_ARRAY(mode
, gptm_state
, 2),
288 VMSTATE_UINT32(control
, gptm_state
),
289 VMSTATE_UINT32(state
, gptm_state
),
290 VMSTATE_UINT32(mask
, gptm_state
),
292 VMSTATE_UINT32_ARRAY(load
, gptm_state
, 2),
293 VMSTATE_UINT32_ARRAY(match
, gptm_state
, 2),
294 VMSTATE_UINT32_ARRAY(prescale
, gptm_state
, 2),
295 VMSTATE_UINT32_ARRAY(match_prescale
, gptm_state
, 2),
296 VMSTATE_UINT32(rtc
, gptm_state
),
297 VMSTATE_INT64_ARRAY(tick
, gptm_state
, 2),
298 VMSTATE_TIMER_ARRAY(timer
, gptm_state
, 2),
299 VMSTATE_END_OF_LIST()
303 static int stellaris_gptm_init(SysBusDevice
*dev
)
305 gptm_state
*s
= FROM_SYSBUS(gptm_state
, dev
);
307 sysbus_init_irq(dev
, &s
->irq
);
308 qdev_init_gpio_out(&dev
->qdev
, &s
->trigger
, 1);
310 memory_region_init_io(&s
->iomem
, &gptm_ops
, s
,
312 sysbus_init_mmio_region(dev
, &s
->iomem
);
314 s
->opaque
[0] = s
->opaque
[1] = s
;
315 s
->timer
[0] = qemu_new_timer_ns(vm_clock
, gptm_tick
, &s
->opaque
[0]);
316 s
->timer
[1] = qemu_new_timer_ns(vm_clock
, gptm_tick
, &s
->opaque
[1]);
317 vmstate_register(&dev
->qdev
, -1, &vmstate_stellaris_gptm
, s
);
322 /* System controller. */
341 stellaris_board_info
*board
;
344 static void ssys_update(ssys_state
*s
)
346 qemu_set_irq(s
->irq
, (s
->int_status
& s
->int_mask
) != 0);
349 static uint32_t pllcfg_sandstorm
[16] = {
351 0x1ae0, /* 1.8432 Mhz */
353 0xd573, /* 2.4576 Mhz */
354 0x37a6, /* 3.57954 Mhz */
355 0x1ae2, /* 3.6864 Mhz */
357 0x98bc, /* 4.906 Mhz */
358 0x935b, /* 4.9152 Mhz */
360 0x4dee, /* 5.12 Mhz */
362 0x75db, /* 6.144 Mhz */
363 0x1ae6, /* 7.3728 Mhz */
365 0x585b /* 8.192 Mhz */
368 static uint32_t pllcfg_fury
[16] = {
370 0x1b20, /* 1.8432 Mhz */
372 0xf42b, /* 2.4576 Mhz */
373 0x37e3, /* 3.57954 Mhz */
374 0x1b21, /* 3.6864 Mhz */
376 0x98ee, /* 4.906 Mhz */
377 0xd5b4, /* 4.9152 Mhz */
379 0x4e27, /* 5.12 Mhz */
381 0xec1c, /* 6.144 Mhz */
382 0x1b23, /* 7.3728 Mhz */
384 0xb11c /* 8.192 Mhz */
387 #define DID0_VER_MASK 0x70000000
388 #define DID0_VER_0 0x00000000
389 #define DID0_VER_1 0x10000000
391 #define DID0_CLASS_MASK 0x00FF0000
392 #define DID0_CLASS_SANDSTORM 0x00000000
393 #define DID0_CLASS_FURY 0x00010000
395 static int ssys_board_class(const ssys_state
*s
)
397 uint32_t did0
= s
->board
->did0
;
398 switch (did0
& DID0_VER_MASK
) {
400 return DID0_CLASS_SANDSTORM
;
402 switch (did0
& DID0_CLASS_MASK
) {
403 case DID0_CLASS_SANDSTORM
:
404 case DID0_CLASS_FURY
:
405 return did0
& DID0_CLASS_MASK
;
407 /* for unknown classes, fall through */
409 hw_error("ssys_board_class: Unknown class 0x%08x\n", did0
);
413 static uint64_t ssys_read(void *opaque
, target_phys_addr_t offset
,
416 ssys_state
*s
= (ssys_state
*)opaque
;
419 case 0x000: /* DID0 */
420 return s
->board
->did0
;
421 case 0x004: /* DID1 */
422 return s
->board
->did1
;
423 case 0x008: /* DC0 */
424 return s
->board
->dc0
;
425 case 0x010: /* DC1 */
426 return s
->board
->dc1
;
427 case 0x014: /* DC2 */
428 return s
->board
->dc2
;
429 case 0x018: /* DC3 */
430 return s
->board
->dc3
;
431 case 0x01c: /* DC4 */
432 return s
->board
->dc4
;
433 case 0x030: /* PBORCTL */
435 case 0x034: /* LDOPCTL */
437 case 0x040: /* SRCR0 */
439 case 0x044: /* SRCR1 */
441 case 0x048: /* SRCR2 */
443 case 0x050: /* RIS */
444 return s
->int_status
;
445 case 0x054: /* IMC */
447 case 0x058: /* MISC */
448 return s
->int_status
& s
->int_mask
;
449 case 0x05c: /* RESC */
451 case 0x060: /* RCC */
453 case 0x064: /* PLLCFG */
456 xtal
= (s
->rcc
>> 6) & 0xf;
457 switch (ssys_board_class(s
)) {
458 case DID0_CLASS_FURY
:
459 return pllcfg_fury
[xtal
];
460 case DID0_CLASS_SANDSTORM
:
461 return pllcfg_sandstorm
[xtal
];
463 hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
467 case 0x070: /* RCC2 */
469 case 0x100: /* RCGC0 */
471 case 0x104: /* RCGC1 */
473 case 0x108: /* RCGC2 */
475 case 0x110: /* SCGC0 */
477 case 0x114: /* SCGC1 */
479 case 0x118: /* SCGC2 */
481 case 0x120: /* DCGC0 */
483 case 0x124: /* DCGC1 */
485 case 0x128: /* DCGC2 */
487 case 0x150: /* CLKVCLR */
489 case 0x160: /* LDOARST */
491 case 0x1e0: /* USER0 */
493 case 0x1e4: /* USER1 */
496 hw_error("ssys_read: Bad offset 0x%x\n", (int)offset
);
501 static bool ssys_use_rcc2(ssys_state
*s
)
503 return (s
->rcc2
>> 31) & 0x1;
507 * Caculate the sys. clock period in ms.
509 static void ssys_calculate_system_clock(ssys_state
*s
)
511 if (ssys_use_rcc2(s
)) {
512 system_clock_scale
= 5 * (((s
->rcc2
>> 23) & 0x3f) + 1);
514 system_clock_scale
= 5 * (((s
->rcc
>> 23) & 0xf) + 1);
518 static void ssys_write(void *opaque
, target_phys_addr_t offset
,
519 uint64_t value
, unsigned size
)
521 ssys_state
*s
= (ssys_state
*)opaque
;
524 case 0x030: /* PBORCTL */
525 s
->pborctl
= value
& 0xffff;
527 case 0x034: /* LDOPCTL */
528 s
->ldopctl
= value
& 0x1f;
530 case 0x040: /* SRCR0 */
531 case 0x044: /* SRCR1 */
532 case 0x048: /* SRCR2 */
533 fprintf(stderr
, "Peripheral reset not implemented\n");
535 case 0x054: /* IMC */
536 s
->int_mask
= value
& 0x7f;
538 case 0x058: /* MISC */
539 s
->int_status
&= ~value
;
541 case 0x05c: /* RESC */
542 s
->resc
= value
& 0x3f;
544 case 0x060: /* RCC */
545 if ((s
->rcc
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
547 s
->int_status
|= (1 << 6);
550 ssys_calculate_system_clock(s
);
552 case 0x070: /* RCC2 */
553 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
557 if ((s
->rcc2
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
559 s
->int_status
|= (1 << 6);
562 ssys_calculate_system_clock(s
);
564 case 0x100: /* RCGC0 */
567 case 0x104: /* RCGC1 */
570 case 0x108: /* RCGC2 */
573 case 0x110: /* SCGC0 */
576 case 0x114: /* SCGC1 */
579 case 0x118: /* SCGC2 */
582 case 0x120: /* DCGC0 */
585 case 0x124: /* DCGC1 */
588 case 0x128: /* DCGC2 */
591 case 0x150: /* CLKVCLR */
594 case 0x160: /* LDOARST */
598 hw_error("ssys_write: Bad offset 0x%x\n", (int)offset
);
603 static const MemoryRegionOps ssys_ops
= {
606 .endianness
= DEVICE_NATIVE_ENDIAN
,
609 static void ssys_reset(void *opaque
)
611 ssys_state
*s
= (ssys_state
*)opaque
;
616 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
619 s
->rcc2
= 0x07802810;
626 static int stellaris_sys_post_load(void *opaque
, int version_id
)
628 ssys_state
*s
= opaque
;
630 ssys_calculate_system_clock(s
);
635 static const VMStateDescription vmstate_stellaris_sys
= {
636 .name
= "stellaris_sys",
638 .minimum_version_id
= 1,
639 .minimum_version_id_old
= 1,
640 .post_load
= stellaris_sys_post_load
,
641 .fields
= (VMStateField
[]) {
642 VMSTATE_UINT32(pborctl
, ssys_state
),
643 VMSTATE_UINT32(ldopctl
, ssys_state
),
644 VMSTATE_UINT32(int_mask
, ssys_state
),
645 VMSTATE_UINT32(int_status
, ssys_state
),
646 VMSTATE_UINT32(resc
, ssys_state
),
647 VMSTATE_UINT32(rcc
, ssys_state
),
648 VMSTATE_UINT32_V(rcc2
, ssys_state
, 2),
649 VMSTATE_UINT32_ARRAY(rcgc
, ssys_state
, 3),
650 VMSTATE_UINT32_ARRAY(scgc
, ssys_state
, 3),
651 VMSTATE_UINT32_ARRAY(dcgc
, ssys_state
, 3),
652 VMSTATE_UINT32(clkvclr
, ssys_state
),
653 VMSTATE_UINT32(ldoarst
, ssys_state
),
654 VMSTATE_END_OF_LIST()
658 static int stellaris_sys_init(uint32_t base
, qemu_irq irq
,
659 stellaris_board_info
* board
,
664 s
= (ssys_state
*)g_malloc0(sizeof(ssys_state
));
667 /* Most devices come preprogrammed with a MAC address in the user data. */
668 s
->user0
= macaddr
[0] | (macaddr
[1] << 8) | (macaddr
[2] << 16);
669 s
->user1
= macaddr
[3] | (macaddr
[4] << 8) | (macaddr
[5] << 16);
671 memory_region_init_io(&s
->iomem
, &ssys_ops
, s
, "ssys", 0x00001000);
672 memory_region_add_subregion(get_system_memory(), base
, &s
->iomem
);
674 vmstate_register(NULL
, -1, &vmstate_stellaris_sys
, s
);
679 /* I2C controller. */
693 } stellaris_i2c_state
;
695 #define STELLARIS_I2C_MCS_BUSY 0x01
696 #define STELLARIS_I2C_MCS_ERROR 0x02
697 #define STELLARIS_I2C_MCS_ADRACK 0x04
698 #define STELLARIS_I2C_MCS_DATACK 0x08
699 #define STELLARIS_I2C_MCS_ARBLST 0x10
700 #define STELLARIS_I2C_MCS_IDLE 0x20
701 #define STELLARIS_I2C_MCS_BUSBSY 0x40
703 static uint64_t stellaris_i2c_read(void *opaque
, target_phys_addr_t offset
,
706 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
712 /* We don't emulate timing, so the controller is never busy. */
713 return s
->mcs
| STELLARIS_I2C_MCS_IDLE
;
716 case 0x0c: /* MTPR */
718 case 0x10: /* MIMR */
720 case 0x14: /* MRIS */
722 case 0x18: /* MMIS */
723 return s
->mris
& s
->mimr
;
727 hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset
);
732 static void stellaris_i2c_update(stellaris_i2c_state
*s
)
736 level
= (s
->mris
& s
->mimr
) != 0;
737 qemu_set_irq(s
->irq
, level
);
740 static void stellaris_i2c_write(void *opaque
, target_phys_addr_t offset
,
741 uint64_t value
, unsigned size
)
743 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
747 s
->msa
= value
& 0xff;
750 if ((s
->mcr
& 0x10) == 0) {
751 /* Disabled. Do nothing. */
754 /* Grab the bus if this is starting a transfer. */
755 if ((value
& 2) && (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
756 if (i2c_start_transfer(s
->bus
, s
->msa
>> 1, s
->msa
& 1)) {
757 s
->mcs
|= STELLARIS_I2C_MCS_ARBLST
;
759 s
->mcs
&= ~STELLARIS_I2C_MCS_ARBLST
;
760 s
->mcs
|= STELLARIS_I2C_MCS_BUSBSY
;
763 /* If we don't have the bus then indicate an error. */
764 if (!i2c_bus_busy(s
->bus
)
765 || (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
766 s
->mcs
|= STELLARIS_I2C_MCS_ERROR
;
769 s
->mcs
&= ~STELLARIS_I2C_MCS_ERROR
;
771 /* Transfer a byte. */
772 /* TODO: Handle errors. */
775 s
->mdr
= i2c_recv(s
->bus
) & 0xff;
778 i2c_send(s
->bus
, s
->mdr
);
780 /* Raise an interrupt. */
784 /* Finish transfer. */
785 i2c_end_transfer(s
->bus
);
786 s
->mcs
&= ~STELLARIS_I2C_MCS_BUSBSY
;
790 s
->mdr
= value
& 0xff;
792 case 0x0c: /* MTPR */
793 s
->mtpr
= value
& 0xff;
795 case 0x10: /* MIMR */
798 case 0x1c: /* MICR */
804 "stellaris_i2c_write: Loopback not implemented\n");
807 "stellaris_i2c_write: Slave mode not implemented\n");
808 s
->mcr
= value
& 0x31;
811 hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
814 stellaris_i2c_update(s
);
817 static void stellaris_i2c_reset(stellaris_i2c_state
*s
)
819 if (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
)
820 i2c_end_transfer(s
->bus
);
829 stellaris_i2c_update(s
);
832 static const MemoryRegionOps stellaris_i2c_ops
= {
833 .read
= stellaris_i2c_read
,
834 .write
= stellaris_i2c_write
,
835 .endianness
= DEVICE_NATIVE_ENDIAN
,
838 static const VMStateDescription vmstate_stellaris_i2c
= {
839 .name
= "stellaris_i2c",
841 .minimum_version_id
= 1,
842 .minimum_version_id_old
= 1,
843 .fields
= (VMStateField
[]) {
844 VMSTATE_UINT32(msa
, stellaris_i2c_state
),
845 VMSTATE_UINT32(mcs
, stellaris_i2c_state
),
846 VMSTATE_UINT32(mdr
, stellaris_i2c_state
),
847 VMSTATE_UINT32(mtpr
, stellaris_i2c_state
),
848 VMSTATE_UINT32(mimr
, stellaris_i2c_state
),
849 VMSTATE_UINT32(mris
, stellaris_i2c_state
),
850 VMSTATE_UINT32(mcr
, stellaris_i2c_state
),
851 VMSTATE_END_OF_LIST()
855 static int stellaris_i2c_init(SysBusDevice
* dev
)
857 stellaris_i2c_state
*s
= FROM_SYSBUS(stellaris_i2c_state
, dev
);
860 sysbus_init_irq(dev
, &s
->irq
);
861 bus
= i2c_init_bus(&dev
->qdev
, "i2c");
864 memory_region_init_io(&s
->iomem
, &stellaris_i2c_ops
, s
,
866 sysbus_init_mmio_region(dev
, &s
->iomem
);
867 /* ??? For now we only implement the master interface. */
868 stellaris_i2c_reset(s
);
869 vmstate_register(&dev
->qdev
, -1, &vmstate_stellaris_i2c
, s
);
873 /* Analogue to Digital Converter. This is only partially implemented,
874 enough for applications that use a combined ADC and timer tick. */
876 #define STELLARIS_ADC_EM_CONTROLLER 0
877 #define STELLARIS_ADC_EM_COMP 1
878 #define STELLARIS_ADC_EM_EXTERNAL 4
879 #define STELLARIS_ADC_EM_TIMER 5
880 #define STELLARIS_ADC_EM_PWM0 6
881 #define STELLARIS_ADC_EM_PWM1 7
882 #define STELLARIS_ADC_EM_PWM2 8
884 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
885 #define STELLARIS_ADC_FIFO_FULL 0x1000
907 } stellaris_adc_state
;
909 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state
*s
, int n
)
913 tail
= s
->fifo
[n
].state
& 0xf;
914 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_EMPTY
) {
917 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf) | ((tail
+ 1) & 0xf);
918 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_FULL
;
919 if (tail
+ 1 == ((s
->fifo
[n
].state
>> 4) & 0xf))
920 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_EMPTY
;
922 return s
->fifo
[n
].data
[tail
];
925 static void stellaris_adc_fifo_write(stellaris_adc_state
*s
, int n
,
930 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
931 FIFO fir each sequencer. */
932 head
= (s
->fifo
[n
].state
>> 4) & 0xf;
933 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_FULL
) {
937 s
->fifo
[n
].data
[head
] = value
;
938 head
= (head
+ 1) & 0xf;
939 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_EMPTY
;
940 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf0) | (head
<< 4);
941 if ((s
->fifo
[n
].state
& 0xf) == head
)
942 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_FULL
;
945 static void stellaris_adc_update(stellaris_adc_state
*s
)
950 for (n
= 0; n
< 4; n
++) {
951 level
= (s
->ris
& s
->im
& (1 << n
)) != 0;
952 qemu_set_irq(s
->irq
[n
], level
);
956 static void stellaris_adc_trigger(void *opaque
, int irq
, int level
)
958 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
961 for (n
= 0; n
< 4; n
++) {
962 if ((s
->actss
& (1 << n
)) == 0) {
966 if (((s
->emux
>> (n
* 4)) & 0xff) != 5) {
970 /* Some applications use the ADC as a random number source, so introduce
971 some variation into the signal. */
972 s
->noise
= s
->noise
* 314159 + 1;
973 /* ??? actual inputs not implemented. Return an arbitrary value. */
974 stellaris_adc_fifo_write(s
, n
, 0x200 + ((s
->noise
>> 16) & 7));
976 stellaris_adc_update(s
);
980 static void stellaris_adc_reset(stellaris_adc_state
*s
)
984 for (n
= 0; n
< 4; n
++) {
987 s
->fifo
[n
].state
= STELLARIS_ADC_FIFO_EMPTY
;
991 static uint64_t stellaris_adc_read(void *opaque
, target_phys_addr_t offset
,
994 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
996 /* TODO: Implement this. */
997 if (offset
>= 0x40 && offset
< 0xc0) {
999 n
= (offset
- 0x40) >> 5;
1000 switch (offset
& 0x1f) {
1001 case 0x00: /* SSMUX */
1003 case 0x04: /* SSCTL */
1005 case 0x08: /* SSFIFO */
1006 return stellaris_adc_fifo_read(s
, n
);
1007 case 0x0c: /* SSFSTAT */
1008 return s
->fifo
[n
].state
;
1014 case 0x00: /* ACTSS */
1016 case 0x04: /* RIS */
1020 case 0x0c: /* ISC */
1021 return s
->ris
& s
->im
;
1022 case 0x10: /* OSTAT */
1024 case 0x14: /* EMUX */
1026 case 0x18: /* USTAT */
1028 case 0x20: /* SSPRI */
1030 case 0x30: /* SAC */
1033 hw_error("strllaris_adc_read: Bad offset 0x%x\n",
1039 static void stellaris_adc_write(void *opaque
, target_phys_addr_t offset
,
1040 uint64_t value
, unsigned size
)
1042 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1044 /* TODO: Implement this. */
1045 if (offset
>= 0x40 && offset
< 0xc0) {
1047 n
= (offset
- 0x40) >> 5;
1048 switch (offset
& 0x1f) {
1049 case 0x00: /* SSMUX */
1050 s
->ssmux
[n
] = value
& 0x33333333;
1052 case 0x04: /* SSCTL */
1054 hw_error("ADC: Unimplemented sequence %" PRIx64
"\n",
1057 s
->ssctl
[n
] = value
;
1064 case 0x00: /* ACTSS */
1065 s
->actss
= value
& 0xf;
1070 case 0x0c: /* ISC */
1073 case 0x10: /* OSTAT */
1076 case 0x14: /* EMUX */
1079 case 0x18: /* USTAT */
1082 case 0x20: /* SSPRI */
1085 case 0x28: /* PSSI */
1086 hw_error("Not implemented: ADC sample initiate\n");
1088 case 0x30: /* SAC */
1092 hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset
);
1094 stellaris_adc_update(s
);
1097 static const MemoryRegionOps stellaris_adc_ops
= {
1098 .read
= stellaris_adc_read
,
1099 .write
= stellaris_adc_write
,
1100 .endianness
= DEVICE_NATIVE_ENDIAN
,
1103 static const VMStateDescription vmstate_stellaris_adc
= {
1104 .name
= "stellaris_adc",
1106 .minimum_version_id
= 1,
1107 .minimum_version_id_old
= 1,
1108 .fields
= (VMStateField
[]) {
1109 VMSTATE_UINT32(actss
, stellaris_adc_state
),
1110 VMSTATE_UINT32(ris
, stellaris_adc_state
),
1111 VMSTATE_UINT32(im
, stellaris_adc_state
),
1112 VMSTATE_UINT32(emux
, stellaris_adc_state
),
1113 VMSTATE_UINT32(ostat
, stellaris_adc_state
),
1114 VMSTATE_UINT32(ustat
, stellaris_adc_state
),
1115 VMSTATE_UINT32(sspri
, stellaris_adc_state
),
1116 VMSTATE_UINT32(sac
, stellaris_adc_state
),
1117 VMSTATE_UINT32(fifo
[0].state
, stellaris_adc_state
),
1118 VMSTATE_UINT32_ARRAY(fifo
[0].data
, stellaris_adc_state
, 16),
1119 VMSTATE_UINT32(ssmux
[0], stellaris_adc_state
),
1120 VMSTATE_UINT32(ssctl
[0], stellaris_adc_state
),
1121 VMSTATE_UINT32(fifo
[1].state
, stellaris_adc_state
),
1122 VMSTATE_UINT32_ARRAY(fifo
[1].data
, stellaris_adc_state
, 16),
1123 VMSTATE_UINT32(ssmux
[1], stellaris_adc_state
),
1124 VMSTATE_UINT32(ssctl
[1], stellaris_adc_state
),
1125 VMSTATE_UINT32(fifo
[2].state
, stellaris_adc_state
),
1126 VMSTATE_UINT32_ARRAY(fifo
[2].data
, stellaris_adc_state
, 16),
1127 VMSTATE_UINT32(ssmux
[2], stellaris_adc_state
),
1128 VMSTATE_UINT32(ssctl
[2], stellaris_adc_state
),
1129 VMSTATE_UINT32(fifo
[3].state
, stellaris_adc_state
),
1130 VMSTATE_UINT32_ARRAY(fifo
[3].data
, stellaris_adc_state
, 16),
1131 VMSTATE_UINT32(ssmux
[3], stellaris_adc_state
),
1132 VMSTATE_UINT32(ssctl
[3], stellaris_adc_state
),
1133 VMSTATE_UINT32(noise
, stellaris_adc_state
),
1134 VMSTATE_END_OF_LIST()
1138 static int stellaris_adc_init(SysBusDevice
*dev
)
1140 stellaris_adc_state
*s
= FROM_SYSBUS(stellaris_adc_state
, dev
);
1143 for (n
= 0; n
< 4; n
++) {
1144 sysbus_init_irq(dev
, &s
->irq
[n
]);
1147 memory_region_init_io(&s
->iomem
, &stellaris_adc_ops
, s
,
1149 sysbus_init_mmio_region(dev
, &s
->iomem
);
1150 stellaris_adc_reset(s
);
1151 qdev_init_gpio_in(&dev
->qdev
, stellaris_adc_trigger
, 1);
1152 vmstate_register(&dev
->qdev
, -1, &vmstate_stellaris_adc
, s
);
1156 /* Some boards have both an OLED controller and SD card connected to
1157 the same SSI port, with the SD card chip select connected to a
1158 GPIO pin. Technically the OLED chip select is connected to the SSI
1159 Fss pin. We do not bother emulating that as both devices should
1160 never be selected simultaneously, and our OLED controller ignores stray
1161 0xff commands that occur when deselecting the SD card. */
1168 } stellaris_ssi_bus_state
;
1170 static void stellaris_ssi_bus_select(void *opaque
, int irq
, int level
)
1172 stellaris_ssi_bus_state
*s
= (stellaris_ssi_bus_state
*)opaque
;
1174 s
->current_dev
= level
;
1177 static uint32_t stellaris_ssi_bus_transfer(SSISlave
*dev
, uint32_t val
)
1179 stellaris_ssi_bus_state
*s
= FROM_SSI_SLAVE(stellaris_ssi_bus_state
, dev
);
1181 return ssi_transfer(s
->bus
[s
->current_dev
], val
);
1184 static const VMStateDescription vmstate_stellaris_ssi_bus
= {
1185 .name
= "stellaris_ssi_bus",
1187 .minimum_version_id
= 1,
1188 .minimum_version_id_old
= 1,
1189 .fields
= (VMStateField
[]) {
1190 VMSTATE_INT32(current_dev
, stellaris_ssi_bus_state
),
1191 VMSTATE_END_OF_LIST()
1195 static int stellaris_ssi_bus_init(SSISlave
*dev
)
1197 stellaris_ssi_bus_state
*s
= FROM_SSI_SLAVE(stellaris_ssi_bus_state
, dev
);
1199 s
->bus
[0] = ssi_create_bus(&dev
->qdev
, "ssi0");
1200 s
->bus
[1] = ssi_create_bus(&dev
->qdev
, "ssi1");
1201 qdev_init_gpio_in(&dev
->qdev
, stellaris_ssi_bus_select
, 1);
1203 vmstate_register(&dev
->qdev
, -1, &vmstate_stellaris_ssi_bus
, s
);
1208 static stellaris_board_info stellaris_boards
[] = {
1212 0x001f001f, /* dc0 */
1222 0x00ff007f, /* dc0 */
1227 BP_OLED_SSI
| BP_GAMEPAD
1231 static void stellaris_init(const char *kernel_filename
, const char *cpu_model
,
1232 stellaris_board_info
*board
)
1234 static const int uart_irq
[] = {5, 6, 33, 34};
1235 static const int timer_irq
[] = {19, 21, 23, 35};
1236 static const uint32_t gpio_addr
[7] =
1237 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1238 0x40024000, 0x40025000, 0x40026000};
1239 static const int gpio_irq
[7] = {0, 1, 2, 3, 4, 30, 31};
1241 MemoryRegion
*address_space_mem
= get_system_memory();
1243 DeviceState
*gpio_dev
[7];
1244 qemu_irq gpio_in
[7][8];
1245 qemu_irq gpio_out
[7][8];
1254 flash_size
= ((board
->dc0
& 0xffff) + 1) << 1;
1255 sram_size
= (board
->dc0
>> 18) + 1;
1256 pic
= armv7m_init(address_space_mem
,
1257 flash_size
, sram_size
, kernel_filename
, cpu_model
);
1259 if (board
->dc1
& (1 << 16)) {
1260 dev
= sysbus_create_varargs("stellaris-adc", 0x40038000,
1261 pic
[14], pic
[15], pic
[16], pic
[17], NULL
);
1262 adc
= qdev_get_gpio_in(dev
, 0);
1266 for (i
= 0; i
< 4; i
++) {
1267 if (board
->dc2
& (0x10000 << i
)) {
1268 dev
= sysbus_create_simple("stellaris-gptm",
1269 0x40030000 + i
* 0x1000,
1271 /* TODO: This is incorrect, but we get away with it because
1272 the ADC output is only ever pulsed. */
1273 qdev_connect_gpio_out(dev
, 0, adc
);
1277 stellaris_sys_init(0x400fe000, pic
[28], board
, nd_table
[0].macaddr
.a
);
1279 for (i
= 0; i
< 7; i
++) {
1280 if (board
->dc4
& (1 << i
)) {
1281 gpio_dev
[i
] = sysbus_create_simple("pl061_luminary", gpio_addr
[i
],
1283 for (j
= 0; j
< 8; j
++) {
1284 gpio_in
[i
][j
] = qdev_get_gpio_in(gpio_dev
[i
], j
);
1285 gpio_out
[i
][j
] = NULL
;
1290 if (board
->dc2
& (1 << 12)) {
1291 dev
= sysbus_create_simple("stellaris-i2c", 0x40020000, pic
[8]);
1292 i2c
= (i2c_bus
*)qdev_get_child_bus(dev
, "i2c");
1293 if (board
->peripherals
& BP_OLED_I2C
) {
1294 i2c_create_slave(i2c
, "ssd0303", 0x3d);
1298 for (i
= 0; i
< 4; i
++) {
1299 if (board
->dc2
& (1 << i
)) {
1300 sysbus_create_simple("pl011_luminary", 0x4000c000 + i
* 0x1000,
1304 if (board
->dc2
& (1 << 4)) {
1305 dev
= sysbus_create_simple("pl022", 0x40008000, pic
[7]);
1306 if (board
->peripherals
& BP_OLED_SSI
) {
1310 bus
= qdev_get_child_bus(dev
, "ssi");
1311 mux
= ssi_create_slave(bus
, "evb6965-ssi");
1312 gpio_out
[GPIO_D
][0] = qdev_get_gpio_in(mux
, 0);
1314 bus
= qdev_get_child_bus(mux
, "ssi0");
1315 ssi_create_slave(bus
, "ssi-sd");
1317 bus
= qdev_get_child_bus(mux
, "ssi1");
1318 dev
= ssi_create_slave(bus
, "ssd0323");
1319 gpio_out
[GPIO_C
][7] = qdev_get_gpio_in(dev
, 0);
1321 /* Make sure the select pin is high. */
1322 qemu_irq_raise(gpio_out
[GPIO_D
][0]);
1325 if (board
->dc4
& (1 << 28)) {
1328 qemu_check_nic_model(&nd_table
[0], "stellaris");
1330 enet
= qdev_create(NULL
, "stellaris_enet");
1331 qdev_set_nic_properties(enet
, &nd_table
[0]);
1332 qdev_init_nofail(enet
);
1333 sysbus_mmio_map(sysbus_from_qdev(enet
), 0, 0x40048000);
1334 sysbus_connect_irq(sysbus_from_qdev(enet
), 0, pic
[42]);
1336 if (board
->peripherals
& BP_GAMEPAD
) {
1337 qemu_irq gpad_irq
[5];
1338 static const int gpad_keycode
[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1340 gpad_irq
[0] = qemu_irq_invert(gpio_in
[GPIO_E
][0]); /* up */
1341 gpad_irq
[1] = qemu_irq_invert(gpio_in
[GPIO_E
][1]); /* down */
1342 gpad_irq
[2] = qemu_irq_invert(gpio_in
[GPIO_E
][2]); /* left */
1343 gpad_irq
[3] = qemu_irq_invert(gpio_in
[GPIO_E
][3]); /* right */
1344 gpad_irq
[4] = qemu_irq_invert(gpio_in
[GPIO_F
][1]); /* select */
1346 stellaris_gamepad_init(5, gpad_irq
, gpad_keycode
);
1348 for (i
= 0; i
< 7; i
++) {
1349 if (board
->dc4
& (1 << i
)) {
1350 for (j
= 0; j
< 8; j
++) {
1351 if (gpio_out
[i
][j
]) {
1352 qdev_connect_gpio_out(gpio_dev
[i
], j
, gpio_out
[i
][j
]);
1359 /* FIXME: Figure out how to generate these from stellaris_boards. */
1360 static void lm3s811evb_init(ram_addr_t ram_size
,
1361 const char *boot_device
,
1362 const char *kernel_filename
, const char *kernel_cmdline
,
1363 const char *initrd_filename
, const char *cpu_model
)
1365 stellaris_init(kernel_filename
, cpu_model
, &stellaris_boards
[0]);
1368 static void lm3s6965evb_init(ram_addr_t ram_size
,
1369 const char *boot_device
,
1370 const char *kernel_filename
, const char *kernel_cmdline
,
1371 const char *initrd_filename
, const char *cpu_model
)
1373 stellaris_init(kernel_filename
, cpu_model
, &stellaris_boards
[1]);
1376 static QEMUMachine lm3s811evb_machine
= {
1377 .name
= "lm3s811evb",
1378 .desc
= "Stellaris LM3S811EVB",
1379 .init
= lm3s811evb_init
,
1382 static QEMUMachine lm3s6965evb_machine
= {
1383 .name
= "lm3s6965evb",
1384 .desc
= "Stellaris LM3S6965EVB",
1385 .init
= lm3s6965evb_init
,
1388 static void stellaris_machine_init(void)
1390 qemu_register_machine(&lm3s811evb_machine
);
1391 qemu_register_machine(&lm3s6965evb_machine
);
1394 machine_init(stellaris_machine_init
);
1396 static SSISlaveInfo stellaris_ssi_bus_info
= {
1397 .qdev
.name
= "evb6965-ssi",
1398 .qdev
.size
= sizeof(stellaris_ssi_bus_state
),
1399 .init
= stellaris_ssi_bus_init
,
1400 .transfer
= stellaris_ssi_bus_transfer
1403 static void stellaris_register_devices(void)
1405 sysbus_register_dev("stellaris-i2c", sizeof(stellaris_i2c_state
),
1406 stellaris_i2c_init
);
1407 sysbus_register_dev("stellaris-gptm", sizeof(gptm_state
),
1408 stellaris_gptm_init
);
1409 sysbus_register_dev("stellaris-adc", sizeof(stellaris_adc_state
),
1410 stellaris_adc_init
);
1411 ssi_register_slave(&stellaris_ssi_bus_info
);
1414 device_init(stellaris_register_devices
)