hw/stellaris.c

   1 /*
   2  * Luminary Micro Stellaris peripherals
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "ssi.h"
  12 #include "arm-misc.h"
  13 #include "devices.h"
  14 #include "qemu-timer.h"
  15 #include "i2c.h"
  16 #include "net.h"
  17 #include "boards.h"
  18 #include "exec-memory.h"
  19
  20 #define GPIO_A 0
  21 #define GPIO_B 1
  22 #define GPIO_C 2
  23 #define GPIO_D 3
  24 #define GPIO_E 4
  25 #define GPIO_F 5
  26 #define GPIO_G 6
  27
  28 #define BP_OLED_I2C  0x01
  29 #define BP_OLED_SSI  0x02
  30 #define BP_GAMEPAD   0x04
  31
  32 typedef const struct {
  33     const char *name;
  34     uint32_t did0;
  35     uint32_t did1;
  36     uint32_t dc0;
  37     uint32_t dc1;
  38     uint32_t dc2;
  39     uint32_t dc3;
  40     uint32_t dc4;
  41     uint32_t peripherals;
  42 } stellaris_board_info;
  43
  44 /* General purpose timer module.  */
  45
  46 typedef struct gptm_state {
  47     SysBusDevice busdev;
  48     uint32_t config;
  49     uint32_t mode[2];
  50     uint32_t control;
  51     uint32_t state;
  52     uint32_t mask;
  53     uint32_t load[2];
  54     uint32_t match[2];
  55     uint32_t prescale[2];
  56     uint32_t match_prescale[2];
  57     uint32_t rtc;
  58     int64_t tick[2];
  59     struct gptm_state *opaque[2];
  60     QEMUTimer *timer[2];
  61     /* The timers have an alternate output used to trigger the ADC.  */
  62     qemu_irq trigger;
  63     qemu_irq irq;
  64 } gptm_state;
  65
  66 static void gptm_update_irq(gptm_state *s)
  67 {
  68     int level;
  69     level = (s->state & s->mask) != 0;
  70     qemu_set_irq(s->irq, level);
  71 }
  72
  73 static void gptm_stop(gptm_state *s, int n)
  74 {
  75     qemu_del_timer(s->timer[n]);
  76 }
  77
  78 static void gptm_reload(gptm_state *s, int n, int reset)
  79 {
  80     int64_t tick;
  81     if (reset)
  82         tick = qemu_get_clock_ns(vm_clock);
  83     else
  84         tick = s->tick[n];
  85
  86     if (s->config == 0) {
  87         /* 32-bit CountDown.  */
  88         uint32_t count;
  89         count = s->load[0] | (s->load[1] << 16);
  90         tick += (int64_t)count * system_clock_scale;
  91     } else if (s->config == 1) {
  92         /* 32-bit RTC.  1Hz tick.  */
  93         tick += get_ticks_per_sec();
  94     } else if (s->mode[n] == 0xa) {
  95         /* PWM mode.  Not implemented.  */
  96     } else {
  97         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
  98     }
  99     s->tick[n] = tick;
 100     qemu_mod_timer(s->timer[n], tick);
 101 }
 102
 103 static void gptm_tick(void *opaque)
 104 {
 105     gptm_state **p = (gptm_state **)opaque;
 106     gptm_state *s;
 107     int n;
 108
 109     s = *p;
 110     n = p - s->opaque;
 111     if (s->config == 0) {
 112         s->state |= 1;
 113         if ((s->control & 0x20)) {
 114             /* Output trigger.  */
 115             qemu_irq_pulse(s->trigger);
 116         }
 117         if (s->mode[0] & 1) {
 118             /* One-shot.  */
 119             s->control &= ~1;
 120         } else {
 121             /* Periodic.  */
 122             gptm_reload(s, 0, 0);
 123         }
 124     } else if (s->config == 1) {
 125         /* RTC.  */
 126         uint32_t match;
 127         s->rtc++;
 128         match = s->match[0] | (s->match[1] << 16);
 129         if (s->rtc > match)
 130             s->rtc = 0;
 131         if (s->rtc == 0) {
 132             s->state |= 8;
 133         }
 134         gptm_reload(s, 0, 0);
 135     } else if (s->mode[n] == 0xa) {
 136         /* PWM mode.  Not implemented.  */
 137     } else {
 138         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
 139     }
 140     gptm_update_irq(s);
 141 }
 142
 143 static uint32_t gptm_read(void *opaque, target_phys_addr_t offset)
 144 {
 145     gptm_state *s = (gptm_state *)opaque;
 146
 147     switch (offset) {
 148     case 0x00: /* CFG */
 149         return s->config;
 150     case 0x04: /* TAMR */
 151         return s->mode[0];
 152     case 0x08: /* TBMR */
 153         return s->mode[1];
 154     case 0x0c: /* CTL */
 155         return s->control;
 156     case 0x18: /* IMR */
 157         return s->mask;
 158     case 0x1c: /* RIS */
 159         return s->state;
 160     case 0x20: /* MIS */
 161         return s->state & s->mask;
 162     case 0x24: /* CR */
 163         return 0;
 164     case 0x28: /* TAILR */
 165         return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
 166     case 0x2c: /* TBILR */
 167         return s->load[1];
 168     case 0x30: /* TAMARCHR */
 169         return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
 170     case 0x34: /* TBMATCHR */
 171         return s->match[1];
 172     case 0x38: /* TAPR */
 173         return s->prescale[0];
 174     case 0x3c: /* TBPR */
 175         return s->prescale[1];
 176     case 0x40: /* TAPMR */
 177         return s->match_prescale[0];
 178     case 0x44: /* TBPMR */
 179         return s->match_prescale[1];
 180     case 0x48: /* TAR */
 181         if (s->control == 1)
 182             return s->rtc;
 183     case 0x4c: /* TBR */
 184         hw_error("TODO: Timer value read\n");
 185     default:
 186         hw_error("gptm_read: Bad offset 0x%x\n", (int)offset);
 187         return 0;
 188     }
 189 }
 190
 191 static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value)
 192 {
 193     gptm_state *s = (gptm_state *)opaque;
 194     uint32_t oldval;
 195
 196     /* The timers should be disabled before changing the configuration.
 197        We take advantage of this and defer everything until the timer
 198        is enabled.  */
 199     switch (offset) {
 200     case 0x00: /* CFG */
 201         s->config = value;
 202         break;
 203     case 0x04: /* TAMR */
 204         s->mode[0] = value;
 205         break;
 206     case 0x08: /* TBMR */
 207         s->mode[1] = value;
 208         break;
 209     case 0x0c: /* CTL */
 210         oldval = s->control;
 211         s->control = value;
 212         /* TODO: Implement pause.  */
 213         if ((oldval ^ value) & 1) {
 214             if (value & 1) {
 215                 gptm_reload(s, 0, 1);
 216             } else {
 217                 gptm_stop(s, 0);
 218             }
 219         }
 220         if (((oldval ^ value) & 0x100) && s->config >= 4) {
 221             if (value & 0x100) {
 222                 gptm_reload(s, 1, 1);
 223             } else {
 224                 gptm_stop(s, 1);
 225             }
 226         }
 227         break;
 228     case 0x18: /* IMR */
 229         s->mask = value & 0x77;
 230         gptm_update_irq(s);
 231         break;
 232     case 0x24: /* CR */
 233         s->state &= ~value;
 234         break;
 235     case 0x28: /* TAILR */
 236         s->load[0] = value & 0xffff;
 237         if (s->config < 4) {
 238             s->load[1] = value >> 16;
 239         }
 240         break;
 241     case 0x2c: /* TBILR */
 242         s->load[1] = value & 0xffff;
 243         break;
 244     case 0x30: /* TAMARCHR */
 245         s->match[0] = value & 0xffff;
 246         if (s->config < 4) {
 247             s->match[1] = value >> 16;
 248         }
 249         break;
 250     case 0x34: /* TBMATCHR */
 251         s->match[1] = value >> 16;
 252         break;
 253     case 0x38: /* TAPR */
 254         s->prescale[0] = value;
 255         break;
 256     case 0x3c: /* TBPR */
 257         s->prescale[1] = value;
 258         break;
 259     case 0x40: /* TAPMR */
 260         s->match_prescale[0] = value;
 261         break;
 262     case 0x44: /* TBPMR */
 263         s->match_prescale[0] = value;
 264         break;
 265     default:
 266         hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
 267     }
 268     gptm_update_irq(s);
 269 }
 270
 271 static CPUReadMemoryFunc * const gptm_readfn[] = {
 272    gptm_read,
 273    gptm_read,
 274    gptm_read
 275 };
 276
 277 static CPUWriteMemoryFunc * const gptm_writefn[] = {
 278    gptm_write,
 279    gptm_write,
 280    gptm_write
 281 };
 282
 283 static const VMStateDescription vmstate_stellaris_gptm = {
 284     .name = "stellaris_gptm",
 285     .version_id = 1,
 286     .minimum_version_id = 1,
 287     .minimum_version_id_old = 1,
 288     .fields      = (VMStateField[]) {
 289         VMSTATE_UINT32(config, gptm_state),
 290         VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
 291         VMSTATE_UINT32(control, gptm_state),
 292         VMSTATE_UINT32(state, gptm_state),
 293         VMSTATE_UINT32(mask, gptm_state),
 294         VMSTATE_UNUSED(8),
 295         VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
 296         VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
 297         VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
 298         VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
 299         VMSTATE_UINT32(rtc, gptm_state),
 300         VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
 301         VMSTATE_TIMER_ARRAY(timer, gptm_state, 2),
 302         VMSTATE_END_OF_LIST()
 303     }
 304 };
 305
 306 static int stellaris_gptm_init(SysBusDevice *dev)
 307 {
 308     int iomemtype;
 309     gptm_state *s = FROM_SYSBUS(gptm_state, dev);
 310
 311     sysbus_init_irq(dev, &s->irq);
 312     qdev_init_gpio_out(&dev->qdev, &s->trigger, 1);
 313
 314     iomemtype = cpu_register_io_memory(gptm_readfn,
 315                                        gptm_writefn, s,
 316                                        DEVICE_NATIVE_ENDIAN);
 317     sysbus_init_mmio(dev, 0x1000, iomemtype);
 318
 319     s->opaque[0] = s->opaque[1] = s;
 320     s->timer[0] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[0]);
 321     s->timer[1] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[1]);
 322     vmstate_register(&dev->qdev, -1, &vmstate_stellaris_gptm, s);
 323     return 0;
 324 }
 325
 326
 327 /* System controller.  */
 328
 329 typedef struct {
 330     MemoryRegion iomem;
 331     uint32_t pborctl;
 332     uint32_t ldopctl;
 333     uint32_t int_status;
 334     uint32_t int_mask;
 335     uint32_t resc;
 336     uint32_t rcc;
 337     uint32_t rcc2;
 338     uint32_t rcgc[3];
 339     uint32_t scgc[3];
 340     uint32_t dcgc[3];
 341     uint32_t clkvclr;
 342     uint32_t ldoarst;
 343     uint32_t user0;
 344     uint32_t user1;
 345     qemu_irq irq;
 346     stellaris_board_info *board;
 347 } ssys_state;
 348
 349 static void ssys_update(ssys_state *s)
 350 {
 351   qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
 352 }
 353
 354 static uint32_t pllcfg_sandstorm[16] = {
 355     0x31c0, /* 1 Mhz */
 356     0x1ae0, /* 1.8432 Mhz */
 357     0x18c0, /* 2 Mhz */
 358     0xd573, /* 2.4576 Mhz */
 359     0x37a6, /* 3.57954 Mhz */
 360     0x1ae2, /* 3.6864 Mhz */
 361     0x0c40, /* 4 Mhz */
 362     0x98bc, /* 4.906 Mhz */
 363     0x935b, /* 4.9152 Mhz */
 364     0x09c0, /* 5 Mhz */
 365     0x4dee, /* 5.12 Mhz */
 366     0x0c41, /* 6 Mhz */
 367     0x75db, /* 6.144 Mhz */
 368     0x1ae6, /* 7.3728 Mhz */
 369     0x0600, /* 8 Mhz */
 370     0x585b /* 8.192 Mhz */
 371 };
 372
 373 static uint32_t pllcfg_fury[16] = {
 374     0x3200, /* 1 Mhz */
 375     0x1b20, /* 1.8432 Mhz */
 376     0x1900, /* 2 Mhz */
 377     0xf42b, /* 2.4576 Mhz */
 378     0x37e3, /* 3.57954 Mhz */
 379     0x1b21, /* 3.6864 Mhz */
 380     0x0c80, /* 4 Mhz */
 381     0x98ee, /* 4.906 Mhz */
 382     0xd5b4, /* 4.9152 Mhz */
 383     0x0a00, /* 5 Mhz */
 384     0x4e27, /* 5.12 Mhz */
 385     0x1902, /* 6 Mhz */
 386     0xec1c, /* 6.144 Mhz */
 387     0x1b23, /* 7.3728 Mhz */
 388     0x0640, /* 8 Mhz */
 389     0xb11c /* 8.192 Mhz */
 390 };
 391
 392 #define DID0_VER_MASK        0x70000000
 393 #define DID0_VER_0           0x00000000
 394 #define DID0_VER_1           0x10000000
 395
 396 #define DID0_CLASS_MASK      0x00FF0000
 397 #define DID0_CLASS_SANDSTORM 0x00000000
 398 #define DID0_CLASS_FURY      0x00010000
 399
 400 static int ssys_board_class(const ssys_state *s)
 401 {
 402     uint32_t did0 = s->board->did0;
 403     switch (did0 & DID0_VER_MASK) {
 404     case DID0_VER_0:
 405         return DID0_CLASS_SANDSTORM;
 406     case DID0_VER_1:
 407         switch (did0 & DID0_CLASS_MASK) {
 408         case DID0_CLASS_SANDSTORM:
 409         case DID0_CLASS_FURY:
 410             return did0 & DID0_CLASS_MASK;
 411         }
 412         /* for unknown classes, fall through */
 413     default:
 414         hw_error("ssys_board_class: Unknown class 0x%08x\n", did0);
 415     }
 416 }
 417
 418 static uint64_t ssys_read(void *opaque, target_phys_addr_t offset,
 419                           unsigned size)
 420 {
 421     ssys_state *s = (ssys_state *)opaque;
 422
 423     switch (offset) {
 424     case 0x000: /* DID0 */
 425         return s->board->did0;
 426     case 0x004: /* DID1 */
 427         return s->board->did1;
 428     case 0x008: /* DC0 */
 429         return s->board->dc0;
 430     case 0x010: /* DC1 */
 431         return s->board->dc1;
 432     case 0x014: /* DC2 */
 433         return s->board->dc2;
 434     case 0x018: /* DC3 */
 435         return s->board->dc3;
 436     case 0x01c: /* DC4 */
 437         return s->board->dc4;
 438     case 0x030: /* PBORCTL */
 439         return s->pborctl;
 440     case 0x034: /* LDOPCTL */
 441         return s->ldopctl;
 442     case 0x040: /* SRCR0 */
 443         return 0;
 444     case 0x044: /* SRCR1 */
 445         return 0;
 446     case 0x048: /* SRCR2 */
 447         return 0;
 448     case 0x050: /* RIS */
 449         return s->int_status;
 450     case 0x054: /* IMC */
 451         return s->int_mask;
 452     case 0x058: /* MISC */
 453         return s->int_status & s->int_mask;
 454     case 0x05c: /* RESC */
 455         return s->resc;
 456     case 0x060: /* RCC */
 457         return s->rcc;
 458     case 0x064: /* PLLCFG */
 459         {
 460             int xtal;
 461             xtal = (s->rcc >> 6) & 0xf;
 462             switch (ssys_board_class(s)) {
 463             case DID0_CLASS_FURY:
 464                 return pllcfg_fury[xtal];
 465             case DID0_CLASS_SANDSTORM:
 466                 return pllcfg_sandstorm[xtal];
 467             default:
 468                 hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
 469                 return 0;
 470             }
 471         }
 472     case 0x070: /* RCC2 */
 473         return s->rcc2;
 474     case 0x100: /* RCGC0 */
 475         return s->rcgc[0];
 476     case 0x104: /* RCGC1 */
 477         return s->rcgc[1];
 478     case 0x108: /* RCGC2 */
 479         return s->rcgc[2];
 480     case 0x110: /* SCGC0 */
 481         return s->scgc[0];
 482     case 0x114: /* SCGC1 */
 483         return s->scgc[1];
 484     case 0x118: /* SCGC2 */
 485         return s->scgc[2];
 486     case 0x120: /* DCGC0 */
 487         return s->dcgc[0];
 488     case 0x124: /* DCGC1 */
 489         return s->dcgc[1];
 490     case 0x128: /* DCGC2 */
 491         return s->dcgc[2];
 492     case 0x150: /* CLKVCLR */
 493         return s->clkvclr;
 494     case 0x160: /* LDOARST */
 495         return s->ldoarst;
 496     case 0x1e0: /* USER0 */
 497         return s->user0;
 498     case 0x1e4: /* USER1 */
 499         return s->user1;
 500     default:
 501         hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
 502         return 0;
 503     }
 504 }
 505
 506 static bool ssys_use_rcc2(ssys_state *s)
 507 {
 508     return (s->rcc2 >> 31) & 0x1;
 509 }
 510
 511 /*
 512  * Caculate the sys. clock period in ms.
 513  */
 514 static void ssys_calculate_system_clock(ssys_state *s)
 515 {
 516     if (ssys_use_rcc2(s)) {
 517         system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
 518     } else {
 519         system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
 520     }
 521 }
 522
 523 static void ssys_write(void *opaque, target_phys_addr_t offset,
 524                        uint64_t value, unsigned size)
 525 {
 526     ssys_state *s = (ssys_state *)opaque;
 527
 528     switch (offset) {
 529     case 0x030: /* PBORCTL */
 530         s->pborctl = value & 0xffff;
 531         break;
 532     case 0x034: /* LDOPCTL */
 533         s->ldopctl = value & 0x1f;
 534         break;
 535     case 0x040: /* SRCR0 */
 536     case 0x044: /* SRCR1 */
 537     case 0x048: /* SRCR2 */
 538         fprintf(stderr, "Peripheral reset not implemented\n");
 539         break;
 540     case 0x054: /* IMC */
 541         s->int_mask = value & 0x7f;
 542         break;
 543     case 0x058: /* MISC */
 544         s->int_status &= ~value;
 545         break;
 546     case 0x05c: /* RESC */
 547         s->resc = value & 0x3f;
 548         break;
 549     case 0x060: /* RCC */
 550         if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 551             /* PLL enable.  */
 552             s->int_status |= (1 << 6);
 553         }
 554         s->rcc = value;
 555         ssys_calculate_system_clock(s);
 556         break;
 557     case 0x070: /* RCC2 */
 558         if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 559             break;
 560         }
 561
 562         if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 563             /* PLL enable.  */
 564             s->int_status |= (1 << 6);
 565         }
 566         s->rcc2 = value;
 567         ssys_calculate_system_clock(s);
 568         break;
 569     case 0x100: /* RCGC0 */
 570         s->rcgc[0] = value;
 571         break;
 572     case 0x104: /* RCGC1 */
 573         s->rcgc[1] = value;
 574         break;
 575     case 0x108: /* RCGC2 */
 576         s->rcgc[2] = value;
 577         break;
 578     case 0x110: /* SCGC0 */
 579         s->scgc[0] = value;
 580         break;
 581     case 0x114: /* SCGC1 */
 582         s->scgc[1] = value;
 583         break;
 584     case 0x118: /* SCGC2 */
 585         s->scgc[2] = value;
 586         break;
 587     case 0x120: /* DCGC0 */
 588         s->dcgc[0] = value;
 589         break;
 590     case 0x124: /* DCGC1 */
 591         s->dcgc[1] = value;
 592         break;
 593     case 0x128: /* DCGC2 */
 594         s->dcgc[2] = value;
 595         break;
 596     case 0x150: /* CLKVCLR */
 597         s->clkvclr = value;
 598         break;
 599     case 0x160: /* LDOARST */
 600         s->ldoarst = value;
 601         break;
 602     default:
 603         hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
 604     }
 605     ssys_update(s);
 606 }
 607
 608 static const MemoryRegionOps ssys_ops = {
 609     .read = ssys_read,
 610     .write = ssys_write,
 611     .endianness = DEVICE_NATIVE_ENDIAN,
 612 };
 613
 614 static void ssys_reset(void *opaque)
 615 {
 616     ssys_state *s = (ssys_state *)opaque;
 617
 618     s->pborctl = 0x7ffd;
 619     s->rcc = 0x078e3ac0;
 620
 621     if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 622         s->rcc2 = 0;
 623     } else {
 624         s->rcc2 = 0x07802810;
 625     }
 626     s->rcgc[0] = 1;
 627     s->scgc[0] = 1;
 628     s->dcgc[0] = 1;
 629 }
 630
 631 static int stellaris_sys_post_load(void *opaque, int version_id)
 632 {
 633     ssys_state *s = opaque;
 634
 635     ssys_calculate_system_clock(s);
 636
 637     return 0;
 638 }
 639
 640 static const VMStateDescription vmstate_stellaris_sys = {
 641     .name = "stellaris_sys",
 642     .version_id = 2,
 643     .minimum_version_id = 1,
 644     .minimum_version_id_old = 1,
 645     .post_load = stellaris_sys_post_load,
 646     .fields      = (VMStateField[]) {
 647         VMSTATE_UINT32(pborctl, ssys_state),
 648         VMSTATE_UINT32(ldopctl, ssys_state),
 649         VMSTATE_UINT32(int_mask, ssys_state),
 650         VMSTATE_UINT32(int_status, ssys_state),
 651         VMSTATE_UINT32(resc, ssys_state),
 652         VMSTATE_UINT32(rcc, ssys_state),
 653         VMSTATE_UINT32_V(rcc2, ssys_state, 2),
 654         VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
 655         VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
 656         VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
 657         VMSTATE_UINT32(clkvclr, ssys_state),
 658         VMSTATE_UINT32(ldoarst, ssys_state),
 659         VMSTATE_END_OF_LIST()
 660     }
 661 };
 662
 663 static int stellaris_sys_init(uint32_t base, qemu_irq irq,
 664                               stellaris_board_info * board,
 665                               uint8_t *macaddr)
 666 {
 667     ssys_state *s;
 668
 669     s = (ssys_state *)g_malloc0(sizeof(ssys_state));
 670     s->irq = irq;
 671     s->board = board;
 672     /* Most devices come preprogrammed with a MAC address in the user data. */
 673     s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
 674     s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
 675
 676     memory_region_init_io(&s->iomem, &ssys_ops, s, "ssys", 0x00001000);
 677     memory_region_add_subregion(get_system_memory(), base, &s->iomem);
 678     ssys_reset(s);
 679     vmstate_register(NULL, -1, &vmstate_stellaris_sys, s);
 680     return 0;
 681 }
 682
 683
 684 /* I2C controller.  */
 685
 686 typedef struct {
 687     SysBusDevice busdev;
 688     i2c_bus *bus;
 689     qemu_irq irq;
 690     MemoryRegion iomem;
 691     uint32_t msa;
 692     uint32_t mcs;
 693     uint32_t mdr;
 694     uint32_t mtpr;
 695     uint32_t mimr;
 696     uint32_t mris;
 697     uint32_t mcr;
 698 } stellaris_i2c_state;
 699
 700 #define STELLARIS_I2C_MCS_BUSY    0x01
 701 #define STELLARIS_I2C_MCS_ERROR   0x02
 702 #define STELLARIS_I2C_MCS_ADRACK  0x04
 703 #define STELLARIS_I2C_MCS_DATACK  0x08
 704 #define STELLARIS_I2C_MCS_ARBLST  0x10
 705 #define STELLARIS_I2C_MCS_IDLE    0x20
 706 #define STELLARIS_I2C_MCS_BUSBSY  0x40
 707
 708 static uint64_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset,
 709                                    unsigned size)
 710 {
 711     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 712
 713     switch (offset) {
 714     case 0x00: /* MSA */
 715         return s->msa;
 716     case 0x04: /* MCS */
 717         /* We don't emulate timing, so the controller is never busy.  */
 718         return s->mcs | STELLARIS_I2C_MCS_IDLE;
 719     case 0x08: /* MDR */
 720         return s->mdr;
 721     case 0x0c: /* MTPR */
 722         return s->mtpr;
 723     case 0x10: /* MIMR */
 724         return s->mimr;
 725     case 0x14: /* MRIS */
 726         return s->mris;
 727     case 0x18: /* MMIS */
 728         return s->mris & s->mimr;
 729     case 0x20: /* MCR */
 730         return s->mcr;
 731     default:
 732         hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
 733         return 0;
 734     }
 735 }
 736
 737 static void stellaris_i2c_update(stellaris_i2c_state *s)
 738 {
 739     int level;
 740
 741     level = (s->mris & s->mimr) != 0;
 742     qemu_set_irq(s->irq, level);
 743 }
 744
 745 static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset,
 746                                 uint64_t value, unsigned size)
 747 {
 748     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 749
 750     switch (offset) {
 751     case 0x00: /* MSA */
 752         s->msa = value & 0xff;
 753         break;
 754     case 0x04: /* MCS */
 755         if ((s->mcr & 0x10) == 0) {
 756             /* Disabled.  Do nothing.  */
 757             break;
 758         }
 759         /* Grab the bus if this is starting a transfer.  */
 760         if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 761             if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
 762                 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
 763             } else {
 764                 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
 765                 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
 766             }
 767         }
 768         /* If we don't have the bus then indicate an error.  */
 769         if (!i2c_bus_busy(s->bus)
 770                 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 771             s->mcs |= STELLARIS_I2C_MCS_ERROR;
 772             break;
 773         }
 774         s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
 775         if (value & 1) {
 776             /* Transfer a byte.  */
 777             /* TODO: Handle errors.  */
 778             if (s->msa & 1) {
 779                 /* Recv */
 780                 s->mdr = i2c_recv(s->bus) & 0xff;
 781             } else {
 782                 /* Send */
 783                 i2c_send(s->bus, s->mdr);
 784             }
 785             /* Raise an interrupt.  */
 786             s->mris |= 1;
 787         }
 788         if (value & 4) {
 789             /* Finish transfer.  */
 790             i2c_end_transfer(s->bus);
 791             s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
 792         }
 793         break;
 794     case 0x08: /* MDR */
 795         s->mdr = value & 0xff;
 796         break;
 797     case 0x0c: /* MTPR */
 798         s->mtpr = value & 0xff;
 799         break;
 800     case 0x10: /* MIMR */
 801         s->mimr = 1;
 802         break;
 803     case 0x1c: /* MICR */
 804         s->mris &= ~value;
 805         break;
 806     case 0x20: /* MCR */
 807         if (value & 1)
 808             hw_error(
 809                       "stellaris_i2c_write: Loopback not implemented\n");
 810         if (value & 0x20)
 811             hw_error(
 812                       "stellaris_i2c_write: Slave mode not implemented\n");
 813         s->mcr = value & 0x31;
 814         break;
 815     default:
 816         hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
 817                   (int)offset);
 818     }
 819     stellaris_i2c_update(s);
 820 }
 821
 822 static void stellaris_i2c_reset(stellaris_i2c_state *s)
 823 {
 824     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
 825         i2c_end_transfer(s->bus);
 826
 827     s->msa = 0;
 828     s->mcs = 0;
 829     s->mdr = 0;
 830     s->mtpr = 1;
 831     s->mimr = 0;
 832     s->mris = 0;
 833     s->mcr = 0;
 834     stellaris_i2c_update(s);
 835 }
 836
 837 static const MemoryRegionOps stellaris_i2c_ops = {
 838     .read = stellaris_i2c_read,
 839     .write = stellaris_i2c_write,
 840     .endianness = DEVICE_NATIVE_ENDIAN,
 841 };
 842
 843 static const VMStateDescription vmstate_stellaris_i2c = {
 844     .name = "stellaris_i2c",
 845     .version_id = 1,
 846     .minimum_version_id = 1,
 847     .minimum_version_id_old = 1,
 848     .fields      = (VMStateField[]) {
 849         VMSTATE_UINT32(msa, stellaris_i2c_state),
 850         VMSTATE_UINT32(mcs, stellaris_i2c_state),
 851         VMSTATE_UINT32(mdr, stellaris_i2c_state),
 852         VMSTATE_UINT32(mtpr, stellaris_i2c_state),
 853         VMSTATE_UINT32(mimr, stellaris_i2c_state),
 854         VMSTATE_UINT32(mris, stellaris_i2c_state),
 855         VMSTATE_UINT32(mcr, stellaris_i2c_state),
 856         VMSTATE_END_OF_LIST()
 857     }
 858 };
 859
 860 static int stellaris_i2c_init(SysBusDevice * dev)
 861 {
 862     stellaris_i2c_state *s = FROM_SYSBUS(stellaris_i2c_state, dev);
 863     i2c_bus *bus;
 864
 865     sysbus_init_irq(dev, &s->irq);
 866     bus = i2c_init_bus(&dev->qdev, "i2c");
 867     s->bus = bus;
 868
 869     memory_region_init_io(&s->iomem, &stellaris_i2c_ops, s,
 870                           "i2c", 0x1000);
 871     sysbus_init_mmio_region(dev, &s->iomem);
 872     /* ??? For now we only implement the master interface.  */
 873     stellaris_i2c_reset(s);
 874     vmstate_register(&dev->qdev, -1, &vmstate_stellaris_i2c, s);
 875     return 0;
 876 }
 877
 878 /* Analogue to Digital Converter.  This is only partially implemented,
 879    enough for applications that use a combined ADC and timer tick.  */
 880
 881 #define STELLARIS_ADC_EM_CONTROLLER 0
 882 #define STELLARIS_ADC_EM_COMP       1
 883 #define STELLARIS_ADC_EM_EXTERNAL   4
 884 #define STELLARIS_ADC_EM_TIMER      5
 885 #define STELLARIS_ADC_EM_PWM0       6
 886 #define STELLARIS_ADC_EM_PWM1       7
 887 #define STELLARIS_ADC_EM_PWM2       8
 888
 889 #define STELLARIS_ADC_FIFO_EMPTY    0x0100
 890 #define STELLARIS_ADC_FIFO_FULL     0x1000
 891
 892 typedef struct
 893 {
 894     SysBusDevice busdev;
 895     MemoryRegion iomem;
 896     uint32_t actss;
 897     uint32_t ris;
 898     uint32_t im;
 899     uint32_t emux;
 900     uint32_t ostat;
 901     uint32_t ustat;
 902     uint32_t sspri;
 903     uint32_t sac;
 904     struct {
 905         uint32_t state;
 906         uint32_t data[16];
 907     } fifo[4];
 908     uint32_t ssmux[4];
 909     uint32_t ssctl[4];
 910     uint32_t noise;
 911     qemu_irq irq[4];
 912 } stellaris_adc_state;
 913
 914 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
 915 {
 916     int tail;
 917
 918     tail = s->fifo[n].state & 0xf;
 919     if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
 920         s->ustat |= 1 << n;
 921     } else {
 922         s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
 923         s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
 924         if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
 925             s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
 926     }
 927     return s->fifo[n].data[tail];
 928 }
 929
 930 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
 931                                      uint32_t value)
 932 {
 933     int head;
 934
 935     /* TODO: Real hardware has limited size FIFOs.  We have a full 16 entry
 936        FIFO fir each sequencer.  */
 937     head = (s->fifo[n].state >> 4) & 0xf;
 938     if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
 939         s->ostat |= 1 << n;
 940         return;
 941     }
 942     s->fifo[n].data[head] = value;
 943     head = (head + 1) & 0xf;
 944     s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
 945     s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
 946     if ((s->fifo[n].state & 0xf) == head)
 947         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
 948 }
 949
 950 static void stellaris_adc_update(stellaris_adc_state *s)
 951 {
 952     int level;
 953     int n;
 954
 955     for (n = 0; n < 4; n++) {
 956         level = (s->ris & s->im & (1 << n)) != 0;
 957         qemu_set_irq(s->irq[n], level);
 958     }
 959 }
 960
 961 static void stellaris_adc_trigger(void *opaque, int irq, int level)
 962 {
 963     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
 964     int n;
 965
 966     for (n = 0; n < 4; n++) {
 967         if ((s->actss & (1 << n)) == 0) {
 968             continue;
 969         }
 970
 971         if (((s->emux >> (n * 4)) & 0xff) != 5) {
 972             continue;
 973         }
 974
 975         /* Some applications use the ADC as a random number source, so introduce
 976            some variation into the signal.  */
 977         s->noise = s->noise * 314159 + 1;
 978         /* ??? actual inputs not implemented.  Return an arbitrary value.  */
 979         stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
 980         s->ris |= (1 << n);
 981         stellaris_adc_update(s);
 982     }
 983 }
 984
 985 static void stellaris_adc_reset(stellaris_adc_state *s)
 986 {
 987     int n;
 988
 989     for (n = 0; n < 4; n++) {
 990         s->ssmux[n] = 0;
 991         s->ssctl[n] = 0;
 992         s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
 993     }
 994 }
 995
 996 static uint64_t stellaris_adc_read(void *opaque, target_phys_addr_t offset,
 997                                    unsigned size)
 998 {
 999     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1000
1001     /* TODO: Implement this.  */
1002     if (offset >= 0x40 && offset < 0xc0) {
1003         int n;
1004         n = (offset - 0x40) >> 5;
1005         switch (offset & 0x1f) {
1006         case 0x00: /* SSMUX */
1007             return s->ssmux[n];
1008         case 0x04: /* SSCTL */
1009             return s->ssctl[n];
1010         case 0x08: /* SSFIFO */
1011             return stellaris_adc_fifo_read(s, n);
1012         case 0x0c: /* SSFSTAT */
1013             return s->fifo[n].state;
1014         default:
1015             break;
1016         }
1017     }
1018     switch (offset) {
1019     case 0x00: /* ACTSS */
1020         return s->actss;
1021     case 0x04: /* RIS */
1022         return s->ris;
1023     case 0x08: /* IM */
1024         return s->im;
1025     case 0x0c: /* ISC */
1026         return s->ris & s->im;
1027     case 0x10: /* OSTAT */
1028         return s->ostat;
1029     case 0x14: /* EMUX */
1030         return s->emux;
1031     case 0x18: /* USTAT */
1032         return s->ustat;
1033     case 0x20: /* SSPRI */
1034         return s->sspri;
1035     case 0x30: /* SAC */
1036         return s->sac;
1037     default:
1038         hw_error("strllaris_adc_read: Bad offset 0x%x\n",
1039                   (int)offset);
1040         return 0;
1041     }
1042 }
1043
1044 static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
1045                                 uint64_t value, unsigned size)
1046 {
1047     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1048
1049     /* TODO: Implement this.  */
1050     if (offset >= 0x40 && offset < 0xc0) {
1051         int n;
1052         n = (offset - 0x40) >> 5;
1053         switch (offset & 0x1f) {
1054         case 0x00: /* SSMUX */
1055             s->ssmux[n] = value & 0x33333333;
1056             return;
1057         case 0x04: /* SSCTL */
1058             if (value != 6) {
1059                 hw_error("ADC: Unimplemented sequence %" PRIx64 "\n",
1060                           value);
1061             }
1062             s->ssctl[n] = value;
1063             return;
1064         default:
1065             break;
1066         }
1067     }
1068     switch (offset) {
1069     case 0x00: /* ACTSS */
1070         s->actss = value & 0xf;
1071         break;
1072     case 0x08: /* IM */
1073         s->im = value;
1074         break;
1075     case 0x0c: /* ISC */
1076         s->ris &= ~value;
1077         break;
1078     case 0x10: /* OSTAT */
1079         s->ostat &= ~value;
1080         break;
1081     case 0x14: /* EMUX */
1082         s->emux = value;
1083         break;
1084     case 0x18: /* USTAT */
1085         s->ustat &= ~value;
1086         break;
1087     case 0x20: /* SSPRI */
1088         s->sspri = value;
1089         break;
1090     case 0x28: /* PSSI */
1091         hw_error("Not implemented:  ADC sample initiate\n");
1092         break;
1093     case 0x30: /* SAC */
1094         s->sac = value;
1095         break;
1096     default:
1097         hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
1098     }
1099     stellaris_adc_update(s);
1100 }
1101
1102 static const MemoryRegionOps stellaris_adc_ops = {
1103     .read = stellaris_adc_read,
1104     .write = stellaris_adc_write,
1105     .endianness = DEVICE_NATIVE_ENDIAN,
1106 };
1107
1108 static const VMStateDescription vmstate_stellaris_adc = {
1109     .name = "stellaris_adc",
1110     .version_id = 1,
1111     .minimum_version_id = 1,
1112     .minimum_version_id_old = 1,
1113     .fields      = (VMStateField[]) {
1114         VMSTATE_UINT32(actss, stellaris_adc_state),
1115         VMSTATE_UINT32(ris, stellaris_adc_state),
1116         VMSTATE_UINT32(im, stellaris_adc_state),
1117         VMSTATE_UINT32(emux, stellaris_adc_state),
1118         VMSTATE_UINT32(ostat, stellaris_adc_state),
1119         VMSTATE_UINT32(ustat, stellaris_adc_state),
1120         VMSTATE_UINT32(sspri, stellaris_adc_state),
1121         VMSTATE_UINT32(sac, stellaris_adc_state),
1122         VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1123         VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1124         VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1125         VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1126         VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1127         VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1128         VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1129         VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1130         VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1131         VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1132         VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1133         VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1134         VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1135         VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1136         VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1137         VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1138         VMSTATE_UINT32(noise, stellaris_adc_state),
1139         VMSTATE_END_OF_LIST()
1140     }
1141 };
1142
1143 static int stellaris_adc_init(SysBusDevice *dev)
1144 {
1145     stellaris_adc_state *s = FROM_SYSBUS(stellaris_adc_state, dev);
1146     int n;
1147
1148     for (n = 0; n < 4; n++) {
1149         sysbus_init_irq(dev, &s->irq[n]);
1150     }
1151
1152     memory_region_init_io(&s->iomem, &stellaris_adc_ops, s,
1153                           "adc", 0x1000);
1154     sysbus_init_mmio_region(dev, &s->iomem);
1155     stellaris_adc_reset(s);
1156     qdev_init_gpio_in(&dev->qdev, stellaris_adc_trigger, 1);
1157     vmstate_register(&dev->qdev, -1, &vmstate_stellaris_adc, s);
1158     return 0;
1159 }
1160
1161 /* Some boards have both an OLED controller and SD card connected to
1162    the same SSI port, with the SD card chip select connected to a
1163    GPIO pin.  Technically the OLED chip select is connected to the SSI
1164    Fss pin.  We do not bother emulating that as both devices should
1165    never be selected simultaneously, and our OLED controller ignores stray
1166    0xff commands that occur when deselecting the SD card.  */
1167
1168 typedef struct {
1169     SSISlave ssidev;
1170     qemu_irq irq;
1171     int current_dev;
1172     SSIBus *bus[2];
1173 } stellaris_ssi_bus_state;
1174
1175 static void stellaris_ssi_bus_select(void *opaque, int irq, int level)
1176 {
1177     stellaris_ssi_bus_state *s = (stellaris_ssi_bus_state *)opaque;
1178
1179     s->current_dev = level;
1180 }
1181
1182 static uint32_t stellaris_ssi_bus_transfer(SSISlave *dev, uint32_t val)
1183 {
1184     stellaris_ssi_bus_state *s = FROM_SSI_SLAVE(stellaris_ssi_bus_state, dev);
1185
1186     return ssi_transfer(s->bus[s->current_dev], val);
1187 }
1188
1189 static const VMStateDescription vmstate_stellaris_ssi_bus = {
1190     .name = "stellaris_ssi_bus",
1191     .version_id = 1,
1192     .minimum_version_id = 1,
1193     .minimum_version_id_old = 1,
1194     .fields      = (VMStateField[]) {
1195         VMSTATE_INT32(current_dev, stellaris_ssi_bus_state),
1196         VMSTATE_END_OF_LIST()
1197     }
1198 };
1199
1200 static int stellaris_ssi_bus_init(SSISlave *dev)
1201 {
1202     stellaris_ssi_bus_state *s = FROM_SSI_SLAVE(stellaris_ssi_bus_state, dev);
1203
1204     s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0");
1205     s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
1206     qdev_init_gpio_in(&dev->qdev, stellaris_ssi_bus_select, 1);
1207
1208     vmstate_register(&dev->qdev, -1, &vmstate_stellaris_ssi_bus, s);
1209     return 0;
1210 }
1211
1212 /* Board init.  */
1213 static stellaris_board_info stellaris_boards[] = {
1214   { "LM3S811EVB",
1215     0,
1216     0x0032000e,
1217     0x001f001f, /* dc0 */
1218     0x001132bf,
1219     0x01071013,
1220     0x3f0f01ff,
1221     0x0000001f,
1222     BP_OLED_I2C
1223   },
1224   { "LM3S6965EVB",
1225     0x10010002,
1226     0x1073402e,
1227     0x00ff007f, /* dc0 */
1228     0x001133ff,
1229     0x030f5317,
1230     0x0f0f87ff,
1231     0x5000007f,
1232     BP_OLED_SSI | BP_GAMEPAD
1233   }
1234 };
1235
1236 static void stellaris_init(const char *kernel_filename, const char *cpu_model,
1237                            stellaris_board_info *board)
1238 {
1239     static const int uart_irq[] = {5, 6, 33, 34};
1240     static const int timer_irq[] = {19, 21, 23, 35};
1241     static const uint32_t gpio_addr[7] =
1242       { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1243         0x40024000, 0x40025000, 0x40026000};
1244     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1245
1246     MemoryRegion *address_space_mem = get_system_memory();
1247     qemu_irq *pic;
1248     DeviceState *gpio_dev[7];
1249     qemu_irq gpio_in[7][8];
1250     qemu_irq gpio_out[7][8];
1251     qemu_irq adc;
1252     int sram_size;
1253     int flash_size;
1254     i2c_bus *i2c;
1255     DeviceState *dev;
1256     int i;
1257     int j;
1258
1259     flash_size = ((board->dc0 & 0xffff) + 1) << 1;
1260     sram_size = (board->dc0 >> 18) + 1;
1261     pic = armv7m_init(address_space_mem,
1262                       flash_size, sram_size, kernel_filename, cpu_model);
1263
1264     if (board->dc1 & (1 << 16)) {
1265         dev = sysbus_create_varargs("stellaris-adc", 0x40038000,
1266                                     pic[14], pic[15], pic[16], pic[17], NULL);
1267         adc = qdev_get_gpio_in(dev, 0);
1268     } else {
1269         adc = NULL;
1270     }
1271     for (i = 0; i < 4; i++) {
1272         if (board->dc2 & (0x10000 << i)) {
1273             dev = sysbus_create_simple("stellaris-gptm",
1274                                        0x40030000 + i * 0x1000,
1275                                        pic[timer_irq[i]]);
1276             /* TODO: This is incorrect, but we get away with it because
1277                the ADC output is only ever pulsed.  */
1278             qdev_connect_gpio_out(dev, 0, adc);
1279         }
1280     }
1281
1282     stellaris_sys_init(0x400fe000, pic[28], board, nd_table[0].macaddr.a);
1283
1284     for (i = 0; i < 7; i++) {
1285         if (board->dc4 & (1 << i)) {
1286             gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1287                                                pic[gpio_irq[i]]);
1288             for (j = 0; j < 8; j++) {
1289                 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1290                 gpio_out[i][j] = NULL;
1291             }
1292         }
1293     }
1294
1295     if (board->dc2 & (1 << 12)) {
1296         dev = sysbus_create_simple("stellaris-i2c", 0x40020000, pic[8]);
1297         i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
1298         if (board->peripherals & BP_OLED_I2C) {
1299             i2c_create_slave(i2c, "ssd0303", 0x3d);
1300         }
1301     }
1302
1303     for (i = 0; i < 4; i++) {
1304         if (board->dc2 & (1 << i)) {
1305             sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000,
1306                                  pic[uart_irq[i]]);
1307         }
1308     }
1309     if (board->dc2 & (1 << 4)) {
1310         dev = sysbus_create_simple("pl022", 0x40008000, pic[7]);
1311         if (board->peripherals & BP_OLED_SSI) {
1312             DeviceState *mux;
1313             void *bus;
1314
1315             bus = qdev_get_child_bus(dev, "ssi");
1316             mux = ssi_create_slave(bus, "evb6965-ssi");
1317             gpio_out[GPIO_D][0] = qdev_get_gpio_in(mux, 0);
1318
1319             bus = qdev_get_child_bus(mux, "ssi0");
1320             ssi_create_slave(bus, "ssi-sd");
1321
1322             bus = qdev_get_child_bus(mux, "ssi1");
1323             dev = ssi_create_slave(bus, "ssd0323");
1324             gpio_out[GPIO_C][7] = qdev_get_gpio_in(dev, 0);
1325
1326             /* Make sure the select pin is high.  */
1327             qemu_irq_raise(gpio_out[GPIO_D][0]);
1328         }
1329     }
1330     if (board->dc4 & (1 << 28)) {
1331         DeviceState *enet;
1332
1333         qemu_check_nic_model(&nd_table[0], "stellaris");
1334
1335         enet = qdev_create(NULL, "stellaris_enet");
1336         qdev_set_nic_properties(enet, &nd_table[0]);
1337         qdev_init_nofail(enet);
1338         sysbus_mmio_map(sysbus_from_qdev(enet), 0, 0x40048000);
1339         sysbus_connect_irq(sysbus_from_qdev(enet), 0, pic[42]);
1340     }
1341     if (board->peripherals & BP_GAMEPAD) {
1342         qemu_irq gpad_irq[5];
1343         static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1344
1345         gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1346         gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1347         gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1348         gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1349         gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1350
1351         stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1352     }
1353     for (i = 0; i < 7; i++) {
1354         if (board->dc4 & (1 << i)) {
1355             for (j = 0; j < 8; j++) {
1356                 if (gpio_out[i][j]) {
1357                     qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1358                 }
1359             }
1360         }
1361     }
1362 }
1363
1364 /* FIXME: Figure out how to generate these from stellaris_boards.  */
1365 static void lm3s811evb_init(ram_addr_t ram_size,
1366                      const char *boot_device,
1367                      const char *kernel_filename, const char *kernel_cmdline,
1368                      const char *initrd_filename, const char *cpu_model)
1369 {
1370     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
1371 }
1372
1373 static void lm3s6965evb_init(ram_addr_t ram_size,
1374                      const char *boot_device,
1375                      const char *kernel_filename, const char *kernel_cmdline,
1376                      const char *initrd_filename, const char *cpu_model)
1377 {
1378     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
1379 }
1380
1381 static QEMUMachine lm3s811evb_machine = {
1382     .name = "lm3s811evb",
1383     .desc = "Stellaris LM3S811EVB",
1384     .init = lm3s811evb_init,
1385 };
1386
1387 static QEMUMachine lm3s6965evb_machine = {
1388     .name = "lm3s6965evb",
1389     .desc = "Stellaris LM3S6965EVB",
1390     .init = lm3s6965evb_init,
1391 };
1392
1393 static void stellaris_machine_init(void)
1394 {
1395     qemu_register_machine(&lm3s811evb_machine);
1396     qemu_register_machine(&lm3s6965evb_machine);
1397 }
1398
1399 machine_init(stellaris_machine_init);
1400
1401 static SSISlaveInfo stellaris_ssi_bus_info = {
1402     .qdev.name = "evb6965-ssi",
1403     .qdev.size = sizeof(stellaris_ssi_bus_state),
1404     .init = stellaris_ssi_bus_init,
1405     .transfer = stellaris_ssi_bus_transfer
1406 };
1407
1408 static void stellaris_register_devices(void)
1409 {
1410     sysbus_register_dev("stellaris-i2c", sizeof(stellaris_i2c_state),
1411                         stellaris_i2c_init);
1412     sysbus_register_dev("stellaris-gptm", sizeof(gptm_state),
1413                         stellaris_gptm_init);
1414     sysbus_register_dev("stellaris-adc", sizeof(stellaris_adc_state),
1415                         stellaris_adc_init);
1416     ssi_register_slave(&stellaris_ssi_bus_info);
1417 }
1418
1419 device_init(stellaris_register_devices)