hw/strongarm.c

   1 /*
   2  * StrongARM SA-1100/SA-1110 emulation
   3  *
   4  * Copyright (C) 2011 Dmitry Eremin-Solenikov
   5  *
   6  * Largely based on StrongARM emulation:
   7  * Copyright (c) 2006 Openedhand Ltd.
   8  * Written by Andrzej Zaborowski <balrog@zabor.org>
   9  *
  10  * UART code based on QEMU 16550A UART emulation
  11  * Copyright (c) 2003-2004 Fabrice Bellard
  12  * Copyright (c) 2008 Citrix Systems, Inc.
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License version 2 as
  16  *  published by the Free Software Foundation.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License along
  24  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  25  *
  26  *  Contributions after 2012-01-13 are licensed under the terms of the
  27  *  GNU GPL, version 2 or (at your option) any later version.
  28  */
  29 #include "sysbus.h"
  30 #include "strongarm.h"
  31 #include "qemu-error.h"
  32 #include "arm-misc.h"
  33 #include "sysemu.h"
  34 #include "ssi.h"
  35
  36 //#define DEBUG
  37
  38 /*
  39  TODO
  40  - Implement cp15, c14 ?
  41  - Implement cp15, c15 !!! (idle used in L)
  42  - Implement idle mode handling/DIM
  43  - Implement sleep mode/Wake sources
  44  - Implement reset control
  45  - Implement memory control regs
  46  - PCMCIA handling
  47  - Maybe support MBGNT/MBREQ
  48  - DMA channels
  49  - GPCLK
  50  - IrDA
  51  - MCP
  52  - Enhance UART with modem signals
  53  */
  54
  55 #ifdef DEBUG
  56 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
  57 #else
  58 # define DPRINTF(format, ...) do { } while (0)
  59 #endif
  60
  61 static struct {
  62     target_phys_addr_t io_base;
  63     int irq;
  64 } sa_serial[] = {
  65     { 0x80010000, SA_PIC_UART1 },
  66     { 0x80030000, SA_PIC_UART2 },
  67     { 0x80050000, SA_PIC_UART3 },
  68     { 0, 0 }
  69 };
  70
  71 /* Interrupt Controller */
  72 typedef struct {
  73     SysBusDevice busdev;
  74     MemoryRegion iomem;
  75     qemu_irq    irq;
  76     qemu_irq    fiq;
  77
  78     uint32_t pending;
  79     uint32_t enabled;
  80     uint32_t is_fiq;
  81     uint32_t int_idle;
  82 } StrongARMPICState;
  83
  84 #define ICIP    0x00
  85 #define ICMR    0x04
  86 #define ICLR    0x08
  87 #define ICFP    0x10
  88 #define ICPR    0x20
  89 #define ICCR    0x0c
  90
  91 #define SA_PIC_SRCS     32
  92
  93
  94 static void strongarm_pic_update(void *opaque)
  95 {
  96     StrongARMPICState *s = opaque;
  97
  98     /* FIXME: reflect DIM */
  99     qemu_set_irq(s->fiq, s->pending & s->enabled &  s->is_fiq);
 100     qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
 101 }
 102
 103 static void strongarm_pic_set_irq(void *opaque, int irq, int level)
 104 {
 105     StrongARMPICState *s = opaque;
 106
 107     if (level) {
 108         s->pending |= 1 << irq;
 109     } else {
 110         s->pending &= ~(1 << irq);
 111     }
 112
 113     strongarm_pic_update(s);
 114 }
 115
 116 static uint64_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset,
 117                                        unsigned size)
 118 {
 119     StrongARMPICState *s = opaque;
 120
 121     switch (offset) {
 122     case ICIP:
 123         return s->pending & ~s->is_fiq & s->enabled;
 124     case ICMR:
 125         return s->enabled;
 126     case ICLR:
 127         return s->is_fiq;
 128     case ICCR:
 129         return s->int_idle == 0;
 130     case ICFP:
 131         return s->pending & s->is_fiq & s->enabled;
 132     case ICPR:
 133         return s->pending;
 134     default:
 135         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 136                         __func__, offset);
 137         return 0;
 138     }
 139 }
 140
 141 static void strongarm_pic_mem_write(void *opaque, target_phys_addr_t offset,
 142                                     uint64_t value, unsigned size)
 143 {
 144     StrongARMPICState *s = opaque;
 145
 146     switch (offset) {
 147     case ICMR:
 148         s->enabled = value;
 149         break;
 150     case ICLR:
 151         s->is_fiq = value;
 152         break;
 153     case ICCR:
 154         s->int_idle = (value & 1) ? 0 : ~0;
 155         break;
 156     default:
 157         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 158                         __func__, offset);
 159         break;
 160     }
 161     strongarm_pic_update(s);
 162 }
 163
 164 static const MemoryRegionOps strongarm_pic_ops = {
 165     .read = strongarm_pic_mem_read,
 166     .write = strongarm_pic_mem_write,
 167     .endianness = DEVICE_NATIVE_ENDIAN,
 168 };
 169
 170 static int strongarm_pic_initfn(SysBusDevice *dev)
 171 {
 172     StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev);
 173
 174     qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS);
 175     memory_region_init_io(&s->iomem, &strongarm_pic_ops, s, "pic", 0x1000);
 176     sysbus_init_mmio(dev, &s->iomem);
 177     sysbus_init_irq(dev, &s->irq);
 178     sysbus_init_irq(dev, &s->fiq);
 179
 180     return 0;
 181 }
 182
 183 static int strongarm_pic_post_load(void *opaque, int version_id)
 184 {
 185     strongarm_pic_update(opaque);
 186     return 0;
 187 }
 188
 189 static VMStateDescription vmstate_strongarm_pic_regs = {
 190     .name = "strongarm_pic",
 191     .version_id = 0,
 192     .minimum_version_id = 0,
 193     .minimum_version_id_old = 0,
 194     .post_load = strongarm_pic_post_load,
 195     .fields = (VMStateField[]) {
 196         VMSTATE_UINT32(pending, StrongARMPICState),
 197         VMSTATE_UINT32(enabled, StrongARMPICState),
 198         VMSTATE_UINT32(is_fiq, StrongARMPICState),
 199         VMSTATE_UINT32(int_idle, StrongARMPICState),
 200         VMSTATE_END_OF_LIST(),
 201     },
 202 };
 203
 204 static void strongarm_pic_class_init(ObjectClass *klass, void *data)
 205 {
 206     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 207
 208     k->init = strongarm_pic_initfn;
 209 }
 210
 211 static DeviceInfo strongarm_pic_info = {
 212     .name = "strongarm_pic",
 213     .desc = "StrongARM PIC",
 214     .size = sizeof(StrongARMPICState),
 215     .vmsd = &vmstate_strongarm_pic_regs,
 216     .class_init = strongarm_pic_class_init,
 217 };
 218
 219 /* Real-Time Clock */
 220 #define RTAR 0x00 /* RTC Alarm register */
 221 #define RCNR 0x04 /* RTC Counter register */
 222 #define RTTR 0x08 /* RTC Timer Trim register */
 223 #define RTSR 0x10 /* RTC Status register */
 224
 225 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
 226 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
 227 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
 228 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
 229
 230 /* 16 LSB of RTTR are clockdiv for internal trim logic,
 231  * trim delete isn't emulated, so
 232  * f = 32 768 / (RTTR_trim + 1) */
 233
 234 typedef struct {
 235     SysBusDevice busdev;
 236     MemoryRegion iomem;
 237     uint32_t rttr;
 238     uint32_t rtsr;
 239     uint32_t rtar;
 240     uint32_t last_rcnr;
 241     int64_t last_hz;
 242     QEMUTimer *rtc_alarm;
 243     QEMUTimer *rtc_hz;
 244     qemu_irq rtc_irq;
 245     qemu_irq rtc_hz_irq;
 246 } StrongARMRTCState;
 247
 248 static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
 249 {
 250     qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
 251     qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
 252 }
 253
 254 static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
 255 {
 256     int64_t rt = qemu_get_clock_ms(rt_clock);
 257     s->last_rcnr += ((rt - s->last_hz) << 15) /
 258             (1000 * ((s->rttr & 0xffff) + 1));
 259     s->last_hz = rt;
 260 }
 261
 262 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
 263 {
 264     if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
 265         qemu_mod_timer(s->rtc_hz, s->last_hz + 1000);
 266     } else {
 267         qemu_del_timer(s->rtc_hz);
 268     }
 269
 270     if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
 271         qemu_mod_timer(s->rtc_alarm, s->last_hz +
 272                 (((s->rtar - s->last_rcnr) * 1000 *
 273                   ((s->rttr & 0xffff) + 1)) >> 15));
 274     } else {
 275         qemu_del_timer(s->rtc_alarm);
 276     }
 277 }
 278
 279 static inline void strongarm_rtc_alarm_tick(void *opaque)
 280 {
 281     StrongARMRTCState *s = opaque;
 282     s->rtsr |= RTSR_AL;
 283     strongarm_rtc_timer_update(s);
 284     strongarm_rtc_int_update(s);
 285 }
 286
 287 static inline void strongarm_rtc_hz_tick(void *opaque)
 288 {
 289     StrongARMRTCState *s = opaque;
 290     s->rtsr |= RTSR_HZ;
 291     strongarm_rtc_timer_update(s);
 292     strongarm_rtc_int_update(s);
 293 }
 294
 295 static uint64_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr,
 296                                    unsigned size)
 297 {
 298     StrongARMRTCState *s = opaque;
 299
 300     switch (addr) {
 301     case RTTR:
 302         return s->rttr;
 303     case RTSR:
 304         return s->rtsr;
 305     case RTAR:
 306         return s->rtar;
 307     case RCNR:
 308         return s->last_rcnr +
 309                 ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
 310                 (1000 * ((s->rttr & 0xffff) + 1));
 311     default:
 312         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 313         return 0;
 314     }
 315 }
 316
 317 static void strongarm_rtc_write(void *opaque, target_phys_addr_t addr,
 318                                 uint64_t value, unsigned size)
 319 {
 320     StrongARMRTCState *s = opaque;
 321     uint32_t old_rtsr;
 322
 323     switch (addr) {
 324     case RTTR:
 325         strongarm_rtc_hzupdate(s);
 326         s->rttr = value;
 327         strongarm_rtc_timer_update(s);
 328         break;
 329
 330     case RTSR:
 331         old_rtsr = s->rtsr;
 332         s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
 333                   (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
 334
 335         if (s->rtsr != old_rtsr) {
 336             strongarm_rtc_timer_update(s);
 337         }
 338
 339         strongarm_rtc_int_update(s);
 340         break;
 341
 342     case RTAR:
 343         s->rtar = value;
 344         strongarm_rtc_timer_update(s);
 345         break;
 346
 347     case RCNR:
 348         strongarm_rtc_hzupdate(s);
 349         s->last_rcnr = value;
 350         strongarm_rtc_timer_update(s);
 351         break;
 352
 353     default:
 354         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 355     }
 356 }
 357
 358 static const MemoryRegionOps strongarm_rtc_ops = {
 359     .read = strongarm_rtc_read,
 360     .write = strongarm_rtc_write,
 361     .endianness = DEVICE_NATIVE_ENDIAN,
 362 };
 363
 364 static int strongarm_rtc_init(SysBusDevice *dev)
 365 {
 366     StrongARMRTCState *s = FROM_SYSBUS(StrongARMRTCState, dev);
 367     struct tm tm;
 368
 369     s->rttr = 0x0;
 370     s->rtsr = 0;
 371
 372     qemu_get_timedate(&tm, 0);
 373
 374     s->last_rcnr = (uint32_t) mktimegm(&tm);
 375     s->last_hz = qemu_get_clock_ms(rt_clock);
 376
 377     s->rtc_alarm = qemu_new_timer_ms(rt_clock, strongarm_rtc_alarm_tick, s);
 378     s->rtc_hz = qemu_new_timer_ms(rt_clock, strongarm_rtc_hz_tick, s);
 379
 380     sysbus_init_irq(dev, &s->rtc_irq);
 381     sysbus_init_irq(dev, &s->rtc_hz_irq);
 382
 383     memory_region_init_io(&s->iomem, &strongarm_rtc_ops, s, "rtc", 0x10000);
 384     sysbus_init_mmio(dev, &s->iomem);
 385
 386     return 0;
 387 }
 388
 389 static void strongarm_rtc_pre_save(void *opaque)
 390 {
 391     StrongARMRTCState *s = opaque;
 392
 393     strongarm_rtc_hzupdate(s);
 394 }
 395
 396 static int strongarm_rtc_post_load(void *opaque, int version_id)
 397 {
 398     StrongARMRTCState *s = opaque;
 399
 400     strongarm_rtc_timer_update(s);
 401     strongarm_rtc_int_update(s);
 402
 403     return 0;
 404 }
 405
 406 static const VMStateDescription vmstate_strongarm_rtc_regs = {
 407     .name = "strongarm-rtc",
 408     .version_id = 0,
 409     .minimum_version_id = 0,
 410     .minimum_version_id_old = 0,
 411     .pre_save = strongarm_rtc_pre_save,
 412     .post_load = strongarm_rtc_post_load,
 413     .fields = (VMStateField[]) {
 414         VMSTATE_UINT32(rttr, StrongARMRTCState),
 415         VMSTATE_UINT32(rtsr, StrongARMRTCState),
 416         VMSTATE_UINT32(rtar, StrongARMRTCState),
 417         VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
 418         VMSTATE_INT64(last_hz, StrongARMRTCState),
 419         VMSTATE_END_OF_LIST(),
 420     },
 421 };
 422
 423 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
 424 {
 425     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 426
 427     k->init = strongarm_rtc_init;
 428 }
 429
 430 static DeviceInfo strongarm_rtc_sysbus_info = {
 431     .name = "strongarm-rtc",
 432     .desc = "StrongARM RTC Controller",
 433     .size = sizeof(StrongARMRTCState),
 434     .vmsd = &vmstate_strongarm_rtc_regs,
 435     .class_init = strongarm_rtc_sysbus_class_init,
 436 };
 437
 438 /* GPIO */
 439 #define GPLR 0x00
 440 #define GPDR 0x04
 441 #define GPSR 0x08
 442 #define GPCR 0x0c
 443 #define GRER 0x10
 444 #define GFER 0x14
 445 #define GEDR 0x18
 446 #define GAFR 0x1c
 447
 448 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
 449 struct StrongARMGPIOInfo {
 450     SysBusDevice busdev;
 451     MemoryRegion iomem;
 452     qemu_irq handler[28];
 453     qemu_irq irqs[11];
 454     qemu_irq irqX;
 455
 456     uint32_t ilevel;
 457     uint32_t olevel;
 458     uint32_t dir;
 459     uint32_t rising;
 460     uint32_t falling;
 461     uint32_t status;
 462     uint32_t gpsr;
 463     uint32_t gafr;
 464
 465     uint32_t prev_level;
 466 };
 467
 468
 469 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
 470 {
 471     int i;
 472     for (i = 0; i < 11; i++) {
 473         qemu_set_irq(s->irqs[i], s->status & (1 << i));
 474     }
 475
 476     qemu_set_irq(s->irqX, (s->status & ~0x7ff));
 477 }
 478
 479 static void strongarm_gpio_set(void *opaque, int line, int level)
 480 {
 481     StrongARMGPIOInfo *s = opaque;
 482     uint32_t mask;
 483
 484     mask = 1 << line;
 485
 486     if (level) {
 487         s->status |= s->rising & mask &
 488                 ~s->ilevel & ~s->dir;
 489         s->ilevel |= mask;
 490     } else {
 491         s->status |= s->falling & mask &
 492                 s->ilevel & ~s->dir;
 493         s->ilevel &= ~mask;
 494     }
 495
 496     if (s->status & mask) {
 497         strongarm_gpio_irq_update(s);
 498     }
 499 }
 500
 501 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
 502 {
 503     uint32_t level, diff;
 504     int bit;
 505
 506     level = s->olevel & s->dir;
 507
 508     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 509         bit = ffs(diff) - 1;
 510         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 511     }
 512
 513     s->prev_level = level;
 514 }
 515
 516 static uint64_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset,
 517                                     unsigned size)
 518 {
 519     StrongARMGPIOInfo *s = opaque;
 520
 521     switch (offset) {
 522     case GPDR:        /* GPIO Pin-Direction registers */
 523         return s->dir;
 524
 525     case GPSR:        /* GPIO Pin-Output Set registers */
 526         DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
 527                         __func__, offset);
 528         return s->gpsr;    /* Return last written value.  */
 529
 530     case GPCR:        /* GPIO Pin-Output Clear registers */
 531         DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
 532                         __func__, offset);
 533         return 31337;        /* Specified as unpredictable in the docs.  */
 534
 535     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 536         return s->rising;
 537
 538     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 539         return s->falling;
 540
 541     case GAFR:        /* GPIO Alternate Function registers */
 542         return s->gafr;
 543
 544     case GPLR:        /* GPIO Pin-Level registers */
 545         return (s->olevel & s->dir) |
 546                (s->ilevel & ~s->dir);
 547
 548     case GEDR:        /* GPIO Edge Detect Status registers */
 549         return s->status;
 550
 551     default:
 552         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 553     }
 554
 555     return 0;
 556 }
 557
 558 static void strongarm_gpio_write(void *opaque, target_phys_addr_t offset,
 559                                  uint64_t value, unsigned size)
 560 {
 561     StrongARMGPIOInfo *s = opaque;
 562
 563     switch (offset) {
 564     case GPDR:        /* GPIO Pin-Direction registers */
 565         s->dir = value;
 566         strongarm_gpio_handler_update(s);
 567         break;
 568
 569     case GPSR:        /* GPIO Pin-Output Set registers */
 570         s->olevel |= value;
 571         strongarm_gpio_handler_update(s);
 572         s->gpsr = value;
 573         break;
 574
 575     case GPCR:        /* GPIO Pin-Output Clear registers */
 576         s->olevel &= ~value;
 577         strongarm_gpio_handler_update(s);
 578         break;
 579
 580     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 581         s->rising = value;
 582         break;
 583
 584     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 585         s->falling = value;
 586         break;
 587
 588     case GAFR:        /* GPIO Alternate Function registers */
 589         s->gafr = value;
 590         break;
 591
 592     case GEDR:        /* GPIO Edge Detect Status registers */
 593         s->status &= ~value;
 594         strongarm_gpio_irq_update(s);
 595         break;
 596
 597     default:
 598         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 599     }
 600 }
 601
 602 static const MemoryRegionOps strongarm_gpio_ops = {
 603     .read = strongarm_gpio_read,
 604     .write = strongarm_gpio_write,
 605     .endianness = DEVICE_NATIVE_ENDIAN,
 606 };
 607
 608 static DeviceState *strongarm_gpio_init(target_phys_addr_t base,
 609                 DeviceState *pic)
 610 {
 611     DeviceState *dev;
 612     int i;
 613
 614     dev = qdev_create(NULL, "strongarm-gpio");
 615     qdev_init_nofail(dev);
 616
 617     sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
 618     for (i = 0; i < 12; i++)
 619         sysbus_connect_irq(sysbus_from_qdev(dev), i,
 620                     qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
 621
 622     return dev;
 623 }
 624
 625 static int strongarm_gpio_initfn(SysBusDevice *dev)
 626 {
 627     StrongARMGPIOInfo *s;
 628     int i;
 629
 630     s = FROM_SYSBUS(StrongARMGPIOInfo, dev);
 631
 632     qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28);
 633     qdev_init_gpio_out(&dev->qdev, s->handler, 28);
 634
 635     memory_region_init_io(&s->iomem, &strongarm_gpio_ops, s, "gpio", 0x1000);
 636
 637     sysbus_init_mmio(dev, &s->iomem);
 638     for (i = 0; i < 11; i++) {
 639         sysbus_init_irq(dev, &s->irqs[i]);
 640     }
 641     sysbus_init_irq(dev, &s->irqX);
 642
 643     return 0;
 644 }
 645
 646 static const VMStateDescription vmstate_strongarm_gpio_regs = {
 647     .name = "strongarm-gpio",
 648     .version_id = 0,
 649     .minimum_version_id = 0,
 650     .minimum_version_id_old = 0,
 651     .fields = (VMStateField[]) {
 652         VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
 653         VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
 654         VMSTATE_UINT32(dir, StrongARMGPIOInfo),
 655         VMSTATE_UINT32(rising, StrongARMGPIOInfo),
 656         VMSTATE_UINT32(falling, StrongARMGPIOInfo),
 657         VMSTATE_UINT32(status, StrongARMGPIOInfo),
 658         VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
 659         VMSTATE_END_OF_LIST(),
 660     },
 661 };
 662
 663 static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
 664 {
 665     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 666
 667     k->init = strongarm_gpio_initfn;
 668 }
 669
 670 static DeviceInfo strongarm_gpio_info = {
 671     .name = "strongarm-gpio",
 672     .desc = "StrongARM GPIO controller",
 673     .size = sizeof(StrongARMGPIOInfo),
 674     .class_init = strongarm_gpio_class_init,
 675 };
 676
 677 /* Peripheral Pin Controller */
 678 #define PPDR 0x00
 679 #define PPSR 0x04
 680 #define PPAR 0x08
 681 #define PSDR 0x0c
 682 #define PPFR 0x10
 683
 684 typedef struct StrongARMPPCInfo StrongARMPPCInfo;
 685 struct StrongARMPPCInfo {
 686     SysBusDevice busdev;
 687     MemoryRegion iomem;
 688     qemu_irq handler[28];
 689
 690     uint32_t ilevel;
 691     uint32_t olevel;
 692     uint32_t dir;
 693     uint32_t ppar;
 694     uint32_t psdr;
 695     uint32_t ppfr;
 696
 697     uint32_t prev_level;
 698 };
 699
 700 static void strongarm_ppc_set(void *opaque, int line, int level)
 701 {
 702     StrongARMPPCInfo *s = opaque;
 703
 704     if (level) {
 705         s->ilevel |= 1 << line;
 706     } else {
 707         s->ilevel &= ~(1 << line);
 708     }
 709 }
 710
 711 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
 712 {
 713     uint32_t level, diff;
 714     int bit;
 715
 716     level = s->olevel & s->dir;
 717
 718     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 719         bit = ffs(diff) - 1;
 720         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 721     }
 722
 723     s->prev_level = level;
 724 }
 725
 726 static uint64_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset,
 727                                    unsigned size)
 728 {
 729     StrongARMPPCInfo *s = opaque;
 730
 731     switch (offset) {
 732     case PPDR:        /* PPC Pin Direction registers */
 733         return s->dir | ~0x3fffff;
 734
 735     case PPSR:        /* PPC Pin State registers */
 736         return (s->olevel & s->dir) |
 737                (s->ilevel & ~s->dir) |
 738                ~0x3fffff;
 739
 740     case PPAR:
 741         return s->ppar | ~0x41000;
 742
 743     case PSDR:
 744         return s->psdr;
 745
 746     case PPFR:
 747         return s->ppfr | ~0x7f001;
 748
 749     default:
 750         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 751     }
 752
 753     return 0;
 754 }
 755
 756 static void strongarm_ppc_write(void *opaque, target_phys_addr_t offset,
 757                                 uint64_t value, unsigned size)
 758 {
 759     StrongARMPPCInfo *s = opaque;
 760
 761     switch (offset) {
 762     case PPDR:        /* PPC Pin Direction registers */
 763         s->dir = value & 0x3fffff;
 764         strongarm_ppc_handler_update(s);
 765         break;
 766
 767     case PPSR:        /* PPC Pin State registers */
 768         s->olevel = value & s->dir & 0x3fffff;
 769         strongarm_ppc_handler_update(s);
 770         break;
 771
 772     case PPAR:
 773         s->ppar = value & 0x41000;
 774         break;
 775
 776     case PSDR:
 777         s->psdr = value & 0x3fffff;
 778         break;
 779
 780     case PPFR:
 781         s->ppfr = value & 0x7f001;
 782         break;
 783
 784     default:
 785         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 786     }
 787 }
 788
 789 static const MemoryRegionOps strongarm_ppc_ops = {
 790     .read = strongarm_ppc_read,
 791     .write = strongarm_ppc_write,
 792     .endianness = DEVICE_NATIVE_ENDIAN,
 793 };
 794
 795 static int strongarm_ppc_init(SysBusDevice *dev)
 796 {
 797     StrongARMPPCInfo *s;
 798
 799     s = FROM_SYSBUS(StrongARMPPCInfo, dev);
 800
 801     qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22);
 802     qdev_init_gpio_out(&dev->qdev, s->handler, 22);
 803
 804     memory_region_init_io(&s->iomem, &strongarm_ppc_ops, s, "ppc", 0x1000);
 805
 806     sysbus_init_mmio(dev, &s->iomem);
 807
 808     return 0;
 809 }
 810
 811 static const VMStateDescription vmstate_strongarm_ppc_regs = {
 812     .name = "strongarm-ppc",
 813     .version_id = 0,
 814     .minimum_version_id = 0,
 815     .minimum_version_id_old = 0,
 816     .fields = (VMStateField[]) {
 817         VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
 818         VMSTATE_UINT32(olevel, StrongARMPPCInfo),
 819         VMSTATE_UINT32(dir, StrongARMPPCInfo),
 820         VMSTATE_UINT32(ppar, StrongARMPPCInfo),
 821         VMSTATE_UINT32(psdr, StrongARMPPCInfo),
 822         VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
 823         VMSTATE_END_OF_LIST(),
 824     },
 825 };
 826
 827 static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
 828 {
 829     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 830
 831     k->init = strongarm_ppc_init;
 832 }
 833
 834 static DeviceInfo strongarm_ppc_info = {
 835     .name = "strongarm-ppc",
 836     .desc = "StrongARM PPC controller",
 837     .size = sizeof(StrongARMPPCInfo),
 838     .class_init = strongarm_ppc_class_init,
 839 };
 840
 841 /* UART Ports */
 842 #define UTCR0 0x00
 843 #define UTCR1 0x04
 844 #define UTCR2 0x08
 845 #define UTCR3 0x0c
 846 #define UTDR  0x14
 847 #define UTSR0 0x1c
 848 #define UTSR1 0x20
 849
 850 #define UTCR0_PE  (1 << 0) /* Parity enable */
 851 #define UTCR0_OES (1 << 1) /* Even parity */
 852 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
 853 #define UTCR0_DSS (1 << 3) /* 8-bit data */
 854
 855 #define UTCR3_RXE (1 << 0) /* Rx enable */
 856 #define UTCR3_TXE (1 << 1) /* Tx enable */
 857 #define UTCR3_BRK (1 << 2) /* Force Break */
 858 #define UTCR3_RIE (1 << 3) /* Rx int enable */
 859 #define UTCR3_TIE (1 << 4) /* Tx int enable */
 860 #define UTCR3_LBM (1 << 5) /* Loopback */
 861
 862 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
 863 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
 864 #define UTSR0_RID (1 << 2) /* Receiver Idle */
 865 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
 866 #define UTSR0_REB (1 << 4) /* Receiver end break */
 867 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
 868
 869 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
 870 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
 871 #define UTSR1_PRE (1 << 3) /* Parity error */
 872 #define UTSR1_FRE (1 << 4) /* Frame error */
 873 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
 874
 875 #define RX_FIFO_PRE (1 << 8)
 876 #define RX_FIFO_FRE (1 << 9)
 877 #define RX_FIFO_ROR (1 << 10)
 878
 879 typedef struct {
 880     SysBusDevice busdev;
 881     MemoryRegion iomem;
 882     CharDriverState *chr;
 883     qemu_irq irq;
 884
 885     uint8_t utcr0;
 886     uint16_t brd;
 887     uint8_t utcr3;
 888     uint8_t utsr0;
 889     uint8_t utsr1;
 890
 891     uint8_t tx_fifo[8];
 892     uint8_t tx_start;
 893     uint8_t tx_len;
 894     uint16_t rx_fifo[12]; /* value + error flags in high bits */
 895     uint8_t rx_start;
 896     uint8_t rx_len;
 897
 898     uint64_t char_transmit_time; /* time to transmit a char in ticks*/
 899     bool wait_break_end;
 900     QEMUTimer *rx_timeout_timer;
 901     QEMUTimer *tx_timer;
 902 } StrongARMUARTState;
 903
 904 static void strongarm_uart_update_status(StrongARMUARTState *s)
 905 {
 906     uint16_t utsr1 = 0;
 907
 908     if (s->tx_len != 8) {
 909         utsr1 |= UTSR1_TNF;
 910     }
 911
 912     if (s->rx_len != 0) {
 913         uint16_t ent = s->rx_fifo[s->rx_start];
 914
 915         utsr1 |= UTSR1_RNE;
 916         if (ent & RX_FIFO_PRE) {
 917             s->utsr1 |= UTSR1_PRE;
 918         }
 919         if (ent & RX_FIFO_FRE) {
 920             s->utsr1 |= UTSR1_FRE;
 921         }
 922         if (ent & RX_FIFO_ROR) {
 923             s->utsr1 |= UTSR1_ROR;
 924         }
 925     }
 926
 927     s->utsr1 = utsr1;
 928 }
 929
 930 static void strongarm_uart_update_int_status(StrongARMUARTState *s)
 931 {
 932     uint16_t utsr0 = s->utsr0 &
 933             (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
 934     int i;
 935
 936     if ((s->utcr3 & UTCR3_TXE) &&
 937                 (s->utcr3 & UTCR3_TIE) &&
 938                 s->tx_len <= 4) {
 939         utsr0 |= UTSR0_TFS;
 940     }
 941
 942     if ((s->utcr3 & UTCR3_RXE) &&
 943                 (s->utcr3 & UTCR3_RIE) &&
 944                 s->rx_len > 4) {
 945         utsr0 |= UTSR0_RFS;
 946     }
 947
 948     for (i = 0; i < s->rx_len && i < 4; i++)
 949         if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
 950             utsr0 |= UTSR0_EIF;
 951             break;
 952         }
 953
 954     s->utsr0 = utsr0;
 955     qemu_set_irq(s->irq, utsr0);
 956 }
 957
 958 static void strongarm_uart_update_parameters(StrongARMUARTState *s)
 959 {
 960     int speed, parity, data_bits, stop_bits, frame_size;
 961     QEMUSerialSetParams ssp;
 962
 963     /* Start bit. */
 964     frame_size = 1;
 965     if (s->utcr0 & UTCR0_PE) {
 966         /* Parity bit. */
 967         frame_size++;
 968         if (s->utcr0 & UTCR0_OES) {
 969             parity = 'E';
 970         } else {
 971             parity = 'O';
 972         }
 973     } else {
 974             parity = 'N';
 975     }
 976     if (s->utcr0 & UTCR0_SBS) {
 977         stop_bits = 2;
 978     } else {
 979         stop_bits = 1;
 980     }
 981
 982     data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
 983     frame_size += data_bits + stop_bits;
 984     speed = 3686400 / 16 / (s->brd + 1);
 985     ssp.speed = speed;
 986     ssp.parity = parity;
 987     ssp.data_bits = data_bits;
 988     ssp.stop_bits = stop_bits;
 989     s->char_transmit_time =  (get_ticks_per_sec() / speed) * frame_size;
 990     if (s->chr) {
 991         qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 992     }
 993
 994     DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
 995             speed, parity, data_bits, stop_bits);
 996 }
 997
 998 static void strongarm_uart_rx_to(void *opaque)
 999 {
1000     StrongARMUARTState *s = opaque;
1001
1002     if (s->rx_len) {
1003         s->utsr0 |= UTSR0_RID;
1004         strongarm_uart_update_int_status(s);
1005     }
1006 }
1007
1008 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1009 {
1010     if ((s->utcr3 & UTCR3_RXE) == 0) {
1011         /* rx disabled */
1012         return;
1013     }
1014
1015     if (s->wait_break_end) {
1016         s->utsr0 |= UTSR0_REB;
1017         s->wait_break_end = false;
1018     }
1019
1020     if (s->rx_len < 12) {
1021         s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1022         s->rx_len++;
1023     } else
1024         s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1025 }
1026
1027 static int strongarm_uart_can_receive(void *opaque)
1028 {
1029     StrongARMUARTState *s = opaque;
1030
1031     if (s->rx_len == 12) {
1032         return 0;
1033     }
1034     /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1035     if (s->rx_len < 8) {
1036         return 8 - s->rx_len;
1037     }
1038     return 1;
1039 }
1040
1041 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1042 {
1043     StrongARMUARTState *s = opaque;
1044     int i;
1045
1046     for (i = 0; i < size; i++) {
1047         strongarm_uart_rx_push(s, buf[i]);
1048     }
1049
1050     /* call the timeout receive callback in 3 char transmit time */
1051     qemu_mod_timer(s->rx_timeout_timer,
1052                     qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1053
1054     strongarm_uart_update_status(s);
1055     strongarm_uart_update_int_status(s);
1056 }
1057
1058 static void strongarm_uart_event(void *opaque, int event)
1059 {
1060     StrongARMUARTState *s = opaque;
1061     if (event == CHR_EVENT_BREAK) {
1062         s->utsr0 |= UTSR0_RBB;
1063         strongarm_uart_rx_push(s, RX_FIFO_FRE);
1064         s->wait_break_end = true;
1065         strongarm_uart_update_status(s);
1066         strongarm_uart_update_int_status(s);
1067     }
1068 }
1069
1070 static void strongarm_uart_tx(void *opaque)
1071 {
1072     StrongARMUARTState *s = opaque;
1073     uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
1074
1075     if (s->utcr3 & UTCR3_LBM) /* loopback */ {
1076         strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1077     } else if (s->chr) {
1078         qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1);
1079     }
1080
1081     s->tx_start = (s->tx_start + 1) % 8;
1082     s->tx_len--;
1083     if (s->tx_len) {
1084         qemu_mod_timer(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1085     }
1086     strongarm_uart_update_status(s);
1087     strongarm_uart_update_int_status(s);
1088 }
1089
1090 static uint64_t strongarm_uart_read(void *opaque, target_phys_addr_t addr,
1091                                     unsigned size)
1092 {
1093     StrongARMUARTState *s = opaque;
1094     uint16_t ret;
1095
1096     switch (addr) {
1097     case UTCR0:
1098         return s->utcr0;
1099
1100     case UTCR1:
1101         return s->brd >> 8;
1102
1103     case UTCR2:
1104         return s->brd & 0xff;
1105
1106     case UTCR3:
1107         return s->utcr3;
1108
1109     case UTDR:
1110         if (s->rx_len != 0) {
1111             ret = s->rx_fifo[s->rx_start];
1112             s->rx_start = (s->rx_start + 1) % 12;
1113             s->rx_len--;
1114             strongarm_uart_update_status(s);
1115             strongarm_uart_update_int_status(s);
1116             return ret;
1117         }
1118         return 0;
1119
1120     case UTSR0:
1121         return s->utsr0;
1122
1123     case UTSR1:
1124         return s->utsr1;
1125
1126     default:
1127         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1128         return 0;
1129     }
1130 }
1131
1132 static void strongarm_uart_write(void *opaque, target_phys_addr_t addr,
1133                                  uint64_t value, unsigned size)
1134 {
1135     StrongARMUARTState *s = opaque;
1136
1137     switch (addr) {
1138     case UTCR0:
1139         s->utcr0 = value & 0x7f;
1140         strongarm_uart_update_parameters(s);
1141         break;
1142
1143     case UTCR1:
1144         s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1145         strongarm_uart_update_parameters(s);
1146         break;
1147
1148     case UTCR2:
1149         s->brd = (s->brd & 0xf00) | (value & 0xff);
1150         strongarm_uart_update_parameters(s);
1151         break;
1152
1153     case UTCR3:
1154         s->utcr3 = value & 0x3f;
1155         if ((s->utcr3 & UTCR3_RXE) == 0) {
1156             s->rx_len = 0;
1157         }
1158         if ((s->utcr3 & UTCR3_TXE) == 0) {
1159             s->tx_len = 0;
1160         }
1161         strongarm_uart_update_status(s);
1162         strongarm_uart_update_int_status(s);
1163         break;
1164
1165     case UTDR:
1166         if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1167             s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1168             s->tx_len++;
1169             strongarm_uart_update_status(s);
1170             strongarm_uart_update_int_status(s);
1171             if (s->tx_len == 1) {
1172                 strongarm_uart_tx(s);
1173             }
1174         }
1175         break;
1176
1177     case UTSR0:
1178         s->utsr0 = s->utsr0 & ~(value &
1179                 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1180         strongarm_uart_update_int_status(s);
1181         break;
1182
1183     default:
1184         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1185     }
1186 }
1187
1188 static const MemoryRegionOps strongarm_uart_ops = {
1189     .read = strongarm_uart_read,
1190     .write = strongarm_uart_write,
1191     .endianness = DEVICE_NATIVE_ENDIAN,
1192 };
1193
1194 static int strongarm_uart_init(SysBusDevice *dev)
1195 {
1196     StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev);
1197
1198     memory_region_init_io(&s->iomem, &strongarm_uart_ops, s, "uart", 0x10000);
1199     sysbus_init_mmio(dev, &s->iomem);
1200     sysbus_init_irq(dev, &s->irq);
1201
1202     s->rx_timeout_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_rx_to, s);
1203     s->tx_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_tx, s);
1204
1205     if (s->chr) {
1206         qemu_chr_add_handlers(s->chr,
1207                         strongarm_uart_can_receive,
1208                         strongarm_uart_receive,
1209                         strongarm_uart_event,
1210                         s);
1211     }
1212
1213     return 0;
1214 }
1215
1216 static void strongarm_uart_reset(DeviceState *dev)
1217 {
1218     StrongARMUARTState *s = DO_UPCAST(StrongARMUARTState, busdev.qdev, dev);
1219
1220     s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
1221     s->brd = 23;    /* 9600 */
1222     /* enable send & recv - this actually violates spec */
1223     s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1224
1225     s->rx_len = s->tx_len = 0;
1226
1227     strongarm_uart_update_parameters(s);
1228     strongarm_uart_update_status(s);
1229     strongarm_uart_update_int_status(s);
1230 }
1231
1232 static int strongarm_uart_post_load(void *opaque, int version_id)
1233 {
1234     StrongARMUARTState *s = opaque;
1235
1236     strongarm_uart_update_parameters(s);
1237     strongarm_uart_update_status(s);
1238     strongarm_uart_update_int_status(s);
1239
1240     /* tx and restart timer */
1241     if (s->tx_len) {
1242         strongarm_uart_tx(s);
1243     }
1244
1245     /* restart rx timeout timer */
1246     if (s->rx_len) {
1247         qemu_mod_timer(s->rx_timeout_timer,
1248                 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1249     }
1250
1251     return 0;
1252 }
1253
1254 static const VMStateDescription vmstate_strongarm_uart_regs = {
1255     .name = "strongarm-uart",
1256     .version_id = 0,
1257     .minimum_version_id = 0,
1258     .minimum_version_id_old = 0,
1259     .post_load = strongarm_uart_post_load,
1260     .fields = (VMStateField[]) {
1261         VMSTATE_UINT8(utcr0, StrongARMUARTState),
1262         VMSTATE_UINT16(brd, StrongARMUARTState),
1263         VMSTATE_UINT8(utcr3, StrongARMUARTState),
1264         VMSTATE_UINT8(utsr0, StrongARMUARTState),
1265         VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1266         VMSTATE_UINT8(tx_start, StrongARMUARTState),
1267         VMSTATE_UINT8(tx_len, StrongARMUARTState),
1268         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1269         VMSTATE_UINT8(rx_start, StrongARMUARTState),
1270         VMSTATE_UINT8(rx_len, StrongARMUARTState),
1271         VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1272         VMSTATE_END_OF_LIST(),
1273     },
1274 };
1275
1276 static Property strongarm_uart_properties[] = {
1277     DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1278     DEFINE_PROP_END_OF_LIST(),
1279 };
1280
1281 static void strongarm_uart_class_init(ObjectClass *klass, void *data)
1282 {
1283     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1284
1285     k->init = strongarm_uart_init;
1286 }
1287
1288 static DeviceInfo strongarm_uart_info = {
1289     .name = "strongarm-uart",
1290     .desc = "StrongARM UART controller",
1291     .size = sizeof(StrongARMUARTState),
1292     .reset = strongarm_uart_reset,
1293     .vmsd = &vmstate_strongarm_uart_regs,
1294     .props = strongarm_uart_properties,
1295     .class_init = strongarm_uart_class_init,
1296 };
1297
1298 /* Synchronous Serial Ports */
1299 typedef struct {
1300     SysBusDevice busdev;
1301     MemoryRegion iomem;
1302     qemu_irq irq;
1303     SSIBus *bus;
1304
1305     uint16_t sscr[2];
1306     uint16_t sssr;
1307
1308     uint16_t rx_fifo[8];
1309     uint8_t rx_level;
1310     uint8_t rx_start;
1311 } StrongARMSSPState;
1312
1313 #define SSCR0 0x60 /* SSP Control register 0 */
1314 #define SSCR1 0x64 /* SSP Control register 1 */
1315 #define SSDR  0x6c /* SSP Data register */
1316 #define SSSR  0x74 /* SSP Status register */
1317
1318 /* Bitfields for above registers */
1319 #define SSCR0_SPI(x)    (((x) & 0x30) == 0x00)
1320 #define SSCR0_SSP(x)    (((x) & 0x30) == 0x10)
1321 #define SSCR0_UWIRE(x)  (((x) & 0x30) == 0x20)
1322 #define SSCR0_PSP(x)    (((x) & 0x30) == 0x30)
1323 #define SSCR0_SSE       (1 << 7)
1324 #define SSCR0_DSS(x)    (((x) & 0xf) + 1)
1325 #define SSCR1_RIE       (1 << 0)
1326 #define SSCR1_TIE       (1 << 1)
1327 #define SSCR1_LBM       (1 << 2)
1328 #define SSSR_TNF        (1 << 2)
1329 #define SSSR_RNE        (1 << 3)
1330 #define SSSR_TFS        (1 << 5)
1331 #define SSSR_RFS        (1 << 6)
1332 #define SSSR_ROR        (1 << 7)
1333 #define SSSR_RW         0x0080
1334
1335 static void strongarm_ssp_int_update(StrongARMSSPState *s)
1336 {
1337     int level = 0;
1338
1339     level |= (s->sssr & SSSR_ROR);
1340     level |= (s->sssr & SSSR_RFS)  &&  (s->sscr[1] & SSCR1_RIE);
1341     level |= (s->sssr & SSSR_TFS)  &&  (s->sscr[1] & SSCR1_TIE);
1342     qemu_set_irq(s->irq, level);
1343 }
1344
1345 static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1346 {
1347     s->sssr &= ~SSSR_TFS;
1348     s->sssr &= ~SSSR_TNF;
1349     if (s->sscr[0] & SSCR0_SSE) {
1350         if (s->rx_level >= 4) {
1351             s->sssr |= SSSR_RFS;
1352         } else {
1353             s->sssr &= ~SSSR_RFS;
1354         }
1355         if (s->rx_level) {
1356             s->sssr |= SSSR_RNE;
1357         } else {
1358             s->sssr &= ~SSSR_RNE;
1359         }
1360         /* TX FIFO is never filled, so it is always in underrun
1361            condition if SSP is enabled */
1362         s->sssr |= SSSR_TFS;
1363         s->sssr |= SSSR_TNF;
1364     }
1365
1366     strongarm_ssp_int_update(s);
1367 }
1368
1369 static uint64_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr,
1370                                    unsigned size)
1371 {
1372     StrongARMSSPState *s = opaque;
1373     uint32_t retval;
1374
1375     switch (addr) {
1376     case SSCR0:
1377         return s->sscr[0];
1378     case SSCR1:
1379         return s->sscr[1];
1380     case SSSR:
1381         return s->sssr;
1382     case SSDR:
1383         if (~s->sscr[0] & SSCR0_SSE) {
1384             return 0xffffffff;
1385         }
1386         if (s->rx_level < 1) {
1387             printf("%s: SSP Rx Underrun\n", __func__);
1388             return 0xffffffff;
1389         }
1390         s->rx_level--;
1391         retval = s->rx_fifo[s->rx_start++];
1392         s->rx_start &= 0x7;
1393         strongarm_ssp_fifo_update(s);
1394         return retval;
1395     default:
1396         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1397         break;
1398     }
1399     return 0;
1400 }
1401
1402 static void strongarm_ssp_write(void *opaque, target_phys_addr_t addr,
1403                                 uint64_t value, unsigned size)
1404 {
1405     StrongARMSSPState *s = opaque;
1406
1407     switch (addr) {
1408     case SSCR0:
1409         s->sscr[0] = value & 0xffbf;
1410         if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1411             printf("%s: Wrong data size: %i bits\n", __func__,
1412                    (int)SSCR0_DSS(value));
1413         }
1414         if (!(value & SSCR0_SSE)) {
1415             s->sssr = 0;
1416             s->rx_level = 0;
1417         }
1418         strongarm_ssp_fifo_update(s);
1419         break;
1420
1421     case SSCR1:
1422         s->sscr[1] = value & 0x2f;
1423         if (value & SSCR1_LBM) {
1424             printf("%s: Attempt to use SSP LBM mode\n", __func__);
1425         }
1426         strongarm_ssp_fifo_update(s);
1427         break;
1428
1429     case SSSR:
1430         s->sssr &= ~(value & SSSR_RW);
1431         strongarm_ssp_int_update(s);
1432         break;
1433
1434     case SSDR:
1435         if (SSCR0_UWIRE(s->sscr[0])) {
1436             value &= 0xff;
1437         } else
1438             /* Note how 32bits overflow does no harm here */
1439             value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1440
1441         /* Data goes from here to the Tx FIFO and is shifted out from
1442          * there directly to the slave, no need to buffer it.
1443          */
1444         if (s->sscr[0] & SSCR0_SSE) {
1445             uint32_t readval;
1446             if (s->sscr[1] & SSCR1_LBM) {
1447                 readval = value;
1448             } else {
1449                 readval = ssi_transfer(s->bus, value);
1450             }
1451
1452             if (s->rx_level < 0x08) {
1453                 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1454             } else {
1455                 s->sssr |= SSSR_ROR;
1456             }
1457         }
1458         strongarm_ssp_fifo_update(s);
1459         break;
1460
1461     default:
1462         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1463         break;
1464     }
1465 }
1466
1467 static const MemoryRegionOps strongarm_ssp_ops = {
1468     .read = strongarm_ssp_read,
1469     .write = strongarm_ssp_write,
1470     .endianness = DEVICE_NATIVE_ENDIAN,
1471 };
1472
1473 static int strongarm_ssp_post_load(void *opaque, int version_id)
1474 {
1475     StrongARMSSPState *s = opaque;
1476
1477     strongarm_ssp_fifo_update(s);
1478
1479     return 0;
1480 }
1481
1482 static int strongarm_ssp_init(SysBusDevice *dev)
1483 {
1484     StrongARMSSPState *s = FROM_SYSBUS(StrongARMSSPState, dev);
1485
1486     sysbus_init_irq(dev, &s->irq);
1487
1488     memory_region_init_io(&s->iomem, &strongarm_ssp_ops, s, "ssp", 0x1000);
1489     sysbus_init_mmio(dev, &s->iomem);
1490
1491     s->bus = ssi_create_bus(&dev->qdev, "ssi");
1492     return 0;
1493 }
1494
1495 static void strongarm_ssp_reset(DeviceState *dev)
1496 {
1497     StrongARMSSPState *s = DO_UPCAST(StrongARMSSPState, busdev.qdev, dev);
1498     s->sssr = 0x03; /* 3 bit data, SPI, disabled */
1499     s->rx_start = 0;
1500     s->rx_level = 0;
1501 }
1502
1503 static const VMStateDescription vmstate_strongarm_ssp_regs = {
1504     .name = "strongarm-ssp",
1505     .version_id = 0,
1506     .minimum_version_id = 0,
1507     .minimum_version_id_old = 0,
1508     .post_load = strongarm_ssp_post_load,
1509     .fields = (VMStateField[]) {
1510         VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1511         VMSTATE_UINT16(sssr, StrongARMSSPState),
1512         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1513         VMSTATE_UINT8(rx_start, StrongARMSSPState),
1514         VMSTATE_UINT8(rx_level, StrongARMSSPState),
1515         VMSTATE_END_OF_LIST(),
1516     },
1517 };
1518
1519 static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
1520 {
1521     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1522
1523     k->init = strongarm_ssp_init;
1524 }
1525
1526 static DeviceInfo strongarm_ssp_info = {
1527     .name = "strongarm-ssp",
1528     .desc = "StrongARM SSP controller",
1529     .size = sizeof(StrongARMSSPState),
1530     .reset = strongarm_ssp_reset,
1531     .vmsd = &vmstate_strongarm_ssp_regs,
1532     .class_init = strongarm_ssp_class_init,
1533 };
1534
1535 /* Main CPU functions */
1536 StrongARMState *sa1110_init(MemoryRegion *sysmem,
1537                             unsigned int sdram_size, const char *rev)
1538 {
1539     StrongARMState *s;
1540     qemu_irq *pic;
1541     int i;
1542
1543     s = g_malloc0(sizeof(StrongARMState));
1544
1545     if (!rev) {
1546         rev = "sa1110-b5";
1547     }
1548
1549     if (strncmp(rev, "sa1110", 6)) {
1550         error_report("Machine requires a SA1110 processor.");
1551         exit(1);
1552     }
1553
1554     s->env = cpu_init(rev);
1555
1556     if (!s->env) {
1557         error_report("Unable to find CPU definition");
1558         exit(1);
1559     }
1560
1561     memory_region_init_ram(&s->sdram, "strongarm.sdram", sdram_size);
1562     vmstate_register_ram_global(&s->sdram);
1563     memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
1564
1565     pic = arm_pic_init_cpu(s->env);
1566     s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1567                     pic[ARM_PIC_CPU_IRQ], pic[ARM_PIC_CPU_FIQ], NULL);
1568
1569     sysbus_create_varargs("pxa25x-timer", 0x90000000,
1570                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1571                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1572                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1573                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1574                     NULL);
1575
1576     sysbus_create_simple("strongarm-rtc", 0x90010000,
1577                     qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1578
1579     s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1580
1581     s->ppc = sysbus_create_varargs("strongarm-ppc", 0x90060000, NULL);
1582
1583     for (i = 0; sa_serial[i].io_base; i++) {
1584         DeviceState *dev = qdev_create(NULL, "strongarm-uart");
1585         qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
1586         qdev_init_nofail(dev);
1587         sysbus_mmio_map(sysbus_from_qdev(dev), 0,
1588                 sa_serial[i].io_base);
1589         sysbus_connect_irq(sysbus_from_qdev(dev), 0,
1590                 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1591     }
1592
1593     s->ssp = sysbus_create_varargs("strongarm-ssp", 0x80070000,
1594                 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1595     s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1596
1597     return s;
1598 }
1599
1600 static void strongarm_register_devices(void)
1601 {
1602     sysbus_register_withprop(&strongarm_pic_info);
1603     sysbus_register_withprop(&strongarm_rtc_sysbus_info);
1604     sysbus_register_withprop(&strongarm_gpio_info);
1605     sysbus_register_withprop(&strongarm_ppc_info);
1606     sysbus_register_withprop(&strongarm_uart_info);
1607     sysbus_register_withprop(&strongarm_ssp_info);
1608 }
1609 device_init(strongarm_register_devices)