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1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38
39 //#define DEBUG_IRQ
40
41 /*
42 * Sun4m architecture was used in the following machines:
43 *
44 * SPARCserver 6xxMP/xx
45 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
46 * SPARCclassic X (4/10)
47 * SPARCstation LX/ZX (4/30)
48 * SPARCstation Voyager
49 * SPARCstation 10/xx, SPARCserver 10/xx
50 * SPARCstation 5, SPARCserver 5
51 * SPARCstation 20/xx, SPARCserver 20
52 * SPARCstation 4
53 *
54 * Sun4d architecture was used in the following machines:
55 *
56 * SPARCcenter 2000
57 * SPARCserver 1000
58 *
59 * Sun4c architecture was used in the following machines:
60 * SPARCstation 1/1+, SPARCserver 1/1+
61 * SPARCstation SLC
62 * SPARCstation IPC
63 * SPARCstation ELC
64 * SPARCstation IPX
65 *
66 * See for example: http://www.sunhelp.org/faq/sunref1.html
67 */
68
69 #ifdef DEBUG_IRQ
70 #define DPRINTF(fmt, args...) \
71 do { printf("CPUIRQ: " fmt , ##args); } while (0)
72 #else
73 #define DPRINTF(fmt, args...)
74 #endif
75
76 #define KERNEL_LOAD_ADDR 0x00004000
77 #define CMDLINE_ADDR 0x007ff000
78 #define INITRD_LOAD_ADDR 0x00800000
79 #define PROM_SIZE_MAX (1024 * 1024)
80 #define PROM_VADDR 0xffd00000
81 #define PROM_FILENAME "openbios-sparc32"
82 #define CFG_ADDR 0xd00000510ULL
83 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
84
85 // Control plane, 8-bit and 24-bit planes
86 #define TCX_SIZE (9 * 1024 * 1024)
87
88 #define MAX_CPUS 16
89 #define MAX_PILS 16
90
91 struct sun4m_hwdef {
92 target_phys_addr_t iommu_base, slavio_base;
93 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94 target_phys_addr_t serial_base, fd_base;
95 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
96 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 target_phys_addr_t ecc_base;
98 uint32_t ecc_version;
99 long vram_size, nvram_size;
100 // IRQ numbers are not PIL ones, but master interrupt controller
101 // register bit numbers
102 int esp_irq, le_irq, clock_irq, clock1_irq;
103 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104 uint8_t nvram_machine_id;
105 uint16_t machine_id;
106 uint32_t iommu_version;
107 uint32_t intbit_to_level[32];
108 uint64_t max_mem;
109 const char * const default_cpu_model;
110 };
111
112 #define MAX_IOUNITS 5
113
114 struct sun4d_hwdef {
115 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117 target_phys_addr_t serial_base;
118 target_phys_addr_t espdma_base, esp_base;
119 target_phys_addr_t ledma_base, le_base;
120 target_phys_addr_t tcx_base;
121 target_phys_addr_t sbi_base;
122 unsigned long vram_size, nvram_size;
123 // IRQ numbers are not PIL ones, but SBI register bit numbers
124 int esp_irq, le_irq, clock_irq, clock1_irq;
125 int ser_irq, ms_kb_irq, me_irq;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 struct sun4c_hwdef {
134 target_phys_addr_t iommu_base, slavio_base;
135 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136 target_phys_addr_t serial_base, fd_base;
137 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138 target_phys_addr_t tcx_base, aux1_base;
139 long vram_size, nvram_size;
140 // IRQ numbers are not PIL ones, but master interrupt controller
141 // register bit numbers
142 int esp_irq, le_irq, clock_irq, clock1_irq;
143 int ser_irq, ms_kb_irq, fd_irq, me_irq;
144 uint8_t nvram_machine_id;
145 uint16_t machine_id;
146 uint32_t iommu_version;
147 uint32_t intbit_to_level[32];
148 uint64_t max_mem;
149 const char * const default_cpu_model;
150 };
151
152 int DMA_get_channel_mode (int nchan)
153 {
154 return 0;
155 }
156 int DMA_read_memory (int nchan, void *buf, int pos, int size)
157 {
158 return 0;
159 }
160 int DMA_write_memory (int nchan, void *buf, int pos, int size)
161 {
162 return 0;
163 }
164 void DMA_hold_DREQ (int nchan) {}
165 void DMA_release_DREQ (int nchan) {}
166 void DMA_schedule(int nchan) {}
167 void DMA_init (int high_page_enable) {}
168 void DMA_register_channel (int nchan,
169 DMA_transfer_handler transfer_handler,
170 void *opaque)
171 {
172 }
173
174 static int nvram_boot_set(void *opaque, const char *boot_device)
175 {
176 unsigned int i;
177 uint8_t image[sizeof(ohwcfg_v3_t)];
178 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
179 m48t59_t *nvram = (m48t59_t *)opaque;
180
181 for (i = 0; i < sizeof(image); i++)
182 image[i] = m48t59_read(nvram, i) & 0xff;
183
184 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
185 boot_device);
186 header->nboot_devices = strlen(boot_device) & 0xff;
187 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
188
189 for (i = 0; i < sizeof(image); i++)
190 m48t59_write(nvram, i, image[i]);
191
192 return 0;
193 }
194
195 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
196 const char *boot_devices, ram_addr_t RAM_size,
197 uint32_t kernel_size,
198 int width, int height, int depth,
199 int nvram_machine_id, const char *arch)
200 {
201 unsigned int i;
202 uint32_t start, end;
203 uint8_t image[0x1ff0];
204 ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
205 struct sparc_arch_cfg *sparc_header;
206 struct OpenBIOS_nvpart_v1 *part_header;
207
208 memset(image, '\0', sizeof(image));
209
210 // Try to match PPC NVRAM
211 pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
212 "QEMU_BIOS");
213 header->struct_version = cpu_to_be32(3); /* structure v3 */
214
215 header->nvram_size = cpu_to_be16(0x2000);
216 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
217 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
218 pstrcpy((char *)header->arch, sizeof(header->arch), arch);
219 header->nb_cpus = smp_cpus & 0xff;
220 header->RAM0_base = 0;
221 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
222 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
223 boot_devices);
224 header->nboot_devices = strlen(boot_devices) & 0xff;
225 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
226 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
227 if (cmdline) {
228 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
229 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
230 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
231 }
232 // XXX add initrd_image, initrd_size
233 header->width = cpu_to_be16(width);
234 header->height = cpu_to_be16(height);
235 header->depth = cpu_to_be16(depth);
236 if (nographic)
237 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
238
239 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
240
241 // Architecture specific header
242 start = sizeof(ohwcfg_v3_t);
243 sparc_header = (struct sparc_arch_cfg *)&image[start];
244 sparc_header->valid = 0;
245 start += sizeof(struct sparc_arch_cfg);
246
247 // OpenBIOS nvram variables
248 // Variable partition
249 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
250 part_header->signature = OPENBIOS_PART_SYSTEM;
251 pstrcpy(part_header->name, sizeof(part_header->name), "system");
252
253 end = start + sizeof(struct OpenBIOS_nvpart_v1);
254 for (i = 0; i < nb_prom_envs; i++)
255 end = OpenBIOS_set_var(image, end, prom_envs[i]);
256
257 // End marker
258 image[end++] = '\0';
259
260 end = start + ((end - start + 15) & ~15);
261 OpenBIOS_finish_partition(part_header, end - start);
262
263 // free partition
264 start = end;
265 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
266 part_header->signature = OPENBIOS_PART_FREE;
267 pstrcpy(part_header->name, sizeof(part_header->name), "free");
268
269 end = 0x1fd0;
270 OpenBIOS_finish_partition(part_header, end - start);
271
272 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
273 nvram_machine_id);
274
275 for (i = 0; i < sizeof(image); i++)
276 m48t59_write(nvram, i, image[i]);
277
278 qemu_register_boot_set(nvram_boot_set, nvram);
279 }
280
281 static void *slavio_intctl;
282
283 void pic_info(void)
284 {
285 if (slavio_intctl)
286 slavio_pic_info(slavio_intctl);
287 }
288
289 void irq_info(void)
290 {
291 if (slavio_intctl)
292 slavio_irq_info(slavio_intctl);
293 }
294
295 void cpu_check_irqs(CPUState *env)
296 {
297 if (env->pil_in && (env->interrupt_index == 0 ||
298 (env->interrupt_index & ~15) == TT_EXTINT)) {
299 unsigned int i;
300
301 for (i = 15; i > 0; i--) {
302 if (env->pil_in & (1 << i)) {
303 int old_interrupt = env->interrupt_index;
304
305 env->interrupt_index = TT_EXTINT | i;
306 if (old_interrupt != env->interrupt_index) {
307 DPRINTF("Set CPU IRQ %d\n", i);
308 cpu_interrupt(env, CPU_INTERRUPT_HARD);
309 }
310 break;
311 }
312 }
313 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
314 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
315 env->interrupt_index = 0;
316 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
317 }
318 }
319
320 static void cpu_set_irq(void *opaque, int irq, int level)
321 {
322 CPUState *env = opaque;
323
324 if (level) {
325 DPRINTF("Raise CPU IRQ %d\n", irq);
326 env->halted = 0;
327 env->pil_in |= 1 << irq;
328 cpu_check_irqs(env);
329 } else {
330 DPRINTF("Lower CPU IRQ %d\n", irq);
331 env->pil_in &= ~(1 << irq);
332 cpu_check_irqs(env);
333 }
334 }
335
336 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
337 {
338 }
339
340 static void *slavio_misc;
341
342 void qemu_system_powerdown(void)
343 {
344 slavio_set_power_fail(slavio_misc, 1);
345 }
346
347 static void main_cpu_reset(void *opaque)
348 {
349 CPUState *env = opaque;
350
351 cpu_reset(env);
352 env->halted = 0;
353 }
354
355 static void secondary_cpu_reset(void *opaque)
356 {
357 CPUState *env = opaque;
358
359 cpu_reset(env);
360 env->halted = 1;
361 }
362
363 static void cpu_halt_signal(void *opaque, int irq, int level)
364 {
365 if (level && cpu_single_env)
366 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
367 }
368
369 static unsigned long sun4m_load_kernel(const char *kernel_filename,
370 const char *initrd_filename,
371 ram_addr_t RAM_size)
372 {
373 int linux_boot;
374 unsigned int i;
375 long initrd_size, kernel_size;
376
377 linux_boot = (kernel_filename != NULL);
378
379 kernel_size = 0;
380 if (linux_boot) {
381 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
382 NULL);
383 if (kernel_size < 0)
384 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
385 RAM_size - KERNEL_LOAD_ADDR);
386 if (kernel_size < 0)
387 kernel_size = load_image_targphys(kernel_filename,
388 KERNEL_LOAD_ADDR,
389 RAM_size - KERNEL_LOAD_ADDR);
390 if (kernel_size < 0) {
391 fprintf(stderr, "qemu: could not load kernel '%s'\n",
392 kernel_filename);
393 exit(1);
394 }
395
396 /* load initrd */
397 initrd_size = 0;
398 if (initrd_filename) {
399 initrd_size = load_image_targphys(initrd_filename,
400 INITRD_LOAD_ADDR,
401 RAM_size - INITRD_LOAD_ADDR);
402 if (initrd_size < 0) {
403 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
404 initrd_filename);
405 exit(1);
406 }
407 }
408 if (initrd_size > 0) {
409 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
410 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
411 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
412 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
413 break;
414 }
415 }
416 }
417 }
418 return kernel_size;
419 }
420
421 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
422 const char *boot_device,
423 DisplayState *ds, const char *kernel_filename,
424 const char *kernel_cmdline,
425 const char *initrd_filename, const char *cpu_model)
426
427 {
428 CPUState *env, *envs[MAX_CPUS];
429 unsigned int i;
430 void *iommu, *espdma, *ledma, *main_esp, *nvram;
431 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
432 *espdma_irq, *ledma_irq;
433 qemu_irq *esp_reset, *le_reset;
434 qemu_irq *fdc_tc;
435 qemu_irq *cpu_halt;
436 unsigned long prom_offset, kernel_size;
437 int ret;
438 char buf[1024];
439 BlockDriverState *fd[MAX_FD];
440 int drive_index;
441 void *fw_cfg;
442
443 /* init CPUs */
444 if (!cpu_model)
445 cpu_model = hwdef->default_cpu_model;
446
447 for(i = 0; i < smp_cpus; i++) {
448 env = cpu_init(cpu_model);
449 if (!env) {
450 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
451 exit(1);
452 }
453 cpu_sparc_set_id(env, i);
454 envs[i] = env;
455 if (i == 0) {
456 qemu_register_reset(main_cpu_reset, env);
457 } else {
458 qemu_register_reset(secondary_cpu_reset, env);
459 env->halted = 1;
460 }
461 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
462 env->prom_addr = hwdef->slavio_base;
463 }
464
465 for (i = smp_cpus; i < MAX_CPUS; i++)
466 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
467
468
469 /* allocate RAM */
470 if ((uint64_t)RAM_size > hwdef->max_mem) {
471 fprintf(stderr,
472 "qemu: Too much memory for this machine: %d, maximum %d\n",
473 (unsigned int)(RAM_size / (1024 * 1024)),
474 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
475 exit(1);
476 }
477 cpu_register_physical_memory(0, RAM_size, 0);
478
479 /* load boot prom */
480 prom_offset = RAM_size + hwdef->vram_size;
481 cpu_register_physical_memory(hwdef->slavio_base,
482 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
483 TARGET_PAGE_MASK,
484 prom_offset | IO_MEM_ROM);
485
486 if (bios_name == NULL)
487 bios_name = PROM_FILENAME;
488 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
489 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
490 if (ret < 0 || ret > PROM_SIZE_MAX)
491 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
492 if (ret < 0 || ret > PROM_SIZE_MAX) {
493 fprintf(stderr, "qemu: could not load prom '%s'\n",
494 buf);
495 exit(1);
496 }
497 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
498
499 /* set up devices */
500 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
501 hwdef->intctl_base + 0x10000ULL,
502 &hwdef->intbit_to_level[0],
503 &slavio_irq, &slavio_cpu_irq,
504 cpu_irqs,
505 hwdef->clock_irq);
506
507 if (hwdef->idreg_base != (target_phys_addr_t)-1) {
508 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
509
510 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
511 prom_offset | IO_MEM_ROM);
512 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
513 sizeof(idreg_data));
514 }
515
516 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
517 slavio_irq[hwdef->me_irq]);
518
519 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
520 iommu, &espdma_irq, &esp_reset);
521
522 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
523 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
524 &le_reset);
525
526 if (graphic_depth != 8 && graphic_depth != 24) {
527 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
528 exit (1);
529 }
530 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
531 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
532
533 if (nd_table[0].model == NULL
534 || strcmp(nd_table[0].model, "lance") == 0) {
535 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
536 } else if (strcmp(nd_table[0].model, "?") == 0) {
537 fprintf(stderr, "qemu: Supported NICs: lance\n");
538 exit (1);
539 } else {
540 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
541 exit (1);
542 }
543
544 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
545 hwdef->nvram_size, 8);
546
547 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
548 slavio_cpu_irq, smp_cpus);
549
550 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
551 nographic);
552 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
553 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
554 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
555 serial_hds[1], serial_hds[0]);
556
557 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
558 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
559 hwdef->aux1_base, hwdef->aux2_base,
560 slavio_irq[hwdef->me_irq], cpu_halt[0],
561 &fdc_tc);
562
563 if (hwdef->fd_base != (target_phys_addr_t)-1) {
564 /* there is zero or one floppy drive */
565 memset(fd, 0, sizeof(fd));
566 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
567 if (drive_index != -1)
568 fd[0] = drives_table[drive_index].bdrv;
569
570 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
571 fdc_tc);
572 }
573
574 if (drive_get_max_bus(IF_SCSI) > 0) {
575 fprintf(stderr, "qemu: too many SCSI bus\n");
576 exit(1);
577 }
578
579 main_esp = esp_init(hwdef->esp_base, 2,
580 espdma_memory_read, espdma_memory_write,
581 espdma, *espdma_irq, esp_reset);
582
583 for (i = 0; i < ESP_MAX_DEVS; i++) {
584 drive_index = drive_get_index(IF_SCSI, 0, i);
585 if (drive_index == -1)
586 continue;
587 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
588 }
589
590 if (hwdef->cs_base != (target_phys_addr_t)-1)
591 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
592
593 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
594 RAM_size);
595
596 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
597 boot_device, RAM_size, kernel_size, graphic_width,
598 graphic_height, graphic_depth, hwdef->nvram_machine_id,
599 "Sun4m");
600
601 if (hwdef->ecc_base != (target_phys_addr_t)-1)
602 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
603 hwdef->ecc_version);
604
605 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
606 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
607 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
608 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
609 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
610 }
611
612 enum {
613 ss2_id = 0,
614 ss5_id = 32,
615 vger_id,
616 lx_id,
617 ss4_id,
618 scls_id,
619 sbook_id,
620 ss10_id = 64,
621 ss20_id,
622 ss600mp_id,
623 ss1000_id = 96,
624 ss2000_id,
625 };
626
627 static const struct sun4m_hwdef sun4m_hwdefs[] = {
628 /* SS-5 */
629 {
630 .iommu_base = 0x10000000,
631 .tcx_base = 0x50000000,
632 .cs_base = 0x6c000000,
633 .slavio_base = 0x70000000,
634 .ms_kb_base = 0x71000000,
635 .serial_base = 0x71100000,
636 .nvram_base = 0x71200000,
637 .fd_base = 0x71400000,
638 .counter_base = 0x71d00000,
639 .intctl_base = 0x71e00000,
640 .idreg_base = 0x78000000,
641 .dma_base = 0x78400000,
642 .esp_base = 0x78800000,
643 .le_base = 0x78c00000,
644 .apc_base = 0x6a000000,
645 .aux1_base = 0x71900000,
646 .aux2_base = 0x71910000,
647 .ecc_base = -1,
648 .vram_size = 0x00100000,
649 .nvram_size = 0x2000,
650 .esp_irq = 18,
651 .le_irq = 16,
652 .clock_irq = 7,
653 .clock1_irq = 19,
654 .ms_kb_irq = 14,
655 .ser_irq = 15,
656 .fd_irq = 22,
657 .me_irq = 30,
658 .cs_irq = 5,
659 .nvram_machine_id = 0x80,
660 .machine_id = ss5_id,
661 .iommu_version = 0x05000000,
662 .intbit_to_level = {
663 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
664 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
665 },
666 .max_mem = 0x10000000,
667 .default_cpu_model = "Fujitsu MB86904",
668 },
669 /* SS-10 */
670 {
671 .iommu_base = 0xfe0000000ULL,
672 .tcx_base = 0xe20000000ULL,
673 .cs_base = -1,
674 .slavio_base = 0xff0000000ULL,
675 .ms_kb_base = 0xff1000000ULL,
676 .serial_base = 0xff1100000ULL,
677 .nvram_base = 0xff1200000ULL,
678 .fd_base = 0xff1700000ULL,
679 .counter_base = 0xff1300000ULL,
680 .intctl_base = 0xff1400000ULL,
681 .idreg_base = 0xef0000000ULL,
682 .dma_base = 0xef0400000ULL,
683 .esp_base = 0xef0800000ULL,
684 .le_base = 0xef0c00000ULL,
685 .apc_base = 0xefa000000ULL, // XXX should not exist
686 .aux1_base = 0xff1800000ULL,
687 .aux2_base = 0xff1a01000ULL,
688 .ecc_base = 0xf00000000ULL,
689 .ecc_version = 0x10000000, // version 0, implementation 1
690 .vram_size = 0x00100000,
691 .nvram_size = 0x2000,
692 .esp_irq = 18,
693 .le_irq = 16,
694 .clock_irq = 7,
695 .clock1_irq = 19,
696 .ms_kb_irq = 14,
697 .ser_irq = 15,
698 .fd_irq = 22,
699 .me_irq = 30,
700 .cs_irq = -1,
701 .ecc_irq = 28,
702 .nvram_machine_id = 0x72,
703 .machine_id = ss10_id,
704 .iommu_version = 0x03000000,
705 .intbit_to_level = {
706 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
707 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
708 },
709 .max_mem = 0xf00000000ULL,
710 .default_cpu_model = "TI SuperSparc II",
711 },
712 /* SS-600MP */
713 {
714 .iommu_base = 0xfe0000000ULL,
715 .tcx_base = 0xe20000000ULL,
716 .cs_base = -1,
717 .slavio_base = 0xff0000000ULL,
718 .ms_kb_base = 0xff1000000ULL,
719 .serial_base = 0xff1100000ULL,
720 .nvram_base = 0xff1200000ULL,
721 .fd_base = -1,
722 .counter_base = 0xff1300000ULL,
723 .intctl_base = 0xff1400000ULL,
724 .idreg_base = -1,
725 .dma_base = 0xef0081000ULL,
726 .esp_base = 0xef0080000ULL,
727 .le_base = 0xef0060000ULL,
728 .apc_base = 0xefa000000ULL, // XXX should not exist
729 .aux1_base = 0xff1800000ULL,
730 .aux2_base = 0xff1a01000ULL, // XXX should not exist
731 .ecc_base = 0xf00000000ULL,
732 .ecc_version = 0x00000000, // version 0, implementation 0
733 .vram_size = 0x00100000,
734 .nvram_size = 0x2000,
735 .esp_irq = 18,
736 .le_irq = 16,
737 .clock_irq = 7,
738 .clock1_irq = 19,
739 .ms_kb_irq = 14,
740 .ser_irq = 15,
741 .fd_irq = 22,
742 .me_irq = 30,
743 .cs_irq = -1,
744 .ecc_irq = 28,
745 .nvram_machine_id = 0x71,
746 .machine_id = ss600mp_id,
747 .iommu_version = 0x01000000,
748 .intbit_to_level = {
749 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
750 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
751 },
752 .max_mem = 0xf00000000ULL,
753 .default_cpu_model = "TI SuperSparc II",
754 },
755 /* SS-20 */
756 {
757 .iommu_base = 0xfe0000000ULL,
758 .tcx_base = 0xe20000000ULL,
759 .cs_base = -1,
760 .slavio_base = 0xff0000000ULL,
761 .ms_kb_base = 0xff1000000ULL,
762 .serial_base = 0xff1100000ULL,
763 .nvram_base = 0xff1200000ULL,
764 .fd_base = 0xff1700000ULL,
765 .counter_base = 0xff1300000ULL,
766 .intctl_base = 0xff1400000ULL,
767 .idreg_base = 0xef0000000ULL,
768 .dma_base = 0xef0400000ULL,
769 .esp_base = 0xef0800000ULL,
770 .le_base = 0xef0c00000ULL,
771 .apc_base = 0xefa000000ULL, // XXX should not exist
772 .aux1_base = 0xff1800000ULL,
773 .aux2_base = 0xff1a01000ULL,
774 .ecc_base = 0xf00000000ULL,
775 .ecc_version = 0x20000000, // version 0, implementation 2
776 .vram_size = 0x00100000,
777 .nvram_size = 0x2000,
778 .esp_irq = 18,
779 .le_irq = 16,
780 .clock_irq = 7,
781 .clock1_irq = 19,
782 .ms_kb_irq = 14,
783 .ser_irq = 15,
784 .fd_irq = 22,
785 .me_irq = 30,
786 .cs_irq = -1,
787 .ecc_irq = 28,
788 .nvram_machine_id = 0x72,
789 .machine_id = ss20_id,
790 .iommu_version = 0x13000000,
791 .intbit_to_level = {
792 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
793 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
794 },
795 .max_mem = 0xf00000000ULL,
796 .default_cpu_model = "TI SuperSparc II",
797 },
798 /* Voyager */
799 {
800 .iommu_base = 0x10000000,
801 .tcx_base = 0x50000000,
802 .cs_base = -1,
803 .slavio_base = 0x70000000,
804 .ms_kb_base = 0x71000000,
805 .serial_base = 0x71100000,
806 .nvram_base = 0x71200000,
807 .fd_base = 0x71400000,
808 .counter_base = 0x71d00000,
809 .intctl_base = 0x71e00000,
810 .idreg_base = 0x78000000,
811 .dma_base = 0x78400000,
812 .esp_base = 0x78800000,
813 .le_base = 0x78c00000,
814 .apc_base = 0x71300000, // pmc
815 .aux1_base = 0x71900000,
816 .aux2_base = 0x71910000,
817 .ecc_base = -1,
818 .vram_size = 0x00100000,
819 .nvram_size = 0x2000,
820 .esp_irq = 18,
821 .le_irq = 16,
822 .clock_irq = 7,
823 .clock1_irq = 19,
824 .ms_kb_irq = 14,
825 .ser_irq = 15,
826 .fd_irq = 22,
827 .me_irq = 30,
828 .cs_irq = -1,
829 .nvram_machine_id = 0x80,
830 .machine_id = vger_id,
831 .iommu_version = 0x05000000,
832 .intbit_to_level = {
833 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
834 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
835 },
836 .max_mem = 0x10000000,
837 .default_cpu_model = "Fujitsu MB86904",
838 },
839 /* LX */
840 {
841 .iommu_base = 0x10000000,
842 .tcx_base = 0x50000000,
843 .cs_base = -1,
844 .slavio_base = 0x70000000,
845 .ms_kb_base = 0x71000000,
846 .serial_base = 0x71100000,
847 .nvram_base = 0x71200000,
848 .fd_base = 0x71400000,
849 .counter_base = 0x71d00000,
850 .intctl_base = 0x71e00000,
851 .idreg_base = 0x78000000,
852 .dma_base = 0x78400000,
853 .esp_base = 0x78800000,
854 .le_base = 0x78c00000,
855 .apc_base = -1,
856 .aux1_base = 0x71900000,
857 .aux2_base = 0x71910000,
858 .ecc_base = -1,
859 .vram_size = 0x00100000,
860 .nvram_size = 0x2000,
861 .esp_irq = 18,
862 .le_irq = 16,
863 .clock_irq = 7,
864 .clock1_irq = 19,
865 .ms_kb_irq = 14,
866 .ser_irq = 15,
867 .fd_irq = 22,
868 .me_irq = 30,
869 .cs_irq = -1,
870 .nvram_machine_id = 0x80,
871 .machine_id = lx_id,
872 .iommu_version = 0x04000000,
873 .intbit_to_level = {
874 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
875 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
876 },
877 .max_mem = 0x10000000,
878 .default_cpu_model = "TI MicroSparc I",
879 },
880 /* SS-4 */
881 {
882 .iommu_base = 0x10000000,
883 .tcx_base = 0x50000000,
884 .cs_base = 0x6c000000,
885 .slavio_base = 0x70000000,
886 .ms_kb_base = 0x71000000,
887 .serial_base = 0x71100000,
888 .nvram_base = 0x71200000,
889 .fd_base = 0x71400000,
890 .counter_base = 0x71d00000,
891 .intctl_base = 0x71e00000,
892 .idreg_base = 0x78000000,
893 .dma_base = 0x78400000,
894 .esp_base = 0x78800000,
895 .le_base = 0x78c00000,
896 .apc_base = 0x6a000000,
897 .aux1_base = 0x71900000,
898 .aux2_base = 0x71910000,
899 .ecc_base = -1,
900 .vram_size = 0x00100000,
901 .nvram_size = 0x2000,
902 .esp_irq = 18,
903 .le_irq = 16,
904 .clock_irq = 7,
905 .clock1_irq = 19,
906 .ms_kb_irq = 14,
907 .ser_irq = 15,
908 .fd_irq = 22,
909 .me_irq = 30,
910 .cs_irq = 5,
911 .nvram_machine_id = 0x80,
912 .machine_id = ss4_id,
913 .iommu_version = 0x05000000,
914 .intbit_to_level = {
915 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
916 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
917 },
918 .max_mem = 0x10000000,
919 .default_cpu_model = "Fujitsu MB86904",
920 },
921 /* SPARCClassic */
922 {
923 .iommu_base = 0x10000000,
924 .tcx_base = 0x50000000,
925 .cs_base = -1,
926 .slavio_base = 0x70000000,
927 .ms_kb_base = 0x71000000,
928 .serial_base = 0x71100000,
929 .nvram_base = 0x71200000,
930 .fd_base = 0x71400000,
931 .counter_base = 0x71d00000,
932 .intctl_base = 0x71e00000,
933 .idreg_base = 0x78000000,
934 .dma_base = 0x78400000,
935 .esp_base = 0x78800000,
936 .le_base = 0x78c00000,
937 .apc_base = 0x6a000000,
938 .aux1_base = 0x71900000,
939 .aux2_base = 0x71910000,
940 .ecc_base = -1,
941 .vram_size = 0x00100000,
942 .nvram_size = 0x2000,
943 .esp_irq = 18,
944 .le_irq = 16,
945 .clock_irq = 7,
946 .clock1_irq = 19,
947 .ms_kb_irq = 14,
948 .ser_irq = 15,
949 .fd_irq = 22,
950 .me_irq = 30,
951 .cs_irq = -1,
952 .nvram_machine_id = 0x80,
953 .machine_id = scls_id,
954 .iommu_version = 0x05000000,
955 .intbit_to_level = {
956 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
957 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
958 },
959 .max_mem = 0x10000000,
960 .default_cpu_model = "TI MicroSparc I",
961 },
962 /* SPARCbook */
963 {
964 .iommu_base = 0x10000000,
965 .tcx_base = 0x50000000, // XXX
966 .cs_base = -1,
967 .slavio_base = 0x70000000,
968 .ms_kb_base = 0x71000000,
969 .serial_base = 0x71100000,
970 .nvram_base = 0x71200000,
971 .fd_base = 0x71400000,
972 .counter_base = 0x71d00000,
973 .intctl_base = 0x71e00000,
974 .idreg_base = 0x78000000,
975 .dma_base = 0x78400000,
976 .esp_base = 0x78800000,
977 .le_base = 0x78c00000,
978 .apc_base = 0x6a000000,
979 .aux1_base = 0x71900000,
980 .aux2_base = 0x71910000,
981 .ecc_base = -1,
982 .vram_size = 0x00100000,
983 .nvram_size = 0x2000,
984 .esp_irq = 18,
985 .le_irq = 16,
986 .clock_irq = 7,
987 .clock1_irq = 19,
988 .ms_kb_irq = 14,
989 .ser_irq = 15,
990 .fd_irq = 22,
991 .me_irq = 30,
992 .cs_irq = -1,
993 .nvram_machine_id = 0x80,
994 .machine_id = sbook_id,
995 .iommu_version = 0x05000000,
996 .intbit_to_level = {
997 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
998 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
999 },
1000 .max_mem = 0x10000000,
1001 .default_cpu_model = "TI MicroSparc I",
1002 },
1003 };
1004
1005 /* SPARCstation 5 hardware initialisation */
1006 static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
1007 const char *boot_device, DisplayState *ds,
1008 const char *kernel_filename, const char *kernel_cmdline,
1009 const char *initrd_filename, const char *cpu_model)
1010 {
1011 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1012 kernel_cmdline, initrd_filename, cpu_model);
1013 }
1014
1015 /* SPARCstation 10 hardware initialisation */
1016 static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
1017 const char *boot_device, DisplayState *ds,
1018 const char *kernel_filename, const char *kernel_cmdline,
1019 const char *initrd_filename, const char *cpu_model)
1020 {
1021 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1022 kernel_cmdline, initrd_filename, cpu_model);
1023 }
1024
1025 /* SPARCserver 600MP hardware initialisation */
1026 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
1027 const char *boot_device, DisplayState *ds,
1028 const char *kernel_filename,
1029 const char *kernel_cmdline,
1030 const char *initrd_filename, const char *cpu_model)
1031 {
1032 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
1033 kernel_cmdline, initrd_filename, cpu_model);
1034 }
1035
1036 /* SPARCstation 20 hardware initialisation */
1037 static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
1038 const char *boot_device, DisplayState *ds,
1039 const char *kernel_filename, const char *kernel_cmdline,
1040 const char *initrd_filename, const char *cpu_model)
1041 {
1042 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
1043 kernel_cmdline, initrd_filename, cpu_model);
1044 }
1045
1046 /* SPARCstation Voyager hardware initialisation */
1047 static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
1048 const char *boot_device, DisplayState *ds,
1049 const char *kernel_filename, const char *kernel_cmdline,
1050 const char *initrd_filename, const char *cpu_model)
1051 {
1052 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
1053 kernel_cmdline, initrd_filename, cpu_model);
1054 }
1055
1056 /* SPARCstation LX hardware initialisation */
1057 static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
1058 const char *boot_device, DisplayState *ds,
1059 const char *kernel_filename, const char *kernel_cmdline,
1060 const char *initrd_filename, const char *cpu_model)
1061 {
1062 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
1063 kernel_cmdline, initrd_filename, cpu_model);
1064 }
1065
1066 /* SPARCstation 4 hardware initialisation */
1067 static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
1068 const char *boot_device, DisplayState *ds,
1069 const char *kernel_filename, const char *kernel_cmdline,
1070 const char *initrd_filename, const char *cpu_model)
1071 {
1072 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
1073 kernel_cmdline, initrd_filename, cpu_model);
1074 }
1075
1076 /* SPARCClassic hardware initialisation */
1077 static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1078 const char *boot_device, DisplayState *ds,
1079 const char *kernel_filename, const char *kernel_cmdline,
1080 const char *initrd_filename, const char *cpu_model)
1081 {
1082 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
1083 kernel_cmdline, initrd_filename, cpu_model);
1084 }
1085
1086 /* SPARCbook hardware initialisation */
1087 static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1088 const char *boot_device, DisplayState *ds,
1089 const char *kernel_filename, const char *kernel_cmdline,
1090 const char *initrd_filename, const char *cpu_model)
1091 {
1092 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
1093 kernel_cmdline, initrd_filename, cpu_model);
1094 }
1095
1096 QEMUMachine ss5_machine = {
1097 .name = "SS-5",
1098 .desc = "Sun4m platform, SPARCstation 5",
1099 .init = ss5_init,
1100 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1101 .nodisk_ok = 1,
1102 .use_scsi = 1,
1103 };
1104
1105 QEMUMachine ss10_machine = {
1106 .name = "SS-10",
1107 .desc = "Sun4m platform, SPARCstation 10",
1108 .init = ss10_init,
1109 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1110 .nodisk_ok = 1,
1111 .use_scsi = 1,
1112 .max_cpus = 4,
1113 };
1114
1115 QEMUMachine ss600mp_machine = {
1116 .name = "SS-600MP",
1117 .desc = "Sun4m platform, SPARCserver 600MP",
1118 .init = ss600mp_init,
1119 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1120 .nodisk_ok = 1,
1121 .use_scsi = 1,
1122 .max_cpus = 4,
1123 };
1124
1125 QEMUMachine ss20_machine = {
1126 .name = "SS-20",
1127 .desc = "Sun4m platform, SPARCstation 20",
1128 .init = ss20_init,
1129 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1130 .nodisk_ok = 1,
1131 .use_scsi = 1,
1132 .max_cpus = 4,
1133 };
1134
1135 QEMUMachine voyager_machine = {
1136 .name = "Voyager",
1137 .desc = "Sun4m platform, SPARCstation Voyager",
1138 .init = vger_init,
1139 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1140 .nodisk_ok = 1,
1141 .use_scsi = 1,
1142 };
1143
1144 QEMUMachine ss_lx_machine = {
1145 .name = "LX",
1146 .desc = "Sun4m platform, SPARCstation LX",
1147 .init = ss_lx_init,
1148 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1149 .nodisk_ok = 1,
1150 .use_scsi = 1,
1151 };
1152
1153 QEMUMachine ss4_machine = {
1154 .name = "SS-4",
1155 .desc = "Sun4m platform, SPARCstation 4",
1156 .init = ss4_init,
1157 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1158 .nodisk_ok = 1,
1159 .use_scsi = 1,
1160 };
1161
1162 QEMUMachine scls_machine = {
1163 .name = "SPARCClassic",
1164 .desc = "Sun4m platform, SPARCClassic",
1165 .init = scls_init,
1166 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1167 .nodisk_ok = 1,
1168 .use_scsi = 1,
1169 };
1170
1171 QEMUMachine sbook_machine = {
1172 .name = "SPARCbook",
1173 .desc = "Sun4m platform, SPARCbook",
1174 .init = sbook_init,
1175 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1176 .nodisk_ok = 1,
1177 .use_scsi = 1,
1178 };
1179
1180 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1181 /* SS-1000 */
1182 {
1183 .iounit_bases = {
1184 0xfe0200000ULL,
1185 0xfe1200000ULL,
1186 0xfe2200000ULL,
1187 0xfe3200000ULL,
1188 -1,
1189 },
1190 .tcx_base = 0x820000000ULL,
1191 .slavio_base = 0xf00000000ULL,
1192 .ms_kb_base = 0xf00240000ULL,
1193 .serial_base = 0xf00200000ULL,
1194 .nvram_base = 0xf00280000ULL,
1195 .counter_base = 0xf00300000ULL,
1196 .espdma_base = 0x800081000ULL,
1197 .esp_base = 0x800080000ULL,
1198 .ledma_base = 0x800040000ULL,
1199 .le_base = 0x800060000ULL,
1200 .sbi_base = 0xf02800000ULL,
1201 .vram_size = 0x00100000,
1202 .nvram_size = 0x2000,
1203 .esp_irq = 3,
1204 .le_irq = 4,
1205 .clock_irq = 14,
1206 .clock1_irq = 10,
1207 .ms_kb_irq = 12,
1208 .ser_irq = 12,
1209 .nvram_machine_id = 0x80,
1210 .machine_id = ss1000_id,
1211 .iounit_version = 0x03000000,
1212 .max_mem = 0xf00000000ULL,
1213 .default_cpu_model = "TI SuperSparc II",
1214 },
1215 /* SS-2000 */
1216 {
1217 .iounit_bases = {
1218 0xfe0200000ULL,
1219 0xfe1200000ULL,
1220 0xfe2200000ULL,
1221 0xfe3200000ULL,
1222 0xfe4200000ULL,
1223 },
1224 .tcx_base = 0x820000000ULL,
1225 .slavio_base = 0xf00000000ULL,
1226 .ms_kb_base = 0xf00240000ULL,
1227 .serial_base = 0xf00200000ULL,
1228 .nvram_base = 0xf00280000ULL,
1229 .counter_base = 0xf00300000ULL,
1230 .espdma_base = 0x800081000ULL,
1231 .esp_base = 0x800080000ULL,
1232 .ledma_base = 0x800040000ULL,
1233 .le_base = 0x800060000ULL,
1234 .sbi_base = 0xf02800000ULL,
1235 .vram_size = 0x00100000,
1236 .nvram_size = 0x2000,
1237 .esp_irq = 3,
1238 .le_irq = 4,
1239 .clock_irq = 14,
1240 .clock1_irq = 10,
1241 .ms_kb_irq = 12,
1242 .ser_irq = 12,
1243 .nvram_machine_id = 0x80,
1244 .machine_id = ss2000_id,
1245 .iounit_version = 0x03000000,
1246 .max_mem = 0xf00000000ULL,
1247 .default_cpu_model = "TI SuperSparc II",
1248 },
1249 };
1250
1251 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1252 const char *boot_device,
1253 DisplayState *ds, const char *kernel_filename,
1254 const char *kernel_cmdline,
1255 const char *initrd_filename, const char *cpu_model)
1256 {
1257 CPUState *env, *envs[MAX_CPUS];
1258 unsigned int i;
1259 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1260 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1261 *espdma_irq, *ledma_irq;
1262 qemu_irq *esp_reset, *le_reset;
1263 unsigned long prom_offset, kernel_size;
1264 int ret;
1265 char buf[1024];
1266 int drive_index;
1267 void *fw_cfg;
1268
1269 /* init CPUs */
1270 if (!cpu_model)
1271 cpu_model = hwdef->default_cpu_model;
1272
1273 for (i = 0; i < smp_cpus; i++) {
1274 env = cpu_init(cpu_model);
1275 if (!env) {
1276 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1277 exit(1);
1278 }
1279 cpu_sparc_set_id(env, i);
1280 envs[i] = env;
1281 if (i == 0) {
1282 qemu_register_reset(main_cpu_reset, env);
1283 } else {
1284 qemu_register_reset(secondary_cpu_reset, env);
1285 env->halted = 1;
1286 }
1287 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1288 env->prom_addr = hwdef->slavio_base;
1289 }
1290
1291 for (i = smp_cpus; i < MAX_CPUS; i++)
1292 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1293
1294 /* allocate RAM */
1295 if ((uint64_t)RAM_size > hwdef->max_mem) {
1296 fprintf(stderr,
1297 "qemu: Too much memory for this machine: %d, maximum %d\n",
1298 (unsigned int)(RAM_size / (1024 * 1024)),
1299 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1300 exit(1);
1301 }
1302 cpu_register_physical_memory(0, RAM_size, 0);
1303
1304 /* load boot prom */
1305 prom_offset = RAM_size + hwdef->vram_size;
1306 cpu_register_physical_memory(hwdef->slavio_base,
1307 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1308 TARGET_PAGE_MASK,
1309 prom_offset | IO_MEM_ROM);
1310
1311 if (bios_name == NULL)
1312 bios_name = PROM_FILENAME;
1313 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1314 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1315 if (ret < 0 || ret > PROM_SIZE_MAX)
1316 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1317 if (ret < 0 || ret > PROM_SIZE_MAX) {
1318 fprintf(stderr, "qemu: could not load prom '%s'\n",
1319 buf);
1320 exit(1);
1321 }
1322
1323 /* set up devices */
1324 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1325
1326 for (i = 0; i < MAX_IOUNITS; i++)
1327 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1328 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1329 hwdef->iounit_version,
1330 sbi_irq[hwdef->me_irq]);
1331
1332 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1333 iounits[0], &espdma_irq, &esp_reset);
1334
1335 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1336 iounits[0], &ledma_irq, &le_reset);
1337
1338 if (graphic_depth != 8 && graphic_depth != 24) {
1339 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1340 exit (1);
1341 }
1342 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1343 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1344
1345 if (nd_table[0].model == NULL
1346 || strcmp(nd_table[0].model, "lance") == 0) {
1347 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1348 } else if (strcmp(nd_table[0].model, "?") == 0) {
1349 fprintf(stderr, "qemu: Supported NICs: lance\n");
1350 exit (1);
1351 } else {
1352 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1353 exit (1);
1354 }
1355
1356 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1357 hwdef->nvram_size, 8);
1358
1359 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1360 sbi_cpu_irq, smp_cpus);
1361
1362 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1363 nographic);
1364 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1365 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1366 slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1367 serial_hds[1], serial_hds[0]);
1368
1369 if (drive_get_max_bus(IF_SCSI) > 0) {
1370 fprintf(stderr, "qemu: too many SCSI bus\n");
1371 exit(1);
1372 }
1373
1374 main_esp = esp_init(hwdef->esp_base, 2,
1375 espdma_memory_read, espdma_memory_write,
1376 espdma, *espdma_irq, esp_reset);
1377
1378 for (i = 0; i < ESP_MAX_DEVS; i++) {
1379 drive_index = drive_get_index(IF_SCSI, 0, i);
1380 if (drive_index == -1)
1381 continue;
1382 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1383 }
1384
1385 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1386 RAM_size);
1387
1388 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1389 boot_device, RAM_size, kernel_size, graphic_width,
1390 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1391 "Sun4d");
1392
1393 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1394 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1395 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1396 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1397 }
1398
1399 /* SPARCserver 1000 hardware initialisation */
1400 static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1401 const char *boot_device, DisplayState *ds,
1402 const char *kernel_filename, const char *kernel_cmdline,
1403 const char *initrd_filename, const char *cpu_model)
1404 {
1405 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1406 kernel_cmdline, initrd_filename, cpu_model);
1407 }
1408
1409 /* SPARCcenter 2000 hardware initialisation */
1410 static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1411 const char *boot_device, DisplayState *ds,
1412 const char *kernel_filename, const char *kernel_cmdline,
1413 const char *initrd_filename, const char *cpu_model)
1414 {
1415 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1416 kernel_cmdline, initrd_filename, cpu_model);
1417 }
1418
1419 QEMUMachine ss1000_machine = {
1420 .name = "SS-1000",
1421 .desc = "Sun4d platform, SPARCserver 1000",
1422 .init = ss1000_init,
1423 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1424 .nodisk_ok = 1,
1425 .use_scsi = 1,
1426 .max_cpus = 8,
1427 };
1428
1429 QEMUMachine ss2000_machine = {
1430 .name = "SS-2000",
1431 .desc = "Sun4d platform, SPARCcenter 2000",
1432 .init = ss2000_init,
1433 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1434 .nodisk_ok = 1,
1435 .use_scsi = 1,
1436 .max_cpus = 20,
1437 };
1438
1439 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1440 /* SS-2 */
1441 {
1442 .iommu_base = 0xf8000000,
1443 .tcx_base = 0xfe000000,
1444 .slavio_base = 0xf6000000,
1445 .intctl_base = 0xf5000000,
1446 .counter_base = 0xf3000000,
1447 .ms_kb_base = 0xf0000000,
1448 .serial_base = 0xf1000000,
1449 .nvram_base = 0xf2000000,
1450 .fd_base = 0xf7200000,
1451 .dma_base = 0xf8400000,
1452 .esp_base = 0xf8800000,
1453 .le_base = 0xf8c00000,
1454 .aux1_base = 0xf7400003,
1455 .vram_size = 0x00100000,
1456 .nvram_size = 0x800,
1457 .esp_irq = 2,
1458 .le_irq = 3,
1459 .clock_irq = 5,
1460 .clock1_irq = 7,
1461 .ms_kb_irq = 1,
1462 .ser_irq = 1,
1463 .fd_irq = 1,
1464 .me_irq = 1,
1465 .nvram_machine_id = 0x55,
1466 .machine_id = ss2_id,
1467 .max_mem = 0x10000000,
1468 .default_cpu_model = "Cypress CY7C601",
1469 },
1470 };
1471
1472 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1473 const char *boot_device,
1474 DisplayState *ds, const char *kernel_filename,
1475 const char *kernel_cmdline,
1476 const char *initrd_filename, const char *cpu_model)
1477 {
1478 CPUState *env;
1479 unsigned int i;
1480 void *iommu, *espdma, *ledma, *main_esp, *nvram;
1481 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
1482 qemu_irq *esp_reset, *le_reset;
1483 qemu_irq *fdc_tc;
1484 unsigned long prom_offset, kernel_size;
1485 int ret;
1486 char buf[1024];
1487 BlockDriverState *fd[MAX_FD];
1488 int drive_index;
1489 void *fw_cfg;
1490
1491 /* init CPU */
1492 if (!cpu_model)
1493 cpu_model = hwdef->default_cpu_model;
1494
1495 env = cpu_init(cpu_model);
1496 if (!env) {
1497 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1498 exit(1);
1499 }
1500
1501 cpu_sparc_set_id(env, 0);
1502
1503 qemu_register_reset(main_cpu_reset, env);
1504 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1505 env->prom_addr = hwdef->slavio_base;
1506
1507 /* allocate RAM */
1508 if ((uint64_t)RAM_size > hwdef->max_mem) {
1509 fprintf(stderr,
1510 "qemu: Too much memory for this machine: %d, maximum %d\n",
1511 (unsigned int)(RAM_size / (1024 * 1024)),
1512 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1513 exit(1);
1514 }
1515 cpu_register_physical_memory(0, RAM_size, 0);
1516
1517 /* load boot prom */
1518 prom_offset = RAM_size + hwdef->vram_size;
1519 cpu_register_physical_memory(hwdef->slavio_base,
1520 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1521 TARGET_PAGE_MASK,
1522 prom_offset | IO_MEM_ROM);
1523
1524 if (bios_name == NULL)
1525 bios_name = PROM_FILENAME;
1526 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1527 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1528 if (ret < 0 || ret > PROM_SIZE_MAX)
1529 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1530 if (ret < 0 || ret > PROM_SIZE_MAX) {
1531 fprintf(stderr, "qemu: could not load prom '%s'\n",
1532 buf);
1533 exit(1);
1534 }
1535 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
1536
1537 /* set up devices */
1538 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1539 &slavio_irq, cpu_irqs);
1540
1541 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1542 slavio_irq[hwdef->me_irq]);
1543
1544 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1545 iommu, &espdma_irq, &esp_reset);
1546
1547 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1548 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1549 &le_reset);
1550
1551 if (graphic_depth != 8 && graphic_depth != 24) {
1552 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1553 exit (1);
1554 }
1555 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1556 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1557
1558 if (nd_table[0].model == NULL
1559 || strcmp(nd_table[0].model, "lance") == 0) {
1560 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1561 } else if (strcmp(nd_table[0].model, "?") == 0) {
1562 fprintf(stderr, "qemu: Supported NICs: lance\n");
1563 exit (1);
1564 } else {
1565 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1566 exit (1);
1567 }
1568
1569 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1570 hwdef->nvram_size, 2);
1571
1572 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1573 nographic);
1574 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1575 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1576 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1577 serial_hds[1], serial_hds[0]);
1578
1579 slavio_misc = slavio_misc_init(0, -1, hwdef->aux1_base, -1,
1580 slavio_irq[hwdef->me_irq], NULL, &fdc_tc);
1581
1582 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1583 /* there is zero or one floppy drive */
1584 fd[1] = fd[0] = NULL;
1585 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1586 if (drive_index != -1)
1587 fd[0] = drives_table[drive_index].bdrv;
1588
1589 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1590 fdc_tc);
1591 }
1592
1593 if (drive_get_max_bus(IF_SCSI) > 0) {
1594 fprintf(stderr, "qemu: too many SCSI bus\n");
1595 exit(1);
1596 }
1597
1598 main_esp = esp_init(hwdef->esp_base, 2,
1599 espdma_memory_read, espdma_memory_write,
1600 espdma, *espdma_irq, esp_reset);
1601
1602 for (i = 0; i < ESP_MAX_DEVS; i++) {
1603 drive_index = drive_get_index(IF_SCSI, 0, i);
1604 if (drive_index == -1)
1605 continue;
1606 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1607 }
1608
1609 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1610 RAM_size);
1611
1612 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1613 boot_device, RAM_size, kernel_size, graphic_width,
1614 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1615 "Sun4c");
1616
1617 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1618 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1619 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1620 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1621 }
1622
1623 /* SPARCstation 2 hardware initialisation */
1624 static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1625 const char *boot_device, DisplayState *ds,
1626 const char *kernel_filename, const char *kernel_cmdline,
1627 const char *initrd_filename, const char *cpu_model)
1628 {
1629 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1630 kernel_cmdline, initrd_filename, cpu_model);
1631 }
1632
1633 QEMUMachine ss2_machine = {
1634 .name = "SS-2",
1635 .desc = "Sun4c platform, SPARCstation 2",
1636 .init = ss2_init,
1637 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1638 .nodisk_ok = 1,
1639 .use_scsi = 1,
1640 };
1641
Qemu copy for testing