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Refactor DEC 21154 PCI bridge
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1 /*
2 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc_mac.h"
26 #include "pci.h"
27 #include "pci_host.h"
28
29 /* debug UniNorth */
30 //#define DEBUG_UNIN
31
32 #ifdef DEBUG_UNIN
33 #define UNIN_DPRINTF(fmt, ...) \
34 do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
35 #else
36 #define UNIN_DPRINTF(fmt, ...)
37 #endif
38
39 typedef struct UNINState {
40 SysBusDevice busdev;
41 PCIHostState host_state;
42 } UNINState;
43
44 /* Don't know if this matches real hardware, but it agrees with OHW. */
45 static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
46 {
47 return (irq_num + (pci_dev->devfn >> 3)) & 3;
48 }
49
50 static void pci_unin_set_irq(void *opaque, int irq_num, int level)
51 {
52 qemu_irq *pic = opaque;
53
54 qemu_set_irq(pic[irq_num + 8], level);
55 }
56
57 static void pci_unin_save(QEMUFile* f, void *opaque)
58 {
59 PCIDevice *d = opaque;
60
61 pci_device_save(d, f);
62 }
63
64 static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
65 {
66 PCIDevice *d = opaque;
67
68 if (version_id != 1)
69 return -EINVAL;
70
71 return pci_device_load(d, f);
72 }
73
74 static void pci_unin_reset(void *opaque)
75 {
76 }
77
78 static int pci_unin_main_init_device(SysBusDevice *dev)
79 {
80 UNINState *s;
81 int pci_mem_config, pci_mem_data;
82
83 /* Use values found on a real PowerMac */
84 /* Uninorth main bus */
85 s = FROM_SYSBUS(UNINState, dev);
86
87 pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
88 pci_mem_data = pci_host_data_register_mmio(&s->host_state);
89 sysbus_init_mmio(dev, 0x1000, pci_mem_config);
90 sysbus_init_mmio(dev, 0x1000, pci_mem_data);
91
92 register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
93 qemu_register_reset(pci_unin_reset, &s->host_state);
94 return 0;
95 }
96
97 static int pci_unin_agp_init_device(SysBusDevice *dev)
98 {
99 UNINState *s;
100 int pci_mem_config, pci_mem_data;
101
102 /* Uninorth AGP bus */
103 s = FROM_SYSBUS(UNINState, dev);
104
105 pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
106 pci_mem_data = pci_host_data_register_mmio(&s->host_state);
107 sysbus_init_mmio(dev, 0x1000, pci_mem_config);
108 sysbus_init_mmio(dev, 0x1000, pci_mem_data);
109 return 0;
110 }
111
112 static int pci_unin_internal_init_device(SysBusDevice *dev)
113 {
114 UNINState *s;
115 int pci_mem_config, pci_mem_data;
116
117 /* Uninorth internal bus */
118 s = FROM_SYSBUS(UNINState, dev);
119
120 pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
121 pci_mem_data = pci_host_data_register_mmio(&s->host_state);
122 sysbus_init_mmio(dev, 0x1000, pci_mem_config);
123 sysbus_init_mmio(dev, 0x1000, pci_mem_data);
124 return 0;
125 }
126
127 PCIBus *pci_pmac_init(qemu_irq *pic)
128 {
129 DeviceState *dev;
130 SysBusDevice *s;
131 UNINState *d;
132
133 /* Use values found on a real PowerMac */
134 /* Uninorth main bus */
135 dev = qdev_create(NULL, "uni-north");
136 qdev_init_nofail(dev);
137 s = sysbus_from_qdev(dev);
138 d = FROM_SYSBUS(UNINState, s);
139 d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
140 pci_unin_set_irq, pci_unin_map_irq,
141 pic, 11 << 3, 4);
142
143 #if 0
144 pci_create_simple(d->host_state.bus, 11 << 3, "uni-north");
145 #endif
146
147 sysbus_mmio_map(s, 0, 0xf2800000);
148 sysbus_mmio_map(s, 1, 0xf2c00000);
149
150 /* DEC 21154 bridge */
151 #if 0
152 /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
153 pci_create_simple(d->host_state.bus, 12 << 3, "dec-21154");
154 #endif
155
156 /* Uninorth AGP bus */
157 pci_create_simple(d->host_state.bus, 11 << 3, "uni-north-agp");
158 dev = qdev_create(NULL, "uni-north-agp");
159 qdev_init_nofail(dev);
160 s = sysbus_from_qdev(dev);
161 sysbus_mmio_map(s, 0, 0xf0800000);
162 sysbus_mmio_map(s, 1, 0xf0c00000);
163
164 /* Uninorth internal bus */
165 #if 0
166 /* XXX: not needed for now */
167 pci_create_simple(d->host_state.bus, 14 << 3, "uni-north-pci");
168 dev = qdev_create(NULL, "uni-north-pci");
169 qdev_init_nofail(dev);
170 s = sysbus_from_qdev(dev);
171 sysbus_mmio_map(s, 0, 0xf4800000);
172 sysbus_mmio_map(s, 1, 0xf4c00000);
173 #endif
174
175 return d->host_state.bus;
176 }
177
178 static int unin_main_pci_host_init(PCIDevice *d)
179 {
180 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
181 pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
182 d->config[0x08] = 0x00; // revision
183 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
184 d->config[0x0C] = 0x08; // cache_line_size
185 d->config[0x0D] = 0x10; // latency_timer
186 d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
187 d->config[0x34] = 0x00; // capabilities_pointer
188 return 0;
189 }
190
191 static int unin_agp_pci_host_init(PCIDevice *d)
192 {
193 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
194 pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
195 d->config[0x08] = 0x00; // revision
196 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
197 d->config[0x0C] = 0x08; // cache_line_size
198 d->config[0x0D] = 0x10; // latency_timer
199 d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
200 // d->config[0x34] = 0x80; // capabilities_pointer
201 return 0;
202 }
203
204 static int unin_internal_pci_host_init(PCIDevice *d)
205 {
206 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
207 pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
208 d->config[0x08] = 0x00; // revision
209 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
210 d->config[0x0C] = 0x08; // cache_line_size
211 d->config[0x0D] = 0x10; // latency_timer
212 d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
213 d->config[0x34] = 0x00; // capabilities_pointer
214 return 0;
215 }
216
217 static PCIDeviceInfo unin_main_pci_host_info = {
218 .qdev.name = "uni-north",
219 .qdev.size = sizeof(PCIDevice),
220 .init = unin_main_pci_host_init,
221 };
222
223 static PCIDeviceInfo unin_agp_pci_host_info = {
224 .qdev.name = "uni-north-agp",
225 .qdev.size = sizeof(PCIDevice),
226 .init = unin_agp_pci_host_init,
227 };
228
229 static PCIDeviceInfo unin_internal_pci_host_info = {
230 .qdev.name = "uni-north-pci",
231 .qdev.size = sizeof(PCIDevice),
232 .init = unin_internal_pci_host_init,
233 };
234
235 static void unin_register_devices(void)
236 {
237 sysbus_register_dev("uni-north", sizeof(UNINState),
238 pci_unin_main_init_device);
239 pci_qdev_register(&unin_main_pci_host_info);
240 sysbus_register_dev("uni-north-agp", sizeof(UNINState),
241 pci_unin_agp_init_device);
242 pci_qdev_register(&unin_agp_pci_host_info);
243 sysbus_register_dev("uni-north-pci", sizeof(UNINState),
244 pci_unin_internal_init_device);
245 pci_qdev_register(&unin_internal_pci_host_info);
246 }
247
248 device_init(unin_register_devices)