2 * QEMU USB EHCI Emulation
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 * Copyright(c) 2011-2012 Red Hat, Inc.
8 * Gerd Hoffmann <kraxel@redhat.com>
9 * Hans de Goede <hdegoede@redhat.com>
11 * EHCI project was started by Mark Burkley, with contributions by
12 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
13 * Jan Kiszka and Vincent Palatin contributed bugfixes.
16 * This library is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU Lesser General Public
18 * License as published by the Free Software Foundation; either
19 * version 2 of the License, or(at your option) any later version.
21 * This library is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24 * Lesser General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31 #include "qemu-timer.h"
42 #define DPRINTF printf
47 /* internal processing - reset HC to try and recover */
48 #define USB_RET_PROCERR (-99)
50 #define MMIO_SIZE 0x1000
52 /* Capability Registers Base Address - section 2.2 */
53 #define CAPREGBASE 0x0000
54 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
55 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
56 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
57 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
58 #define EECP HCCPARAMS + 1
59 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
60 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
62 #define OPREGBASE 0x0020 // Operational Registers Base Address
64 #define USBCMD OPREGBASE + 0x0000
65 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
66 #define USBCMD_HCRESET (1 << 1) // HC Reset
67 #define USBCMD_FLS (3 << 2) // Frame List Size
68 #define USBCMD_FLS_SH 2 // Frame List Size Shift
69 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
70 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
71 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
72 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
73 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
74 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
75 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
76 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
78 #define USBSTS OPREGBASE + 0x0004
79 #define USBSTS_RO_MASK 0x0000003f
80 #define USBSTS_INT (1 << 0) // USB Interrupt
81 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
82 #define USBSTS_PCD (1 << 2) // Port Change Detect
83 #define USBSTS_FLR (1 << 3) // Frame List Rollover
84 #define USBSTS_HSE (1 << 4) // Host System Error
85 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
86 #define USBSTS_HALT (1 << 12) // HC Halted
87 #define USBSTS_REC (1 << 13) // Reclamation
88 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
89 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
92 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
93 * so no need to redefine here.
95 #define USBINTR OPREGBASE + 0x0008
96 #define USBINTR_MASK 0x0000003f
98 #define FRINDEX OPREGBASE + 0x000c
99 #define CTRLDSSEGMENT OPREGBASE + 0x0010
100 #define PERIODICLISTBASE OPREGBASE + 0x0014
101 #define ASYNCLISTADDR OPREGBASE + 0x0018
102 #define ASYNCLISTADDR_MASK 0xffffffe0
104 #define CONFIGFLAG OPREGBASE + 0x0040
106 #define PORTSC (OPREGBASE + 0x0044)
107 #define PORTSC_BEGIN PORTSC
108 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
110 * Bits that are reserved or are read-only are masked out of values
111 * written to us by software
113 #define PORTSC_RO_MASK 0x007001c0
114 #define PORTSC_RWC_MASK 0x0000002a
115 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
116 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
117 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
118 #define PORTSC_PTC (15 << 16) // Port Test Control
119 #define PORTSC_PTC_SH 16 // Port Test Control shift
120 #define PORTSC_PIC (3 << 14) // Port Indicator Control
121 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
122 #define PORTSC_POWNER (1 << 13) // Port Owner
123 #define PORTSC_PPOWER (1 << 12) // Port Power
124 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
125 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
126 #define PORTSC_PRESET (1 << 8) // Port Reset
127 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
128 #define PORTSC_FPRES (1 << 6) // Force Port Resume
129 #define PORTSC_OCC (1 << 5) // Over Current Change
130 #define PORTSC_OCA (1 << 4) // Over Current Active
131 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
132 #define PORTSC_PED (1 << 2) // Port Enable/Disable
133 #define PORTSC_CSC (1 << 1) // Connect Status Change
134 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
136 #define FRAME_TIMER_FREQ 1000
137 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
139 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
140 #define NB_PORTS 6 // Number of downstream ports
141 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
142 #define MAX_QH 100 // Max allowable queue heads in a chain
143 #define MIN_FR_PER_TICK 3 // Min frames to process when catching up
145 /* Internal periodic / asynchronous schedule state machine states
152 /* The following states are internal to the state machine function
166 /* macros for accessing fields within next link pointer entry */
167 #define NLPTR_GET(x) ((x) & 0xffffffe0)
168 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
169 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
171 /* link pointer types */
172 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
173 #define NLPTR_TYPE_QH 1 // queue head
174 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
175 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
178 /* EHCI spec version 1.0 Section 3.3
180 typedef struct EHCIitd
{
183 uint32_t transact
[8];
184 #define ITD_XACT_ACTIVE (1 << 31)
185 #define ITD_XACT_DBERROR (1 << 30)
186 #define ITD_XACT_BABBLE (1 << 29)
187 #define ITD_XACT_XACTERR (1 << 28)
188 #define ITD_XACT_LENGTH_MASK 0x0fff0000
189 #define ITD_XACT_LENGTH_SH 16
190 #define ITD_XACT_IOC (1 << 15)
191 #define ITD_XACT_PGSEL_MASK 0x00007000
192 #define ITD_XACT_PGSEL_SH 12
193 #define ITD_XACT_OFFSET_MASK 0x00000fff
196 #define ITD_BUFPTR_MASK 0xfffff000
197 #define ITD_BUFPTR_SH 12
198 #define ITD_BUFPTR_EP_MASK 0x00000f00
199 #define ITD_BUFPTR_EP_SH 8
200 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
201 #define ITD_BUFPTR_DEVADDR_SH 0
202 #define ITD_BUFPTR_DIRECTION (1 << 11)
203 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
204 #define ITD_BUFPTR_MAXPKT_SH 0
205 #define ITD_BUFPTR_MULT_MASK 0x00000003
206 #define ITD_BUFPTR_MULT_SH 0
209 /* EHCI spec version 1.0 Section 3.4
211 typedef struct EHCIsitd
{
212 uint32_t next
; // Standard next link pointer
214 #define SITD_EPCHAR_IO (1 << 31)
215 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
216 #define SITD_EPCHAR_PORTNUM_SH 24
217 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
218 #define SITD_EPCHAR_HUBADDR_SH 16
219 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
220 #define SITD_EPCHAR_EPNUM_SH 8
221 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
224 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
225 #define SITD_UFRAME_CMASK_SH 8
226 #define SITD_UFRAME_SMASK_MASK 0x000000ff
229 #define SITD_RESULTS_IOC (1 << 31)
230 #define SITD_RESULTS_PGSEL (1 << 30)
231 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
232 #define SITD_RESULTS_TYBYTES_SH 16
233 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
234 #define SITD_RESULTS_CPROGMASK_SH 8
235 #define SITD_RESULTS_ACTIVE (1 << 7)
236 #define SITD_RESULTS_ERR (1 << 6)
237 #define SITD_RESULTS_DBERR (1 << 5)
238 #define SITD_RESULTS_BABBLE (1 << 4)
239 #define SITD_RESULTS_XACTERR (1 << 3)
240 #define SITD_RESULTS_MISSEDUF (1 << 2)
241 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
244 #define SITD_BUFPTR_MASK 0xfffff000
245 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
246 #define SITD_BUFPTR_TPOS_MASK 0x00000018
247 #define SITD_BUFPTR_TPOS_SH 3
248 #define SITD_BUFPTR_TCNT_MASK 0x00000007
250 uint32_t backptr
; // Standard next link pointer
253 /* EHCI spec version 1.0 Section 3.5
255 typedef struct EHCIqtd
{
256 uint32_t next
; // Standard next link pointer
257 uint32_t altnext
; // Standard next link pointer
259 #define QTD_TOKEN_DTOGGLE (1 << 31)
260 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
261 #define QTD_TOKEN_TBYTES_SH 16
262 #define QTD_TOKEN_IOC (1 << 15)
263 #define QTD_TOKEN_CPAGE_MASK 0x00007000
264 #define QTD_TOKEN_CPAGE_SH 12
265 #define QTD_TOKEN_CERR_MASK 0x00000c00
266 #define QTD_TOKEN_CERR_SH 10
267 #define QTD_TOKEN_PID_MASK 0x00000300
268 #define QTD_TOKEN_PID_SH 8
269 #define QTD_TOKEN_ACTIVE (1 << 7)
270 #define QTD_TOKEN_HALT (1 << 6)
271 #define QTD_TOKEN_DBERR (1 << 5)
272 #define QTD_TOKEN_BABBLE (1 << 4)
273 #define QTD_TOKEN_XACTERR (1 << 3)
274 #define QTD_TOKEN_MISSEDUF (1 << 2)
275 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
276 #define QTD_TOKEN_PING (1 << 0)
278 uint32_t bufptr
[5]; // Standard buffer pointer
279 #define QTD_BUFPTR_MASK 0xfffff000
280 #define QTD_BUFPTR_SH 12
283 /* EHCI spec version 1.0 Section 3.6
285 typedef struct EHCIqh
{
286 uint32_t next
; // Standard next link pointer
288 /* endpoint characteristics */
290 #define QH_EPCHAR_RL_MASK 0xf0000000
291 #define QH_EPCHAR_RL_SH 28
292 #define QH_EPCHAR_C (1 << 27)
293 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
294 #define QH_EPCHAR_MPLEN_SH 16
295 #define QH_EPCHAR_H (1 << 15)
296 #define QH_EPCHAR_DTC (1 << 14)
297 #define QH_EPCHAR_EPS_MASK 0x00003000
298 #define QH_EPCHAR_EPS_SH 12
299 #define EHCI_QH_EPS_FULL 0
300 #define EHCI_QH_EPS_LOW 1
301 #define EHCI_QH_EPS_HIGH 2
302 #define EHCI_QH_EPS_RESERVED 3
304 #define QH_EPCHAR_EP_MASK 0x00000f00
305 #define QH_EPCHAR_EP_SH 8
306 #define QH_EPCHAR_I (1 << 7)
307 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
308 #define QH_EPCHAR_DEVADDR_SH 0
310 /* endpoint capabilities */
312 #define QH_EPCAP_MULT_MASK 0xc0000000
313 #define QH_EPCAP_MULT_SH 30
314 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
315 #define QH_EPCAP_PORTNUM_SH 23
316 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
317 #define QH_EPCAP_HUBADDR_SH 16
318 #define QH_EPCAP_CMASK_MASK 0x0000ff00
319 #define QH_EPCAP_CMASK_SH 8
320 #define QH_EPCAP_SMASK_MASK 0x000000ff
321 #define QH_EPCAP_SMASK_SH 0
323 uint32_t current_qtd
; // Standard next link pointer
324 uint32_t next_qtd
; // Standard next link pointer
325 uint32_t altnext_qtd
;
326 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
327 #define QH_ALTNEXT_NAKCNT_SH 1
329 uint32_t token
; // Same as QTD token
330 uint32_t bufptr
[5]; // Standard buffer pointer
331 #define BUFPTR_CPROGMASK_MASK 0x000000ff
332 #define BUFPTR_FRAMETAG_MASK 0x0000001f
333 #define BUFPTR_SBYTES_MASK 0x00000fe0
334 #define BUFPTR_SBYTES_SH 5
337 /* EHCI spec version 1.0 Section 3.7
339 typedef struct EHCIfstn
{
340 uint32_t next
; // Standard next link pointer
341 uint32_t backptr
; // Standard next link pointer
344 typedef struct EHCIPacket EHCIPacket
;
345 typedef struct EHCIQueue EHCIQueue
;
346 typedef struct EHCIState EHCIState
;
350 EHCI_ASYNC_INITIALIZED
,
357 QTAILQ_ENTRY(EHCIPacket
) next
;
359 EHCIqtd qtd
; /* copy of current QTD (being worked on) */
360 uint32_t qtdaddr
; /* address QTD read from */
366 enum async_state async
;
372 QTAILQ_ENTRY(EHCIQueue
) next
;
378 /* cached data from guest - needs to be flushed
379 * when guest removes an entry (doorbell, handshake sequence)
381 EHCIqh qh
; /* copy of current QH (being worked on) */
382 uint32_t qhaddr
; /* address QH read from */
383 uint32_t qtdaddr
; /* address QTD read from */
385 QTAILQ_HEAD(, EHCIPacket
) packets
;
388 typedef QTAILQ_HEAD(EHCIQueueHead
, EHCIQueue
) EHCIQueueHead
;
395 MemoryRegion mem_caps
;
396 MemoryRegion mem_opreg
;
397 MemoryRegion mem_ports
;
404 * EHCI spec version 1.0 Section 2.3
405 * Host Controller Operational Registers
407 uint8_t caps
[OPREGBASE
];
409 uint32_t opreg
[(PORTSC_BEGIN
-OPREGBASE
)/sizeof(uint32_t)];
415 uint32_t ctrldssegment
;
416 uint32_t periodiclistbase
;
417 uint32_t asynclistaddr
;
422 uint32_t portsc
[NB_PORTS
];
425 * Internal states, shadow registers, etc
427 QEMUTimer
*frame_timer
;
429 uint32_t astate
; /* Current state in asynchronous schedule */
430 uint32_t pstate
; /* Current state in periodic schedule */
431 USBPort ports
[NB_PORTS
];
432 USBPort
*companion_ports
[NB_PORTS
];
433 uint32_t usbsts_pending
;
434 uint32_t usbsts_frindex
;
435 EHCIQueueHead aqueues
;
436 EHCIQueueHead pqueues
;
438 /* which address to look at next */
439 uint32_t a_fetch_addr
;
440 uint32_t p_fetch_addr
;
445 uint64_t last_run_ns
;
446 uint32_t async_stepdown
;
449 #define SET_LAST_RUN_CLOCK(s) \
450 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
452 /* nifty macros from Arnon's EHCI version */
453 #define get_field(data, field) \
454 (((data) & field##_MASK) >> field##_SH)
456 #define set_field(data, newval, field) do { \
457 uint32_t val = *data; \
458 val &= ~ field##_MASK; \
459 val |= ((newval) << field##_SH) & field##_MASK; \
463 static const char *ehci_state_names
[] = {
464 [EST_INACTIVE
] = "INACTIVE",
465 [EST_ACTIVE
] = "ACTIVE",
466 [EST_EXECUTING
] = "EXECUTING",
467 [EST_SLEEPING
] = "SLEEPING",
468 [EST_WAITLISTHEAD
] = "WAITLISTHEAD",
469 [EST_FETCHENTRY
] = "FETCH ENTRY",
470 [EST_FETCHQH
] = "FETCH QH",
471 [EST_FETCHITD
] = "FETCH ITD",
472 [EST_ADVANCEQUEUE
] = "ADVANCEQUEUE",
473 [EST_FETCHQTD
] = "FETCH QTD",
474 [EST_EXECUTE
] = "EXECUTE",
475 [EST_WRITEBACK
] = "WRITEBACK",
476 [EST_HORIZONTALQH
] = "HORIZONTALQH",
479 static const char *ehci_mmio_names
[] = {
482 [USBINTR
] = "USBINTR",
483 [FRINDEX
] = "FRINDEX",
484 [PERIODICLISTBASE
] = "P-LIST BASE",
485 [ASYNCLISTADDR
] = "A-LIST ADDR",
486 [CONFIGFLAG
] = "CONFIGFLAG",
489 static int ehci_state_executing(EHCIQueue
*q
);
490 static int ehci_state_writeback(EHCIQueue
*q
);
492 static const char *nr2str(const char **n
, size_t len
, uint32_t nr
)
494 if (nr
< len
&& n
[nr
] != NULL
) {
501 static const char *state2str(uint32_t state
)
503 return nr2str(ehci_state_names
, ARRAY_SIZE(ehci_state_names
), state
);
506 static const char *addr2str(target_phys_addr_t addr
)
508 return nr2str(ehci_mmio_names
, ARRAY_SIZE(ehci_mmio_names
),
512 static void ehci_trace_usbsts(uint32_t mask
, int state
)
515 if (mask
& USBSTS_INT
) {
516 trace_usb_ehci_usbsts("INT", state
);
518 if (mask
& USBSTS_ERRINT
) {
519 trace_usb_ehci_usbsts("ERRINT", state
);
521 if (mask
& USBSTS_PCD
) {
522 trace_usb_ehci_usbsts("PCD", state
);
524 if (mask
& USBSTS_FLR
) {
525 trace_usb_ehci_usbsts("FLR", state
);
527 if (mask
& USBSTS_HSE
) {
528 trace_usb_ehci_usbsts("HSE", state
);
530 if (mask
& USBSTS_IAA
) {
531 trace_usb_ehci_usbsts("IAA", state
);
535 if (mask
& USBSTS_HALT
) {
536 trace_usb_ehci_usbsts("HALT", state
);
538 if (mask
& USBSTS_REC
) {
539 trace_usb_ehci_usbsts("REC", state
);
541 if (mask
& USBSTS_PSS
) {
542 trace_usb_ehci_usbsts("PSS", state
);
544 if (mask
& USBSTS_ASS
) {
545 trace_usb_ehci_usbsts("ASS", state
);
549 static inline void ehci_set_usbsts(EHCIState
*s
, int mask
)
551 if ((s
->usbsts
& mask
) == mask
) {
554 ehci_trace_usbsts(mask
, 1);
558 static inline void ehci_clear_usbsts(EHCIState
*s
, int mask
)
560 if ((s
->usbsts
& mask
) == 0) {
563 ehci_trace_usbsts(mask
, 0);
567 /* update irq line */
568 static inline void ehci_update_irq(EHCIState
*s
)
572 if ((s
->usbsts
& USBINTR_MASK
) & s
->usbintr
) {
576 trace_usb_ehci_irq(level
, s
->frindex
, s
->usbsts
, s
->usbintr
);
577 qemu_set_irq(s
->irq
, level
);
580 /* flag interrupt condition */
581 static inline void ehci_raise_irq(EHCIState
*s
, int intr
)
583 if (intr
& (USBSTS_PCD
| USBSTS_FLR
| USBSTS_HSE
)) {
587 s
->usbsts_pending
|= intr
;
592 * Commit pending interrupts (added via ehci_raise_irq),
593 * at the rate allowed by "Interrupt Threshold Control".
595 static inline void ehci_commit_irq(EHCIState
*s
)
599 if (!s
->usbsts_pending
) {
602 if (s
->usbsts_frindex
> s
->frindex
) {
606 itc
= (s
->usbcmd
>> 16) & 0xff;
607 s
->usbsts
|= s
->usbsts_pending
;
608 s
->usbsts_pending
= 0;
609 s
->usbsts_frindex
= s
->frindex
+ itc
;
613 static void ehci_update_halt(EHCIState
*s
)
615 if (s
->usbcmd
& USBCMD_RUNSTOP
) {
616 ehci_clear_usbsts(s
, USBSTS_HALT
);
618 if (s
->astate
== EST_INACTIVE
&& s
->pstate
== EST_INACTIVE
) {
619 ehci_set_usbsts(s
, USBSTS_HALT
);
624 static void ehci_set_state(EHCIState
*s
, int async
, int state
)
627 trace_usb_ehci_state("async", state2str(state
));
629 if (s
->astate
== EST_INACTIVE
) {
630 ehci_clear_usbsts(s
, USBSTS_ASS
);
633 ehci_set_usbsts(s
, USBSTS_ASS
);
636 trace_usb_ehci_state("periodic", state2str(state
));
638 if (s
->pstate
== EST_INACTIVE
) {
639 ehci_clear_usbsts(s
, USBSTS_PSS
);
642 ehci_set_usbsts(s
, USBSTS_PSS
);
647 static int ehci_get_state(EHCIState
*s
, int async
)
649 return async
? s
->astate
: s
->pstate
;
652 static void ehci_set_fetch_addr(EHCIState
*s
, int async
, uint32_t addr
)
655 s
->a_fetch_addr
= addr
;
657 s
->p_fetch_addr
= addr
;
661 static int ehci_get_fetch_addr(EHCIState
*s
, int async
)
663 return async
? s
->a_fetch_addr
: s
->p_fetch_addr
;
666 static void ehci_trace_qh(EHCIQueue
*q
, target_phys_addr_t addr
, EHCIqh
*qh
)
668 /* need three here due to argument count limits */
669 trace_usb_ehci_qh_ptrs(q
, addr
, qh
->next
,
670 qh
->current_qtd
, qh
->next_qtd
, qh
->altnext_qtd
);
671 trace_usb_ehci_qh_fields(addr
,
672 get_field(qh
->epchar
, QH_EPCHAR_RL
),
673 get_field(qh
->epchar
, QH_EPCHAR_MPLEN
),
674 get_field(qh
->epchar
, QH_EPCHAR_EPS
),
675 get_field(qh
->epchar
, QH_EPCHAR_EP
),
676 get_field(qh
->epchar
, QH_EPCHAR_DEVADDR
));
677 trace_usb_ehci_qh_bits(addr
,
678 (bool)(qh
->epchar
& QH_EPCHAR_C
),
679 (bool)(qh
->epchar
& QH_EPCHAR_H
),
680 (bool)(qh
->epchar
& QH_EPCHAR_DTC
),
681 (bool)(qh
->epchar
& QH_EPCHAR_I
));
684 static void ehci_trace_qtd(EHCIQueue
*q
, target_phys_addr_t addr
, EHCIqtd
*qtd
)
686 /* need three here due to argument count limits */
687 trace_usb_ehci_qtd_ptrs(q
, addr
, qtd
->next
, qtd
->altnext
);
688 trace_usb_ehci_qtd_fields(addr
,
689 get_field(qtd
->token
, QTD_TOKEN_TBYTES
),
690 get_field(qtd
->token
, QTD_TOKEN_CPAGE
),
691 get_field(qtd
->token
, QTD_TOKEN_CERR
),
692 get_field(qtd
->token
, QTD_TOKEN_PID
));
693 trace_usb_ehci_qtd_bits(addr
,
694 (bool)(qtd
->token
& QTD_TOKEN_IOC
),
695 (bool)(qtd
->token
& QTD_TOKEN_ACTIVE
),
696 (bool)(qtd
->token
& QTD_TOKEN_HALT
),
697 (bool)(qtd
->token
& QTD_TOKEN_BABBLE
),
698 (bool)(qtd
->token
& QTD_TOKEN_XACTERR
));
701 static void ehci_trace_itd(EHCIState
*s
, target_phys_addr_t addr
, EHCIitd
*itd
)
703 trace_usb_ehci_itd(addr
, itd
->next
,
704 get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
),
705 get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
),
706 get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
),
707 get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
));
710 static void ehci_trace_sitd(EHCIState
*s
, target_phys_addr_t addr
,
713 trace_usb_ehci_sitd(addr
, sitd
->next
,
714 (bool)(sitd
->results
& SITD_RESULTS_ACTIVE
));
717 static void ehci_trace_guest_bug(EHCIState
*s
, const char *message
)
719 trace_usb_ehci_guest_bug(message
);
720 fprintf(stderr
, "ehci warning: %s\n", message
);
723 static inline bool ehci_enabled(EHCIState
*s
)
725 return s
->usbcmd
& USBCMD_RUNSTOP
;
728 static inline bool ehci_async_enabled(EHCIState
*s
)
730 return ehci_enabled(s
) && (s
->usbcmd
& USBCMD_ASE
);
733 static inline bool ehci_periodic_enabled(EHCIState
*s
)
735 return ehci_enabled(s
) && (s
->usbcmd
& USBCMD_PSE
);
738 /* packet management */
740 static EHCIPacket
*ehci_alloc_packet(EHCIQueue
*q
)
744 p
= g_new0(EHCIPacket
, 1);
746 usb_packet_init(&p
->packet
);
747 QTAILQ_INSERT_TAIL(&q
->packets
, p
, next
);
748 trace_usb_ehci_packet_action(p
->queue
, p
, "alloc");
752 static void ehci_free_packet(EHCIPacket
*p
)
754 if (p
->async
== EHCI_ASYNC_FINISHED
) {
755 int state
= ehci_get_state(p
->queue
->ehci
, p
->queue
->async
);
756 /* This is a normal, but rare condition (cancel racing completion) */
757 fprintf(stderr
, "EHCI: Warning packet completed but not processed\n");
758 ehci_state_executing(p
->queue
);
759 ehci_state_writeback(p
->queue
);
760 ehci_set_state(p
->queue
->ehci
, p
->queue
->async
, state
);
761 /* state_writeback recurses into us with async == EHCI_ASYNC_NONE!! */
764 trace_usb_ehci_packet_action(p
->queue
, p
, "free");
765 if (p
->async
== EHCI_ASYNC_INITIALIZED
) {
766 usb_packet_unmap(&p
->packet
, &p
->sgl
);
767 qemu_sglist_destroy(&p
->sgl
);
769 if (p
->async
== EHCI_ASYNC_INFLIGHT
) {
770 usb_cancel_packet(&p
->packet
);
771 usb_packet_unmap(&p
->packet
, &p
->sgl
);
772 qemu_sglist_destroy(&p
->sgl
);
774 QTAILQ_REMOVE(&p
->queue
->packets
, p
, next
);
775 usb_packet_cleanup(&p
->packet
);
779 /* queue management */
781 static EHCIQueue
*ehci_alloc_queue(EHCIState
*ehci
, uint32_t addr
, int async
)
783 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
786 q
= g_malloc0(sizeof(*q
));
790 QTAILQ_INIT(&q
->packets
);
791 QTAILQ_INSERT_HEAD(head
, q
, next
);
792 trace_usb_ehci_queue_action(q
, "alloc");
796 static int ehci_cancel_queue(EHCIQueue
*q
)
801 p
= QTAILQ_FIRST(&q
->packets
);
806 trace_usb_ehci_queue_action(q
, "cancel");
810 } while ((p
= QTAILQ_FIRST(&q
->packets
)) != NULL
);
814 static int ehci_reset_queue(EHCIQueue
*q
)
818 trace_usb_ehci_queue_action(q
, "reset");
819 packets
= ehci_cancel_queue(q
);
825 static void ehci_free_queue(EHCIQueue
*q
, const char *warn
)
827 EHCIQueueHead
*head
= q
->async
? &q
->ehci
->aqueues
: &q
->ehci
->pqueues
;
830 trace_usb_ehci_queue_action(q
, "free");
831 cancelled
= ehci_cancel_queue(q
);
832 if (warn
&& cancelled
> 0) {
833 ehci_trace_guest_bug(q
->ehci
, warn
);
835 QTAILQ_REMOVE(head
, q
, next
);
839 static EHCIQueue
*ehci_find_queue_by_qh(EHCIState
*ehci
, uint32_t addr
,
842 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
845 QTAILQ_FOREACH(q
, head
, next
) {
846 if (addr
== q
->qhaddr
) {
853 static void ehci_queues_rip_unused(EHCIState
*ehci
, int async
)
855 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
856 const char *warn
= async
? "guest unlinked busy QH" : NULL
;
857 uint64_t maxage
= FRAME_TIMER_NS
* ehci
->maxframes
* 4;
860 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
863 q
->ts
= ehci
->last_run_ns
;
866 if (ehci
->last_run_ns
< q
->ts
+ maxage
) {
869 ehci_free_queue(q
, warn
);
873 static void ehci_queues_rip_unseen(EHCIState
*ehci
, int async
)
875 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
878 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
880 ehci_free_queue(q
, NULL
);
885 static void ehci_queues_rip_device(EHCIState
*ehci
, USBDevice
*dev
, int async
)
887 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
890 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
894 ehci_free_queue(q
, NULL
);
898 static void ehci_queues_rip_all(EHCIState
*ehci
, int async
)
900 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
901 const char *warn
= async
? "guest stopped busy async schedule" : NULL
;
904 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
905 ehci_free_queue(q
, warn
);
909 /* Attach or detach a device on root hub */
911 static void ehci_attach(USBPort
*port
)
913 EHCIState
*s
= port
->opaque
;
914 uint32_t *portsc
= &s
->portsc
[port
->index
];
915 const char *owner
= (*portsc
& PORTSC_POWNER
) ? "comp" : "ehci";
917 trace_usb_ehci_port_attach(port
->index
, owner
, port
->dev
->product_desc
);
919 if (*portsc
& PORTSC_POWNER
) {
920 USBPort
*companion
= s
->companion_ports
[port
->index
];
921 companion
->dev
= port
->dev
;
922 companion
->ops
->attach(companion
);
926 *portsc
|= PORTSC_CONNECT
;
927 *portsc
|= PORTSC_CSC
;
929 ehci_raise_irq(s
, USBSTS_PCD
);
933 static void ehci_detach(USBPort
*port
)
935 EHCIState
*s
= port
->opaque
;
936 uint32_t *portsc
= &s
->portsc
[port
->index
];
937 const char *owner
= (*portsc
& PORTSC_POWNER
) ? "comp" : "ehci";
939 trace_usb_ehci_port_detach(port
->index
, owner
);
941 if (*portsc
& PORTSC_POWNER
) {
942 USBPort
*companion
= s
->companion_ports
[port
->index
];
943 companion
->ops
->detach(companion
);
944 companion
->dev
= NULL
;
946 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
947 * the port ownership is returned immediately to the EHCI controller."
949 *portsc
&= ~PORTSC_POWNER
;
953 ehci_queues_rip_device(s
, port
->dev
, 0);
954 ehci_queues_rip_device(s
, port
->dev
, 1);
956 *portsc
&= ~(PORTSC_CONNECT
|PORTSC_PED
);
957 *portsc
|= PORTSC_CSC
;
959 ehci_raise_irq(s
, USBSTS_PCD
);
963 static void ehci_child_detach(USBPort
*port
, USBDevice
*child
)
965 EHCIState
*s
= port
->opaque
;
966 uint32_t portsc
= s
->portsc
[port
->index
];
968 if (portsc
& PORTSC_POWNER
) {
969 USBPort
*companion
= s
->companion_ports
[port
->index
];
970 companion
->ops
->child_detach(companion
, child
);
974 ehci_queues_rip_device(s
, child
, 0);
975 ehci_queues_rip_device(s
, child
, 1);
978 static void ehci_wakeup(USBPort
*port
)
980 EHCIState
*s
= port
->opaque
;
981 uint32_t portsc
= s
->portsc
[port
->index
];
983 if (portsc
& PORTSC_POWNER
) {
984 USBPort
*companion
= s
->companion_ports
[port
->index
];
985 if (companion
->ops
->wakeup
) {
986 companion
->ops
->wakeup(companion
);
991 qemu_bh_schedule(s
->async_bh
);
994 static int ehci_register_companion(USBBus
*bus
, USBPort
*ports
[],
995 uint32_t portcount
, uint32_t firstport
)
997 EHCIState
*s
= container_of(bus
, EHCIState
, bus
);
1000 if (firstport
+ portcount
> NB_PORTS
) {
1001 qerror_report(QERR_INVALID_PARAMETER_VALUE
, "firstport",
1002 "firstport on masterbus");
1003 error_printf_unless_qmp(
1004 "firstport value of %u makes companion take ports %u - %u, which "
1005 "is outside of the valid range of 0 - %u\n", firstport
, firstport
,
1006 firstport
+ portcount
- 1, NB_PORTS
- 1);
1010 for (i
= 0; i
< portcount
; i
++) {
1011 if (s
->companion_ports
[firstport
+ i
]) {
1012 qerror_report(QERR_INVALID_PARAMETER_VALUE
, "masterbus",
1013 "an USB masterbus");
1014 error_printf_unless_qmp(
1015 "port %u on masterbus %s already has a companion assigned\n",
1016 firstport
+ i
, bus
->qbus
.name
);
1021 for (i
= 0; i
< portcount
; i
++) {
1022 s
->companion_ports
[firstport
+ i
] = ports
[i
];
1023 s
->ports
[firstport
+ i
].speedmask
|=
1024 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
;
1025 /* Ensure devs attached before the initial reset go to the companion */
1026 s
->portsc
[firstport
+ i
] = PORTSC_POWNER
;
1029 s
->companion_count
++;
1030 s
->caps
[0x05] = (s
->companion_count
<< 4) | portcount
;
1035 static USBDevice
*ehci_find_device(EHCIState
*ehci
, uint8_t addr
)
1041 for (i
= 0; i
< NB_PORTS
; i
++) {
1042 port
= &ehci
->ports
[i
];
1043 if (!(ehci
->portsc
[i
] & PORTSC_PED
)) {
1044 DPRINTF("Port %d not enabled\n", i
);
1047 dev
= usb_find_device(port
, addr
);
1055 /* 4.1 host controller initialization */
1056 static void ehci_reset(void *opaque
)
1058 EHCIState
*s
= opaque
;
1060 USBDevice
*devs
[NB_PORTS
];
1062 trace_usb_ehci_reset();
1065 * Do the detach before touching portsc, so that it correctly gets send to
1066 * us or to our companion based on PORTSC_POWNER before the reset.
1068 for(i
= 0; i
< NB_PORTS
; i
++) {
1069 devs
[i
] = s
->ports
[i
].dev
;
1070 if (devs
[i
] && devs
[i
]->attached
) {
1071 usb_detach(&s
->ports
[i
]);
1075 memset(&s
->opreg
, 0x00, sizeof(s
->opreg
));
1076 memset(&s
->portsc
, 0x00, sizeof(s
->portsc
));
1078 s
->usbcmd
= NB_MAXINTRATE
<< USBCMD_ITC_SH
;
1079 s
->usbsts
= USBSTS_HALT
;
1080 s
->usbsts_pending
= 0;
1081 s
->usbsts_frindex
= 0;
1083 s
->astate
= EST_INACTIVE
;
1084 s
->pstate
= EST_INACTIVE
;
1086 for(i
= 0; i
< NB_PORTS
; i
++) {
1087 if (s
->companion_ports
[i
]) {
1088 s
->portsc
[i
] = PORTSC_POWNER
| PORTSC_PPOWER
;
1090 s
->portsc
[i
] = PORTSC_PPOWER
;
1092 if (devs
[i
] && devs
[i
]->attached
) {
1093 usb_attach(&s
->ports
[i
]);
1094 usb_device_reset(devs
[i
]);
1097 ehci_queues_rip_all(s
, 0);
1098 ehci_queues_rip_all(s
, 1);
1099 qemu_del_timer(s
->frame_timer
);
1100 qemu_bh_cancel(s
->async_bh
);
1103 static uint64_t ehci_caps_read(void *ptr
, target_phys_addr_t addr
,
1107 return s
->caps
[addr
];
1110 static uint64_t ehci_opreg_read(void *ptr
, target_phys_addr_t addr
,
1116 val
= s
->opreg
[addr
>> 2];
1117 trace_usb_ehci_opreg_read(addr
+ OPREGBASE
, addr2str(addr
), val
);
1121 static uint64_t ehci_port_read(void *ptr
, target_phys_addr_t addr
,
1127 val
= s
->portsc
[addr
>> 2];
1128 trace_usb_ehci_portsc_read(addr
+ PORTSC_BEGIN
, addr
>> 2, val
);
1132 static void handle_port_owner_write(EHCIState
*s
, int port
, uint32_t owner
)
1134 USBDevice
*dev
= s
->ports
[port
].dev
;
1135 uint32_t *portsc
= &s
->portsc
[port
];
1138 if (s
->companion_ports
[port
] == NULL
)
1141 owner
= owner
& PORTSC_POWNER
;
1142 orig
= *portsc
& PORTSC_POWNER
;
1144 if (!(owner
^ orig
)) {
1148 if (dev
&& dev
->attached
) {
1149 usb_detach(&s
->ports
[port
]);
1152 *portsc
&= ~PORTSC_POWNER
;
1155 if (dev
&& dev
->attached
) {
1156 usb_attach(&s
->ports
[port
]);
1160 static void ehci_port_write(void *ptr
, target_phys_addr_t addr
,
1161 uint64_t val
, unsigned size
)
1164 int port
= addr
>> 2;
1165 uint32_t *portsc
= &s
->portsc
[port
];
1166 uint32_t old
= *portsc
;
1167 USBDevice
*dev
= s
->ports
[port
].dev
;
1169 trace_usb_ehci_portsc_write(addr
+ PORTSC_BEGIN
, addr
>> 2, val
);
1171 /* Clear rwc bits */
1172 *portsc
&= ~(val
& PORTSC_RWC_MASK
);
1173 /* The guest may clear, but not set the PED bit */
1174 *portsc
&= val
| ~PORTSC_PED
;
1175 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1176 handle_port_owner_write(s
, port
, val
);
1177 /* And finally apply RO_MASK */
1178 val
&= PORTSC_RO_MASK
;
1180 if ((val
& PORTSC_PRESET
) && !(*portsc
& PORTSC_PRESET
)) {
1181 trace_usb_ehci_port_reset(port
, 1);
1184 if (!(val
& PORTSC_PRESET
) &&(*portsc
& PORTSC_PRESET
)) {
1185 trace_usb_ehci_port_reset(port
, 0);
1186 if (dev
&& dev
->attached
) {
1187 usb_port_reset(&s
->ports
[port
]);
1188 *portsc
&= ~PORTSC_CSC
;
1192 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1193 * to SW that this port has a high speed device attached
1195 if (dev
&& dev
->attached
&& (dev
->speedmask
& USB_SPEED_MASK_HIGH
)) {
1200 *portsc
&= ~PORTSC_RO_MASK
;
1202 trace_usb_ehci_portsc_change(addr
+ PORTSC_BEGIN
, addr
>> 2, *portsc
, old
);
1205 static void ehci_opreg_write(void *ptr
, target_phys_addr_t addr
,
1206 uint64_t val
, unsigned size
)
1209 uint32_t *mmio
= s
->opreg
+ (addr
>> 2);
1210 uint32_t old
= *mmio
;
1213 trace_usb_ehci_opreg_write(addr
+ OPREGBASE
, addr2str(addr
), val
);
1215 switch (addr
+ OPREGBASE
) {
1217 if (val
& USBCMD_HCRESET
) {
1223 /* not supporting dynamic frame list size at the moment */
1224 if ((val
& USBCMD_FLS
) && !(s
->usbcmd
& USBCMD_FLS
)) {
1225 fprintf(stderr
, "attempt to set frame list size -- value %d\n",
1226 (int)val
& USBCMD_FLS
);
1230 if (val
& USBCMD_IAAD
) {
1232 * Process IAAD immediately, otherwise the Linux IAAD watchdog may
1233 * trigger and re-use a qh without us seeing the unlink.
1235 s
->async_stepdown
= 0;
1236 qemu_bh_schedule(s
->async_bh
);
1237 trace_usb_ehci_doorbell_ring();
1240 if (((USBCMD_RUNSTOP
| USBCMD_PSE
| USBCMD_ASE
) & val
) !=
1241 ((USBCMD_RUNSTOP
| USBCMD_PSE
| USBCMD_ASE
) & s
->usbcmd
)) {
1242 if (s
->pstate
== EST_INACTIVE
) {
1243 SET_LAST_RUN_CLOCK(s
);
1245 s
->usbcmd
= val
; /* Set usbcmd for ehci_update_halt() */
1246 ehci_update_halt(s
);
1247 s
->async_stepdown
= 0;
1248 qemu_mod_timer(s
->frame_timer
, qemu_get_clock_ns(vm_clock
));
1253 val
&= USBSTS_RO_MASK
; // bits 6 through 31 are RO
1254 ehci_clear_usbsts(s
, val
); // bits 0 through 5 are R/WC
1260 val
&= USBINTR_MASK
;
1264 val
&= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
1270 for(i
= 0; i
< NB_PORTS
; i
++)
1271 handle_port_owner_write(s
, i
, 0);
1275 case PERIODICLISTBASE
:
1276 if (ehci_periodic_enabled(s
)) {
1278 "ehci: PERIODIC list base register set while periodic schedule\n"
1279 " is enabled and HC is enabled\n");
1284 if (ehci_async_enabled(s
)) {
1286 "ehci: ASYNC list address register set while async schedule\n"
1287 " is enabled and HC is enabled\n");
1293 trace_usb_ehci_opreg_change(addr
+ OPREGBASE
, addr2str(addr
), *mmio
, old
);
1297 // TODO : Put in common header file, duplication from usb-ohci.c
1299 /* Get an array of dwords from main memory */
1300 static inline int get_dwords(EHCIState
*ehci
, uint32_t addr
,
1301 uint32_t *buf
, int num
)
1305 for(i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
1306 pci_dma_read(&ehci
->dev
, addr
, buf
, sizeof(*buf
));
1307 *buf
= le32_to_cpu(*buf
);
1313 /* Put an array of dwords in to main memory */
1314 static inline int put_dwords(EHCIState
*ehci
, uint32_t addr
,
1315 uint32_t *buf
, int num
)
1319 for(i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
1320 uint32_t tmp
= cpu_to_le32(*buf
);
1321 pci_dma_write(&ehci
->dev
, addr
, &tmp
, sizeof(tmp
));
1328 * Write the qh back to guest physical memory. This step isn't
1329 * in the EHCI spec but we need to do it since we don't share
1330 * physical memory with our guest VM.
1332 * The first three dwords are read-only for the EHCI, so skip them
1333 * when writing back the qh.
1335 static void ehci_flush_qh(EHCIQueue
*q
)
1337 uint32_t *qh
= (uint32_t *) &q
->qh
;
1338 uint32_t dwords
= sizeof(EHCIqh
) >> 2;
1339 uint32_t addr
= NLPTR_GET(q
->qhaddr
);
1341 put_dwords(q
->ehci
, addr
+ 3 * sizeof(uint32_t), qh
+ 3, dwords
- 3);
1346 static int ehci_qh_do_overlay(EHCIQueue
*q
)
1348 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1356 assert(p
->qtdaddr
== q
->qtdaddr
);
1358 // remember values in fields to preserve in qh after overlay
1360 dtoggle
= q
->qh
.token
& QTD_TOKEN_DTOGGLE
;
1361 ping
= q
->qh
.token
& QTD_TOKEN_PING
;
1363 q
->qh
.current_qtd
= p
->qtdaddr
;
1364 q
->qh
.next_qtd
= p
->qtd
.next
;
1365 q
->qh
.altnext_qtd
= p
->qtd
.altnext
;
1366 q
->qh
.token
= p
->qtd
.token
;
1369 eps
= get_field(q
->qh
.epchar
, QH_EPCHAR_EPS
);
1370 if (eps
== EHCI_QH_EPS_HIGH
) {
1371 q
->qh
.token
&= ~QTD_TOKEN_PING
;
1372 q
->qh
.token
|= ping
;
1375 reload
= get_field(q
->qh
.epchar
, QH_EPCHAR_RL
);
1376 set_field(&q
->qh
.altnext_qtd
, reload
, QH_ALTNEXT_NAKCNT
);
1378 for (i
= 0; i
< 5; i
++) {
1379 q
->qh
.bufptr
[i
] = p
->qtd
.bufptr
[i
];
1382 if (!(q
->qh
.epchar
& QH_EPCHAR_DTC
)) {
1383 // preserve QH DT bit
1384 q
->qh
.token
&= ~QTD_TOKEN_DTOGGLE
;
1385 q
->qh
.token
|= dtoggle
;
1388 q
->qh
.bufptr
[1] &= ~BUFPTR_CPROGMASK_MASK
;
1389 q
->qh
.bufptr
[2] &= ~BUFPTR_FRAMETAG_MASK
;
1396 static int ehci_init_transfer(EHCIPacket
*p
)
1398 uint32_t cpage
, offset
, bytes
, plen
;
1401 cpage
= get_field(p
->qtd
.token
, QTD_TOKEN_CPAGE
);
1402 bytes
= get_field(p
->qtd
.token
, QTD_TOKEN_TBYTES
);
1403 offset
= p
->qtd
.bufptr
[0] & ~QTD_BUFPTR_MASK
;
1404 pci_dma_sglist_init(&p
->sgl
, &p
->queue
->ehci
->dev
, 5);
1408 fprintf(stderr
, "cpage out of range (%d)\n", cpage
);
1409 return USB_RET_PROCERR
;
1412 page
= p
->qtd
.bufptr
[cpage
] & QTD_BUFPTR_MASK
;
1415 if (plen
> 4096 - offset
) {
1416 plen
= 4096 - offset
;
1421 qemu_sglist_add(&p
->sgl
, page
, plen
);
1427 static void ehci_finish_transfer(EHCIQueue
*q
, int status
)
1429 uint32_t cpage
, offset
;
1432 /* update cpage & offset */
1433 cpage
= get_field(q
->qh
.token
, QTD_TOKEN_CPAGE
);
1434 offset
= q
->qh
.bufptr
[0] & ~QTD_BUFPTR_MASK
;
1437 cpage
+= offset
>> QTD_BUFPTR_SH
;
1438 offset
&= ~QTD_BUFPTR_MASK
;
1440 set_field(&q
->qh
.token
, cpage
, QTD_TOKEN_CPAGE
);
1441 q
->qh
.bufptr
[0] &= QTD_BUFPTR_MASK
;
1442 q
->qh
.bufptr
[0] |= offset
;
1446 static void ehci_async_complete_packet(USBPort
*port
, USBPacket
*packet
)
1449 EHCIState
*s
= port
->opaque
;
1450 uint32_t portsc
= s
->portsc
[port
->index
];
1452 if (portsc
& PORTSC_POWNER
) {
1453 USBPort
*companion
= s
->companion_ports
[port
->index
];
1454 companion
->ops
->complete(companion
, packet
);
1458 p
= container_of(packet
, EHCIPacket
, packet
);
1459 trace_usb_ehci_packet_action(p
->queue
, p
, "wakeup");
1460 assert(p
->async
== EHCI_ASYNC_INFLIGHT
);
1461 p
->async
= EHCI_ASYNC_FINISHED
;
1462 p
->usb_status
= packet
->result
;
1464 if (p
->queue
->async
) {
1465 qemu_bh_schedule(p
->queue
->ehci
->async_bh
);
1469 static void ehci_execute_complete(EHCIQueue
*q
)
1471 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1474 assert(p
->qtdaddr
== q
->qtdaddr
);
1475 assert(p
->async
== EHCI_ASYNC_INITIALIZED
||
1476 p
->async
== EHCI_ASYNC_FINISHED
);
1478 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1479 q
->qhaddr
, q
->qh
.next
, q
->qtdaddr
, q
->usb_status
);
1481 if (p
->usb_status
< 0) {
1482 switch (p
->usb_status
) {
1483 case USB_RET_IOERROR
:
1485 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_XACTERR
);
1486 set_field(&q
->qh
.token
, 0, QTD_TOKEN_CERR
);
1487 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1490 q
->qh
.token
|= QTD_TOKEN_HALT
;
1491 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1494 set_field(&q
->qh
.altnext_qtd
, 0, QH_ALTNEXT_NAKCNT
);
1495 return; /* We're not done yet with this transaction */
1496 case USB_RET_BABBLE
:
1497 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_BABBLE
);
1498 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1501 /* should not be triggerable */
1502 fprintf(stderr
, "USB invalid response %d\n", p
->usb_status
);
1507 // TODO check 4.12 for splits
1509 if (p
->tbytes
&& p
->pid
== USB_TOKEN_IN
) {
1510 p
->tbytes
-= p
->usb_status
;
1515 DPRINTF("updating tbytes to %d\n", p
->tbytes
);
1516 set_field(&q
->qh
.token
, p
->tbytes
, QTD_TOKEN_TBYTES
);
1518 ehci_finish_transfer(q
, p
->usb_status
);
1519 usb_packet_unmap(&p
->packet
, &p
->sgl
);
1520 qemu_sglist_destroy(&p
->sgl
);
1521 p
->async
= EHCI_ASYNC_NONE
;
1523 q
->qh
.token
^= QTD_TOKEN_DTOGGLE
;
1524 q
->qh
.token
&= ~QTD_TOKEN_ACTIVE
;
1526 if (q
->qh
.token
& QTD_TOKEN_IOC
) {
1527 ehci_raise_irq(q
->ehci
, USBSTS_INT
);
1533 static int ehci_execute(EHCIPacket
*p
, const char *action
)
1539 assert(p
->async
== EHCI_ASYNC_NONE
||
1540 p
->async
== EHCI_ASYNC_INITIALIZED
);
1542 if (!(p
->qtd
.token
& QTD_TOKEN_ACTIVE
)) {
1543 fprintf(stderr
, "Attempting to execute inactive qtd\n");
1544 return USB_RET_PROCERR
;
1547 p
->tbytes
= (p
->qtd
.token
& QTD_TOKEN_TBYTES_MASK
) >> QTD_TOKEN_TBYTES_SH
;
1548 if (p
->tbytes
> BUFF_SIZE
) {
1549 ehci_trace_guest_bug(p
->queue
->ehci
,
1550 "guest requested more bytes than allowed");
1551 return USB_RET_PROCERR
;
1554 p
->pid
= (p
->qtd
.token
& QTD_TOKEN_PID_MASK
) >> QTD_TOKEN_PID_SH
;
1557 p
->pid
= USB_TOKEN_OUT
;
1560 p
->pid
= USB_TOKEN_IN
;
1563 p
->pid
= USB_TOKEN_SETUP
;
1566 fprintf(stderr
, "bad token\n");
1570 endp
= get_field(p
->queue
->qh
.epchar
, QH_EPCHAR_EP
);
1571 ep
= usb_ep_get(p
->queue
->dev
, p
->pid
, endp
);
1573 if (p
->async
== EHCI_ASYNC_NONE
) {
1574 if (ehci_init_transfer(p
) != 0) {
1575 return USB_RET_PROCERR
;
1578 usb_packet_setup(&p
->packet
, p
->pid
, ep
, p
->qtdaddr
);
1579 usb_packet_map(&p
->packet
, &p
->sgl
);
1580 p
->async
= EHCI_ASYNC_INITIALIZED
;
1583 trace_usb_ehci_packet_action(p
->queue
, p
, action
);
1584 ret
= usb_handle_packet(p
->queue
->dev
, &p
->packet
);
1585 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1586 "(total %d) endp %x ret %d\n",
1587 q
->qhaddr
, q
->qh
.next
, q
->qtdaddr
, q
->pid
,
1588 q
->packet
.iov
.size
, q
->tbytes
, endp
, ret
);
1590 if (ret
> BUFF_SIZE
) {
1591 fprintf(stderr
, "ret from usb_handle_packet > BUFF_SIZE\n");
1592 return USB_RET_PROCERR
;
1601 static int ehci_process_itd(EHCIState
*ehci
,
1608 uint32_t i
, len
, pid
, dir
, devaddr
, endp
;
1609 uint32_t pg
, off
, ptr1
, ptr2
, max
, mult
;
1611 dir
=(itd
->bufptr
[1] & ITD_BUFPTR_DIRECTION
);
1612 devaddr
= get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
);
1613 endp
= get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
);
1614 max
= get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
);
1615 mult
= get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
);
1617 for(i
= 0; i
< 8; i
++) {
1618 if (itd
->transact
[i
] & ITD_XACT_ACTIVE
) {
1619 pg
= get_field(itd
->transact
[i
], ITD_XACT_PGSEL
);
1620 off
= itd
->transact
[i
] & ITD_XACT_OFFSET_MASK
;
1621 ptr1
= (itd
->bufptr
[pg
] & ITD_BUFPTR_MASK
);
1622 ptr2
= (itd
->bufptr
[pg
+1] & ITD_BUFPTR_MASK
);
1623 len
= get_field(itd
->transact
[i
], ITD_XACT_LENGTH
);
1625 if (len
> max
* mult
) {
1629 if (len
> BUFF_SIZE
) {
1630 return USB_RET_PROCERR
;
1633 pci_dma_sglist_init(&ehci
->isgl
, &ehci
->dev
, 2);
1634 if (off
+ len
> 4096) {
1635 /* transfer crosses page border */
1636 uint32_t len2
= off
+ len
- 4096;
1637 uint32_t len1
= len
- len2
;
1638 qemu_sglist_add(&ehci
->isgl
, ptr1
+ off
, len1
);
1639 qemu_sglist_add(&ehci
->isgl
, ptr2
, len2
);
1641 qemu_sglist_add(&ehci
->isgl
, ptr1
+ off
, len
);
1644 pid
= dir
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1646 dev
= ehci_find_device(ehci
, devaddr
);
1647 ep
= usb_ep_get(dev
, pid
, endp
);
1648 if (ep
&& ep
->type
== USB_ENDPOINT_XFER_ISOC
) {
1649 usb_packet_setup(&ehci
->ipacket
, pid
, ep
, addr
);
1650 usb_packet_map(&ehci
->ipacket
, &ehci
->isgl
);
1651 ret
= usb_handle_packet(dev
, &ehci
->ipacket
);
1652 assert(ret
!= USB_RET_ASYNC
);
1653 usb_packet_unmap(&ehci
->ipacket
, &ehci
->isgl
);
1655 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1658 qemu_sglist_destroy(&ehci
->isgl
);
1663 fprintf(stderr
, "Unexpected iso usb result: %d\n", ret
);
1665 case USB_RET_IOERROR
:
1667 /* 3.3.2: XACTERR is only allowed on IN transactions */
1669 itd
->transact
[i
] |= ITD_XACT_XACTERR
;
1670 ehci_raise_irq(ehci
, USBSTS_ERRINT
);
1673 case USB_RET_BABBLE
:
1674 itd
->transact
[i
] |= ITD_XACT_BABBLE
;
1675 ehci_raise_irq(ehci
, USBSTS_ERRINT
);
1678 /* no data for us, so do a zero-length transfer */
1686 set_field(&itd
->transact
[i
], len
- ret
, ITD_XACT_LENGTH
);
1689 set_field(&itd
->transact
[i
], ret
, ITD_XACT_LENGTH
);
1692 if (itd
->transact
[i
] & ITD_XACT_IOC
) {
1693 ehci_raise_irq(ehci
, USBSTS_INT
);
1695 itd
->transact
[i
] &= ~ITD_XACT_ACTIVE
;
1702 /* This state is the entry point for asynchronous schedule
1703 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1705 static int ehci_state_waitlisthead(EHCIState
*ehci
, int async
)
1710 uint32_t entry
= ehci
->asynclistaddr
;
1712 /* set reclamation flag at start event (4.8.6) */
1714 ehci_set_usbsts(ehci
, USBSTS_REC
);
1717 ehci_queues_rip_unused(ehci
, async
);
1719 /* Find the head of the list (4.9.1.1) */
1720 for(i
= 0; i
< MAX_QH
; i
++) {
1721 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &qh
,
1722 sizeof(EHCIqh
) >> 2);
1723 ehci_trace_qh(NULL
, NLPTR_GET(entry
), &qh
);
1725 if (qh
.epchar
& QH_EPCHAR_H
) {
1727 entry
|= (NLPTR_TYPE_QH
<< 1);
1730 ehci_set_fetch_addr(ehci
, async
, entry
);
1731 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1737 if (entry
== ehci
->asynclistaddr
) {
1742 /* no head found for list. */
1744 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1751 /* This state is the entry point for periodic schedule processing as
1752 * well as being a continuation state for async processing.
1754 static int ehci_state_fetchentry(EHCIState
*ehci
, int async
)
1757 uint32_t entry
= ehci_get_fetch_addr(ehci
, async
);
1759 if (NLPTR_TBIT(entry
)) {
1760 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1764 /* section 4.8, only QH in async schedule */
1765 if (async
&& (NLPTR_TYPE_GET(entry
) != NLPTR_TYPE_QH
)) {
1766 fprintf(stderr
, "non queue head request in async schedule\n");
1770 switch (NLPTR_TYPE_GET(entry
)) {
1772 ehci_set_state(ehci
, async
, EST_FETCHQH
);
1776 case NLPTR_TYPE_ITD
:
1777 ehci_set_state(ehci
, async
, EST_FETCHITD
);
1781 case NLPTR_TYPE_STITD
:
1782 ehci_set_state(ehci
, async
, EST_FETCHSITD
);
1787 /* TODO: handle FSTN type */
1788 fprintf(stderr
, "FETCHENTRY: entry at %X is of type %d "
1789 "which is not supported yet\n", entry
, NLPTR_TYPE_GET(entry
));
1797 static EHCIQueue
*ehci_state_fetchqh(EHCIState
*ehci
, int async
)
1800 uint32_t entry
, devaddr
, endp
;
1804 entry
= ehci_get_fetch_addr(ehci
, async
);
1805 q
= ehci_find_queue_by_qh(ehci
, entry
, async
);
1807 q
= ehci_alloc_queue(ehci
, entry
, async
);
1809 p
= QTAILQ_FIRST(&q
->packets
);
1813 /* we are going in circles -- stop processing */
1814 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1819 get_dwords(ehci
, NLPTR_GET(q
->qhaddr
),
1820 (uint32_t *) &qh
, sizeof(EHCIqh
) >> 2);
1821 ehci_trace_qh(q
, NLPTR_GET(q
->qhaddr
), &qh
);
1824 * The overlay area of the qh should never be changed by the guest,
1825 * except when idle, in which case the reset is a nop.
1827 devaddr
= get_field(qh
.epchar
, QH_EPCHAR_DEVADDR
);
1828 endp
= get_field(qh
.epchar
, QH_EPCHAR_EP
);
1829 if ((devaddr
!= get_field(q
->qh
.epchar
, QH_EPCHAR_DEVADDR
)) ||
1830 (endp
!= get_field(q
->qh
.epchar
, QH_EPCHAR_EP
)) ||
1831 (memcmp(&qh
.current_qtd
, &q
->qh
.current_qtd
,
1832 9 * sizeof(uint32_t)) != 0) ||
1833 (q
->dev
!= NULL
&& q
->dev
->addr
!= devaddr
)) {
1834 if (ehci_reset_queue(q
) > 0) {
1835 ehci_trace_guest_bug(ehci
, "guest updated active QH");
1841 q
->transact_ctr
= get_field(q
->qh
.epcap
, QH_EPCAP_MULT
);
1842 if (q
->transact_ctr
== 0) { /* Guest bug in some versions of windows */
1843 q
->transact_ctr
= 4;
1846 if (q
->dev
== NULL
) {
1847 q
->dev
= ehci_find_device(q
->ehci
, devaddr
);
1850 if (p
&& p
->async
== EHCI_ASYNC_FINISHED
) {
1851 /* I/O finished -- continue processing queue */
1852 trace_usb_ehci_packet_action(p
->queue
, p
, "complete");
1853 ehci_set_state(ehci
, async
, EST_EXECUTING
);
1857 if (async
&& (q
->qh
.epchar
& QH_EPCHAR_H
)) {
1859 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1860 if (ehci
->usbsts
& USBSTS_REC
) {
1861 ehci_clear_usbsts(ehci
, USBSTS_REC
);
1863 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1864 " - done processing\n", q
->qhaddr
);
1865 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1872 if (q
->qhaddr
!= q
->qh
.next
) {
1873 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1875 q
->qh
.epchar
& QH_EPCHAR_H
,
1876 q
->qh
.token
& QTD_TOKEN_HALT
,
1877 q
->qh
.token
& QTD_TOKEN_ACTIVE
,
1882 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
1883 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1885 } else if ((q
->qh
.token
& QTD_TOKEN_ACTIVE
) &&
1886 (NLPTR_TBIT(q
->qh
.current_qtd
) == 0)) {
1887 q
->qtdaddr
= q
->qh
.current_qtd
;
1888 ehci_set_state(ehci
, async
, EST_FETCHQTD
);
1891 /* EHCI spec version 1.0 Section 4.10.2 */
1892 ehci_set_state(ehci
, async
, EST_ADVANCEQUEUE
);
1899 static int ehci_state_fetchitd(EHCIState
*ehci
, int async
)
1905 entry
= ehci_get_fetch_addr(ehci
, async
);
1907 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &itd
,
1908 sizeof(EHCIitd
) >> 2);
1909 ehci_trace_itd(ehci
, entry
, &itd
);
1911 if (ehci_process_itd(ehci
, &itd
, entry
) != 0) {
1915 put_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &itd
,
1916 sizeof(EHCIitd
) >> 2);
1917 ehci_set_fetch_addr(ehci
, async
, itd
.next
);
1918 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1923 static int ehci_state_fetchsitd(EHCIState
*ehci
, int async
)
1929 entry
= ehci_get_fetch_addr(ehci
, async
);
1931 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *)&sitd
,
1932 sizeof(EHCIsitd
) >> 2);
1933 ehci_trace_sitd(ehci
, entry
, &sitd
);
1935 if (!(sitd
.results
& SITD_RESULTS_ACTIVE
)) {
1936 /* siTD is not active, nothing to do */;
1938 /* TODO: split transfers are not implemented */
1939 fprintf(stderr
, "WARNING: Skipping active siTD\n");
1942 ehci_set_fetch_addr(ehci
, async
, sitd
.next
);
1943 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1947 /* Section 4.10.2 - paragraph 3 */
1948 static int ehci_state_advqueue(EHCIQueue
*q
)
1951 /* TO-DO: 4.10.2 - paragraph 2
1952 * if I-bit is set to 1 and QH is not active
1953 * go to horizontal QH
1956 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1962 * want data and alt-next qTD is valid
1964 if (((q
->qh
.token
& QTD_TOKEN_TBYTES_MASK
) != 0) &&
1965 (NLPTR_TBIT(q
->qh
.altnext_qtd
) == 0)) {
1966 q
->qtdaddr
= q
->qh
.altnext_qtd
;
1967 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHQTD
);
1972 } else if (NLPTR_TBIT(q
->qh
.next_qtd
) == 0) {
1973 q
->qtdaddr
= q
->qh
.next_qtd
;
1974 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHQTD
);
1977 * no valid qTD, try next QH
1980 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1986 /* Section 4.10.2 - paragraph 4 */
1987 static int ehci_state_fetchqtd(EHCIQueue
*q
)
1993 get_dwords(q
->ehci
, NLPTR_GET(q
->qtdaddr
), (uint32_t *) &qtd
,
1994 sizeof(EHCIqtd
) >> 2);
1995 ehci_trace_qtd(q
, NLPTR_GET(q
->qtdaddr
), &qtd
);
1997 p
= QTAILQ_FIRST(&q
->packets
);
1999 if (p
->qtdaddr
!= q
->qtdaddr
||
2000 (!NLPTR_TBIT(p
->qtd
.next
) && (p
->qtd
.next
!= qtd
.next
)) ||
2001 (!NLPTR_TBIT(p
->qtd
.altnext
) && (p
->qtd
.altnext
!= qtd
.altnext
)) ||
2002 p
->qtd
.bufptr
[0] != qtd
.bufptr
[0]) {
2003 ehci_cancel_queue(q
);
2004 ehci_trace_guest_bug(q
->ehci
, "guest updated active QH or qTD");
2008 ehci_qh_do_overlay(q
);
2012 if (!(qtd
.token
& QTD_TOKEN_ACTIVE
)) {
2014 /* transfer canceled by guest (clear active) */
2015 ehci_cancel_queue(q
);
2018 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2020 } else if (p
!= NULL
) {
2022 case EHCI_ASYNC_NONE
:
2023 case EHCI_ASYNC_INITIALIZED
:
2024 /* Not yet executed (MULT), or previously nacked (int) packet */
2025 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTE
);
2027 case EHCI_ASYNC_INFLIGHT
:
2028 /* Unfinished async handled packet, go horizontal */
2029 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2031 case EHCI_ASYNC_FINISHED
:
2033 * We get here when advqueue moves to a packet which is already
2034 * finished, which can happen with packets queued up by fill_queue
2036 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTING
);
2041 p
= ehci_alloc_packet(q
);
2042 p
->qtdaddr
= q
->qtdaddr
;
2044 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTE
);
2051 static int ehci_state_horizqh(EHCIQueue
*q
)
2055 if (ehci_get_fetch_addr(q
->ehci
, q
->async
) != q
->qh
.next
) {
2056 ehci_set_fetch_addr(q
->ehci
, q
->async
, q
->qh
.next
);
2057 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHENTRY
);
2060 ehci_set_state(q
->ehci
, q
->async
, EST_ACTIVE
);
2066 static int ehci_fill_queue(EHCIPacket
*p
)
2068 EHCIQueue
*q
= p
->queue
;
2069 EHCIqtd qtd
= p
->qtd
;
2073 if (NLPTR_TBIT(qtd
.altnext
) == 0) {
2076 if (NLPTR_TBIT(qtd
.next
) != 0) {
2080 get_dwords(q
->ehci
, NLPTR_GET(qtdaddr
),
2081 (uint32_t *) &qtd
, sizeof(EHCIqtd
) >> 2);
2082 ehci_trace_qtd(q
, NLPTR_GET(qtdaddr
), &qtd
);
2083 if (!(qtd
.token
& QTD_TOKEN_ACTIVE
)) {
2086 p
= ehci_alloc_packet(q
);
2087 p
->qtdaddr
= qtdaddr
;
2089 p
->usb_status
= ehci_execute(p
, "queue");
2090 if (p
->usb_status
== USB_RET_PROCERR
) {
2093 assert(p
->usb_status
== USB_RET_ASYNC
);
2094 p
->async
= EHCI_ASYNC_INFLIGHT
;
2096 return p
->usb_status
;
2099 static int ehci_state_execute(EHCIQueue
*q
)
2101 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2105 assert(p
->qtdaddr
== q
->qtdaddr
);
2107 if (ehci_qh_do_overlay(q
) != 0) {
2111 // TODO verify enough time remains in the uframe as in 4.4.1.1
2112 // TODO write back ptr to async list when done or out of time
2114 /* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */
2115 if (!q
->async
&& q
->transact_ctr
== 0) {
2116 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2122 ehci_set_usbsts(q
->ehci
, USBSTS_REC
);
2125 p
->usb_status
= ehci_execute(p
, "process");
2126 if (p
->usb_status
== USB_RET_PROCERR
) {
2130 if (p
->usb_status
== USB_RET_ASYNC
) {
2132 trace_usb_ehci_packet_action(p
->queue
, p
, "async");
2133 p
->async
= EHCI_ASYNC_INFLIGHT
;
2134 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2136 again
= (ehci_fill_queue(p
) == USB_RET_PROCERR
) ? -1 : 1;
2143 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTING
);
2150 static int ehci_state_executing(EHCIQueue
*q
)
2152 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2155 assert(p
->qtdaddr
== q
->qtdaddr
);
2157 ehci_execute_complete(q
);
2160 if (!q
->async
&& q
->transact_ctr
> 0) {
2165 if (p
->usb_status
== USB_RET_NAK
) {
2166 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2168 ehci_set_state(q
->ehci
, q
->async
, EST_WRITEBACK
);
2176 static int ehci_state_writeback(EHCIQueue
*q
)
2178 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2179 uint32_t *qtd
, addr
;
2182 /* Write back the QTD from the QH area */
2184 assert(p
->qtdaddr
== q
->qtdaddr
);
2186 ehci_trace_qtd(q
, NLPTR_GET(p
->qtdaddr
), (EHCIqtd
*) &q
->qh
.next_qtd
);
2187 qtd
= (uint32_t *) &q
->qh
.next_qtd
;
2188 addr
= NLPTR_GET(p
->qtdaddr
);
2189 put_dwords(q
->ehci
, addr
+ 2 * sizeof(uint32_t), qtd
+ 2, 2);
2190 ehci_free_packet(p
);
2193 * EHCI specs say go horizontal here.
2195 * We can also advance the queue here for performance reasons. We
2196 * need to take care to only take that shortcut in case we've
2197 * processed the qtd just written back without errors, i.e. halt
2200 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
2202 * We should not do any further processing on a halted queue!
2203 * This is esp. important for bulk endpoints with pipelining enabled
2204 * (redirection to a real USB device), where we must cancel all the
2205 * transfers after this one so that:
2206 * 1) If they've completed already, they are not processed further
2207 * causing more stalls, originating from the same failed transfer
2208 * 2) If still in flight, they are cancelled before the guest does
2209 * a clear stall, otherwise the guest and device can loose sync!
2211 while ((p
= QTAILQ_FIRST(&q
->packets
)) != NULL
) {
2212 ehci_free_packet(p
);
2214 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2217 ehci_set_state(q
->ehci
, q
->async
, EST_ADVANCEQUEUE
);
2224 * This is the state machine that is common to both async and periodic
2227 static void ehci_advance_state(EHCIState
*ehci
, int async
)
2229 EHCIQueue
*q
= NULL
;
2233 switch(ehci_get_state(ehci
, async
)) {
2234 case EST_WAITLISTHEAD
:
2235 again
= ehci_state_waitlisthead(ehci
, async
);
2238 case EST_FETCHENTRY
:
2239 again
= ehci_state_fetchentry(ehci
, async
);
2243 q
= ehci_state_fetchqh(ehci
, async
);
2245 assert(q
->async
== async
);
2253 again
= ehci_state_fetchitd(ehci
, async
);
2257 again
= ehci_state_fetchsitd(ehci
, async
);
2260 case EST_ADVANCEQUEUE
:
2261 again
= ehci_state_advqueue(q
);
2265 again
= ehci_state_fetchqtd(q
);
2268 case EST_HORIZONTALQH
:
2269 again
= ehci_state_horizqh(q
);
2273 again
= ehci_state_execute(q
);
2275 ehci
->async_stepdown
= 0;
2282 ehci
->async_stepdown
= 0;
2284 again
= ehci_state_executing(q
);
2289 again
= ehci_state_writeback(q
);
2293 fprintf(stderr
, "Bad state!\n");
2300 fprintf(stderr
, "processing error - resetting ehci HC\n");
2308 static void ehci_advance_async_state(EHCIState
*ehci
)
2310 const int async
= 1;
2312 switch(ehci_get_state(ehci
, async
)) {
2314 if (!ehci_async_enabled(ehci
)) {
2317 ehci_set_state(ehci
, async
, EST_ACTIVE
);
2318 // No break, fall through to ACTIVE
2321 if (!ehci_async_enabled(ehci
)) {
2322 ehci_queues_rip_all(ehci
, async
);
2323 ehci_set_state(ehci
, async
, EST_INACTIVE
);
2327 /* make sure guest has acknowledged the doorbell interrupt */
2328 /* TO-DO: is this really needed? */
2329 if (ehci
->usbsts
& USBSTS_IAA
) {
2330 DPRINTF("IAA status bit still set.\n");
2334 /* check that address register has been set */
2335 if (ehci
->asynclistaddr
== 0) {
2339 ehci_set_state(ehci
, async
, EST_WAITLISTHEAD
);
2340 ehci_advance_state(ehci
, async
);
2342 /* If the doorbell is set, the guest wants to make a change to the
2343 * schedule. The host controller needs to release cached data.
2346 if (ehci
->usbcmd
& USBCMD_IAAD
) {
2347 /* Remove all unseen qhs from the async qhs queue */
2348 ehci_queues_rip_unseen(ehci
, async
);
2349 trace_usb_ehci_doorbell_ack();
2350 ehci
->usbcmd
&= ~USBCMD_IAAD
;
2351 ehci_raise_irq(ehci
, USBSTS_IAA
);
2356 /* this should only be due to a developer mistake */
2357 fprintf(stderr
, "ehci: Bad asynchronous state %d. "
2358 "Resetting to active\n", ehci
->astate
);
2363 static void ehci_advance_periodic_state(EHCIState
*ehci
)
2367 const int async
= 0;
2371 switch(ehci_get_state(ehci
, async
)) {
2373 if (!(ehci
->frindex
& 7) && ehci_periodic_enabled(ehci
)) {
2374 ehci_set_state(ehci
, async
, EST_ACTIVE
);
2375 // No break, fall through to ACTIVE
2380 if (!(ehci
->frindex
& 7) && !ehci_periodic_enabled(ehci
)) {
2381 ehci_queues_rip_all(ehci
, async
);
2382 ehci_set_state(ehci
, async
, EST_INACTIVE
);
2386 list
= ehci
->periodiclistbase
& 0xfffff000;
2387 /* check that register has been set */
2391 list
|= ((ehci
->frindex
& 0x1ff8) >> 1);
2393 pci_dma_read(&ehci
->dev
, list
, &entry
, sizeof entry
);
2394 entry
= le32_to_cpu(entry
);
2396 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2397 ehci
->frindex
/ 8, list
, entry
);
2398 ehci_set_fetch_addr(ehci
, async
,entry
);
2399 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
2400 ehci_advance_state(ehci
, async
);
2401 ehci_queues_rip_unused(ehci
, async
);
2405 /* this should only be due to a developer mistake */
2406 fprintf(stderr
, "ehci: Bad periodic state %d. "
2407 "Resetting to active\n", ehci
->pstate
);
2412 static void ehci_update_frindex(EHCIState
*ehci
, int frames
)
2416 if (!ehci_enabled(ehci
)) {
2420 for (i
= 0; i
< frames
; i
++) {
2423 if (ehci
->frindex
== 0x00002000) {
2424 ehci_raise_irq(ehci
, USBSTS_FLR
);
2427 if (ehci
->frindex
== 0x00004000) {
2428 ehci_raise_irq(ehci
, USBSTS_FLR
);
2430 if (ehci
->usbsts_frindex
>= 0x00004000) {
2431 ehci
->usbsts_frindex
-= 0x00004000;
2433 ehci
->usbsts_frindex
= 0;
2439 static void ehci_frame_timer(void *opaque
)
2441 EHCIState
*ehci
= opaque
;
2443 int64_t expire_time
, t_now
;
2444 uint64_t ns_elapsed
;
2445 int frames
, skipped_frames
;
2448 t_now
= qemu_get_clock_ns(vm_clock
);
2449 ns_elapsed
= t_now
- ehci
->last_run_ns
;
2450 frames
= ns_elapsed
/ FRAME_TIMER_NS
;
2452 if (ehci_periodic_enabled(ehci
) || ehci
->pstate
!= EST_INACTIVE
) {
2454 ehci
->async_stepdown
= 0;
2456 if (frames
> ehci
->maxframes
) {
2457 skipped_frames
= frames
- ehci
->maxframes
;
2458 ehci_update_frindex(ehci
, skipped_frames
);
2459 ehci
->last_run_ns
+= FRAME_TIMER_NS
* skipped_frames
;
2460 frames
-= skipped_frames
;
2461 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames
);
2464 for (i
= 0; i
< frames
; i
++) {
2466 * If we're running behind schedule, we should not catch up
2467 * too fast, as that will make some guests unhappy:
2468 * 1) We must process a minimum of MIN_FR_PER_TICK frames,
2469 * otherwise we will never catch up
2470 * 2) Process frames until the guest has requested an irq (IOC)
2472 if (i
>= MIN_FR_PER_TICK
) {
2473 ehci_commit_irq(ehci
);
2474 if ((ehci
->usbsts
& USBINTR_MASK
) & ehci
->usbintr
) {
2478 ehci_update_frindex(ehci
, 1);
2479 ehci_advance_periodic_state(ehci
);
2480 ehci
->last_run_ns
+= FRAME_TIMER_NS
;
2483 if (ehci
->async_stepdown
< ehci
->maxframes
/ 2) {
2484 ehci
->async_stepdown
++;
2486 ehci_update_frindex(ehci
, frames
);
2487 ehci
->last_run_ns
+= FRAME_TIMER_NS
* frames
;
2490 /* Async is not inside loop since it executes everything it can once
2493 if (ehci_async_enabled(ehci
) || ehci
->astate
!= EST_INACTIVE
) {
2495 ehci_advance_async_state(ehci
);
2498 ehci_commit_irq(ehci
);
2499 if (ehci
->usbsts_pending
) {
2501 ehci
->async_stepdown
= 0;
2505 expire_time
= t_now
+ (get_ticks_per_sec()
2506 * (ehci
->async_stepdown
+1) / FRAME_TIMER_FREQ
);
2507 qemu_mod_timer(ehci
->frame_timer
, expire_time
);
2511 static void ehci_async_bh(void *opaque
)
2513 EHCIState
*ehci
= opaque
;
2514 ehci_advance_async_state(ehci
);
2517 static const MemoryRegionOps ehci_mmio_caps_ops
= {
2518 .read
= ehci_caps_read
,
2519 .valid
.min_access_size
= 1,
2520 .valid
.max_access_size
= 4,
2521 .impl
.min_access_size
= 1,
2522 .impl
.max_access_size
= 1,
2523 .endianness
= DEVICE_LITTLE_ENDIAN
,
2526 static const MemoryRegionOps ehci_mmio_opreg_ops
= {
2527 .read
= ehci_opreg_read
,
2528 .write
= ehci_opreg_write
,
2529 .valid
.min_access_size
= 4,
2530 .valid
.max_access_size
= 4,
2531 .endianness
= DEVICE_LITTLE_ENDIAN
,
2534 static const MemoryRegionOps ehci_mmio_port_ops
= {
2535 .read
= ehci_port_read
,
2536 .write
= ehci_port_write
,
2537 .valid
.min_access_size
= 4,
2538 .valid
.max_access_size
= 4,
2539 .endianness
= DEVICE_LITTLE_ENDIAN
,
2542 static int usb_ehci_initfn(PCIDevice
*dev
);
2544 static USBPortOps ehci_port_ops
= {
2545 .attach
= ehci_attach
,
2546 .detach
= ehci_detach
,
2547 .child_detach
= ehci_child_detach
,
2548 .wakeup
= ehci_wakeup
,
2549 .complete
= ehci_async_complete_packet
,
2552 static USBBusOps ehci_bus_ops
= {
2553 .register_companion
= ehci_register_companion
,
2556 static int usb_ehci_post_load(void *opaque
, int version_id
)
2558 EHCIState
*s
= opaque
;
2561 for (i
= 0; i
< NB_PORTS
; i
++) {
2562 USBPort
*companion
= s
->companion_ports
[i
];
2563 if (companion
== NULL
) {
2566 if (s
->portsc
[i
] & PORTSC_POWNER
) {
2567 companion
->dev
= s
->ports
[i
].dev
;
2569 companion
->dev
= NULL
;
2576 static void usb_ehci_vm_state_change(void *opaque
, int running
, RunState state
)
2578 EHCIState
*ehci
= opaque
;
2581 * We don't migrate the EHCIQueue-s, instead we rebuild them for the
2582 * schedule in guest memory. We must do the rebuilt ASAP, so that
2583 * USB-devices which have async handled packages have a packet in the
2584 * ep queue to match the completion with.
2586 if (state
== RUN_STATE_RUNNING
) {
2587 ehci_advance_async_state(ehci
);
2591 * The schedule rebuilt from guest memory could cause the migration dest
2592 * to miss a QH unlink, and fail to cancel packets, since the unlinked QH
2593 * will never have existed on the destination. Therefor we must flush the
2594 * async schedule on savevm to catch any not yet noticed unlinks.
2596 if (state
== RUN_STATE_SAVE_VM
) {
2597 ehci_advance_async_state(ehci
);
2598 ehci_queues_rip_unseen(ehci
, 1);
2602 static const VMStateDescription vmstate_ehci
= {
2605 .minimum_version_id
= 1,
2606 .post_load
= usb_ehci_post_load
,
2607 .fields
= (VMStateField
[]) {
2608 VMSTATE_PCI_DEVICE(dev
, EHCIState
),
2609 /* mmio registers */
2610 VMSTATE_UINT32(usbcmd
, EHCIState
),
2611 VMSTATE_UINT32(usbsts
, EHCIState
),
2612 VMSTATE_UINT32_V(usbsts_pending
, EHCIState
, 2),
2613 VMSTATE_UINT32_V(usbsts_frindex
, EHCIState
, 2),
2614 VMSTATE_UINT32(usbintr
, EHCIState
),
2615 VMSTATE_UINT32(frindex
, EHCIState
),
2616 VMSTATE_UINT32(ctrldssegment
, EHCIState
),
2617 VMSTATE_UINT32(periodiclistbase
, EHCIState
),
2618 VMSTATE_UINT32(asynclistaddr
, EHCIState
),
2619 VMSTATE_UINT32(configflag
, EHCIState
),
2620 VMSTATE_UINT32(portsc
[0], EHCIState
),
2621 VMSTATE_UINT32(portsc
[1], EHCIState
),
2622 VMSTATE_UINT32(portsc
[2], EHCIState
),
2623 VMSTATE_UINT32(portsc
[3], EHCIState
),
2624 VMSTATE_UINT32(portsc
[4], EHCIState
),
2625 VMSTATE_UINT32(portsc
[5], EHCIState
),
2627 VMSTATE_TIMER(frame_timer
, EHCIState
),
2628 VMSTATE_UINT64(last_run_ns
, EHCIState
),
2629 VMSTATE_UINT32(async_stepdown
, EHCIState
),
2630 /* schedule state */
2631 VMSTATE_UINT32(astate
, EHCIState
),
2632 VMSTATE_UINT32(pstate
, EHCIState
),
2633 VMSTATE_UINT32(a_fetch_addr
, EHCIState
),
2634 VMSTATE_UINT32(p_fetch_addr
, EHCIState
),
2635 VMSTATE_END_OF_LIST()
2639 static Property ehci_properties
[] = {
2640 DEFINE_PROP_UINT32("maxframes", EHCIState
, maxframes
, 128),
2641 DEFINE_PROP_END_OF_LIST(),
2644 static void ehci_class_init(ObjectClass
*klass
, void *data
)
2646 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2647 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2649 k
->init
= usb_ehci_initfn
;
2650 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
2651 k
->device_id
= PCI_DEVICE_ID_INTEL_82801D
; /* ich4 */
2653 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2654 dc
->vmsd
= &vmstate_ehci
;
2655 dc
->props
= ehci_properties
;
2658 static TypeInfo ehci_info
= {
2660 .parent
= TYPE_PCI_DEVICE
,
2661 .instance_size
= sizeof(EHCIState
),
2662 .class_init
= ehci_class_init
,
2665 static void ich9_ehci_class_init(ObjectClass
*klass
, void *data
)
2667 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2668 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2670 k
->init
= usb_ehci_initfn
;
2671 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
2672 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_EHCI1
;
2674 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2675 dc
->vmsd
= &vmstate_ehci
;
2676 dc
->props
= ehci_properties
;
2679 static TypeInfo ich9_ehci_info
= {
2680 .name
= "ich9-usb-ehci1",
2681 .parent
= TYPE_PCI_DEVICE
,
2682 .instance_size
= sizeof(EHCIState
),
2683 .class_init
= ich9_ehci_class_init
,
2686 static int usb_ehci_initfn(PCIDevice
*dev
)
2688 EHCIState
*s
= DO_UPCAST(EHCIState
, dev
, dev
);
2689 uint8_t *pci_conf
= s
->dev
.config
;
2692 pci_set_byte(&pci_conf
[PCI_CLASS_PROG
], 0x20);
2694 /* capabilities pointer */
2695 pci_set_byte(&pci_conf
[PCI_CAPABILITY_LIST
], 0x00);
2696 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2698 pci_set_byte(&pci_conf
[PCI_INTERRUPT_PIN
], 4); /* interrupt pin D */
2699 pci_set_byte(&pci_conf
[PCI_MIN_GNT
], 0);
2700 pci_set_byte(&pci_conf
[PCI_MAX_LAT
], 0);
2702 // pci_conf[0x50] = 0x01; // power management caps
2704 pci_set_byte(&pci_conf
[USB_SBRN
], USB_RELEASE_2
); // release number (2.1.4)
2705 pci_set_byte(&pci_conf
[0x61], 0x20); // frame length adjustment (2.1.5)
2706 pci_set_word(&pci_conf
[0x62], 0x00); // port wake up capability (2.1.6)
2708 pci_conf
[0x64] = 0x00;
2709 pci_conf
[0x65] = 0x00;
2710 pci_conf
[0x66] = 0x00;
2711 pci_conf
[0x67] = 0x00;
2712 pci_conf
[0x68] = 0x01;
2713 pci_conf
[0x69] = 0x00;
2714 pci_conf
[0x6a] = 0x00;
2715 pci_conf
[0x6b] = 0x00; // USBLEGSUP
2716 pci_conf
[0x6c] = 0x00;
2717 pci_conf
[0x6d] = 0x00;
2718 pci_conf
[0x6e] = 0x00;
2719 pci_conf
[0x6f] = 0xc0; // USBLEFCTLSTS
2721 /* 2.2 host controller interface version */
2722 s
->caps
[0x00] = (uint8_t) OPREGBASE
;
2723 s
->caps
[0x01] = 0x00;
2724 s
->caps
[0x02] = 0x00;
2725 s
->caps
[0x03] = 0x01; /* HC version */
2726 s
->caps
[0x04] = NB_PORTS
; /* Number of downstream ports */
2727 s
->caps
[0x05] = 0x00; /* No companion ports at present */
2728 s
->caps
[0x06] = 0x00;
2729 s
->caps
[0x07] = 0x00;
2730 s
->caps
[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
2731 s
->caps
[0x09] = 0x68; /* EECP */
2732 s
->caps
[0x0a] = 0x00;
2733 s
->caps
[0x0b] = 0x00;
2735 s
->irq
= s
->dev
.irq
[3];
2737 usb_bus_new(&s
->bus
, &ehci_bus_ops
, &s
->dev
.qdev
);
2738 for(i
= 0; i
< NB_PORTS
; i
++) {
2739 usb_register_port(&s
->bus
, &s
->ports
[i
], s
, i
, &ehci_port_ops
,
2740 USB_SPEED_MASK_HIGH
);
2741 s
->ports
[i
].dev
= 0;
2744 s
->frame_timer
= qemu_new_timer_ns(vm_clock
, ehci_frame_timer
, s
);
2745 s
->async_bh
= qemu_bh_new(ehci_async_bh
, s
);
2746 QTAILQ_INIT(&s
->aqueues
);
2747 QTAILQ_INIT(&s
->pqueues
);
2748 usb_packet_init(&s
->ipacket
);
2750 qemu_register_reset(ehci_reset
, s
);
2751 qemu_add_vm_change_state_handler(usb_ehci_vm_state_change
, s
);
2753 memory_region_init(&s
->mem
, "ehci", MMIO_SIZE
);
2754 memory_region_init_io(&s
->mem_caps
, &ehci_mmio_caps_ops
, s
,
2755 "capabilities", OPREGBASE
);
2756 memory_region_init_io(&s
->mem_opreg
, &ehci_mmio_opreg_ops
, s
,
2757 "operational", PORTSC_BEGIN
- OPREGBASE
);
2758 memory_region_init_io(&s
->mem_ports
, &ehci_mmio_port_ops
, s
,
2759 "ports", PORTSC_END
- PORTSC_BEGIN
);
2761 memory_region_add_subregion(&s
->mem
, 0, &s
->mem_caps
);
2762 memory_region_add_subregion(&s
->mem
, OPREGBASE
, &s
->mem_opreg
);
2763 memory_region_add_subregion(&s
->mem
, PORTSC_BEGIN
, &s
->mem_ports
);
2765 pci_register_bar(&s
->dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->mem
);
2770 static void ehci_register_types(void)
2772 type_register_static(&ehci_info
);
2773 type_register_static(&ich9_ehci_info
);
2776 type_init(ehci_register_types
)
2779 * vim: expandtab ts=4